Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * OMAP2 McSPI controller driver |
| 3 | * |
| 4 | * Copyright (C) 2005, 2006 Nokia Corporation |
| 5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and |
Charulatha V | 1a5d819 | 2011-02-02 17:52:14 +0530 | [diff] [blame] | 6 | * Juha Yrj�l� <juha.yrjola@nokia.com> |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #include <linux/kernel.h> |
| 25 | #include <linux/init.h> |
| 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/module.h> |
| 28 | #include <linux/device.h> |
| 29 | #include <linux/delay.h> |
| 30 | #include <linux/dma-mapping.h> |
| 31 | #include <linux/platform_device.h> |
| 32 | #include <linux/err.h> |
| 33 | #include <linux/clk.h> |
| 34 | #include <linux/io.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 35 | #include <linux/slab.h> |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 36 | #include <linux/pm_runtime.h> |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 37 | #include <linux/of.h> |
| 38 | #include <linux/of_device.h> |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 39 | |
| 40 | #include <linux/spi/spi.h> |
| 41 | |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 42 | #include <plat/dma.h> |
| 43 | #include <plat/clock.h> |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 44 | #include <plat/mcspi.h> |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 45 | |
| 46 | #define OMAP2_MCSPI_MAX_FREQ 48000000 |
| 47 | |
| 48 | #define OMAP2_MCSPI_REVISION 0x00 |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 49 | #define OMAP2_MCSPI_SYSSTATUS 0x14 |
| 50 | #define OMAP2_MCSPI_IRQSTATUS 0x18 |
| 51 | #define OMAP2_MCSPI_IRQENABLE 0x1c |
| 52 | #define OMAP2_MCSPI_WAKEUPENABLE 0x20 |
| 53 | #define OMAP2_MCSPI_SYST 0x24 |
| 54 | #define OMAP2_MCSPI_MODULCTRL 0x28 |
| 55 | |
| 56 | /* per-channel banks, 0x14 bytes each, first is: */ |
| 57 | #define OMAP2_MCSPI_CHCONF0 0x2c |
| 58 | #define OMAP2_MCSPI_CHSTAT0 0x30 |
| 59 | #define OMAP2_MCSPI_CHCTRL0 0x34 |
| 60 | #define OMAP2_MCSPI_TX0 0x38 |
| 61 | #define OMAP2_MCSPI_RX0 0x3c |
| 62 | |
| 63 | /* per-register bitmasks: */ |
| 64 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 65 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) |
| 66 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) |
| 67 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 68 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 69 | #define OMAP2_MCSPI_CHCONF_PHA BIT(0) |
| 70 | #define OMAP2_MCSPI_CHCONF_POL BIT(1) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 71 | #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 72 | #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 73 | #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 74 | #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) |
| 75 | #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 76 | #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 77 | #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) |
| 78 | #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) |
| 79 | #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) |
| 80 | #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) |
| 81 | #define OMAP2_MCSPI_CHCONF_IS BIT(18) |
| 82 | #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) |
| 83 | #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 84 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 85 | #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) |
| 86 | #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) |
| 87 | #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 88 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 89 | #define OMAP2_MCSPI_CHCTRL_EN BIT(0) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 90 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 91 | #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 92 | |
| 93 | /* We have 2 DMA channels per CS, one for RX and one for TX */ |
| 94 | struct omap2_mcspi_dma { |
| 95 | int dma_tx_channel; |
| 96 | int dma_rx_channel; |
| 97 | |
| 98 | int dma_tx_sync_dev; |
| 99 | int dma_rx_sync_dev; |
| 100 | |
| 101 | struct completion dma_tx_completion; |
| 102 | struct completion dma_rx_completion; |
| 103 | }; |
| 104 | |
| 105 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and |
| 106 | * cache operations; better heuristics consider wordsize and bitrate. |
| 107 | */ |
Roman Tereshonkov | 8b66c13 | 2010-04-12 09:07:54 +0000 | [diff] [blame] | 108 | #define DMA_MIN_BYTES 160 |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 109 | |
| 110 | |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame^] | 111 | /* |
| 112 | * Used for context save and restore, structure members to be updated whenever |
| 113 | * corresponding registers are modified. |
| 114 | */ |
| 115 | struct omap2_mcspi_regs { |
| 116 | u32 modulctrl; |
| 117 | u32 wakeupenable; |
| 118 | struct list_head cs; |
| 119 | }; |
| 120 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 121 | struct omap2_mcspi { |
| 122 | struct work_struct work; |
| 123 | /* lock protects queue and registers */ |
| 124 | spinlock_t lock; |
| 125 | struct list_head msg_queue; |
| 126 | struct spi_master *master; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 127 | /* Virtual base address of the controller */ |
| 128 | void __iomem *base; |
Russell King | e5480b73 | 2008-09-01 21:51:50 +0100 | [diff] [blame] | 129 | unsigned long phys; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 130 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
| 131 | struct omap2_mcspi_dma *dma_channels; |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame^] | 132 | struct device *dev; |
Shubhrajyoti D | 2856ac1 | 2011-10-28 17:14:17 +0530 | [diff] [blame] | 133 | struct workqueue_struct *wq; |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame^] | 134 | struct omap2_mcspi_regs ctx; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 135 | }; |
| 136 | |
| 137 | struct omap2_mcspi_cs { |
| 138 | void __iomem *base; |
Russell King | e5480b73 | 2008-09-01 21:51:50 +0100 | [diff] [blame] | 139 | unsigned long phys; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 140 | int word_len; |
Tero Kristo | 89c0537 | 2009-09-22 16:46:17 -0700 | [diff] [blame] | 141 | struct list_head node; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 142 | /* Context save and restore shadow register */ |
| 143 | u32 chconf0; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 144 | }; |
| 145 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 146 | #define MOD_REG_BIT(val, mask, set) do { \ |
| 147 | if (set) \ |
| 148 | val |= mask; \ |
| 149 | else \ |
| 150 | val &= ~mask; \ |
| 151 | } while (0) |
| 152 | |
| 153 | static inline void mcspi_write_reg(struct spi_master *master, |
| 154 | int idx, u32 val) |
| 155 | { |
| 156 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
| 157 | |
| 158 | __raw_writel(val, mcspi->base + idx); |
| 159 | } |
| 160 | |
| 161 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) |
| 162 | { |
| 163 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
| 164 | |
| 165 | return __raw_readl(mcspi->base + idx); |
| 166 | } |
| 167 | |
| 168 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, |
| 169 | int idx, u32 val) |
| 170 | { |
| 171 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 172 | |
| 173 | __raw_writel(val, cs->base + idx); |
| 174 | } |
| 175 | |
| 176 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) |
| 177 | { |
| 178 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 179 | |
| 180 | return __raw_readl(cs->base + idx); |
| 181 | } |
| 182 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 183 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) |
| 184 | { |
| 185 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 186 | |
| 187 | return cs->chconf0; |
| 188 | } |
| 189 | |
| 190 | static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) |
| 191 | { |
| 192 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 193 | |
| 194 | cs->chconf0 = val; |
| 195 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); |
Roman Tereshonkov | a330ce2 | 2010-03-15 09:06:28 +0000 | [diff] [blame] | 196 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 197 | } |
| 198 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 199 | static void omap2_mcspi_set_dma_req(const struct spi_device *spi, |
| 200 | int is_read, int enable) |
| 201 | { |
| 202 | u32 l, rw; |
| 203 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 204 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 205 | |
| 206 | if (is_read) /* 1 is read, 0 write */ |
| 207 | rw = OMAP2_MCSPI_CHCONF_DMAR; |
| 208 | else |
| 209 | rw = OMAP2_MCSPI_CHCONF_DMAW; |
| 210 | |
| 211 | MOD_REG_BIT(l, rw, enable); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 212 | mcspi_write_chconf0(spi, l); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 213 | } |
| 214 | |
| 215 | static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) |
| 216 | { |
| 217 | u32 l; |
| 218 | |
| 219 | l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0; |
| 220 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l); |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 221 | /* Flash post-writes */ |
| 222 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 223 | } |
| 224 | |
| 225 | static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) |
| 226 | { |
| 227 | u32 l; |
| 228 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 229 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 230 | MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 231 | mcspi_write_chconf0(spi, l); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 232 | } |
| 233 | |
| 234 | static void omap2_mcspi_set_master_mode(struct spi_master *master) |
| 235 | { |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame^] | 236 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
| 237 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 238 | u32 l; |
| 239 | |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame^] | 240 | /* |
| 241 | * Setup when switching from (reset default) slave mode |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 242 | * to single-channel master mode |
| 243 | */ |
| 244 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); |
| 245 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0); |
| 246 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0); |
| 247 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1); |
| 248 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 249 | |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame^] | 250 | ctx->modulctrl = l; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 251 | } |
| 252 | |
| 253 | static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) |
| 254 | { |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame^] | 255 | struct spi_master *spi_cntrl = mcspi->master; |
| 256 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
| 257 | struct omap2_mcspi_cs *cs; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 258 | |
| 259 | /* McSPI: context restore */ |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame^] | 260 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); |
| 261 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 262 | |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame^] | 263 | list_for_each_entry(cs, &ctx->cs, node) |
Tero Kristo | 89c0537 | 2009-09-22 16:46:17 -0700 | [diff] [blame] | 264 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 265 | } |
| 266 | static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi) |
| 267 | { |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 268 | pm_runtime_put_sync(mcspi->dev); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 269 | } |
| 270 | |
| 271 | static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi) |
| 272 | { |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 273 | return pm_runtime_get_sync(mcspi->dev); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 274 | } |
| 275 | |
Ilkka Koskinen | 2764c50 | 2010-10-19 17:07:31 +0300 | [diff] [blame] | 276 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
| 277 | { |
| 278 | unsigned long timeout; |
| 279 | |
| 280 | timeout = jiffies + msecs_to_jiffies(1000); |
| 281 | while (!(__raw_readl(reg) & bit)) { |
| 282 | if (time_after(jiffies, timeout)) |
| 283 | return -1; |
| 284 | cpu_relax(); |
| 285 | } |
| 286 | return 0; |
| 287 | } |
| 288 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 289 | static unsigned |
| 290 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) |
| 291 | { |
| 292 | struct omap2_mcspi *mcspi; |
| 293 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 294 | struct omap2_mcspi_dma *mcspi_dma; |
| 295 | unsigned int count, c; |
| 296 | unsigned long base, tx_reg, rx_reg; |
| 297 | int word_len, data_type, element_count; |
Govindraj.R | 8b20c8c | 2011-06-01 11:31:24 +0530 | [diff] [blame] | 298 | int elements = 0; |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 299 | u32 l; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 300 | u8 * rx; |
| 301 | const u8 * tx; |
Ilkka Koskinen | 2764c50 | 2010-10-19 17:07:31 +0300 | [diff] [blame] | 302 | void __iomem *chstat_reg; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 303 | |
| 304 | mcspi = spi_master_get_devdata(spi->master); |
| 305 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 306 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 307 | |
Ilkka Koskinen | 2764c50 | 2010-10-19 17:07:31 +0300 | [diff] [blame] | 308 | chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; |
| 309 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 310 | count = xfer->len; |
| 311 | c = count; |
| 312 | word_len = cs->word_len; |
| 313 | |
Russell King | e5480b73 | 2008-09-01 21:51:50 +0100 | [diff] [blame] | 314 | base = cs->phys; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 315 | tx_reg = base + OMAP2_MCSPI_TX0; |
| 316 | rx_reg = base + OMAP2_MCSPI_RX0; |
| 317 | rx = xfer->rx_buf; |
| 318 | tx = xfer->tx_buf; |
| 319 | |
| 320 | if (word_len <= 8) { |
| 321 | data_type = OMAP_DMA_DATA_TYPE_S8; |
| 322 | element_count = count; |
| 323 | } else if (word_len <= 16) { |
| 324 | data_type = OMAP_DMA_DATA_TYPE_S16; |
| 325 | element_count = count >> 1; |
| 326 | } else /* word_len <= 32 */ { |
| 327 | data_type = OMAP_DMA_DATA_TYPE_S32; |
| 328 | element_count = count >> 2; |
| 329 | } |
| 330 | |
| 331 | if (tx != NULL) { |
| 332 | omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel, |
| 333 | data_type, element_count, 1, |
| 334 | OMAP_DMA_SYNC_ELEMENT, |
| 335 | mcspi_dma->dma_tx_sync_dev, 0); |
| 336 | |
| 337 | omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0, |
| 338 | OMAP_DMA_AMODE_CONSTANT, |
| 339 | tx_reg, 0, 0); |
| 340 | |
| 341 | omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0, |
| 342 | OMAP_DMA_AMODE_POST_INC, |
| 343 | xfer->tx_dma, 0, 0); |
| 344 | } |
| 345 | |
| 346 | if (rx != NULL) { |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 347 | elements = element_count - 1; |
| 348 | if (l & OMAP2_MCSPI_CHCONF_TURBO) |
| 349 | elements--; |
| 350 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 351 | omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel, |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 352 | data_type, elements, 1, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 353 | OMAP_DMA_SYNC_ELEMENT, |
| 354 | mcspi_dma->dma_rx_sync_dev, 1); |
| 355 | |
| 356 | omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0, |
| 357 | OMAP_DMA_AMODE_CONSTANT, |
| 358 | rx_reg, 0, 0); |
| 359 | |
| 360 | omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0, |
| 361 | OMAP_DMA_AMODE_POST_INC, |
| 362 | xfer->rx_dma, 0, 0); |
| 363 | } |
| 364 | |
| 365 | if (tx != NULL) { |
| 366 | omap_start_dma(mcspi_dma->dma_tx_channel); |
| 367 | omap2_mcspi_set_dma_req(spi, 0, 1); |
| 368 | } |
| 369 | |
| 370 | if (rx != NULL) { |
| 371 | omap_start_dma(mcspi_dma->dma_rx_channel); |
| 372 | omap2_mcspi_set_dma_req(spi, 1, 1); |
| 373 | } |
| 374 | |
| 375 | if (tx != NULL) { |
| 376 | wait_for_completion(&mcspi_dma->dma_tx_completion); |
Russell King - ARM Linux | 07fe035 | 2011-01-07 15:49:20 +0000 | [diff] [blame] | 377 | dma_unmap_single(&spi->dev, xfer->tx_dma, count, DMA_TO_DEVICE); |
Ilkka Koskinen | 2764c50 | 2010-10-19 17:07:31 +0300 | [diff] [blame] | 378 | |
| 379 | /* for TX_ONLY mode, be sure all words have shifted out */ |
| 380 | if (rx == NULL) { |
| 381 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 382 | OMAP2_MCSPI_CHSTAT_TXS) < 0) |
| 383 | dev_err(&spi->dev, "TXS timed out\n"); |
| 384 | else if (mcspi_wait_for_reg_bit(chstat_reg, |
| 385 | OMAP2_MCSPI_CHSTAT_EOT) < 0) |
| 386 | dev_err(&spi->dev, "EOT timed out\n"); |
| 387 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 388 | } |
| 389 | |
| 390 | if (rx != NULL) { |
| 391 | wait_for_completion(&mcspi_dma->dma_rx_completion); |
Russell King - ARM Linux | 07fe035 | 2011-01-07 15:49:20 +0000 | [diff] [blame] | 392 | dma_unmap_single(&spi->dev, xfer->rx_dma, count, DMA_FROM_DEVICE); |
Eero Nurkkala | 57c5c28d | 2009-07-29 15:02:12 -0700 | [diff] [blame] | 393 | omap2_mcspi_set_enable(spi, 0); |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 394 | |
| 395 | if (l & OMAP2_MCSPI_CHCONF_TURBO) { |
| 396 | |
| 397 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
| 398 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
| 399 | u32 w; |
| 400 | |
| 401 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); |
| 402 | if (word_len <= 8) |
| 403 | ((u8 *)xfer->rx_buf)[elements++] = w; |
| 404 | else if (word_len <= 16) |
| 405 | ((u16 *)xfer->rx_buf)[elements++] = w; |
| 406 | else /* word_len <= 32 */ |
| 407 | ((u32 *)xfer->rx_buf)[elements++] = w; |
| 408 | } else { |
| 409 | dev_err(&spi->dev, |
| 410 | "DMA RX penultimate word empty"); |
| 411 | count -= (word_len <= 8) ? 2 : |
| 412 | (word_len <= 16) ? 4 : |
| 413 | /* word_len <= 32 */ 8; |
| 414 | omap2_mcspi_set_enable(spi, 1); |
| 415 | return count; |
| 416 | } |
| 417 | } |
| 418 | |
Eero Nurkkala | 57c5c28d | 2009-07-29 15:02:12 -0700 | [diff] [blame] | 419 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
| 420 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
| 421 | u32 w; |
| 422 | |
| 423 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); |
| 424 | if (word_len <= 8) |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 425 | ((u8 *)xfer->rx_buf)[elements] = w; |
Eero Nurkkala | 57c5c28d | 2009-07-29 15:02:12 -0700 | [diff] [blame] | 426 | else if (word_len <= 16) |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 427 | ((u16 *)xfer->rx_buf)[elements] = w; |
Eero Nurkkala | 57c5c28d | 2009-07-29 15:02:12 -0700 | [diff] [blame] | 428 | else /* word_len <= 32 */ |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 429 | ((u32 *)xfer->rx_buf)[elements] = w; |
Eero Nurkkala | 57c5c28d | 2009-07-29 15:02:12 -0700 | [diff] [blame] | 430 | } else { |
| 431 | dev_err(&spi->dev, "DMA RX last word empty"); |
| 432 | count -= (word_len <= 8) ? 1 : |
| 433 | (word_len <= 16) ? 2 : |
| 434 | /* word_len <= 32 */ 4; |
| 435 | } |
| 436 | omap2_mcspi_set_enable(spi, 1); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 437 | } |
| 438 | return count; |
| 439 | } |
| 440 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 441 | static unsigned |
| 442 | omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) |
| 443 | { |
| 444 | struct omap2_mcspi *mcspi; |
| 445 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 446 | unsigned int count, c; |
| 447 | u32 l; |
| 448 | void __iomem *base = cs->base; |
| 449 | void __iomem *tx_reg; |
| 450 | void __iomem *rx_reg; |
| 451 | void __iomem *chstat_reg; |
| 452 | int word_len; |
| 453 | |
| 454 | mcspi = spi_master_get_devdata(spi->master); |
| 455 | count = xfer->len; |
| 456 | c = count; |
| 457 | word_len = cs->word_len; |
| 458 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 459 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 460 | |
| 461 | /* We store the pre-calculated register addresses on stack to speed |
| 462 | * up the transfer loop. */ |
| 463 | tx_reg = base + OMAP2_MCSPI_TX0; |
| 464 | rx_reg = base + OMAP2_MCSPI_RX0; |
| 465 | chstat_reg = base + OMAP2_MCSPI_CHSTAT0; |
| 466 | |
Michael Jones | adef658 | 2011-02-25 16:55:11 +0100 | [diff] [blame] | 467 | if (c < (word_len>>3)) |
| 468 | return 0; |
| 469 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 470 | if (word_len <= 8) { |
| 471 | u8 *rx; |
| 472 | const u8 *tx; |
| 473 | |
| 474 | rx = xfer->rx_buf; |
| 475 | tx = xfer->tx_buf; |
| 476 | |
| 477 | do { |
Kalle Valo | feed9ba | 2008-01-24 14:00:40 -0800 | [diff] [blame] | 478 | c -= 1; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 479 | if (tx != NULL) { |
| 480 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 481 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
| 482 | dev_err(&spi->dev, "TXS timed out\n"); |
| 483 | goto out; |
| 484 | } |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 485 | dev_vdbg(&spi->dev, "write-%d %02x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 486 | word_len, *tx); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 487 | __raw_writel(*tx++, tx_reg); |
| 488 | } |
| 489 | if (rx != NULL) { |
| 490 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 491 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 492 | dev_err(&spi->dev, "RXS timed out\n"); |
| 493 | goto out; |
| 494 | } |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 495 | |
| 496 | if (c == 1 && tx == NULL && |
| 497 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { |
| 498 | omap2_mcspi_set_enable(spi, 0); |
| 499 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 500 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 501 | word_len, *(rx - 1)); |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 502 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 503 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 504 | dev_err(&spi->dev, |
| 505 | "RXS timed out\n"); |
| 506 | goto out; |
| 507 | } |
| 508 | c = 0; |
| 509 | } else if (c == 0 && tx == NULL) { |
| 510 | omap2_mcspi_set_enable(spi, 0); |
| 511 | } |
| 512 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 513 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 514 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 515 | word_len, *(rx - 1)); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 516 | } |
Jarkko Nikula | 95c5c3a | 2011-03-21 16:27:30 +0200 | [diff] [blame] | 517 | } while (c); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 518 | } else if (word_len <= 16) { |
| 519 | u16 *rx; |
| 520 | const u16 *tx; |
| 521 | |
| 522 | rx = xfer->rx_buf; |
| 523 | tx = xfer->tx_buf; |
| 524 | do { |
Kalle Valo | feed9ba | 2008-01-24 14:00:40 -0800 | [diff] [blame] | 525 | c -= 2; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 526 | if (tx != NULL) { |
| 527 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 528 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
| 529 | dev_err(&spi->dev, "TXS timed out\n"); |
| 530 | goto out; |
| 531 | } |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 532 | dev_vdbg(&spi->dev, "write-%d %04x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 533 | word_len, *tx); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 534 | __raw_writel(*tx++, tx_reg); |
| 535 | } |
| 536 | if (rx != NULL) { |
| 537 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 538 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 539 | dev_err(&spi->dev, "RXS timed out\n"); |
| 540 | goto out; |
| 541 | } |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 542 | |
| 543 | if (c == 2 && tx == NULL && |
| 544 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { |
| 545 | omap2_mcspi_set_enable(spi, 0); |
| 546 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 547 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 548 | word_len, *(rx - 1)); |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 549 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 550 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 551 | dev_err(&spi->dev, |
| 552 | "RXS timed out\n"); |
| 553 | goto out; |
| 554 | } |
| 555 | c = 0; |
| 556 | } else if (c == 0 && tx == NULL) { |
| 557 | omap2_mcspi_set_enable(spi, 0); |
| 558 | } |
| 559 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 560 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 561 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 562 | word_len, *(rx - 1)); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 563 | } |
Jarkko Nikula | 95c5c3a | 2011-03-21 16:27:30 +0200 | [diff] [blame] | 564 | } while (c >= 2); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 565 | } else if (word_len <= 32) { |
| 566 | u32 *rx; |
| 567 | const u32 *tx; |
| 568 | |
| 569 | rx = xfer->rx_buf; |
| 570 | tx = xfer->tx_buf; |
| 571 | do { |
Kalle Valo | feed9ba | 2008-01-24 14:00:40 -0800 | [diff] [blame] | 572 | c -= 4; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 573 | if (tx != NULL) { |
| 574 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 575 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
| 576 | dev_err(&spi->dev, "TXS timed out\n"); |
| 577 | goto out; |
| 578 | } |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 579 | dev_vdbg(&spi->dev, "write-%d %08x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 580 | word_len, *tx); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 581 | __raw_writel(*tx++, tx_reg); |
| 582 | } |
| 583 | if (rx != NULL) { |
| 584 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 585 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 586 | dev_err(&spi->dev, "RXS timed out\n"); |
| 587 | goto out; |
| 588 | } |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 589 | |
| 590 | if (c == 4 && tx == NULL && |
| 591 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { |
| 592 | omap2_mcspi_set_enable(spi, 0); |
| 593 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 594 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 595 | word_len, *(rx - 1)); |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 596 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 597 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 598 | dev_err(&spi->dev, |
| 599 | "RXS timed out\n"); |
| 600 | goto out; |
| 601 | } |
| 602 | c = 0; |
| 603 | } else if (c == 0 && tx == NULL) { |
| 604 | omap2_mcspi_set_enable(spi, 0); |
| 605 | } |
| 606 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 607 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 608 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 609 | word_len, *(rx - 1)); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 610 | } |
Jarkko Nikula | 95c5c3a | 2011-03-21 16:27:30 +0200 | [diff] [blame] | 611 | } while (c >= 4); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 612 | } |
| 613 | |
| 614 | /* for TX_ONLY mode, be sure all words have shifted out */ |
| 615 | if (xfer->rx_buf == NULL) { |
| 616 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 617 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
| 618 | dev_err(&spi->dev, "TXS timed out\n"); |
| 619 | } else if (mcspi_wait_for_reg_bit(chstat_reg, |
| 620 | OMAP2_MCSPI_CHSTAT_EOT) < 0) |
| 621 | dev_err(&spi->dev, "EOT timed out\n"); |
Jason Wang | e1993ed | 2010-10-19 18:03:27 +0800 | [diff] [blame] | 622 | |
| 623 | /* disable chan to purge rx datas received in TX_ONLY transfer, |
| 624 | * otherwise these rx datas will affect the direct following |
| 625 | * RX_ONLY transfer. |
| 626 | */ |
| 627 | omap2_mcspi_set_enable(spi, 0); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 628 | } |
| 629 | out: |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 630 | omap2_mcspi_set_enable(spi, 1); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 631 | return count - c; |
| 632 | } |
| 633 | |
Hannu Heikkinen | 57d9c10 | 2011-02-24 21:31:33 +0200 | [diff] [blame] | 634 | static u32 omap2_mcspi_calc_divisor(u32 speed_hz) |
| 635 | { |
| 636 | u32 div; |
| 637 | |
| 638 | for (div = 0; div < 15; div++) |
| 639 | if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) |
| 640 | return div; |
| 641 | |
| 642 | return 15; |
| 643 | } |
| 644 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 645 | /* called only when no transfer is active to this device */ |
| 646 | static int omap2_mcspi_setup_transfer(struct spi_device *spi, |
| 647 | struct spi_transfer *t) |
| 648 | { |
| 649 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 650 | struct omap2_mcspi *mcspi; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 651 | struct spi_master *spi_cntrl; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 652 | u32 l = 0, div = 0; |
| 653 | u8 word_len = spi->bits_per_word; |
Scott Ellis | 9bd4517 | 2010-03-10 14:23:13 -0700 | [diff] [blame] | 654 | u32 speed_hz = spi->max_speed_hz; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 655 | |
| 656 | mcspi = spi_master_get_devdata(spi->master); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 657 | spi_cntrl = mcspi->master; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 658 | |
| 659 | if (t != NULL && t->bits_per_word) |
| 660 | word_len = t->bits_per_word; |
| 661 | |
| 662 | cs->word_len = word_len; |
| 663 | |
Scott Ellis | 9bd4517 | 2010-03-10 14:23:13 -0700 | [diff] [blame] | 664 | if (t && t->speed_hz) |
| 665 | speed_hz = t->speed_hz; |
| 666 | |
Hannu Heikkinen | 57d9c10 | 2011-02-24 21:31:33 +0200 | [diff] [blame] | 667 | speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); |
| 668 | div = omap2_mcspi_calc_divisor(speed_hz); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 669 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 670 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 671 | |
| 672 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS |
| 673 | * REVISIT: this controller could support SPI_3WIRE mode. |
| 674 | */ |
| 675 | l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1); |
| 676 | l |= OMAP2_MCSPI_CHCONF_DPE0; |
| 677 | |
| 678 | /* wordlength */ |
| 679 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; |
| 680 | l |= (word_len - 1) << 7; |
| 681 | |
| 682 | /* set chipselect polarity; manage with FORCE */ |
| 683 | if (!(spi->mode & SPI_CS_HIGH)) |
| 684 | l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ |
| 685 | else |
| 686 | l &= ~OMAP2_MCSPI_CHCONF_EPOL; |
| 687 | |
| 688 | /* set clock divisor */ |
| 689 | l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; |
| 690 | l |= div << 2; |
| 691 | |
| 692 | /* set SPI mode 0..3 */ |
| 693 | if (spi->mode & SPI_CPOL) |
| 694 | l |= OMAP2_MCSPI_CHCONF_POL; |
| 695 | else |
| 696 | l &= ~OMAP2_MCSPI_CHCONF_POL; |
| 697 | if (spi->mode & SPI_CPHA) |
| 698 | l |= OMAP2_MCSPI_CHCONF_PHA; |
| 699 | else |
| 700 | l &= ~OMAP2_MCSPI_CHCONF_PHA; |
| 701 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 702 | mcspi_write_chconf0(spi, l); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 703 | |
| 704 | dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", |
Hannu Heikkinen | 57d9c10 | 2011-02-24 21:31:33 +0200 | [diff] [blame] | 705 | OMAP2_MCSPI_MAX_FREQ >> div, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 706 | (spi->mode & SPI_CPHA) ? "trailing" : "leading", |
| 707 | (spi->mode & SPI_CPOL) ? "inverted" : "normal"); |
| 708 | |
| 709 | return 0; |
| 710 | } |
| 711 | |
| 712 | static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data) |
| 713 | { |
| 714 | struct spi_device *spi = data; |
| 715 | struct omap2_mcspi *mcspi; |
| 716 | struct omap2_mcspi_dma *mcspi_dma; |
| 717 | |
| 718 | mcspi = spi_master_get_devdata(spi->master); |
| 719 | mcspi_dma = &(mcspi->dma_channels[spi->chip_select]); |
| 720 | |
| 721 | complete(&mcspi_dma->dma_rx_completion); |
| 722 | |
| 723 | /* We must disable the DMA RX request */ |
| 724 | omap2_mcspi_set_dma_req(spi, 1, 0); |
| 725 | } |
| 726 | |
| 727 | static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data) |
| 728 | { |
| 729 | struct spi_device *spi = data; |
| 730 | struct omap2_mcspi *mcspi; |
| 731 | struct omap2_mcspi_dma *mcspi_dma; |
| 732 | |
| 733 | mcspi = spi_master_get_devdata(spi->master); |
| 734 | mcspi_dma = &(mcspi->dma_channels[spi->chip_select]); |
| 735 | |
| 736 | complete(&mcspi_dma->dma_tx_completion); |
| 737 | |
| 738 | /* We must disable the DMA TX request */ |
| 739 | omap2_mcspi_set_dma_req(spi, 0, 0); |
| 740 | } |
| 741 | |
| 742 | static int omap2_mcspi_request_dma(struct spi_device *spi) |
| 743 | { |
| 744 | struct spi_master *master = spi->master; |
| 745 | struct omap2_mcspi *mcspi; |
| 746 | struct omap2_mcspi_dma *mcspi_dma; |
| 747 | |
| 748 | mcspi = spi_master_get_devdata(master); |
| 749 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
| 750 | |
| 751 | if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX", |
| 752 | omap2_mcspi_dma_rx_callback, spi, |
| 753 | &mcspi_dma->dma_rx_channel)) { |
| 754 | dev_err(&spi->dev, "no RX DMA channel for McSPI\n"); |
| 755 | return -EAGAIN; |
| 756 | } |
| 757 | |
| 758 | if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX", |
| 759 | omap2_mcspi_dma_tx_callback, spi, |
| 760 | &mcspi_dma->dma_tx_channel)) { |
| 761 | omap_free_dma(mcspi_dma->dma_rx_channel); |
| 762 | mcspi_dma->dma_rx_channel = -1; |
| 763 | dev_err(&spi->dev, "no TX DMA channel for McSPI\n"); |
| 764 | return -EAGAIN; |
| 765 | } |
| 766 | |
| 767 | init_completion(&mcspi_dma->dma_rx_completion); |
| 768 | init_completion(&mcspi_dma->dma_tx_completion); |
| 769 | |
| 770 | return 0; |
| 771 | } |
| 772 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 773 | static int omap2_mcspi_setup(struct spi_device *spi) |
| 774 | { |
| 775 | int ret; |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame^] | 776 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
| 777 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 778 | struct omap2_mcspi_dma *mcspi_dma; |
| 779 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 780 | |
David Brownell | 7d07719 | 2009-06-17 16:26:03 -0700 | [diff] [blame] | 781 | if (spi->bits_per_word < 4 || spi->bits_per_word > 32) { |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 782 | dev_dbg(&spi->dev, "setup: unsupported %d bit words\n", |
| 783 | spi->bits_per_word); |
| 784 | return -EINVAL; |
| 785 | } |
| 786 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 787 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
| 788 | |
| 789 | if (!cs) { |
Shubhrajyoti D | 1a77b12 | 2012-03-17 12:44:01 +0530 | [diff] [blame] | 790 | cs = devm_kzalloc(&spi->dev , sizeof *cs, GFP_KERNEL); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 791 | if (!cs) |
| 792 | return -ENOMEM; |
| 793 | cs->base = mcspi->base + spi->chip_select * 0x14; |
Russell King | e5480b73 | 2008-09-01 21:51:50 +0100 | [diff] [blame] | 794 | cs->phys = mcspi->phys + spi->chip_select * 0x14; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 795 | cs->chconf0 = 0; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 796 | spi->controller_state = cs; |
Tero Kristo | 89c0537 | 2009-09-22 16:46:17 -0700 | [diff] [blame] | 797 | /* Link this to context save list */ |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame^] | 798 | list_add_tail(&cs->node, &ctx->cs); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 799 | } |
| 800 | |
| 801 | if (mcspi_dma->dma_rx_channel == -1 |
| 802 | || mcspi_dma->dma_tx_channel == -1) { |
| 803 | ret = omap2_mcspi_request_dma(spi); |
| 804 | if (ret < 0) |
| 805 | return ret; |
| 806 | } |
| 807 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 808 | ret = omap2_mcspi_enable_clocks(mcspi); |
| 809 | if (ret < 0) |
| 810 | return ret; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 811 | |
Kyungmin Park | 86eeb6f | 2007-10-16 01:27:45 -0700 | [diff] [blame] | 812 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 813 | omap2_mcspi_disable_clocks(mcspi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 814 | |
| 815 | return ret; |
| 816 | } |
| 817 | |
| 818 | static void omap2_mcspi_cleanup(struct spi_device *spi) |
| 819 | { |
| 820 | struct omap2_mcspi *mcspi; |
| 821 | struct omap2_mcspi_dma *mcspi_dma; |
Tero Kristo | 89c0537 | 2009-09-22 16:46:17 -0700 | [diff] [blame] | 822 | struct omap2_mcspi_cs *cs; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 823 | |
| 824 | mcspi = spi_master_get_devdata(spi->master); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 825 | |
Scott Ellis | 5e77494 | 2010-03-10 14:22:45 -0700 | [diff] [blame] | 826 | if (spi->controller_state) { |
| 827 | /* Unlink controller state from context save list */ |
| 828 | cs = spi->controller_state; |
| 829 | list_del(&cs->node); |
Tero Kristo | 89c0537 | 2009-09-22 16:46:17 -0700 | [diff] [blame] | 830 | |
Scott Ellis | 5e77494 | 2010-03-10 14:22:45 -0700 | [diff] [blame] | 831 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 832 | |
Scott Ellis | 99f1a43 | 2010-05-24 14:20:27 +0000 | [diff] [blame] | 833 | if (spi->chip_select < spi->master->num_chipselect) { |
| 834 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
| 835 | |
| 836 | if (mcspi_dma->dma_rx_channel != -1) { |
| 837 | omap_free_dma(mcspi_dma->dma_rx_channel); |
| 838 | mcspi_dma->dma_rx_channel = -1; |
| 839 | } |
| 840 | if (mcspi_dma->dma_tx_channel != -1) { |
| 841 | omap_free_dma(mcspi_dma->dma_tx_channel); |
| 842 | mcspi_dma->dma_tx_channel = -1; |
| 843 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 844 | } |
| 845 | } |
| 846 | |
| 847 | static void omap2_mcspi_work(struct work_struct *work) |
| 848 | { |
| 849 | struct omap2_mcspi *mcspi; |
| 850 | |
| 851 | mcspi = container_of(work, struct omap2_mcspi, work); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 852 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 853 | if (omap2_mcspi_enable_clocks(mcspi) < 0) |
| 854 | return; |
| 855 | |
| 856 | spin_lock_irq(&mcspi->lock); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 857 | |
| 858 | /* We only enable one channel at a time -- the one whose message is |
| 859 | * at the head of the queue -- although this controller would gladly |
| 860 | * arbitrate among multiple channels. This corresponds to "single |
| 861 | * channel" master mode. As a side effect, we need to manage the |
| 862 | * chipselect with the FORCE bit ... CS != channel enable. |
| 863 | */ |
| 864 | while (!list_empty(&mcspi->msg_queue)) { |
| 865 | struct spi_message *m; |
| 866 | struct spi_device *spi; |
| 867 | struct spi_transfer *t = NULL; |
| 868 | int cs_active = 0; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 869 | struct omap2_mcspi_cs *cs; |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 870 | struct omap2_mcspi_device_config *cd; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 871 | int par_override = 0; |
| 872 | int status = 0; |
| 873 | u32 chconf; |
| 874 | |
| 875 | m = container_of(mcspi->msg_queue.next, struct spi_message, |
| 876 | queue); |
| 877 | |
| 878 | list_del_init(&m->queue); |
| 879 | spin_unlock_irq(&mcspi->lock); |
| 880 | |
| 881 | spi = m->spi; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 882 | cs = spi->controller_state; |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 883 | cd = spi->controller_data; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 884 | |
| 885 | omap2_mcspi_set_enable(spi, 1); |
| 886 | list_for_each_entry(t, &m->transfers, transfer_list) { |
| 887 | if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { |
| 888 | status = -EINVAL; |
| 889 | break; |
| 890 | } |
| 891 | if (par_override || t->speed_hz || t->bits_per_word) { |
| 892 | par_override = 1; |
| 893 | status = omap2_mcspi_setup_transfer(spi, t); |
| 894 | if (status < 0) |
| 895 | break; |
| 896 | if (!t->speed_hz && !t->bits_per_word) |
| 897 | par_override = 0; |
| 898 | } |
| 899 | |
| 900 | if (!cs_active) { |
| 901 | omap2_mcspi_force_cs(spi, 1); |
| 902 | cs_active = 1; |
| 903 | } |
| 904 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 905 | chconf = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 906 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 907 | chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; |
| 908 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 909 | if (t->tx_buf == NULL) |
| 910 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; |
| 911 | else if (t->rx_buf == NULL) |
| 912 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 913 | |
| 914 | if (cd && cd->turbo_mode && t->tx_buf == NULL) { |
| 915 | /* Turbo mode is for more than one word */ |
| 916 | if (t->len > ((cs->word_len + 7) >> 3)) |
| 917 | chconf |= OMAP2_MCSPI_CHCONF_TURBO; |
| 918 | } |
| 919 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 920 | mcspi_write_chconf0(spi, chconf); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 921 | |
| 922 | if (t->len) { |
| 923 | unsigned count; |
| 924 | |
| 925 | /* RX_ONLY mode needs dummy data in TX reg */ |
| 926 | if (t->tx_buf == NULL) |
| 927 | __raw_writel(0, cs->base |
| 928 | + OMAP2_MCSPI_TX0); |
| 929 | |
| 930 | if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES) |
| 931 | count = omap2_mcspi_txrx_dma(spi, t); |
| 932 | else |
| 933 | count = omap2_mcspi_txrx_pio(spi, t); |
| 934 | m->actual_length += count; |
| 935 | |
| 936 | if (count != t->len) { |
| 937 | status = -EIO; |
| 938 | break; |
| 939 | } |
| 940 | } |
| 941 | |
| 942 | if (t->delay_usecs) |
| 943 | udelay(t->delay_usecs); |
| 944 | |
| 945 | /* ignore the "leave it on after last xfer" hint */ |
| 946 | if (t->cs_change) { |
| 947 | omap2_mcspi_force_cs(spi, 0); |
| 948 | cs_active = 0; |
| 949 | } |
| 950 | } |
| 951 | |
| 952 | /* Restore defaults if they were overriden */ |
| 953 | if (par_override) { |
| 954 | par_override = 0; |
| 955 | status = omap2_mcspi_setup_transfer(spi, NULL); |
| 956 | } |
| 957 | |
| 958 | if (cs_active) |
| 959 | omap2_mcspi_force_cs(spi, 0); |
| 960 | |
| 961 | omap2_mcspi_set_enable(spi, 0); |
| 962 | |
| 963 | m->status = status; |
| 964 | m->complete(m->context); |
| 965 | |
| 966 | spin_lock_irq(&mcspi->lock); |
| 967 | } |
| 968 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 969 | spin_unlock_irq(&mcspi->lock); |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 970 | |
| 971 | omap2_mcspi_disable_clocks(mcspi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 972 | } |
| 973 | |
| 974 | static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m) |
| 975 | { |
| 976 | struct omap2_mcspi *mcspi; |
| 977 | unsigned long flags; |
| 978 | struct spi_transfer *t; |
| 979 | |
| 980 | m->actual_length = 0; |
| 981 | m->status = 0; |
| 982 | |
| 983 | /* reject invalid messages and transfers */ |
| 984 | if (list_empty(&m->transfers) || !m->complete) |
| 985 | return -EINVAL; |
| 986 | list_for_each_entry(t, &m->transfers, transfer_list) { |
| 987 | const void *tx_buf = t->tx_buf; |
| 988 | void *rx_buf = t->rx_buf; |
| 989 | unsigned len = t->len; |
| 990 | |
| 991 | if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ |
| 992 | || (len && !(rx_buf || tx_buf)) |
| 993 | || (t->bits_per_word && |
| 994 | ( t->bits_per_word < 4 |
| 995 | || t->bits_per_word > 32))) { |
| 996 | dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", |
| 997 | t->speed_hz, |
| 998 | len, |
| 999 | tx_buf ? "tx" : "", |
| 1000 | rx_buf ? "rx" : "", |
| 1001 | t->bits_per_word); |
| 1002 | return -EINVAL; |
| 1003 | } |
Hannu Heikkinen | 57d9c10 | 2011-02-24 21:31:33 +0200 | [diff] [blame] | 1004 | if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) { |
| 1005 | dev_dbg(&spi->dev, "speed_hz %d below minimum %d Hz\n", |
| 1006 | t->speed_hz, |
| 1007 | OMAP2_MCSPI_MAX_FREQ >> 15); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1008 | return -EINVAL; |
| 1009 | } |
| 1010 | |
| 1011 | if (m->is_dma_mapped || len < DMA_MIN_BYTES) |
| 1012 | continue; |
| 1013 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1014 | if (tx_buf != NULL) { |
| 1015 | t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf, |
| 1016 | len, DMA_TO_DEVICE); |
FUJITA Tomonori | 8d8bb39 | 2008-07-25 19:44:49 -0700 | [diff] [blame] | 1017 | if (dma_mapping_error(&spi->dev, t->tx_dma)) { |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1018 | dev_dbg(&spi->dev, "dma %cX %d bytes error\n", |
| 1019 | 'T', len); |
| 1020 | return -EINVAL; |
| 1021 | } |
| 1022 | } |
| 1023 | if (rx_buf != NULL) { |
| 1024 | t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len, |
| 1025 | DMA_FROM_DEVICE); |
FUJITA Tomonori | 8d8bb39 | 2008-07-25 19:44:49 -0700 | [diff] [blame] | 1026 | if (dma_mapping_error(&spi->dev, t->rx_dma)) { |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1027 | dev_dbg(&spi->dev, "dma %cX %d bytes error\n", |
| 1028 | 'R', len); |
| 1029 | if (tx_buf != NULL) |
Russell King - ARM Linux | 07fe035 | 2011-01-07 15:49:20 +0000 | [diff] [blame] | 1030 | dma_unmap_single(&spi->dev, t->tx_dma, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1031 | len, DMA_TO_DEVICE); |
| 1032 | return -EINVAL; |
| 1033 | } |
| 1034 | } |
| 1035 | } |
| 1036 | |
| 1037 | mcspi = spi_master_get_devdata(spi->master); |
| 1038 | |
| 1039 | spin_lock_irqsave(&mcspi->lock, flags); |
| 1040 | list_add_tail(&m->queue, &mcspi->msg_queue); |
Shubhrajyoti D | 2856ac1 | 2011-10-28 17:14:17 +0530 | [diff] [blame] | 1041 | queue_work(mcspi->wq, &mcspi->work); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1042 | spin_unlock_irqrestore(&mcspi->lock, flags); |
| 1043 | |
| 1044 | return 0; |
| 1045 | } |
| 1046 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1047 | static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1048 | { |
| 1049 | struct spi_master *master = mcspi->master; |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame^] | 1050 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1051 | u32 tmp; |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame^] | 1052 | int ret = 0; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1053 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1054 | ret = omap2_mcspi_enable_clocks(mcspi); |
| 1055 | if (ret < 0) |
| 1056 | return ret; |
Jouni Hogander | ddb2219 | 2009-07-29 15:02:11 -0700 | [diff] [blame] | 1057 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 1058 | tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN; |
| 1059 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp); |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame^] | 1060 | ctx->wakeupenable = tmp; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1061 | |
| 1062 | omap2_mcspi_set_master_mode(master); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 1063 | omap2_mcspi_disable_clocks(mcspi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1064 | return 0; |
| 1065 | } |
| 1066 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1067 | static int omap_mcspi_runtime_resume(struct device *dev) |
| 1068 | { |
| 1069 | struct omap2_mcspi *mcspi; |
| 1070 | struct spi_master *master; |
| 1071 | |
| 1072 | master = dev_get_drvdata(dev); |
| 1073 | mcspi = spi_master_get_devdata(master); |
| 1074 | omap2_mcspi_restore_ctx(mcspi); |
| 1075 | |
| 1076 | return 0; |
| 1077 | } |
| 1078 | |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1079 | static struct omap2_mcspi_platform_config omap2_pdata = { |
| 1080 | .regs_offset = 0, |
| 1081 | }; |
| 1082 | |
| 1083 | static struct omap2_mcspi_platform_config omap4_pdata = { |
| 1084 | .regs_offset = OMAP4_MCSPI_REG_OFFSET, |
| 1085 | }; |
| 1086 | |
| 1087 | static const struct of_device_id omap_mcspi_of_match[] = { |
| 1088 | { |
| 1089 | .compatible = "ti,omap2-mcspi", |
| 1090 | .data = &omap2_pdata, |
| 1091 | }, |
| 1092 | { |
| 1093 | .compatible = "ti,omap4-mcspi", |
| 1094 | .data = &omap4_pdata, |
| 1095 | }, |
| 1096 | { }, |
| 1097 | }; |
| 1098 | MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); |
Girish | ccc7bae | 2008-02-06 01:38:16 -0800 | [diff] [blame] | 1099 | |
Felipe Balbi | 7d6b6d8 | 2012-03-14 11:18:30 +0200 | [diff] [blame] | 1100 | static int __devinit omap2_mcspi_probe(struct platform_device *pdev) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1101 | { |
| 1102 | struct spi_master *master; |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1103 | struct omap2_mcspi_platform_config *pdata; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1104 | struct omap2_mcspi *mcspi; |
| 1105 | struct resource *r; |
| 1106 | int status = 0, i; |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1107 | u32 regs_offset = 0; |
| 1108 | static int bus_num = 1; |
| 1109 | struct device_node *node = pdev->dev.of_node; |
| 1110 | const struct of_device_id *match; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1111 | |
| 1112 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); |
| 1113 | if (master == NULL) { |
| 1114 | dev_dbg(&pdev->dev, "master allocation failed\n"); |
| 1115 | return -ENOMEM; |
| 1116 | } |
| 1117 | |
David Brownell | e7db06b | 2009-06-17 16:26:04 -0700 | [diff] [blame] | 1118 | /* the spi->mode bits understood by this driver: */ |
| 1119 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
| 1120 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1121 | master->setup = omap2_mcspi_setup; |
| 1122 | master->transfer = omap2_mcspi_transfer; |
| 1123 | master->cleanup = omap2_mcspi_cleanup; |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1124 | master->dev.of_node = node; |
| 1125 | |
| 1126 | match = of_match_device(omap_mcspi_of_match, &pdev->dev); |
| 1127 | if (match) { |
| 1128 | u32 num_cs = 1; /* default number of chipselect */ |
| 1129 | pdata = match->data; |
| 1130 | |
| 1131 | of_property_read_u32(node, "ti,spi-num-cs", &num_cs); |
| 1132 | master->num_chipselect = num_cs; |
| 1133 | master->bus_num = bus_num++; |
| 1134 | } else { |
| 1135 | pdata = pdev->dev.platform_data; |
| 1136 | master->num_chipselect = pdata->num_cs; |
| 1137 | if (pdev->id != -1) |
| 1138 | master->bus_num = pdev->id; |
| 1139 | } |
| 1140 | regs_offset = pdata->regs_offset; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1141 | |
| 1142 | dev_set_drvdata(&pdev->dev, master); |
| 1143 | |
| 1144 | mcspi = spi_master_get_devdata(master); |
| 1145 | mcspi->master = master; |
| 1146 | |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame^] | 1147 | mcspi->wq = alloc_workqueue(dev_name(&pdev->dev), WQ_MEM_RECLAIM, 1); |
Shubhrajyoti D | 2856ac1 | 2011-10-28 17:14:17 +0530 | [diff] [blame] | 1148 | if (mcspi->wq == NULL) { |
| 1149 | status = -ENOMEM; |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1150 | goto free_master; |
Shubhrajyoti D | 2856ac1 | 2011-10-28 17:14:17 +0530 | [diff] [blame] | 1151 | } |
| 1152 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1153 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1154 | if (r == NULL) { |
| 1155 | status = -ENODEV; |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1156 | goto free_master; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1157 | } |
Shubhrajyoti D | 1458d16 | 2011-10-24 15:54:24 +0530 | [diff] [blame] | 1158 | |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1159 | r->start += regs_offset; |
| 1160 | r->end += regs_offset; |
Shubhrajyoti D | 1458d16 | 2011-10-24 15:54:24 +0530 | [diff] [blame] | 1161 | mcspi->phys = r->start; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1162 | |
Shubhrajyoti D | 1a77b12 | 2012-03-17 12:44:01 +0530 | [diff] [blame] | 1163 | mcspi->base = devm_request_and_ioremap(&pdev->dev, r); |
Russell King | 55c381e | 2008-09-04 14:07:22 +0100 | [diff] [blame] | 1164 | if (!mcspi->base) { |
| 1165 | dev_dbg(&pdev->dev, "can't ioremap MCSPI\n"); |
| 1166 | status = -ENOMEM; |
Shubhrajyoti D | 1a77b12 | 2012-03-17 12:44:01 +0530 | [diff] [blame] | 1167 | goto free_master; |
Russell King | 55c381e | 2008-09-04 14:07:22 +0100 | [diff] [blame] | 1168 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1169 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1170 | mcspi->dev = &pdev->dev; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1171 | INIT_WORK(&mcspi->work, omap2_mcspi_work); |
| 1172 | |
| 1173 | spin_lock_init(&mcspi->lock); |
| 1174 | INIT_LIST_HEAD(&mcspi->msg_queue); |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame^] | 1175 | INIT_LIST_HEAD(&mcspi->ctx.cs); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1176 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1177 | mcspi->dma_channels = kcalloc(master->num_chipselect, |
| 1178 | sizeof(struct omap2_mcspi_dma), |
| 1179 | GFP_KERNEL); |
| 1180 | |
| 1181 | if (mcspi->dma_channels == NULL) |
Shubhrajyoti D | 1a77b12 | 2012-03-17 12:44:01 +0530 | [diff] [blame] | 1182 | goto free_master; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1183 | |
Charulatha V | 1a5d819 | 2011-02-02 17:52:14 +0530 | [diff] [blame] | 1184 | for (i = 0; i < master->num_chipselect; i++) { |
| 1185 | char dma_ch_name[14]; |
| 1186 | struct resource *dma_res; |
| 1187 | |
| 1188 | sprintf(dma_ch_name, "rx%d", i); |
| 1189 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, |
| 1190 | dma_ch_name); |
| 1191 | if (!dma_res) { |
| 1192 | dev_dbg(&pdev->dev, "cannot get DMA RX channel\n"); |
| 1193 | status = -ENODEV; |
| 1194 | break; |
| 1195 | } |
| 1196 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1197 | mcspi->dma_channels[i].dma_rx_channel = -1; |
Charulatha V | 1a5d819 | 2011-02-02 17:52:14 +0530 | [diff] [blame] | 1198 | mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start; |
| 1199 | sprintf(dma_ch_name, "tx%d", i); |
| 1200 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, |
| 1201 | dma_ch_name); |
| 1202 | if (!dma_res) { |
| 1203 | dev_dbg(&pdev->dev, "cannot get DMA TX channel\n"); |
| 1204 | status = -ENODEV; |
| 1205 | break; |
| 1206 | } |
| 1207 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1208 | mcspi->dma_channels[i].dma_tx_channel = -1; |
Charulatha V | 1a5d819 | 2011-02-02 17:52:14 +0530 | [diff] [blame] | 1209 | mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1210 | } |
| 1211 | |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1212 | if (status < 0) |
| 1213 | goto dma_chnl_free; |
| 1214 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1215 | pm_runtime_enable(&pdev->dev); |
| 1216 | |
| 1217 | if (status || omap2_mcspi_master_setup(mcspi) < 0) |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1218 | goto disable_pm; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1219 | |
| 1220 | status = spi_register_master(master); |
| 1221 | if (status < 0) |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1222 | goto err_spi_register; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1223 | |
| 1224 | return status; |
| 1225 | |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1226 | err_spi_register: |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1227 | spi_master_put(master); |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1228 | disable_pm: |
Shubhrajyoti D | 751c925 | 2011-10-28 17:14:18 +0530 | [diff] [blame] | 1229 | pm_runtime_disable(&pdev->dev); |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1230 | dma_chnl_free: |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1231 | kfree(mcspi->dma_channels); |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1232 | free_master: |
| 1233 | kfree(master); |
| 1234 | platform_set_drvdata(pdev, NULL); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1235 | return status; |
| 1236 | } |
| 1237 | |
Felipe Balbi | 7d6b6d8 | 2012-03-14 11:18:30 +0200 | [diff] [blame] | 1238 | static int __devexit omap2_mcspi_remove(struct platform_device *pdev) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1239 | { |
| 1240 | struct spi_master *master; |
| 1241 | struct omap2_mcspi *mcspi; |
| 1242 | struct omap2_mcspi_dma *dma_channels; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1243 | |
| 1244 | master = dev_get_drvdata(&pdev->dev); |
| 1245 | mcspi = spi_master_get_devdata(master); |
| 1246 | dma_channels = mcspi->dma_channels; |
| 1247 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1248 | omap2_mcspi_disable_clocks(mcspi); |
Shubhrajyoti D | 751c925 | 2011-10-28 17:14:18 +0530 | [diff] [blame] | 1249 | pm_runtime_disable(&pdev->dev); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1250 | |
| 1251 | spi_unregister_master(master); |
| 1252 | kfree(dma_channels); |
Shubhrajyoti D | 2856ac1 | 2011-10-28 17:14:17 +0530 | [diff] [blame] | 1253 | destroy_workqueue(mcspi->wq); |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1254 | platform_set_drvdata(pdev, NULL); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1255 | |
| 1256 | return 0; |
| 1257 | } |
| 1258 | |
Kay Sievers | 7e38c3c | 2008-04-10 21:29:20 -0700 | [diff] [blame] | 1259 | /* work with hotplug and coldplug */ |
| 1260 | MODULE_ALIAS("platform:omap2_mcspi"); |
| 1261 | |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1262 | #ifdef CONFIG_SUSPEND |
| 1263 | /* |
| 1264 | * When SPI wake up from off-mode, CS is in activate state. If it was in |
| 1265 | * unactive state when driver was suspend, then force it to unactive state at |
| 1266 | * wake up. |
| 1267 | */ |
| 1268 | static int omap2_mcspi_resume(struct device *dev) |
| 1269 | { |
| 1270 | struct spi_master *master = dev_get_drvdata(dev); |
| 1271 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame^] | 1272 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
| 1273 | struct omap2_mcspi_cs *cs; |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1274 | |
| 1275 | omap2_mcspi_enable_clocks(mcspi); |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame^] | 1276 | list_for_each_entry(cs, &ctx->cs, node) { |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1277 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1278 | /* |
| 1279 | * We need to toggle CS state for OMAP take this |
| 1280 | * change in account. |
| 1281 | */ |
| 1282 | MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 1); |
| 1283 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
| 1284 | MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 0); |
| 1285 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
| 1286 | } |
| 1287 | } |
| 1288 | omap2_mcspi_disable_clocks(mcspi); |
| 1289 | return 0; |
| 1290 | } |
| 1291 | #else |
| 1292 | #define omap2_mcspi_resume NULL |
| 1293 | #endif |
| 1294 | |
| 1295 | static const struct dev_pm_ops omap2_mcspi_pm_ops = { |
| 1296 | .resume = omap2_mcspi_resume, |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1297 | .runtime_resume = omap_mcspi_runtime_resume, |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1298 | }; |
| 1299 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1300 | static struct platform_driver omap2_mcspi_driver = { |
| 1301 | .driver = { |
| 1302 | .name = "omap2_mcspi", |
| 1303 | .owner = THIS_MODULE, |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1304 | .pm = &omap2_mcspi_pm_ops, |
| 1305 | .of_match_table = omap_mcspi_of_match, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1306 | }, |
Felipe Balbi | 7d6b6d8 | 2012-03-14 11:18:30 +0200 | [diff] [blame] | 1307 | .probe = omap2_mcspi_probe, |
| 1308 | .remove = __devexit_p(omap2_mcspi_remove), |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1309 | }; |
| 1310 | |
Felipe Balbi | 9fdca9d | 2012-03-14 11:18:31 +0200 | [diff] [blame] | 1311 | module_platform_driver(omap2_mcspi_driver); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1312 | MODULE_LICENSE("GPL"); |