David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 1 | /* |
| 2 | * QLogic iSCSI HBA Driver |
Vikas Chaudhary | c68cdbf | 2012-08-22 07:55:09 -0400 | [diff] [blame] | 3 | * Copyright (c) 2003-2012 QLogic Corporation |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 4 | * |
| 5 | * See LICENSE.qla4xxx for copyright and licensing details. |
| 6 | */ |
| 7 | |
| 8 | #ifndef _QLA4X_FW_H |
| 9 | #define _QLA4X_FW_H |
| 10 | |
| 11 | |
| 12 | #define MAX_PRST_DEV_DB_ENTRIES 64 |
| 13 | #define MIN_DISC_DEV_DB_ENTRY MAX_PRST_DEV_DB_ENTRIES |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 14 | #define MAX_DEV_DB_ENTRIES 512 |
Mike Christie | 1348373 | 2011-12-01 21:38:41 -0600 | [diff] [blame] | 15 | #define MAX_DEV_DB_ENTRIES_40XX 256 |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 16 | |
| 17 | /************************************************************************* |
| 18 | * |
| 19 | * ISP 4010 I/O Register Set Structure and Definitions |
| 20 | * |
| 21 | *************************************************************************/ |
| 22 | |
| 23 | struct port_ctrl_stat_regs { |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 24 | __le32 ext_hw_conf; /* 0x50 R/W */ |
| 25 | __le32 rsrvd0; /* 0x54 */ |
| 26 | __le32 port_ctrl; /* 0x58 */ |
| 27 | __le32 port_status; /* 0x5c */ |
| 28 | __le32 rsrvd1[32]; /* 0x60-0xdf */ |
| 29 | __le32 gp_out; /* 0xe0 */ |
| 30 | __le32 gp_in; /* 0xe4 */ |
| 31 | __le32 rsrvd2[5]; /* 0xe8-0xfb */ |
| 32 | __le32 port_err_status; /* 0xfc */ |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 33 | }; |
| 34 | |
| 35 | struct host_mem_cfg_regs { |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 36 | __le32 rsrvd0[12]; /* 0x50-0x79 */ |
| 37 | __le32 req_q_out; /* 0x80 */ |
| 38 | __le32 rsrvd1[31]; /* 0x84-0xFF */ |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 39 | }; |
| 40 | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 41 | /* |
| 42 | * ISP 82xx I/O Register Set structure definitions. |
| 43 | */ |
| 44 | struct device_reg_82xx { |
| 45 | __le32 req_q_out; /* 0x0000 (R): Request Queue out-Pointer. */ |
| 46 | __le32 reserve1[63]; /* Request Queue out-Pointer. (64 * 4) */ |
| 47 | __le32 rsp_q_in; /* 0x0100 (R/W): Response Queue In-Pointer. */ |
| 48 | __le32 reserve2[63]; /* Response Queue In-Pointer. */ |
| 49 | __le32 rsp_q_out; /* 0x0200 (R/W): Response Queue Out-Pointer. */ |
| 50 | __le32 reserve3[63]; /* Response Queue Out-Pointer. */ |
| 51 | |
| 52 | __le32 mailbox_in[8]; /* 0x0300 (R/W): Mail box In registers */ |
| 53 | __le32 reserve4[24]; |
| 54 | __le32 hint; /* 0x0380 (R/W): Host interrupt register */ |
| 55 | #define HINT_MBX_INT_PENDING BIT_0 |
| 56 | __le32 reserve5[31]; |
| 57 | __le32 mailbox_out[8]; /* 0x0400 (R): Mail box Out registers */ |
| 58 | __le32 reserve6[56]; |
| 59 | |
| 60 | __le32 host_status; /* Offset 0x500 (R): host status */ |
| 61 | #define HSRX_RISC_MB_INT BIT_0 /* RISC to Host Mailbox interrupt */ |
| 62 | #define HSRX_RISC_IOCB_INT BIT_1 /* RISC to Host IOCB interrupt */ |
| 63 | |
| 64 | __le32 host_int; /* Offset 0x0504 (R/W): Interrupt status. */ |
| 65 | #define ISRX_82XX_RISC_INT BIT_0 /* RISC interrupt. */ |
| 66 | }; |
| 67 | |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 68 | /* ISP 83xx I/O Register Set structure */ |
| 69 | struct device_reg_83xx { |
| 70 | __le32 mailbox_in[16]; /* 0x0000 */ |
| 71 | __le32 reserve1[496]; /* 0x0040 */ |
| 72 | __le32 mailbox_out[16]; /* 0x0800 */ |
| 73 | __le32 reserve2[496]; |
| 74 | __le32 mbox_int; /* 0x1000 */ |
| 75 | __le32 reserve3[63]; |
| 76 | __le32 req_q_out; /* 0x1100 */ |
| 77 | __le32 reserve4[63]; |
| 78 | |
| 79 | __le32 rsp_q_in; /* 0x1200 */ |
| 80 | __le32 reserve5[1919]; |
| 81 | |
| 82 | __le32 req_q_in; /* 0x3000 */ |
| 83 | __le32 reserve6[3]; |
| 84 | __le32 iocb_int_mask; /* 0x3010 */ |
| 85 | __le32 reserve7[3]; |
| 86 | __le32 rsp_q_out; /* 0x3020 */ |
| 87 | __le32 reserve8[3]; |
| 88 | __le32 anonymousbuff; /* 0x3030 */ |
| 89 | __le32 mb_int_mask; /* 0x3034 */ |
| 90 | |
| 91 | __le32 host_intr; /* 0x3038 - Host Interrupt Register */ |
| 92 | __le32 risc_intr; /* 0x303C - RISC Interrupt Register */ |
| 93 | __le32 reserve9[544]; |
| 94 | __le32 leg_int_ptr; /* 0x38C0 - Legacy Interrupt Pointer Register */ |
| 95 | __le32 leg_int_trig; /* 0x38C4 - Legacy Interrupt Trigger Control */ |
| 96 | __le32 leg_int_mask; /* 0x38C8 - Legacy Interrupt Mask Register */ |
| 97 | }; |
| 98 | |
| 99 | #define INT_ENABLE_FW_MB (1 << 2) |
| 100 | #define INT_MASK_FW_MB (1 << 2) |
| 101 | |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 102 | /* remote register set (access via PCI memory read/write) */ |
| 103 | struct isp_reg { |
| 104 | #define MBOX_REG_COUNT 8 |
| 105 | __le32 mailbox[MBOX_REG_COUNT]; |
| 106 | |
| 107 | __le32 flash_address; /* 0x20 */ |
| 108 | __le32 flash_data; |
| 109 | __le32 ctrl_status; |
| 110 | |
| 111 | union { |
| 112 | struct { |
| 113 | __le32 nvram; |
| 114 | __le32 reserved1[2]; /* 0x30 */ |
| 115 | } __attribute__ ((packed)) isp4010; |
| 116 | struct { |
| 117 | __le32 intr_mask; |
| 118 | __le32 nvram; /* 0x30 */ |
| 119 | __le32 semaphore; |
| 120 | } __attribute__ ((packed)) isp4022; |
| 121 | } u1; |
| 122 | |
| 123 | __le32 req_q_in; /* SCSI Request Queue Producer Index */ |
| 124 | __le32 rsp_q_out; /* SCSI Completion Queue Consumer Index */ |
| 125 | |
| 126 | __le32 reserved2[4]; /* 0x40 */ |
| 127 | |
| 128 | union { |
| 129 | struct { |
| 130 | __le32 ext_hw_conf; /* 0x50 */ |
| 131 | __le32 flow_ctrl; |
| 132 | __le32 port_ctrl; |
| 133 | __le32 port_status; |
| 134 | |
| 135 | __le32 reserved3[8]; /* 0x60 */ |
| 136 | |
| 137 | __le32 req_q_out; /* 0x80 */ |
| 138 | |
| 139 | __le32 reserved4[23]; /* 0x84 */ |
| 140 | |
| 141 | __le32 gp_out; /* 0xe0 */ |
| 142 | __le32 gp_in; |
| 143 | |
| 144 | __le32 reserved5[5]; |
| 145 | |
| 146 | __le32 port_err_status; /* 0xfc */ |
| 147 | } __attribute__ ((packed)) isp4010; |
| 148 | struct { |
| 149 | union { |
| 150 | struct port_ctrl_stat_regs p0; |
| 151 | struct host_mem_cfg_regs p1; |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 152 | }; |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 153 | } __attribute__ ((packed)) isp4022; |
| 154 | } u2; |
| 155 | }; /* 256 x100 */ |
| 156 | |
| 157 | |
| 158 | /* Semaphore Defines for 4010 */ |
| 159 | #define QL4010_DRVR_SEM_BITS 0x00000030 |
| 160 | #define QL4010_GPIO_SEM_BITS 0x000000c0 |
| 161 | #define QL4010_SDRAM_SEM_BITS 0x00000300 |
| 162 | #define QL4010_PHY_SEM_BITS 0x00000c00 |
| 163 | #define QL4010_NVRAM_SEM_BITS 0x00003000 |
| 164 | #define QL4010_FLASH_SEM_BITS 0x0000c000 |
| 165 | |
| 166 | #define QL4010_DRVR_SEM_MASK 0x00300000 |
| 167 | #define QL4010_GPIO_SEM_MASK 0x00c00000 |
| 168 | #define QL4010_SDRAM_SEM_MASK 0x03000000 |
| 169 | #define QL4010_PHY_SEM_MASK 0x0c000000 |
| 170 | #define QL4010_NVRAM_SEM_MASK 0x30000000 |
| 171 | #define QL4010_FLASH_SEM_MASK 0xc0000000 |
| 172 | |
| 173 | /* Semaphore Defines for 4022 */ |
| 174 | #define QL4022_RESOURCE_MASK_BASE_CODE 0x7 |
| 175 | #define QL4022_RESOURCE_BITS_BASE_CODE 0x4 |
| 176 | |
| 177 | |
| 178 | #define QL4022_DRVR_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (1+16)) |
| 179 | #define QL4022_DDR_RAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (4+16)) |
| 180 | #define QL4022_PHY_GIO_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (7+16)) |
| 181 | #define QL4022_NVRAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (10+16)) |
| 182 | #define QL4022_FLASH_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (13+16)) |
| 183 | |
Manish Rangankar | 2a991c2 | 2011-07-25 13:48:55 -0500 | [diff] [blame] | 184 | /* nvram address for 4032 */ |
| 185 | #define NVRAM_PORT0_BOOT_MODE 0x03b1 |
| 186 | #define NVRAM_PORT0_BOOT_PRI_TGT 0x03b2 |
| 187 | #define NVRAM_PORT0_BOOT_SEC_TGT 0x03bb |
| 188 | #define NVRAM_PORT1_BOOT_MODE 0x07b1 |
| 189 | #define NVRAM_PORT1_BOOT_PRI_TGT 0x07b2 |
| 190 | #define NVRAM_PORT1_BOOT_SEC_TGT 0x07bb |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 191 | |
| 192 | |
| 193 | /* Page # defines for 4022 */ |
| 194 | #define PORT_CTRL_STAT_PAGE 0 /* 4022 */ |
| 195 | #define HOST_MEM_CFG_PAGE 1 /* 4022 */ |
| 196 | #define LOCAL_RAM_CFG_PAGE 2 /* 4022 */ |
| 197 | #define PROT_STAT_PAGE 3 /* 4022 */ |
| 198 | |
| 199 | /* Register Mask - sets corresponding mask bits in the upper word */ |
| 200 | static inline uint32_t set_rmask(uint32_t val) |
| 201 | { |
| 202 | return (val & 0xffff) | (val << 16); |
| 203 | } |
| 204 | |
| 205 | |
| 206 | static inline uint32_t clr_rmask(uint32_t val) |
| 207 | { |
| 208 | return 0 | (val << 16); |
| 209 | } |
| 210 | |
| 211 | /* ctrl_status definitions */ |
| 212 | #define CSR_SCSI_PAGE_SELECT 0x00000003 |
| 213 | #define CSR_SCSI_INTR_ENABLE 0x00000004 /* 4010 */ |
| 214 | #define CSR_SCSI_RESET_INTR 0x00000008 |
| 215 | #define CSR_SCSI_COMPLETION_INTR 0x00000010 |
| 216 | #define CSR_SCSI_PROCESSOR_INTR 0x00000020 |
| 217 | #define CSR_INTR_RISC 0x00000040 |
| 218 | #define CSR_BOOT_ENABLE 0x00000080 |
| 219 | #define CSR_NET_PAGE_SELECT 0x00000300 /* 4010 */ |
| 220 | #define CSR_FUNC_NUM 0x00000700 /* 4022 */ |
| 221 | #define CSR_NET_RESET_INTR 0x00000800 /* 4010 */ |
| 222 | #define CSR_FORCE_SOFT_RESET 0x00002000 /* 4022 */ |
| 223 | #define CSR_FATAL_ERROR 0x00004000 |
| 224 | #define CSR_SOFT_RESET 0x00008000 |
| 225 | #define ISP_CONTROL_FN_MASK CSR_FUNC_NUM |
| 226 | #define ISP_CONTROL_FN0_SCSI 0x0500 |
| 227 | #define ISP_CONTROL_FN1_SCSI 0x0700 |
| 228 | |
| 229 | #define INTR_PENDING (CSR_SCSI_COMPLETION_INTR |\ |
| 230 | CSR_SCSI_PROCESSOR_INTR |\ |
| 231 | CSR_SCSI_RESET_INTR) |
| 232 | |
| 233 | /* ISP InterruptMask definitions */ |
| 234 | #define IMR_SCSI_INTR_ENABLE 0x00000004 /* 4022 */ |
| 235 | |
| 236 | /* ISP 4022 nvram definitions */ |
| 237 | #define NVR_WRITE_ENABLE 0x00000010 /* 4022 */ |
| 238 | |
Harish Zunjarrao | 7c07d13 | 2011-08-01 03:26:16 -0700 | [diff] [blame] | 239 | #define QL4010_NVRAM_SIZE 0x200 |
| 240 | #define QL40X2_NVRAM_SIZE 0x800 |
| 241 | |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 242 | /* ISP port_status definitions */ |
| 243 | |
| 244 | /* ISP Semaphore definitions */ |
| 245 | |
| 246 | /* ISP General Purpose Output definitions */ |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 247 | #define GPOR_TOPCAT_RESET 0x00000004 |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 248 | |
| 249 | /* shadow registers (DMA'd from HA to system memory. read only) */ |
| 250 | struct shadow_regs { |
| 251 | /* SCSI Request Queue Consumer Index */ |
| 252 | __le32 req_q_out; /* 0 x0 R */ |
| 253 | |
| 254 | /* SCSI Completion Queue Producer Index */ |
| 255 | __le32 rsp_q_in; /* 4 x4 R */ |
| 256 | }; /* 8 x8 */ |
| 257 | |
| 258 | |
| 259 | /* External hardware configuration register */ |
| 260 | union external_hw_config_reg { |
| 261 | struct { |
| 262 | /* FIXME: Do we even need this? All values are |
| 263 | * referred to by 16 bit quantities. Platform and |
| 264 | * endianess issues. */ |
| 265 | __le32 bReserved0:1; |
| 266 | __le32 bSDRAMProtectionMethod:2; |
| 267 | __le32 bSDRAMBanks:1; |
| 268 | __le32 bSDRAMChipWidth:1; |
| 269 | __le32 bSDRAMChipSize:2; |
| 270 | __le32 bParityDisable:1; |
| 271 | __le32 bExternalMemoryType:1; |
| 272 | __le32 bFlashBIOSWriteEnable:1; |
| 273 | __le32 bFlashUpperBankSelect:1; |
| 274 | __le32 bWriteBurst:2; |
| 275 | __le32 bReserved1:3; |
| 276 | __le32 bMask:16; |
| 277 | }; |
| 278 | uint32_t Asuint32_t; |
| 279 | }; |
| 280 | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 281 | /* 82XX Support start */ |
| 282 | /* 82xx Default FLT Addresses */ |
| 283 | #define FA_FLASH_LAYOUT_ADDR_82 0xFC400 |
| 284 | #define FA_FLASH_DESCR_ADDR_82 0xFC000 |
| 285 | #define FA_BOOT_LOAD_ADDR_82 0x04000 |
| 286 | #define FA_BOOT_CODE_ADDR_82 0x20000 |
| 287 | #define FA_RISC_CODE_ADDR_82 0x40000 |
| 288 | #define FA_GOLD_RISC_CODE_ADDR_82 0x80000 |
Lalit Chandivade | 4549415 | 2011-10-07 16:55:42 -0700 | [diff] [blame] | 289 | #define FA_FLASH_ISCSI_CHAP 0x540000 |
| 290 | #define FA_FLASH_CHAP_SIZE 0xC0000 |
Adheer Chandravanshi | 1e9e2be | 2013-03-22 07:41:31 -0400 | [diff] [blame^] | 291 | #define FA_FLASH_ISCSI_DDB 0x420000 |
| 292 | #define FA_FLASH_DDB_SIZE 0x080000 |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 293 | |
| 294 | /* Flash Description Table */ |
| 295 | struct qla_fdt_layout { |
| 296 | uint8_t sig[4]; |
| 297 | uint16_t version; |
| 298 | uint16_t len; |
| 299 | uint16_t checksum; |
| 300 | uint8_t unused1[2]; |
| 301 | uint8_t model[16]; |
| 302 | uint16_t man_id; |
| 303 | uint16_t id; |
| 304 | uint8_t flags; |
| 305 | uint8_t erase_cmd; |
| 306 | uint8_t alt_erase_cmd; |
| 307 | uint8_t wrt_enable_cmd; |
| 308 | uint8_t wrt_enable_bits; |
| 309 | uint8_t wrt_sts_reg_cmd; |
| 310 | uint8_t unprotect_sec_cmd; |
| 311 | uint8_t read_man_id_cmd; |
| 312 | uint32_t block_size; |
| 313 | uint32_t alt_block_size; |
| 314 | uint32_t flash_size; |
| 315 | uint32_t wrt_enable_data; |
| 316 | uint8_t read_id_addr_len; |
| 317 | uint8_t wrt_disable_bits; |
| 318 | uint8_t read_dev_id_len; |
| 319 | uint8_t chip_erase_cmd; |
| 320 | uint16_t read_timeout; |
| 321 | uint8_t protect_sec_cmd; |
| 322 | uint8_t unused2[65]; |
| 323 | }; |
| 324 | |
| 325 | /* Flash Layout Table */ |
| 326 | |
| 327 | struct qla_flt_location { |
| 328 | uint8_t sig[4]; |
| 329 | uint16_t start_lo; |
| 330 | uint16_t start_hi; |
| 331 | uint8_t version; |
| 332 | uint8_t unused[5]; |
| 333 | uint16_t checksum; |
| 334 | }; |
| 335 | |
| 336 | struct qla_flt_header { |
| 337 | uint16_t version; |
| 338 | uint16_t length; |
| 339 | uint16_t checksum; |
| 340 | uint16_t unused; |
| 341 | }; |
| 342 | |
| 343 | /* 82xx FLT Regions */ |
| 344 | #define FLT_REG_FDT 0x1a |
| 345 | #define FLT_REG_FLT 0x1c |
| 346 | #define FLT_REG_BOOTLOAD_82 0x72 |
| 347 | #define FLT_REG_FW_82 0x74 |
Nilesh Javali | 9382395 | 2011-10-07 16:55:39 -0700 | [diff] [blame] | 348 | #define FLT_REG_FW_82_1 0x97 |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 349 | #define FLT_REG_GOLD_FW_82 0x75 |
| 350 | #define FLT_REG_BOOT_CODE_82 0x78 |
Manish Rangankar | 2a991c2 | 2011-07-25 13:48:55 -0500 | [diff] [blame] | 351 | #define FLT_REG_ISCSI_PARAM 0x65 |
Lalit Chandivade | 4549415 | 2011-10-07 16:55:42 -0700 | [diff] [blame] | 352 | #define FLT_REG_ISCSI_CHAP 0x63 |
Adheer Chandravanshi | 1e9e2be | 2013-03-22 07:41:31 -0400 | [diff] [blame^] | 353 | #define FLT_REG_ISCSI_DDB 0x6A |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 354 | |
| 355 | struct qla_flt_region { |
| 356 | uint32_t code; |
| 357 | uint32_t size; |
| 358 | uint32_t start; |
| 359 | uint32_t end; |
| 360 | }; |
| 361 | |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 362 | /************************************************************************* |
| 363 | * |
| 364 | * Mailbox Commands Structures and Definitions |
| 365 | * |
| 366 | *************************************************************************/ |
| 367 | |
| 368 | /* Mailbox command definitions */ |
| 369 | #define MBOX_CMD_ABOUT_FW 0x0009 |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 370 | #define MBOX_CMD_PING 0x000B |
Vikas Chaudhary | c0b9d3f | 2012-02-13 18:30:49 +0530 | [diff] [blame] | 371 | #define PING_IPV6_PROTOCOL_ENABLE 0x1 |
| 372 | #define PING_IPV6_LINKLOCAL_ADDR 0x4 |
| 373 | #define PING_IPV6_ADDR0 0x8 |
| 374 | #define PING_IPV6_ADDR1 0xC |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 375 | #define MBOX_CMD_ENABLE_INTRS 0x0010 |
| 376 | #define INTR_DISABLE 0 |
| 377 | #define INTR_ENABLE 1 |
| 378 | #define MBOX_CMD_STOP_FW 0x0014 |
Vikas Chaudhary | 09a0f71 | 2010-04-28 11:42:24 +0530 | [diff] [blame] | 379 | #define MBOX_CMD_ABORT_TASK 0x0015 |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 380 | #define MBOX_CMD_LUN_RESET 0x0016 |
Mike Christie | ce54503 | 2008-02-29 18:25:20 -0600 | [diff] [blame] | 381 | #define MBOX_CMD_TARGET_WARM_RESET 0x0017 |
David C Somayajulu | d915058 | 2006-11-15 17:38:40 -0800 | [diff] [blame] | 382 | #define MBOX_CMD_GET_MANAGEMENT_DATA 0x001E |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 383 | #define MBOX_CMD_GET_FW_STATUS 0x001F |
| 384 | #define MBOX_CMD_SET_ISNS_SERVICE 0x0021 |
| 385 | #define ISNS_DISABLE 0 |
| 386 | #define ISNS_ENABLE 1 |
David C Somayajulu | d915058 | 2006-11-15 17:38:40 -0800 | [diff] [blame] | 387 | #define MBOX_CMD_COPY_FLASH 0x0024 |
| 388 | #define MBOX_CMD_WRITE_FLASH 0x0025 |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 389 | #define MBOX_CMD_READ_FLASH 0x0026 |
| 390 | #define MBOX_CMD_CLEAR_DATABASE_ENTRY 0x0031 |
Manish Rangankar | b3a271a | 2011-07-25 13:48:53 -0500 | [diff] [blame] | 391 | #define MBOX_CMD_CONN_OPEN 0x0074 |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 392 | #define MBOX_CMD_CONN_CLOSE_SESS_LOGOUT 0x0056 |
Manish Rangankar | b3a271a | 2011-07-25 13:48:53 -0500 | [diff] [blame] | 393 | #define LOGOUT_OPTION_CLOSE_SESSION 0x0002 |
| 394 | #define LOGOUT_OPTION_RELOGIN 0x0004 |
| 395 | #define LOGOUT_OPTION_FREE_DDB 0x0008 |
Manish Dusane | cfb2787 | 2012-09-20 07:35:01 -0400 | [diff] [blame] | 396 | #define MBOX_CMD_SET_PARAM 0x0059 |
| 397 | #define SET_DRVR_VERSION 0x200 |
| 398 | #define MAX_DRVR_VER_LEN 24 |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 399 | #define MBOX_CMD_EXECUTE_IOCB_A64 0x005A |
| 400 | #define MBOX_CMD_INITIALIZE_FIRMWARE 0x0060 |
| 401 | #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK 0x0061 |
| 402 | #define MBOX_CMD_REQUEST_DATABASE_ENTRY 0x0062 |
| 403 | #define MBOX_CMD_SET_DATABASE_ENTRY 0x0063 |
| 404 | #define MBOX_CMD_GET_DATABASE_ENTRY 0x0064 |
| 405 | #define DDB_DS_UNASSIGNED 0x00 |
| 406 | #define DDB_DS_NO_CONNECTION_ACTIVE 0x01 |
Manish Rangankar | b3a271a | 2011-07-25 13:48:53 -0500 | [diff] [blame] | 407 | #define DDB_DS_DISCOVERY 0x02 |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 408 | #define DDB_DS_SESSION_ACTIVE 0x04 |
| 409 | #define DDB_DS_SESSION_FAILED 0x06 |
| 410 | #define DDB_DS_LOGIN_IN_PROCESS 0x07 |
| 411 | #define MBOX_CMD_GET_FW_STATE 0x0069 |
David C Somayajulu | d915058 | 2006-11-15 17:38:40 -0800 | [diff] [blame] | 412 | #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK_DEFAULTS 0x006A |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 413 | #define MBOX_CMD_GET_SYS_INFO 0x0078 |
Harish Zunjarrao | 7c07d13 | 2011-08-01 03:26:16 -0700 | [diff] [blame] | 414 | #define MBOX_CMD_GET_NVRAM 0x0078 /* For 40xx */ |
| 415 | #define MBOX_CMD_SET_NVRAM 0x0079 /* For 40xx */ |
David C Somayajulu | d915058 | 2006-11-15 17:38:40 -0800 | [diff] [blame] | 416 | #define MBOX_CMD_RESTORE_FACTORY_DEFAULTS 0x0087 |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 417 | #define MBOX_CMD_SET_ACB 0x0088 |
| 418 | #define MBOX_CMD_GET_ACB 0x0089 |
| 419 | #define MBOX_CMD_DISABLE_ACB 0x008A |
| 420 | #define MBOX_CMD_GET_IPV6_NEIGHBOR_CACHE 0x008B |
| 421 | #define MBOX_CMD_GET_IPV6_DEST_CACHE 0x008C |
| 422 | #define MBOX_CMD_GET_IPV6_DEF_ROUTER_LIST 0x008D |
| 423 | #define MBOX_CMD_GET_IPV6_LCL_PREFIX_LIST 0x008E |
| 424 | #define MBOX_CMD_SET_IPV6_NEIGHBOR_CACHE 0x0090 |
| 425 | #define MBOX_CMD_GET_IP_ADDR_STATE 0x0091 |
| 426 | #define MBOX_CMD_SEND_IPV6_ROUTER_SOL 0x0092 |
| 427 | #define MBOX_CMD_GET_DB_ENTRY_CURRENT_IP_ADDR 0x0093 |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 428 | #define MBOX_CMD_MINIDUMP 0x0129 |
| 429 | |
| 430 | /* Minidump subcommand */ |
| 431 | #define MINIDUMP_GET_SIZE_SUBCOMMAND 0x00 |
| 432 | #define MINIDUMP_GET_TMPLT_SUBCOMMAND 0x01 |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 433 | |
| 434 | /* Mailbox 1 */ |
| 435 | #define FW_STATE_READY 0x0000 |
| 436 | #define FW_STATE_CONFIG_WAIT 0x0001 |
Vikas Chaudhary | 2a49a78 | 2010-04-28 11:37:07 +0530 | [diff] [blame] | 437 | #define FW_STATE_WAIT_AUTOCONNECT 0x0002 |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 438 | #define FW_STATE_ERROR 0x0004 |
Vikas Chaudhary | 2a49a78 | 2010-04-28 11:37:07 +0530 | [diff] [blame] | 439 | #define FW_STATE_CONFIGURING_IP 0x0008 |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 440 | |
| 441 | /* Mailbox 3 */ |
| 442 | #define FW_ADDSTATE_OPTICAL_MEDIA 0x0001 |
Vikas Chaudhary | 2a49a78 | 2010-04-28 11:37:07 +0530 | [diff] [blame] | 443 | #define FW_ADDSTATE_DHCPv4_ENABLED 0x0002 |
| 444 | #define FW_ADDSTATE_DHCPv4_LEASE_ACQUIRED 0x0004 |
| 445 | #define FW_ADDSTATE_DHCPv4_LEASE_EXPIRED 0x0008 |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 446 | #define FW_ADDSTATE_LINK_UP 0x0010 |
| 447 | #define FW_ADDSTATE_ISNS_SVC_ENABLED 0x0020 |
Vikas Chaudhary | 3254dbe | 2012-01-19 03:06:56 -0800 | [diff] [blame] | 448 | #define FW_ADDSTATE_LINK_SPEED_10MBPS 0x0100 |
| 449 | #define FW_ADDSTATE_LINK_SPEED_100MBPS 0x0200 |
| 450 | #define FW_ADDSTATE_LINK_SPEED_1GBPS 0x0400 |
| 451 | #define FW_ADDSTATE_LINK_SPEED_10GBPS 0x0800 |
Manish Rangankar | b3a271a | 2011-07-25 13:48:53 -0500 | [diff] [blame] | 452 | |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 453 | #define MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS 0x006B |
Manish Rangankar | b3a271a | 2011-07-25 13:48:53 -0500 | [diff] [blame] | 454 | #define IPV6_DEFAULT_DDB_ENTRY 0x0001 |
| 455 | |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 456 | #define MBOX_CMD_CONN_OPEN_SESS_LOGIN 0x0074 |
| 457 | #define MBOX_CMD_GET_CRASH_RECORD 0x0076 /* 4010 only */ |
| 458 | #define MBOX_CMD_GET_CONN_EVENT_LOG 0x0077 |
| 459 | |
Nilesh Javali | 320a61d | 2012-09-20 07:35:10 -0400 | [diff] [blame] | 460 | #define MBOX_CMD_IDC_ACK 0x0101 |
| 461 | #define MBOX_CMD_PORT_RESET 0x0120 |
| 462 | #define MBOX_CMD_SET_PORT_CONFIG 0x0122 |
| 463 | |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 464 | /* Mailbox status definitions */ |
| 465 | #define MBOX_COMPLETION_STATUS 4 |
| 466 | #define MBOX_STS_BUSY 0x0007 |
| 467 | #define MBOX_STS_INTERMEDIATE_COMPLETION 0x1000 |
| 468 | #define MBOX_STS_COMMAND_COMPLETE 0x4000 |
| 469 | #define MBOX_STS_COMMAND_ERROR 0x4005 |
| 470 | |
| 471 | #define MBOX_ASYNC_EVENT_STATUS 8 |
| 472 | #define MBOX_ASTS_SYSTEM_ERROR 0x8002 |
| 473 | #define MBOX_ASTS_REQUEST_TRANSFER_ERROR 0x8003 |
| 474 | #define MBOX_ASTS_RESPONSE_TRANSFER_ERROR 0x8004 |
| 475 | #define MBOX_ASTS_PROTOCOL_STATISTIC_ALARM 0x8005 |
| 476 | #define MBOX_ASTS_SCSI_COMMAND_PDU_REJECTED 0x8006 |
| 477 | #define MBOX_ASTS_LINK_UP 0x8010 |
| 478 | #define MBOX_ASTS_LINK_DOWN 0x8011 |
| 479 | #define MBOX_ASTS_DATABASE_CHANGED 0x8014 |
| 480 | #define MBOX_ASTS_UNSOLICITED_PDU_RECEIVED 0x8015 |
| 481 | #define MBOX_ASTS_SELF_TEST_FAILED 0x8016 |
| 482 | #define MBOX_ASTS_LOGIN_FAILED 0x8017 |
| 483 | #define MBOX_ASTS_DNS 0x8018 |
| 484 | #define MBOX_ASTS_HEARTBEAT 0x8019 |
| 485 | #define MBOX_ASTS_NVRAM_INVALID 0x801A |
| 486 | #define MBOX_ASTS_MAC_ADDRESS_CHANGED 0x801B |
| 487 | #define MBOX_ASTS_IP_ADDRESS_CHANGED 0x801C |
| 488 | #define MBOX_ASTS_DHCP_LEASE_EXPIRED 0x801D |
| 489 | #define MBOX_ASTS_DHCP_LEASE_ACQUIRED 0x801F |
| 490 | #define MBOX_ASTS_ISNS_UNSOLICITED_PDU_RECEIVED 0x8021 |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 491 | #define MBOX_ASTS_DUPLICATE_IP 0x8025 |
| 492 | #define MBOX_ASTS_ARP_COMPLETE 0x8026 |
| 493 | #define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027 |
| 494 | #define MBOX_ASTS_RESPONSE_QUEUE_FULL 0x8028 |
| 495 | #define MBOX_ASTS_IP_ADDR_STATE_CHANGED 0x8029 |
| 496 | #define MBOX_ASTS_IPV6_PREFIX_EXPIRED 0x802B |
| 497 | #define MBOX_ASTS_IPV6_ND_PREFIX_IGNORED 0x802C |
| 498 | #define MBOX_ASTS_IPV6_LCL_PREFIX_IGNORED 0x802D |
| 499 | #define MBOX_ASTS_ICMPV6_ERROR_MSG_RCVD 0x802E |
Nilesh Javali | 320a61d | 2012-09-20 07:35:10 -0400 | [diff] [blame] | 500 | #define MBOX_ASTS_IDC_COMPLETE 0x8100 |
Nilesh Javali | 9cb33f1 | 2013-01-20 23:50:57 -0500 | [diff] [blame] | 501 | #define MBOX_ASTS_IDC_REQUEST_NOTIFICATION 0x8101 |
Shyam Sundar | 6434080 | 2010-10-06 22:49:40 -0700 | [diff] [blame] | 502 | #define MBOX_ASTS_TXSCVR_INSERTED 0x8130 |
| 503 | #define MBOX_ASTS_TXSCVR_REMOVED 0x8131 |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 504 | |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 505 | #define ISNS_EVENT_DATA_RECEIVED 0x0000 |
| 506 | #define ISNS_EVENT_CONNECTION_OPENED 0x0001 |
| 507 | #define ISNS_EVENT_CONNECTION_FAILED 0x0002 |
| 508 | #define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR 0x8022 |
| 509 | #define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027 |
| 510 | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 511 | /* ACB State Defines */ |
| 512 | #define ACB_STATE_UNCONFIGURED 0x00 |
| 513 | #define ACB_STATE_INVALID 0x01 |
| 514 | #define ACB_STATE_ACQUIRING 0x02 |
| 515 | #define ACB_STATE_TENTATIVE 0x03 |
| 516 | #define ACB_STATE_DEPRICATED 0x04 |
| 517 | #define ACB_STATE_VALID 0x05 |
| 518 | #define ACB_STATE_DISABLING 0x06 |
| 519 | |
Mike Christie | d00efe3 | 2011-07-25 13:48:38 -0500 | [diff] [blame] | 520 | /* FLASH offsets */ |
| 521 | #define FLASH_SEGMENT_IFCB 0x04000000 |
| 522 | |
| 523 | #define FLASH_OPT_RMW_HOLD 0 |
| 524 | #define FLASH_OPT_RMW_INIT 1 |
| 525 | #define FLASH_OPT_COMMIT 2 |
| 526 | #define FLASH_OPT_RMW_COMMIT 3 |
| 527 | |
Nilesh Javali | 026fbd3 | 2013-01-20 23:50:58 -0500 | [diff] [blame] | 528 | /* Loopback type */ |
| 529 | #define ENABLE_INTERNAL_LOOPBACK 0x04 |
| 530 | #define ENABLE_EXTERNAL_LOOPBACK 0x08 |
| 531 | |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 532 | /*************************************************************************/ |
| 533 | |
| 534 | /* Host Adapter Initialization Control Block (from host) */ |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 535 | struct addr_ctrl_blk { |
| 536 | uint8_t version; /* 00 */ |
Vikas Chaudhary | 2a49a78 | 2010-04-28 11:37:07 +0530 | [diff] [blame] | 537 | #define IFCB_VER_MIN 0x01 |
| 538 | #define IFCB_VER_MAX 0x02 |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 539 | uint8_t control; /* 01 */ |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 540 | |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 541 | uint16_t fw_options; /* 02-03 */ |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 542 | #define FWOPT_HEARTBEAT_ENABLE 0x1000 |
| 543 | #define FWOPT_SESSION_MODE 0x0040 |
| 544 | #define FWOPT_INITIATOR_MODE 0x0020 |
| 545 | #define FWOPT_TARGET_MODE 0x0010 |
Shyam Sundar | 2657c80 | 2010-10-06 22:50:29 -0700 | [diff] [blame] | 546 | #define FWOPT_ENABLE_CRBDB 0x8000 |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 547 | |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 548 | uint16_t exec_throttle; /* 04-05 */ |
| 549 | uint8_t zio_count; /* 06 */ |
| 550 | uint8_t res0; /* 07 */ |
| 551 | uint16_t eth_mtu_size; /* 08-09 */ |
| 552 | uint16_t add_fw_options; /* 0A-0B */ |
Manish Rangankar | b3a271a | 2011-07-25 13:48:53 -0500 | [diff] [blame] | 553 | #define ADFWOPT_SERIALIZE_TASK_MGMT 0x0400 |
| 554 | #define ADFWOPT_AUTOCONN_DISABLE 0x0002 |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 555 | |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 556 | uint8_t hb_interval; /* 0C */ |
| 557 | uint8_t inst_num; /* 0D */ |
| 558 | uint16_t res1; /* 0E-0F */ |
| 559 | uint16_t rqq_consumer_idx; /* 10-11 */ |
| 560 | uint16_t compq_producer_idx; /* 12-13 */ |
| 561 | uint16_t rqq_len; /* 14-15 */ |
| 562 | uint16_t compq_len; /* 16-17 */ |
| 563 | uint32_t rqq_addr_lo; /* 18-1B */ |
| 564 | uint32_t rqq_addr_hi; /* 1C-1F */ |
| 565 | uint32_t compq_addr_lo; /* 20-23 */ |
| 566 | uint32_t compq_addr_hi; /* 24-27 */ |
| 567 | uint32_t shdwreg_addr_lo; /* 28-2B */ |
| 568 | uint32_t shdwreg_addr_hi; /* 2C-2F */ |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 569 | |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 570 | uint16_t iscsi_opts; /* 30-31 */ |
| 571 | uint16_t ipv4_tcp_opts; /* 32-33 */ |
Mike Christie | d00efe3 | 2011-07-25 13:48:38 -0500 | [diff] [blame] | 572 | #define TCPOPT_DHCP_ENABLE 0x0200 |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 573 | uint16_t ipv4_ip_opts; /* 34-35 */ |
Vikas Chaudhary | 2bab08f | 2011-07-25 13:48:39 -0500 | [diff] [blame] | 574 | #define IPOPT_IPV4_PROTOCOL_ENABLE 0x8000 |
Vikas Chaudhary | 6ac73e8 | 2011-07-25 13:48:49 -0500 | [diff] [blame] | 575 | #define IPOPT_VLAN_TAGGING_ENABLE 0x2000 |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 576 | |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 577 | uint16_t iscsi_max_pdu_size; /* 36-37 */ |
| 578 | uint8_t ipv4_tos; /* 38 */ |
| 579 | uint8_t ipv4_ttl; /* 39 */ |
| 580 | uint8_t acb_version; /* 3A */ |
Vikas Chaudhary | 2a49a78 | 2010-04-28 11:37:07 +0530 | [diff] [blame] | 581 | #define ACB_NOT_SUPPORTED 0x00 |
| 582 | #define ACB_SUPPORTED 0x02 /* Capable of ACB Version 2 |
| 583 | Features */ |
| 584 | |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 585 | uint8_t res2; /* 3B */ |
| 586 | uint16_t def_timeout; /* 3C-3D */ |
| 587 | uint16_t iscsi_fburst_len; /* 3E-3F */ |
| 588 | uint16_t iscsi_def_time2wait; /* 40-41 */ |
| 589 | uint16_t iscsi_def_time2retain; /* 42-43 */ |
| 590 | uint16_t iscsi_max_outstnd_r2t; /* 44-45 */ |
| 591 | uint16_t conn_ka_timeout; /* 46-47 */ |
| 592 | uint16_t ipv4_port; /* 48-49 */ |
| 593 | uint16_t iscsi_max_burst_len; /* 4A-4B */ |
| 594 | uint32_t res5; /* 4C-4F */ |
| 595 | uint8_t ipv4_addr[4]; /* 50-53 */ |
| 596 | uint16_t ipv4_vlan_tag; /* 54-55 */ |
| 597 | uint8_t ipv4_addr_state; /* 56 */ |
| 598 | uint8_t ipv4_cacheid; /* 57 */ |
| 599 | uint8_t res6[8]; /* 58-5F */ |
| 600 | uint8_t ipv4_subnet[4]; /* 60-63 */ |
| 601 | uint8_t res7[12]; /* 64-6F */ |
| 602 | uint8_t ipv4_gw_addr[4]; /* 70-73 */ |
| 603 | uint8_t res8[0xc]; /* 74-7F */ |
| 604 | uint8_t pri_dns_srvr_ip[4];/* 80-83 */ |
| 605 | uint8_t sec_dns_srvr_ip[4];/* 84-87 */ |
| 606 | uint16_t min_eph_port; /* 88-89 */ |
| 607 | uint16_t max_eph_port; /* 8A-8B */ |
| 608 | uint8_t res9[4]; /* 8C-8F */ |
| 609 | uint8_t iscsi_alias[32];/* 90-AF */ |
| 610 | uint8_t res9_1[0x16]; /* B0-C5 */ |
| 611 | uint16_t tgt_portal_grp;/* C6-C7 */ |
| 612 | uint8_t abort_timer; /* C8 */ |
| 613 | uint8_t ipv4_tcp_wsf; /* C9 */ |
| 614 | uint8_t res10[6]; /* CA-CF */ |
| 615 | uint8_t ipv4_sec_ip_addr[4]; /* D0-D3 */ |
| 616 | uint8_t ipv4_dhcp_vid_len; /* D4 */ |
| 617 | uint8_t ipv4_dhcp_vid[11]; /* D5-DF */ |
| 618 | uint8_t res11[20]; /* E0-F3 */ |
| 619 | uint8_t ipv4_dhcp_alt_cid_len; /* F4 */ |
| 620 | uint8_t ipv4_dhcp_alt_cid[11]; /* F5-FF */ |
| 621 | uint8_t iscsi_name[224]; /* 100-1DF */ |
| 622 | uint8_t res12[32]; /* 1E0-1FF */ |
| 623 | uint32_t cookie; /* 200-203 */ |
| 624 | uint16_t ipv6_port; /* 204-205 */ |
| 625 | uint16_t ipv6_opts; /* 206-207 */ |
Vikas Chaudhary | 2a49a78 | 2010-04-28 11:37:07 +0530 | [diff] [blame] | 626 | #define IPV6_OPT_IPV6_PROTOCOL_ENABLE 0x8000 |
Vikas Chaudhary | 6ac73e8 | 2011-07-25 13:48:49 -0500 | [diff] [blame] | 627 | #define IPV6_OPT_VLAN_TAGGING_ENABLE 0x2000 |
Vikas Chaudhary | 2a49a78 | 2010-04-28 11:37:07 +0530 | [diff] [blame] | 628 | |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 629 | uint16_t ipv6_addtl_opts; /* 208-209 */ |
Vikas Chaudhary | 2a49a78 | 2010-04-28 11:37:07 +0530 | [diff] [blame] | 630 | #define IPV6_ADDOPT_NEIGHBOR_DISCOVERY_ADDR_ENABLE 0x0002 /* Pri ACB |
| 631 | Only */ |
| 632 | #define IPV6_ADDOPT_AUTOCONFIG_LINK_LOCAL_ADDR 0x0001 |
| 633 | |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 634 | uint16_t ipv6_tcp_opts; /* 20A-20B */ |
| 635 | uint8_t ipv6_tcp_wsf; /* 20C */ |
| 636 | uint16_t ipv6_flow_lbl; /* 20D-20F */ |
Vikas Chaudhary | 2a49a78 | 2010-04-28 11:37:07 +0530 | [diff] [blame] | 637 | uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */ |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 638 | uint16_t ipv6_vlan_tag; /* 220-221 */ |
| 639 | uint8_t ipv6_lnk_lcl_addr_state;/* 222 */ |
| 640 | uint8_t ipv6_addr0_state; /* 223 */ |
| 641 | uint8_t ipv6_addr1_state; /* 224 */ |
Vikas Chaudhary | 2a49a78 | 2010-04-28 11:37:07 +0530 | [diff] [blame] | 642 | #define IP_ADDRSTATE_UNCONFIGURED 0 |
| 643 | #define IP_ADDRSTATE_INVALID 1 |
| 644 | #define IP_ADDRSTATE_ACQUIRING 2 |
| 645 | #define IP_ADDRSTATE_TENTATIVE 3 |
| 646 | #define IP_ADDRSTATE_DEPRICATED 4 |
| 647 | #define IP_ADDRSTATE_PREFERRED 5 |
| 648 | #define IP_ADDRSTATE_DISABLING 6 |
| 649 | |
| 650 | uint8_t ipv6_dflt_rtr_state; /* 225 */ |
| 651 | #define IPV6_RTRSTATE_UNKNOWN 0 |
| 652 | #define IPV6_RTRSTATE_MANUAL 1 |
| 653 | #define IPV6_RTRSTATE_ADVERTISED 3 |
| 654 | #define IPV6_RTRSTATE_STALE 4 |
| 655 | |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 656 | uint8_t ipv6_traffic_class; /* 226 */ |
| 657 | uint8_t ipv6_hop_limit; /* 227 */ |
| 658 | uint8_t ipv6_if_id[8]; /* 228-22F */ |
| 659 | uint8_t ipv6_addr0[16]; /* 230-23F */ |
| 660 | uint8_t ipv6_addr1[16]; /* 240-24F */ |
| 661 | uint32_t ipv6_nd_reach_time; /* 250-253 */ |
| 662 | uint32_t ipv6_nd_rexmit_timer; /* 254-257 */ |
| 663 | uint32_t ipv6_nd_stale_timeout; /* 258-25B */ |
| 664 | uint8_t ipv6_dup_addr_detect_count; /* 25C */ |
| 665 | uint8_t ipv6_cache_id; /* 25D */ |
| 666 | uint8_t res13[18]; /* 25E-26F */ |
| 667 | uint32_t ipv6_gw_advrt_mtu; /* 270-273 */ |
| 668 | uint8_t res14[140]; /* 274-2FF */ |
| 669 | }; |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 670 | |
Mike Christie | 1348373 | 2011-12-01 21:38:41 -0600 | [diff] [blame] | 671 | #define IP_ADDR_COUNT 4 /* Total 4 IP address supported in one interface |
| 672 | * One IPv4, one IPv6 link local and 2 IPv6 |
| 673 | */ |
| 674 | |
| 675 | #define IP_STATE_MASK 0x0F000000 |
| 676 | #define IP_STATE_SHIFT 24 |
| 677 | |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 678 | struct init_fw_ctrl_blk { |
| 679 | struct addr_ctrl_blk pri; |
Vikas Chaudhary | 2a49a78 | 2010-04-28 11:37:07 +0530 | [diff] [blame] | 680 | /* struct addr_ctrl_blk sec;*/ |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 681 | }; |
| 682 | |
Vikas Chaudhary | 95d3126 | 2011-08-12 02:51:29 -0700 | [diff] [blame] | 683 | #define PRIMARI_ACB 0 |
| 684 | #define SECONDARY_ACB 1 |
| 685 | |
Mike Christie | d00efe3 | 2011-07-25 13:48:38 -0500 | [diff] [blame] | 686 | struct addr_ctrl_blk_def { |
| 687 | uint8_t reserved1[1]; /* 00 */ |
| 688 | uint8_t control; /* 01 */ |
| 689 | uint8_t reserved2[11]; /* 02-0C */ |
| 690 | uint8_t inst_num; /* 0D */ |
| 691 | uint8_t reserved3[34]; /* 0E-2F */ |
| 692 | uint16_t iscsi_opts; /* 30-31 */ |
| 693 | uint16_t ipv4_tcp_opts; /* 32-33 */ |
| 694 | uint16_t ipv4_ip_opts; /* 34-35 */ |
| 695 | uint16_t iscsi_max_pdu_size; /* 36-37 */ |
| 696 | uint8_t ipv4_tos; /* 38 */ |
| 697 | uint8_t ipv4_ttl; /* 39 */ |
| 698 | uint8_t reserved4[2]; /* 3A-3B */ |
| 699 | uint16_t def_timeout; /* 3C-3D */ |
| 700 | uint16_t iscsi_fburst_len; /* 3E-3F */ |
| 701 | uint8_t reserved5[4]; /* 40-43 */ |
| 702 | uint16_t iscsi_max_outstnd_r2t; /* 44-45 */ |
| 703 | uint8_t reserved6[2]; /* 46-47 */ |
| 704 | uint16_t ipv4_port; /* 48-49 */ |
| 705 | uint16_t iscsi_max_burst_len; /* 4A-4B */ |
| 706 | uint8_t reserved7[4]; /* 4C-4F */ |
| 707 | uint8_t ipv4_addr[4]; /* 50-53 */ |
| 708 | uint16_t ipv4_vlan_tag; /* 54-55 */ |
| 709 | uint8_t ipv4_addr_state; /* 56 */ |
| 710 | uint8_t ipv4_cacheid; /* 57 */ |
| 711 | uint8_t reserved8[8]; /* 58-5F */ |
| 712 | uint8_t ipv4_subnet[4]; /* 60-63 */ |
| 713 | uint8_t reserved9[12]; /* 64-6F */ |
| 714 | uint8_t ipv4_gw_addr[4]; /* 70-73 */ |
| 715 | uint8_t reserved10[84]; /* 74-C7 */ |
| 716 | uint8_t abort_timer; /* C8 */ |
| 717 | uint8_t ipv4_tcp_wsf; /* C9 */ |
| 718 | uint8_t reserved11[10]; /* CA-D3 */ |
| 719 | uint8_t ipv4_dhcp_vid_len; /* D4 */ |
| 720 | uint8_t ipv4_dhcp_vid[11]; /* D5-DF */ |
| 721 | uint8_t reserved12[20]; /* E0-F3 */ |
| 722 | uint8_t ipv4_dhcp_alt_cid_len; /* F4 */ |
| 723 | uint8_t ipv4_dhcp_alt_cid[11]; /* F5-FF */ |
| 724 | uint8_t iscsi_name[224]; /* 100-1DF */ |
| 725 | uint8_t reserved13[32]; /* 1E0-1FF */ |
| 726 | uint32_t cookie; /* 200-203 */ |
| 727 | uint16_t ipv6_port; /* 204-205 */ |
| 728 | uint16_t ipv6_opts; /* 206-207 */ |
| 729 | uint16_t ipv6_addtl_opts; /* 208-209 */ |
| 730 | uint16_t ipv6_tcp_opts; /* 20A-20B */ |
| 731 | uint8_t ipv6_tcp_wsf; /* 20C */ |
| 732 | uint16_t ipv6_flow_lbl; /* 20D-20F */ |
| 733 | uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */ |
| 734 | uint16_t ipv6_vlan_tag; /* 220-221 */ |
| 735 | uint8_t ipv6_lnk_lcl_addr_state; /* 222 */ |
| 736 | uint8_t ipv6_addr0_state; /* 223 */ |
| 737 | uint8_t ipv6_addr1_state; /* 224 */ |
| 738 | uint8_t ipv6_dflt_rtr_state; /* 225 */ |
| 739 | uint8_t ipv6_traffic_class; /* 226 */ |
| 740 | uint8_t ipv6_hop_limit; /* 227 */ |
| 741 | uint8_t ipv6_if_id[8]; /* 228-22F */ |
| 742 | uint8_t ipv6_addr0[16]; /* 230-23F */ |
| 743 | uint8_t ipv6_addr1[16]; /* 240-24F */ |
| 744 | uint32_t ipv6_nd_reach_time; /* 250-253 */ |
| 745 | uint32_t ipv6_nd_rexmit_timer; /* 254-257 */ |
| 746 | uint32_t ipv6_nd_stale_timeout; /* 258-25B */ |
| 747 | uint8_t ipv6_dup_addr_detect_count; /* 25C */ |
| 748 | uint8_t ipv6_cache_id; /* 25D */ |
| 749 | uint8_t reserved14[18]; /* 25E-26F */ |
| 750 | uint32_t ipv6_gw_advrt_mtu; /* 270-273 */ |
| 751 | uint8_t reserved15[140]; /* 274-2FF */ |
| 752 | }; |
| 753 | |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 754 | /*************************************************************************/ |
| 755 | |
Manish Rangankar | b3a271a | 2011-07-25 13:48:53 -0500 | [diff] [blame] | 756 | #define MAX_CHAP_ENTRIES_40XX 128 |
| 757 | #define MAX_CHAP_ENTRIES_82XX 1024 |
Lalit Chandivade | 4549415 | 2011-10-07 16:55:42 -0700 | [diff] [blame] | 758 | #define MAX_RESRV_CHAP_IDX 3 |
| 759 | #define FLASH_CHAP_OFFSET 0x06000000 |
Manish Rangankar | b3a271a | 2011-07-25 13:48:53 -0500 | [diff] [blame] | 760 | |
| 761 | struct ql4_chap_table { |
| 762 | uint16_t link; |
| 763 | uint8_t flags; |
| 764 | uint8_t secret_len; |
| 765 | #define MIN_CHAP_SECRET_LEN 12 |
| 766 | #define MAX_CHAP_SECRET_LEN 100 |
| 767 | uint8_t secret[MAX_CHAP_SECRET_LEN]; |
| 768 | #define MAX_CHAP_NAME_LEN 256 |
| 769 | uint8_t name[MAX_CHAP_NAME_LEN]; |
| 770 | uint16_t reserved; |
| 771 | #define CHAP_VALID_COOKIE 0x4092 |
| 772 | #define CHAP_INVALID_COOKIE 0xFFEE |
| 773 | uint16_t cookie; |
| 774 | }; |
| 775 | |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 776 | struct dev_db_entry { |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 777 | uint16_t options; /* 00-01 */ |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 778 | #define DDB_OPT_DISC_SESSION 0x10 |
| 779 | #define DDB_OPT_TARGET 0x02 /* device is a target */ |
Vikas Chaudhary | 2a49a78 | 2010-04-28 11:37:07 +0530 | [diff] [blame] | 780 | #define DDB_OPT_IPV6_DEVICE 0x100 |
Manish Rangankar | b3a271a | 2011-07-25 13:48:53 -0500 | [diff] [blame] | 781 | #define DDB_OPT_AUTO_SENDTGTS_DISABLE 0x40 |
Vikas Chaudhary | 2a49a78 | 2010-04-28 11:37:07 +0530 | [diff] [blame] | 782 | #define DDB_OPT_IPV6_NULL_LINK_LOCAL 0x800 /* post connection */ |
| 783 | #define DDB_OPT_IPV6_FW_DEFINED_LINK_LOCAL 0x800 /* pre connection */ |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 784 | |
Adheer Chandravanshi | 1e9e2be | 2013-03-22 07:41:31 -0400 | [diff] [blame^] | 785 | #define OPT_IS_FW_ASSIGNED_IPV6 11 |
| 786 | #define OPT_IPV6_DEVICE 8 |
| 787 | #define OPT_AUTO_SENDTGTS_DISABLE 6 |
| 788 | #define OPT_DISC_SESSION 4 |
| 789 | #define OPT_ENTRY_STATE 3 |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 790 | uint16_t exec_throttle; /* 02-03 */ |
| 791 | uint16_t exec_count; /* 04-05 */ |
| 792 | uint16_t res0; /* 06-07 */ |
| 793 | uint16_t iscsi_options; /* 08-09 */ |
Adheer Chandravanshi | 1e9e2be | 2013-03-22 07:41:31 -0400 | [diff] [blame^] | 794 | #define ISCSIOPT_HEADER_DIGEST_EN 13 |
| 795 | #define ISCSIOPT_DATA_DIGEST_EN 12 |
| 796 | #define ISCSIOPT_IMMEDIATE_DATA_EN 11 |
| 797 | #define ISCSIOPT_INITIAL_R2T_EN 10 |
| 798 | #define ISCSIOPT_DATA_SEQ_IN_ORDER 9 |
| 799 | #define ISCSIOPT_DATA_PDU_IN_ORDER 8 |
| 800 | #define ISCSIOPT_CHAP_AUTH_EN 7 |
| 801 | #define ISCSIOPT_SNACK_REQ_EN 6 |
| 802 | #define ISCSIOPT_DISCOVERY_LOGOUT_EN 5 |
| 803 | #define ISCSIOPT_BIDI_CHAP_EN 4 |
| 804 | #define ISCSIOPT_DISCOVERY_AUTH_OPTIONAL 3 |
| 805 | #define ISCSIOPT_ERL1 1 |
| 806 | #define ISCSIOPT_ERL0 0 |
| 807 | |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 808 | uint16_t tcp_options; /* 0A-0B */ |
Adheer Chandravanshi | 1e9e2be | 2013-03-22 07:41:31 -0400 | [diff] [blame^] | 809 | #define TCPOPT_TIMESTAMP_STAT 6 |
| 810 | #define TCPOPT_NAGLE_DISABLE 5 |
| 811 | #define TCPOPT_WSF_DISABLE 4 |
| 812 | #define TCPOPT_TIMER_SCALE3 3 |
| 813 | #define TCPOPT_TIMER_SCALE2 2 |
| 814 | #define TCPOPT_TIMER_SCALE1 1 |
| 815 | #define TCPOPT_TIMESTAMP_EN 0 |
| 816 | |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 817 | uint16_t ip_options; /* 0C-0D */ |
Adheer Chandravanshi | 1e9e2be | 2013-03-22 07:41:31 -0400 | [diff] [blame^] | 818 | #define IPOPT_FRAGMENT_DISABLE 4 |
| 819 | |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 820 | uint16_t iscsi_max_rcv_data_seg_len; /* 0E-0F */ |
Manish Rangankar | b3a271a | 2011-07-25 13:48:53 -0500 | [diff] [blame] | 821 | #define BYTE_UNITS 512 |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 822 | uint32_t res1; /* 10-13 */ |
| 823 | uint16_t iscsi_max_snd_data_seg_len; /* 14-15 */ |
| 824 | uint16_t iscsi_first_burst_len; /* 16-17 */ |
| 825 | uint16_t iscsi_def_time2wait; /* 18-19 */ |
| 826 | uint16_t iscsi_def_time2retain; /* 1A-1B */ |
| 827 | uint16_t iscsi_max_outsnd_r2t; /* 1C-1D */ |
| 828 | uint16_t ka_timeout; /* 1E-1F */ |
| 829 | uint8_t isid[6]; /* 20-25 big-endian, must be converted |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 830 | * to little-endian */ |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 831 | uint16_t tsid; /* 26-27 */ |
| 832 | uint16_t port; /* 28-29 */ |
| 833 | uint16_t iscsi_max_burst_len; /* 2A-2B */ |
| 834 | uint16_t def_timeout; /* 2C-2D */ |
| 835 | uint16_t res2; /* 2E-2F */ |
| 836 | uint8_t ip_addr[0x10]; /* 30-3F */ |
| 837 | uint8_t iscsi_alias[0x20]; /* 40-5F */ |
| 838 | uint8_t tgt_addr[0x20]; /* 60-7F */ |
| 839 | uint16_t mss; /* 80-81 */ |
| 840 | uint16_t res3; /* 82-83 */ |
| 841 | uint16_t lcl_port; /* 84-85 */ |
| 842 | uint8_t ipv4_tos; /* 86 */ |
| 843 | uint16_t ipv6_flow_lbl; /* 87-89 */ |
| 844 | uint8_t res4[0x36]; /* 8A-BF */ |
| 845 | uint8_t iscsi_name[0xE0]; /* C0-19F : xxzzy Make this a |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 846 | * pointer to a string so we |
Justin P. Mattock | 42b2aa8 | 2011-11-28 20:31:00 -0800 | [diff] [blame] | 847 | * don't have to reserve so |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 848 | * much RAM */ |
Vikas Chaudhary | 2a49a78 | 2010-04-28 11:37:07 +0530 | [diff] [blame] | 849 | uint8_t link_local_ipv6_addr[0x10]; /* 1A0-1AF */ |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 850 | uint8_t res5[0x10]; /* 1B0-1BF */ |
Adheer Chandravanshi | 1e9e2be | 2013-03-22 07:41:31 -0400 | [diff] [blame^] | 851 | #define DDB_NO_LINK 0xFFFF |
| 852 | #define DDB_ISNS 0xFFFD |
David C Somayajulu | b285431 | 2007-05-23 17:52:26 -0700 | [diff] [blame] | 853 | uint16_t ddb_link; /* 1C0-1C1 */ |
| 854 | uint16_t chap_tbl_idx; /* 1C2-1C3 */ |
| 855 | uint16_t tgt_portal_grp; /* 1C4-1C5 */ |
| 856 | uint8_t tcp_xmt_wsf; /* 1C6 */ |
| 857 | uint8_t tcp_rcv_wsf; /* 1C7 */ |
| 858 | uint32_t stat_sn; /* 1C8-1CB */ |
| 859 | uint32_t exp_stat_sn; /* 1CC-1CF */ |
Manish Rangankar | 2a991c2 | 2011-07-25 13:48:55 -0500 | [diff] [blame] | 860 | uint8_t res6[0x2b]; /* 1D0-1FB */ |
| 861 | #define DDB_VALID_COOKIE 0x9034 |
| 862 | uint16_t cookie; /* 1FC-1FD */ |
| 863 | uint16_t len; /* 1FE-1FF */ |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 864 | }; |
| 865 | |
| 866 | /*************************************************************************/ |
| 867 | |
| 868 | /* Flash definitions */ |
| 869 | |
| 870 | #define FLASH_OFFSET_SYS_INFO 0x02000000 |
| 871 | #define FLASH_DEFAULTBLOCKSIZE 0x20000 |
| 872 | #define FLASH_EOF_OFFSET (FLASH_DEFAULTBLOCKSIZE-8) /* 4 bytes |
| 873 | * for EOF |
| 874 | * signature */ |
Manish Rangankar | 2a991c2 | 2011-07-25 13:48:55 -0500 | [diff] [blame] | 875 | #define FLASH_RAW_ACCESS_ADDR 0x8e000000 |
| 876 | |
| 877 | #define BOOT_PARAM_OFFSET_PORT0 0x3b0 |
| 878 | #define BOOT_PARAM_OFFSET_PORT1 0x7b0 |
| 879 | |
| 880 | #define FLASH_OFFSET_DB_INFO 0x05000000 |
| 881 | #define FLASH_OFFSET_DB_END (FLASH_OFFSET_DB_INFO + 0x7fff) |
| 882 | |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 883 | |
| 884 | struct sys_info_phys_addr { |
| 885 | uint8_t address[6]; /* 00-05 */ |
| 886 | uint8_t filler[2]; /* 06-07 */ |
| 887 | }; |
| 888 | |
| 889 | struct flash_sys_info { |
| 890 | uint32_t cookie; /* 00-03 */ |
| 891 | uint32_t physAddrCount; /* 04-07 */ |
| 892 | struct sys_info_phys_addr physAddr[4]; /* 08-27 */ |
| 893 | uint8_t vendorId[128]; /* 28-A7 */ |
| 894 | uint8_t productId[128]; /* A8-127 */ |
| 895 | uint32_t serialNumber; /* 128-12B */ |
| 896 | |
| 897 | /* PCI Configuration values */ |
| 898 | uint32_t pciDeviceVendor; /* 12C-12F */ |
| 899 | uint32_t pciDeviceId; /* 130-133 */ |
| 900 | uint32_t pciSubsysVendor; /* 134-137 */ |
| 901 | uint32_t pciSubsysId; /* 138-13B */ |
| 902 | |
| 903 | /* This validates version 1. */ |
| 904 | uint32_t crumbs; /* 13C-13F */ |
| 905 | |
| 906 | uint32_t enterpriseNumber; /* 140-143 */ |
| 907 | |
| 908 | uint32_t mtu; /* 144-147 */ |
| 909 | uint32_t reserved0; /* 148-14b */ |
| 910 | uint32_t crumbs2; /* 14c-14f */ |
| 911 | uint8_t acSerialNumber[16]; /* 150-15f */ |
| 912 | uint32_t crumbs3; /* 160-16f */ |
| 913 | |
| 914 | /* Leave this last in the struct so it is declared invalid if |
| 915 | * any new items are added. |
| 916 | */ |
| 917 | uint32_t reserved1[39]; /* 170-1ff */ |
| 918 | }; /* 200 */ |
| 919 | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 920 | struct mbx_sys_info { |
Vikas Chaudhary | 2ccdf0d | 2010-07-30 14:27:45 +0530 | [diff] [blame] | 921 | uint8_t board_id_str[16]; /* 0-f Keep board ID string first */ |
| 922 | /* in this structure for GUI. */ |
| 923 | uint16_t board_id; /* 10-11 board ID code */ |
| 924 | uint16_t phys_port_cnt; /* 12-13 number of physical network ports */ |
| 925 | uint16_t port_num; /* 14-15 network port for this PCI function */ |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 926 | /* (port 0 is first port) */ |
Vikas Chaudhary | 2ccdf0d | 2010-07-30 14:27:45 +0530 | [diff] [blame] | 927 | uint8_t mac_addr[6]; /* 16-1b MAC address for this PCI function */ |
| 928 | uint32_t iscsi_pci_func_cnt; /* 1c-1f number of iSCSI PCI functions */ |
| 929 | uint32_t pci_func; /* 20-23 this PCI function */ |
| 930 | unsigned char serial_number[16]; /* 24-33 serial number string */ |
| 931 | uint8_t reserved[12]; /* 34-3f */ |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 932 | }; |
| 933 | |
Harish Zunjarrao | 7ad633c | 2011-05-17 23:17:11 -0700 | [diff] [blame] | 934 | struct about_fw_info { |
| 935 | uint16_t fw_major; /* 00 - 01 */ |
| 936 | uint16_t fw_minor; /* 02 - 03 */ |
| 937 | uint16_t fw_patch; /* 04 - 05 */ |
| 938 | uint16_t fw_build; /* 06 - 07 */ |
| 939 | uint8_t fw_build_date[16]; /* 08 - 17 ASCII String */ |
| 940 | uint8_t fw_build_time[16]; /* 18 - 27 ASCII String */ |
| 941 | uint8_t fw_build_user[16]; /* 28 - 37 ASCII String */ |
| 942 | uint16_t fw_load_source; /* 38 - 39 */ |
| 943 | /* 1 = Flash Primary, |
| 944 | 2 = Flash Secondary, |
| 945 | 3 = Host Download |
| 946 | */ |
| 947 | uint8_t reserved1[6]; /* 3A - 3F */ |
| 948 | uint16_t iscsi_major; /* 40 - 41 */ |
| 949 | uint16_t iscsi_minor; /* 42 - 43 */ |
| 950 | uint16_t bootload_major; /* 44 - 45 */ |
| 951 | uint16_t bootload_minor; /* 46 - 47 */ |
| 952 | uint16_t bootload_patch; /* 48 - 49 */ |
| 953 | uint16_t bootload_build; /* 4A - 4B */ |
| 954 | uint8_t reserved2[180]; /* 4C - FF */ |
| 955 | }; |
| 956 | |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 957 | struct crash_record { |
| 958 | uint16_t fw_major_version; /* 00 - 01 */ |
| 959 | uint16_t fw_minor_version; /* 02 - 03 */ |
| 960 | uint16_t fw_patch_version; /* 04 - 05 */ |
| 961 | uint16_t fw_build_version; /* 06 - 07 */ |
| 962 | |
| 963 | uint8_t build_date[16]; /* 08 - 17 */ |
| 964 | uint8_t build_time[16]; /* 18 - 27 */ |
| 965 | uint8_t build_user[16]; /* 28 - 37 */ |
| 966 | uint8_t card_serial_num[16]; /* 38 - 47 */ |
| 967 | |
| 968 | uint32_t time_of_crash_in_secs; /* 48 - 4B */ |
| 969 | uint32_t time_of_crash_in_ms; /* 4C - 4F */ |
| 970 | |
| 971 | uint16_t out_RISC_sd_num_frames; /* 50 - 51 */ |
| 972 | uint16_t OAP_sd_num_words; /* 52 - 53 */ |
| 973 | uint16_t IAP_sd_num_frames; /* 54 - 55 */ |
| 974 | uint16_t in_RISC_sd_num_words; /* 56 - 57 */ |
| 975 | |
| 976 | uint8_t reserved1[28]; /* 58 - 7F */ |
| 977 | |
| 978 | uint8_t out_RISC_reg_dump[256]; /* 80 -17F */ |
| 979 | uint8_t in_RISC_reg_dump[256]; /*180 -27F */ |
| 980 | uint8_t in_out_RISC_stack_dump[0]; /*280 - ??? */ |
| 981 | }; |
| 982 | |
| 983 | struct conn_event_log_entry { |
| 984 | #define MAX_CONN_EVENT_LOG_ENTRIES 100 |
| 985 | uint32_t timestamp_sec; /* 00 - 03 seconds since boot */ |
| 986 | uint32_t timestamp_ms; /* 04 - 07 milliseconds since boot */ |
| 987 | uint16_t device_index; /* 08 - 09 */ |
| 988 | uint16_t fw_conn_state; /* 0A - 0B */ |
| 989 | uint8_t event_type; /* 0C - 0C */ |
| 990 | uint8_t error_code; /* 0D - 0D */ |
| 991 | uint16_t error_code_detail; /* 0E - 0F */ |
| 992 | uint8_t num_consecutive_events; /* 10 - 10 */ |
| 993 | uint8_t rsvd[3]; /* 11 - 13 */ |
| 994 | }; |
| 995 | |
| 996 | /************************************************************************* |
| 997 | * |
| 998 | * IOCB Commands Structures and Definitions |
| 999 | * |
| 1000 | *************************************************************************/ |
| 1001 | #define IOCB_MAX_CDB_LEN 16 /* Bytes in a CBD */ |
| 1002 | #define IOCB_MAX_SENSEDATA_LEN 32 /* Bytes of sense data */ |
Karen Higgins | 94bced3 | 2009-07-15 15:02:58 -0500 | [diff] [blame] | 1003 | #define IOCB_MAX_EXT_SENSEDATA_LEN 60 /* Bytes of extended sense data */ |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 1004 | |
| 1005 | /* IOCB header structure */ |
| 1006 | struct qla4_header { |
| 1007 | uint8_t entryType; |
| 1008 | #define ET_STATUS 0x03 |
| 1009 | #define ET_MARKER 0x04 |
| 1010 | #define ET_CONT_T1 0x0A |
| 1011 | #define ET_STATUS_CONTINUATION 0x10 |
| 1012 | #define ET_CMND_T3 0x19 |
| 1013 | #define ET_PASSTHRU0 0x3A |
| 1014 | #define ET_PASSTHRU_STATUS 0x3C |
Vikas Chaudhary | c0b9d3f | 2012-02-13 18:30:49 +0530 | [diff] [blame] | 1015 | #define ET_MBOX_CMD 0x38 |
| 1016 | #define ET_MBOX_STATUS 0x39 |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 1017 | |
| 1018 | uint8_t entryStatus; |
| 1019 | uint8_t systemDefined; |
Manish Rangankar | b3a271a | 2011-07-25 13:48:53 -0500 | [diff] [blame] | 1020 | #define SD_ISCSI_PDU 0x01 |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 1021 | uint8_t entryCount; |
| 1022 | |
| 1023 | /* SyetemDefined definition */ |
| 1024 | }; |
| 1025 | |
| 1026 | /* Generic queue entry structure*/ |
| 1027 | struct queue_entry { |
| 1028 | uint8_t data[60]; |
| 1029 | uint32_t signature; |
| 1030 | |
| 1031 | }; |
| 1032 | |
| 1033 | /* 64 bit addressing segment counts*/ |
| 1034 | |
| 1035 | #define COMMAND_SEG_A64 1 |
| 1036 | #define CONTINUE_SEG_A64 5 |
| 1037 | |
| 1038 | /* 64 bit addressing segment definition*/ |
| 1039 | |
| 1040 | struct data_seg_a64 { |
| 1041 | struct { |
| 1042 | uint32_t addrLow; |
| 1043 | uint32_t addrHigh; |
| 1044 | |
| 1045 | } base; |
| 1046 | |
| 1047 | uint32_t count; |
| 1048 | |
| 1049 | }; |
| 1050 | |
| 1051 | /* Command Type 3 entry structure*/ |
| 1052 | |
| 1053 | struct command_t3_entry { |
| 1054 | struct qla4_header hdr; /* 00-03 */ |
| 1055 | |
| 1056 | uint32_t handle; /* 04-07 */ |
| 1057 | uint16_t target; /* 08-09 */ |
| 1058 | uint16_t connection_id; /* 0A-0B */ |
| 1059 | |
| 1060 | uint8_t control_flags; /* 0C */ |
| 1061 | |
| 1062 | /* data direction (bits 5-6) */ |
| 1063 | #define CF_WRITE 0x20 |
| 1064 | #define CF_READ 0x40 |
| 1065 | #define CF_NO_DATA 0x00 |
| 1066 | |
| 1067 | /* task attributes (bits 2-0) */ |
| 1068 | #define CF_HEAD_TAG 0x03 |
| 1069 | #define CF_ORDERED_TAG 0x02 |
| 1070 | #define CF_SIMPLE_TAG 0x01 |
| 1071 | |
| 1072 | /* STATE FLAGS FIELD IS A PLACE HOLDER. THE FW WILL SET BITS |
| 1073 | * IN THIS FIELD AS THE COMMAND IS PROCESSED. WHEN THE IOCB IS |
| 1074 | * CHANGED TO AN IOSB THIS FIELD WILL HAVE THE STATE FLAGS SET |
| 1075 | * PROPERLY. |
| 1076 | */ |
| 1077 | uint8_t state_flags; /* 0D */ |
| 1078 | uint8_t cmdRefNum; /* 0E */ |
| 1079 | uint8_t reserved1; /* 0F */ |
| 1080 | uint8_t cdb[IOCB_MAX_CDB_LEN]; /* 10-1F */ |
| 1081 | struct scsi_lun lun; /* FCP LUN (BE). */ |
| 1082 | uint32_t cmdSeqNum; /* 28-2B */ |
| 1083 | uint16_t timeout; /* 2C-2D */ |
| 1084 | uint16_t dataSegCnt; /* 2E-2F */ |
| 1085 | uint32_t ttlByteCnt; /* 30-33 */ |
| 1086 | struct data_seg_a64 dataseg[COMMAND_SEG_A64]; /* 34-3F */ |
| 1087 | |
| 1088 | }; |
| 1089 | |
| 1090 | |
| 1091 | /* Continuation Type 1 entry structure*/ |
| 1092 | struct continuation_t1_entry { |
| 1093 | struct qla4_header hdr; |
| 1094 | |
| 1095 | struct data_seg_a64 dataseg[CONTINUE_SEG_A64]; |
| 1096 | |
| 1097 | }; |
| 1098 | |
| 1099 | /* Parameterize for 64 or 32 bits */ |
| 1100 | #define COMMAND_SEG COMMAND_SEG_A64 |
| 1101 | #define CONTINUE_SEG CONTINUE_SEG_A64 |
| 1102 | |
| 1103 | #define ET_COMMAND ET_CMND_T3 |
| 1104 | #define ET_CONTINUE ET_CONT_T1 |
| 1105 | |
| 1106 | /* Marker entry structure*/ |
Mathieu Desnoyers | 1c3f0b8 | 2007-10-18 23:41:04 -0700 | [diff] [blame] | 1107 | struct qla4_marker_entry { |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 1108 | struct qla4_header hdr; /* 00-03 */ |
| 1109 | |
| 1110 | uint32_t system_defined; /* 04-07 */ |
| 1111 | uint16_t target; /* 08-09 */ |
| 1112 | uint16_t modifier; /* 0A-0B */ |
David C Somayajulu | 9d56291 | 2008-03-19 11:23:03 -0700 | [diff] [blame] | 1113 | #define MM_LUN_RESET 0 |
| 1114 | #define MM_TGT_WARM_RESET 1 |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 1115 | |
| 1116 | uint16_t flags; /* 0C-0D */ |
| 1117 | uint16_t reserved1; /* 0E-0F */ |
| 1118 | struct scsi_lun lun; /* FCP LUN (BE). */ |
| 1119 | uint64_t reserved2; /* 18-1F */ |
| 1120 | uint64_t reserved3; /* 20-27 */ |
| 1121 | uint64_t reserved4; /* 28-2F */ |
| 1122 | uint64_t reserved5; /* 30-37 */ |
| 1123 | uint64_t reserved6; /* 38-3F */ |
| 1124 | }; |
| 1125 | |
| 1126 | /* Status entry structure*/ |
| 1127 | struct status_entry { |
| 1128 | struct qla4_header hdr; /* 00-03 */ |
| 1129 | |
| 1130 | uint32_t handle; /* 04-07 */ |
| 1131 | |
| 1132 | uint8_t scsiStatus; /* 08 */ |
| 1133 | #define SCSI_CHECK_CONDITION 0x02 |
| 1134 | |
| 1135 | uint8_t iscsiFlags; /* 09 */ |
| 1136 | #define ISCSI_FLAG_RESIDUAL_UNDER 0x02 |
| 1137 | #define ISCSI_FLAG_RESIDUAL_OVER 0x04 |
| 1138 | |
| 1139 | uint8_t iscsiResponse; /* 0A */ |
| 1140 | |
| 1141 | uint8_t completionStatus; /* 0B */ |
| 1142 | #define SCS_COMPLETE 0x00 |
| 1143 | #define SCS_INCOMPLETE 0x01 |
| 1144 | #define SCS_RESET_OCCURRED 0x04 |
| 1145 | #define SCS_ABORTED 0x05 |
| 1146 | #define SCS_TIMEOUT 0x06 |
| 1147 | #define SCS_DATA_OVERRUN 0x07 |
| 1148 | #define SCS_DATA_UNDERRUN 0x15 |
| 1149 | #define SCS_QUEUE_FULL 0x1C |
| 1150 | #define SCS_DEVICE_UNAVAILABLE 0x28 |
| 1151 | #define SCS_DEVICE_LOGGED_OUT 0x29 |
| 1152 | |
| 1153 | uint8_t reserved1; /* 0C */ |
| 1154 | |
| 1155 | /* state_flags MUST be at the same location as state_flags in |
| 1156 | * the Command_T3/4_Entry */ |
| 1157 | uint8_t state_flags; /* 0D */ |
| 1158 | |
| 1159 | uint16_t senseDataByteCnt; /* 0E-0F */ |
| 1160 | uint32_t residualByteCnt; /* 10-13 */ |
| 1161 | uint32_t bidiResidualByteCnt; /* 14-17 */ |
| 1162 | uint32_t expSeqNum; /* 18-1B */ |
| 1163 | uint32_t maxCmdSeqNum; /* 1C-1F */ |
| 1164 | uint8_t senseData[IOCB_MAX_SENSEDATA_LEN]; /* 20-3F */ |
| 1165 | |
| 1166 | }; |
| 1167 | |
Karen Higgins | 94bced3 | 2009-07-15 15:02:58 -0500 | [diff] [blame] | 1168 | /* Status Continuation entry */ |
| 1169 | struct status_cont_entry { |
| 1170 | struct qla4_header hdr; /* 00-03 */ |
| 1171 | uint8_t ext_sense_data[IOCB_MAX_EXT_SENSEDATA_LEN]; /* 04-63 */ |
| 1172 | }; |
| 1173 | |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 1174 | struct passthru0 { |
| 1175 | struct qla4_header hdr; /* 00-03 */ |
| 1176 | uint32_t handle; /* 04-07 */ |
| 1177 | uint16_t target; /* 08-09 */ |
Manish Rangankar | b3a271a | 2011-07-25 13:48:53 -0500 | [diff] [blame] | 1178 | uint16_t connection_id; /* 0A-0B */ |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 1179 | #define ISNS_DEFAULT_SERVER_CONN_ID ((uint16_t)0x8000) |
| 1180 | |
Manish Rangankar | b3a271a | 2011-07-25 13:48:53 -0500 | [diff] [blame] | 1181 | uint16_t control_flags; /* 0C-0D */ |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 1182 | #define PT_FLAG_ETHERNET_FRAME 0x8000 |
| 1183 | #define PT_FLAG_ISNS_PDU 0x8000 |
| 1184 | #define PT_FLAG_SEND_BUFFER 0x0200 |
| 1185 | #define PT_FLAG_WAIT_4_RESPONSE 0x0100 |
Manish Rangankar | b3a271a | 2011-07-25 13:48:53 -0500 | [diff] [blame] | 1186 | #define PT_FLAG_ISCSI_PDU 0x1000 |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 1187 | |
| 1188 | uint16_t timeout; /* 0E-0F */ |
| 1189 | #define PT_DEFAULT_TIMEOUT 30 /* seconds */ |
| 1190 | |
Manish Rangankar | b3a271a | 2011-07-25 13:48:53 -0500 | [diff] [blame] | 1191 | struct data_seg_a64 out_dsd; /* 10-1B */ |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 1192 | uint32_t res1; /* 1C-1F */ |
Manish Rangankar | b3a271a | 2011-07-25 13:48:53 -0500 | [diff] [blame] | 1193 | struct data_seg_a64 in_dsd; /* 20-2B */ |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 1194 | uint8_t res2[20]; /* 2C-3F */ |
| 1195 | }; |
| 1196 | |
| 1197 | struct passthru_status { |
| 1198 | struct qla4_header hdr; /* 00-03 */ |
| 1199 | uint32_t handle; /* 04-07 */ |
| 1200 | uint16_t target; /* 08-09 */ |
| 1201 | uint16_t connectionID; /* 0A-0B */ |
| 1202 | |
| 1203 | uint8_t completionStatus; /* 0C */ |
| 1204 | #define PASSTHRU_STATUS_COMPLETE 0x01 |
| 1205 | |
| 1206 | uint8_t residualFlags; /* 0D */ |
| 1207 | |
| 1208 | uint16_t timeout; /* 0E-0F */ |
| 1209 | uint16_t portNumber; /* 10-11 */ |
| 1210 | uint8_t res1[10]; /* 12-1B */ |
| 1211 | uint32_t outResidual; /* 1C-1F */ |
| 1212 | uint8_t res2[12]; /* 20-2B */ |
| 1213 | uint32_t inResidual; /* 2C-2F */ |
| 1214 | uint8_t res4[16]; /* 30-3F */ |
| 1215 | }; |
| 1216 | |
Vikas Chaudhary | c0b9d3f | 2012-02-13 18:30:49 +0530 | [diff] [blame] | 1217 | struct mbox_cmd_iocb { |
| 1218 | struct qla4_header hdr; /* 00-03 */ |
| 1219 | uint32_t handle; /* 04-07 */ |
| 1220 | uint32_t in_mbox[8]; /* 08-25 */ |
| 1221 | uint32_t res1[6]; /* 26-3F */ |
| 1222 | }; |
| 1223 | |
| 1224 | struct mbox_status_iocb { |
| 1225 | struct qla4_header hdr; /* 00-03 */ |
| 1226 | uint32_t handle; /* 04-07 */ |
| 1227 | uint32_t out_mbox[8]; /* 08-25 */ |
| 1228 | uint32_t res1[6]; /* 26-3F */ |
| 1229 | }; |
| 1230 | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1231 | /* |
| 1232 | * ISP queue - response queue entry definition. |
| 1233 | */ |
| 1234 | struct response { |
| 1235 | uint8_t data[60]; |
| 1236 | uint32_t signature; |
| 1237 | #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ |
| 1238 | }; |
| 1239 | |
Manish Rangankar | b3a271a | 2011-07-25 13:48:53 -0500 | [diff] [blame] | 1240 | struct ql_iscsi_stats { |
| 1241 | uint8_t reserved1[656]; /* 0000-028F */ |
| 1242 | uint32_t tx_cmd_pdu; /* 0290-0293 */ |
| 1243 | uint32_t tx_resp_pdu; /* 0294-0297 */ |
| 1244 | uint32_t rx_cmd_pdu; /* 0298-029B */ |
| 1245 | uint32_t rx_resp_pdu; /* 029C-029F */ |
| 1246 | |
| 1247 | uint64_t tx_data_octets; /* 02A0-02A7 */ |
| 1248 | uint64_t rx_data_octets; /* 02A8-02AF */ |
| 1249 | |
| 1250 | uint32_t hdr_digest_err; /* 02B0–02B3 */ |
| 1251 | uint32_t data_digest_err; /* 02B4–02B7 */ |
| 1252 | uint32_t conn_timeout_err; /* 02B8–02BB */ |
| 1253 | uint32_t framing_err; /* 02BC–02BF */ |
| 1254 | |
| 1255 | uint32_t tx_nopout_pdus; /* 02C0–02C3 */ |
| 1256 | uint32_t tx_scsi_cmd_pdus; /* 02C4–02C7 */ |
| 1257 | uint32_t tx_tmf_cmd_pdus; /* 02C8–02CB */ |
| 1258 | uint32_t tx_login_cmd_pdus; /* 02CC–02CF */ |
| 1259 | uint32_t tx_text_cmd_pdus; /* 02D0–02D3 */ |
| 1260 | uint32_t tx_scsi_write_pdus; /* 02D4–02D7 */ |
| 1261 | uint32_t tx_logout_cmd_pdus; /* 02D8–02DB */ |
| 1262 | uint32_t tx_snack_req_pdus; /* 02DC–02DF */ |
| 1263 | |
| 1264 | uint32_t rx_nopin_pdus; /* 02E0–02E3 */ |
| 1265 | uint32_t rx_scsi_resp_pdus; /* 02E4–02E7 */ |
| 1266 | uint32_t rx_tmf_resp_pdus; /* 02E8–02EB */ |
| 1267 | uint32_t rx_login_resp_pdus; /* 02EC–02EF */ |
| 1268 | uint32_t rx_text_resp_pdus; /* 02F0–02F3 */ |
| 1269 | uint32_t rx_scsi_read_pdus; /* 02F4–02F7 */ |
| 1270 | uint32_t rx_logout_resp_pdus; /* 02F8–02FB */ |
| 1271 | |
| 1272 | uint32_t rx_r2t_pdus; /* 02FC–02FF */ |
| 1273 | uint32_t rx_async_pdus; /* 0300–0303 */ |
| 1274 | uint32_t rx_reject_pdus; /* 0304–0307 */ |
| 1275 | |
| 1276 | uint8_t reserved2[264]; /* 0x0308 - 0x040F */ |
| 1277 | }; |
| 1278 | |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 1279 | #define QLA8XXX_DBG_STATE_ARRAY_LEN 16 |
| 1280 | #define QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN 8 |
| 1281 | #define QLA8XXX_DBG_RSVD_ARRAY_LEN 8 |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 1282 | #define QLA83XX_DBG_OCM_WNDREG_ARRAY_LEN 16 |
| 1283 | #define QLA83XX_SS_OCM_WNDREG_INDEX 3 |
| 1284 | #define QLA83XX_SS_PCI_INDEX 0 |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1285 | |
| 1286 | struct qla4_8xxx_minidump_template_hdr { |
| 1287 | uint32_t entry_type; |
| 1288 | uint32_t first_entry_offset; |
| 1289 | uint32_t size_of_template; |
| 1290 | uint32_t capture_debug_level; |
| 1291 | uint32_t num_of_entries; |
| 1292 | uint32_t version; |
| 1293 | uint32_t driver_timestamp; |
| 1294 | uint32_t checksum; |
| 1295 | |
| 1296 | uint32_t driver_capture_mask; |
| 1297 | uint32_t driver_info_word2; |
| 1298 | uint32_t driver_info_word3; |
| 1299 | uint32_t driver_info_word4; |
| 1300 | |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 1301 | uint32_t saved_state_array[QLA8XXX_DBG_STATE_ARRAY_LEN]; |
| 1302 | uint32_t capture_size_array[QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN]; |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 1303 | uint32_t ocm_window_reg[QLA83XX_DBG_OCM_WNDREG_ARRAY_LEN]; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1304 | }; |
| 1305 | |
David Somayajulu | afaf5a2 | 2006-09-19 10:28:00 -0700 | [diff] [blame] | 1306 | #endif /* _QLA4X_FW_H */ |