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Luciano Coelhof5fc0f82009-08-06 16:25:28 +03001/*
2 * This file is part of wl1271
3 *
4 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
5 * Copyright (C) 2008-2009 Nokia Corporation
6 *
7 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25#ifndef __WL1271_H__
26#define __WL1271_H__
27
28#include <linux/mutex.h>
29#include <linux/completion.h>
30#include <linux/spinlock.h>
31#include <linux/list.h>
32#include <linux/bitops.h>
33#include <net/mac80211.h>
34
Juuso Oikarinen2b60100b2009-10-13 12:47:39 +030035#include "wl1271_conf.h"
36
Luciano Coelhof5fc0f82009-08-06 16:25:28 +030037#define DRIVER_NAME "wl1271"
38#define DRIVER_PREFIX DRIVER_NAME ": "
39
40enum {
41 DEBUG_NONE = 0,
42 DEBUG_IRQ = BIT(0),
43 DEBUG_SPI = BIT(1),
44 DEBUG_BOOT = BIT(2),
45 DEBUG_MAILBOX = BIT(3),
46 DEBUG_NETLINK = BIT(4),
47 DEBUG_EVENT = BIT(5),
48 DEBUG_TX = BIT(6),
49 DEBUG_RX = BIT(7),
50 DEBUG_SCAN = BIT(8),
51 DEBUG_CRYPT = BIT(9),
52 DEBUG_PSM = BIT(10),
53 DEBUG_MAC80211 = BIT(11),
54 DEBUG_CMD = BIT(12),
55 DEBUG_ACX = BIT(13),
56 DEBUG_ALL = ~0,
57};
58
59#define DEBUG_LEVEL (DEBUG_NONE)
60
61#define DEBUG_DUMP_LIMIT 1024
62
63#define wl1271_error(fmt, arg...) \
64 printk(KERN_ERR DRIVER_PREFIX "ERROR " fmt "\n", ##arg)
65
66#define wl1271_warning(fmt, arg...) \
67 printk(KERN_WARNING DRIVER_PREFIX "WARNING " fmt "\n", ##arg)
68
69#define wl1271_notice(fmt, arg...) \
70 printk(KERN_INFO DRIVER_PREFIX fmt "\n", ##arg)
71
72#define wl1271_info(fmt, arg...) \
73 printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg)
74
75#define wl1271_debug(level, fmt, arg...) \
76 do { \
77 if (level & DEBUG_LEVEL) \
78 printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg); \
79 } while (0)
80
81#define wl1271_dump(level, prefix, buf, len) \
82 do { \
83 if (level & DEBUG_LEVEL) \
84 print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
85 DUMP_PREFIX_OFFSET, 16, 1, \
86 buf, \
87 min_t(size_t, len, DEBUG_DUMP_LIMIT), \
88 0); \
89 } while (0)
90
91#define wl1271_dump_ascii(level, prefix, buf, len) \
92 do { \
93 if (level & DEBUG_LEVEL) \
94 print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
95 DUMP_PREFIX_OFFSET, 16, 1, \
96 buf, \
97 min_t(size_t, len, DEBUG_DUMP_LIMIT), \
98 true); \
99 } while (0)
100
101#define WL1271_DEFAULT_RX_CONFIG (CFG_UNI_FILTER_EN | \
Juuso Oikarinenc87dec92009-10-08 21:56:31 +0300102 CFG_BSSID_FILTER_EN | \
103 CFG_MC_FILTER_EN)
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300104
105#define WL1271_DEFAULT_RX_FILTER (CFG_RX_RCTS_ACK | CFG_RX_PRSP_EN | \
106 CFG_RX_MGMT_EN | CFG_RX_DATA_EN | \
107 CFG_RX_CTL_EN | CFG_RX_BCN_EN | \
108 CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN)
109
Juuso Oikarinen45b531a2009-10-13 12:47:41 +0300110#define WL1271_DEFAULT_BASIC_RATE_SET (CONF_TX_RATE_MASK_ALL)
Juuso Oikarinend94cd292009-10-08 21:56:25 +0300111
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300112#define WL1271_FW_NAME "wl1271-fw.bin"
113#define WL1271_NVS_NAME "wl1271-nvs.bin"
114
Juuso Oikarinen545f1da2009-10-08 21:56:23 +0300115/*
Teemu Paasikivi1ebec3d2009-10-13 12:47:48 +0300116 * Enable/disable 802.11a support for WL1273
117 */
118#undef WL1271_80211A_ENABLED
119
120/*
Juuso Oikarinen545f1da2009-10-08 21:56:23 +0300121 * FIXME: for the wl1271, a busy word count of 1 here will result in a more
122 * optimal SPI interface. There is some SPI bug however, causing RXS time outs
Juuso Oikarinenc6d5d062009-10-13 12:47:47 +0300123 * with this mode occasionally on boot, so lets have three for now. A value of
124 * three should make sure, that the chipset will always be ready, though this
125 * will impact throughput and latencies slightly.
Juuso Oikarinen545f1da2009-10-08 21:56:23 +0300126 */
Juuso Oikarinenc6d5d062009-10-13 12:47:47 +0300127#define WL1271_BUSY_WORD_CNT 3
Juuso Oikarinen545f1da2009-10-08 21:56:23 +0300128#define WL1271_BUSY_WORD_LEN (WL1271_BUSY_WORD_CNT * sizeof(u32))
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300129
130#define WL1271_ELP_HW_STATE_ASLEEP 0
131#define WL1271_ELP_HW_STATE_IRQ 1
132
Juuso Oikarinend94cd292009-10-08 21:56:25 +0300133#define WL1271_DEFAULT_BEACON_INT 100
134#define WL1271_DEFAULT_DTIM_PERIOD 1
135
Juuso Oikarinenc87dec92009-10-08 21:56:31 +0300136#define ACX_TX_DESCRIPTORS 32
Juuso Oikarinenbe7078c2009-10-08 21:56:26 +0300137
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300138enum wl1271_state {
139 WL1271_STATE_OFF,
140 WL1271_STATE_ON,
141 WL1271_STATE_PLT,
142};
143
144enum wl1271_partition_type {
145 PART_DOWN,
146 PART_WORK,
147 PART_DRPW,
148
149 PART_TABLE_LEN
150};
151
152struct wl1271_partition {
153 u32 size;
154 u32 start;
155};
156
157struct wl1271_partition_set {
158 struct wl1271_partition mem;
159 struct wl1271_partition reg;
Juuso Oikarinen451de972009-10-12 15:08:46 +0300160 struct wl1271_partition mem2;
161 struct wl1271_partition mem3;
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300162};
163
164struct wl1271;
165
166/* FIXME: I'm not sure about this structure name */
167struct wl1271_chip {
168 u32 id;
169 char fw_ver[21];
170};
171
172struct wl1271_stats {
173 struct acx_statistics *fw_stats;
174 unsigned long fw_stats_update;
175
176 unsigned int retry_count;
177 unsigned int excessive_retries;
178};
179
180struct wl1271_debugfs {
181 struct dentry *rootdir;
182 struct dentry *fw_statistics;
183
184 struct dentry *tx_internal_desc_overflow;
185
186 struct dentry *rx_out_of_mem;
187 struct dentry *rx_hdr_overflow;
188 struct dentry *rx_hw_stuck;
189 struct dentry *rx_dropped;
190 struct dentry *rx_fcs_err;
191 struct dentry *rx_xfr_hint_trig;
192 struct dentry *rx_path_reset;
193 struct dentry *rx_reset_counter;
194
195 struct dentry *dma_rx_requested;
196 struct dentry *dma_rx_errors;
197 struct dentry *dma_tx_requested;
198 struct dentry *dma_tx_errors;
199
200 struct dentry *isr_cmd_cmplt;
201 struct dentry *isr_fiqs;
202 struct dentry *isr_rx_headers;
203 struct dentry *isr_rx_mem_overflow;
204 struct dentry *isr_rx_rdys;
205 struct dentry *isr_irqs;
206 struct dentry *isr_tx_procs;
207 struct dentry *isr_decrypt_done;
208 struct dentry *isr_dma0_done;
209 struct dentry *isr_dma1_done;
210 struct dentry *isr_tx_exch_complete;
211 struct dentry *isr_commands;
212 struct dentry *isr_rx_procs;
213 struct dentry *isr_hw_pm_mode_changes;
214 struct dentry *isr_host_acknowledges;
215 struct dentry *isr_pci_pm;
216 struct dentry *isr_wakeups;
217 struct dentry *isr_low_rssi;
218
219 struct dentry *wep_addr_key_count;
220 struct dentry *wep_default_key_count;
221 /* skipping wep.reserved */
222 struct dentry *wep_key_not_found;
223 struct dentry *wep_decrypt_fail;
224 struct dentry *wep_packets;
225 struct dentry *wep_interrupt;
226
227 struct dentry *pwr_ps_enter;
228 struct dentry *pwr_elp_enter;
229 struct dentry *pwr_missing_bcns;
230 struct dentry *pwr_wake_on_host;
231 struct dentry *pwr_wake_on_timer_exp;
232 struct dentry *pwr_tx_with_ps;
233 struct dentry *pwr_tx_without_ps;
234 struct dentry *pwr_rcvd_beacons;
235 struct dentry *pwr_power_save_off;
236 struct dentry *pwr_enable_ps;
237 struct dentry *pwr_disable_ps;
238 struct dentry *pwr_fix_tsf_ps;
239 /* skipping cont_miss_bcns_spread for now */
240 struct dentry *pwr_rcvd_awake_beacons;
241
242 struct dentry *mic_rx_pkts;
243 struct dentry *mic_calc_failure;
244
245 struct dentry *aes_encrypt_fail;
246 struct dentry *aes_decrypt_fail;
247 struct dentry *aes_encrypt_packets;
248 struct dentry *aes_decrypt_packets;
249 struct dentry *aes_encrypt_interrupt;
250 struct dentry *aes_decrypt_interrupt;
251
252 struct dentry *event_heart_beat;
253 struct dentry *event_calibration;
254 struct dentry *event_rx_mismatch;
255 struct dentry *event_rx_mem_empty;
256 struct dentry *event_rx_pool;
257 struct dentry *event_oom_late;
258 struct dentry *event_phy_transmit_error;
259 struct dentry *event_tx_stuck;
260
261 struct dentry *ps_pspoll_timeouts;
262 struct dentry *ps_upsd_timeouts;
263 struct dentry *ps_upsd_max_sptime;
264 struct dentry *ps_upsd_max_apturn;
265 struct dentry *ps_pspoll_max_apturn;
266 struct dentry *ps_pspoll_utilization;
267 struct dentry *ps_upsd_utilization;
268
269 struct dentry *rxpipe_rx_prep_beacon_drop;
270 struct dentry *rxpipe_descr_host_int_trig_rx_data;
271 struct dentry *rxpipe_beacon_buffer_thres_host_int_trig_rx_data;
272 struct dentry *rxpipe_missed_beacon_host_int_trig_rx_data;
273 struct dentry *rxpipe_tx_xfr_host_int_trig_rx_data;
274
275 struct dentry *tx_queue_len;
276
277 struct dentry *retry_count;
278 struct dentry *excessive_retries;
279};
280
281#define NUM_TX_QUEUES 4
282#define NUM_RX_PKT_DESC 8
283
284/* FW status registers */
285struct wl1271_fw_status {
286 u32 intr;
287 u8 fw_rx_counter;
288 u8 drv_rx_counter;
289 u8 reserved;
290 u8 tx_results_counter;
291 u32 rx_pkt_descs[NUM_RX_PKT_DESC];
292 u32 tx_released_blks[NUM_TX_QUEUES];
293 u32 fw_localtime;
294 u32 padding[2];
295} __attribute__ ((packed));
296
297struct wl1271_rx_mem_pool_addr {
298 u32 addr;
299 u32 addr_extra;
300};
301
302struct wl1271 {
303 struct ieee80211_hw *hw;
304 bool mac80211_registered;
305
306 struct spi_device *spi;
307
308 void (*set_power)(bool enable);
309 int irq;
310
311 spinlock_t wl_lock;
312
313 enum wl1271_state state;
314 struct mutex mutex;
315
Juuso Oikarinen451de972009-10-12 15:08:46 +0300316 struct wl1271_partition_set part;
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300317
318 struct wl1271_chip chip;
319
320 int cmd_box_addr;
321 int event_box_addr;
322
323 u8 *fw;
324 size_t fw_len;
325 u8 *nvs;
326 size_t nvs_len;
327
328 u8 bssid[ETH_ALEN];
329 u8 mac_addr[ETH_ALEN];
330 u8 bss_type;
331 u8 ssid[IW_ESSID_MAX_SIZE + 1];
332 u8 ssid_len;
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300333 int channel;
334
335 struct wl1271_acx_mem_map *target_mem_map;
336
337 /* Accounting for allocated / available TX blocks on HW */
338 u32 tx_blocks_freed[NUM_TX_QUEUES];
339 u32 tx_blocks_available;
340 u8 tx_results_count;
341
342 /* Transmitted TX packets counter for chipset interface */
343 int tx_packets_count;
344
345 /* Time-offset between host and chipset clocks */
346 int time_offset;
347
348 /* Session counter for the chipset */
349 int session_counter;
350
351 /* Frames scheduled for transmission, not handled yet */
352 struct sk_buff_head tx_queue;
353 bool tx_queue_stopped;
354
355 struct work_struct tx_work;
Juuso Oikarinenc87dec92009-10-08 21:56:31 +0300356
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300357 struct work_struct filter_work;
Juuso Oikarinenc87dec92009-10-08 21:56:31 +0300358 struct wl1271_filter_params *filter_params;
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300359
360 /* Pending TX frames */
Juuso Oikarinenbe7078c2009-10-08 21:56:26 +0300361 struct sk_buff *tx_frames[ACX_TX_DESCRIPTORS];
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300362
Juuso Oikarinenac4e4ce2009-10-08 21:56:19 +0300363 /* Security sequence number counters */
364 u8 tx_security_last_seq;
365 u16 tx_security_seq_16;
366 u32 tx_security_seq_32;
367
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300368 /* FW Rx counter */
369 u32 rx_counter;
370
371 /* Rx memory pool address */
372 struct wl1271_rx_mem_pool_addr rx_mem_pool_addr;
373
374 /* The target interrupt mask */
375 struct work_struct irq_work;
376
377 /* The mbox event mask */
378 u32 event_mask;
379
380 /* Mailbox pointers */
381 u32 mbox_ptr[2];
382
383 /* Are we currently scanning */
384 bool scanning;
385
386 /* Our association ID */
387 u16 aid;
388
Juuso Oikarinend94cd292009-10-08 21:56:25 +0300389 /* currently configured rate set */
390 u32 basic_rate_set;
391
Juuso Oikarinen8a5a37a2009-10-08 21:56:24 +0300392 /* The current band */
393 enum ieee80211_band band;
394
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300395 /* Default key (for WEP) */
396 u32 default_key;
397
398 unsigned int rx_config;
399 unsigned int rx_filter;
400
401 /* is firmware in elp mode */
402 bool elp;
403
404 struct completion *elp_compl;
Juuso Oikarinen37b70a82009-10-08 21:56:21 +0300405 struct delayed_work elp_work;
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300406
407 /* we can be in psm, but not in elp, we have to differentiate */
408 bool psm;
409
410 /* PSM mode requested */
411 bool psm_requested;
412
413 /* in dBm */
414 int power_level;
415
416 struct wl1271_stats stats;
417 struct wl1271_debugfs debugfs;
418
419 u32 buffer_32;
420 u32 buffer_cmd;
Juuso Oikarinen545f1da2009-10-08 21:56:23 +0300421 u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300422 struct wl1271_rx_descriptor *rx_descriptor;
423
424 struct wl1271_fw_status *fw_status;
425 struct wl1271_tx_hw_res_if *tx_res_if;
Juuso Oikarinenb771eee2009-10-08 21:56:34 +0300426
427 struct ieee80211_vif *vif;
Luciano Coelhod6e19d12009-10-12 15:08:43 +0300428
429 /* Used for a workaround to send disconnect before rejoining */
430 bool joined;
Juuso Oikarinen2b60100b2009-10-13 12:47:39 +0300431
432 /* Current chipset configuration */
433 struct conf_drv_settings conf;
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300434};
435
436int wl1271_plt_start(struct wl1271 *wl);
437int wl1271_plt_stop(struct wl1271 *wl);
438
439#define JOIN_TIMEOUT 5000 /* 5000 milliseconds to join */
440
441#define SESSION_COUNTER_MAX 7 /* maximum value for the session counter */
442
443#define WL1271_DEFAULT_POWER_LEVEL 0
444
445#define WL1271_TX_QUEUE_MAX_LENGTH 20
446
447/* WL1271 needs a 200ms sleep after power on */
448#define WL1271_POWER_ON_SLEEP 200 /* in miliseconds */
449
Teemu Paasikivi1ebec3d2009-10-13 12:47:48 +0300450static inline bool wl1271_11a_enabled(void)
451{
452#ifdef WL1271_80211A_ENABLED
453 return true;
454#else
455 return false;
456#endif
457}
458
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300459#endif