blob: df07842172b7dff8c479d9795bc39afb6c87f5a6 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
2 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 */
8
9#ifndef _T3_H
10#define _T3_H
11
12#define TG3_64BIT_REG_HIGH 0x00UL
13#define TG3_64BIT_REG_LOW 0x04UL
14
15/* Descriptor block info. */
16#define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
17#define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
18#define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
19#define BDINFO_FLAGS_DISABLED 0x00000002
20#define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
21#define BDINFO_FLAGS_MAXLEN_SHIFT 16
22#define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
23#define TG3_BDINFO_SIZE 0x10UL
24
25#define RX_COPY_THRESHOLD 256
26
Michael Chanb5d37722006-09-27 16:06:21 -070027#define TG3_RX_INTERNAL_RING_SZ_5906 32
28
Linus Torvalds1da177e2005-04-16 15:20:36 -070029#define RX_STD_MAX_SIZE 1536
30#define RX_STD_MAX_SIZE_5705 512
31#define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */
32
33/* First 256 bytes are a mirror of PCI config space. */
34#define TG3PCI_VENDOR 0x00000000
35#define TG3PCI_VENDOR_BROADCOM 0x14e4
36#define TG3PCI_DEVICE 0x00000002
37#define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */
38#define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */
39#define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */
40#define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
41#define TG3PCI_COMMAND 0x00000004
42#define TG3PCI_STATUS 0x00000006
43#define TG3PCI_CCREVID 0x00000008
44#define TG3PCI_CACHELINESZ 0x0000000c
45#define TG3PCI_LATTIMER 0x0000000d
46#define TG3PCI_HEADERTYPE 0x0000000e
47#define TG3PCI_BIST 0x0000000f
48#define TG3PCI_BASE0_LOW 0x00000010
49#define TG3PCI_BASE0_HIGH 0x00000014
50/* 0x18 --> 0x2c unused */
51#define TG3PCI_SUBSYSVENID 0x0000002c
52#define TG3PCI_SUBSYSID 0x0000002e
53#define TG3PCI_ROMADDR 0x00000030
54#define TG3PCI_CAPLIST 0x00000034
55/* 0x35 --> 0x3c unused */
56#define TG3PCI_IRQ_LINE 0x0000003c
57#define TG3PCI_IRQ_PIN 0x0000003d
58#define TG3PCI_MIN_GNT 0x0000003e
59#define TG3PCI_MAX_LAT 0x0000003f
Matt Carlson9974a352007-10-07 23:27:28 -070060/* 0x40 --> 0x64 unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -070061#define TG3PCI_MSI_DATA 0x00000064
62/* 0x66 --> 0x68 unused */
63#define TG3PCI_MISC_HOST_CTRL 0x00000068
64#define MISC_HOST_CTRL_CLEAR_INT 0x00000001
65#define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
66#define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
67#define MISC_HOST_CTRL_WORD_SWAP 0x00000008
68#define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
69#define MISC_HOST_CTRL_CLKREG_RW 0x00000020
70#define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
71#define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
72#define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
73#define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
74#define MISC_HOST_CTRL_CHIPREV 0xffff0000
75#define MISC_HOST_CTRL_CHIPREV_SHIFT 16
76#define GET_CHIP_REV_ID(MISC_HOST_CTRL) \
77 (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
78 MISC_HOST_CTRL_CHIPREV_SHIFT)
79#define CHIPREV_ID_5700_A0 0x7000
80#define CHIPREV_ID_5700_A1 0x7001
81#define CHIPREV_ID_5700_B0 0x7100
82#define CHIPREV_ID_5700_B1 0x7101
83#define CHIPREV_ID_5700_B3 0x7102
84#define CHIPREV_ID_5700_ALTIMA 0x7104
85#define CHIPREV_ID_5700_C0 0x7200
86#define CHIPREV_ID_5701_A0 0x0000
87#define CHIPREV_ID_5701_B0 0x0100
88#define CHIPREV_ID_5701_B2 0x0102
89#define CHIPREV_ID_5701_B5 0x0105
90#define CHIPREV_ID_5703_A0 0x1000
91#define CHIPREV_ID_5703_A1 0x1001
92#define CHIPREV_ID_5703_A2 0x1002
93#define CHIPREV_ID_5703_A3 0x1003
94#define CHIPREV_ID_5704_A0 0x2000
95#define CHIPREV_ID_5704_A1 0x2001
96#define CHIPREV_ID_5704_A2 0x2002
97#define CHIPREV_ID_5704_A3 0x2003
98#define CHIPREV_ID_5705_A0 0x3000
99#define CHIPREV_ID_5705_A1 0x3001
100#define CHIPREV_ID_5705_A2 0x3002
101#define CHIPREV_ID_5705_A3 0x3003
102#define CHIPREV_ID_5750_A0 0x4000
103#define CHIPREV_ID_5750_A1 0x4001
104#define CHIPREV_ID_5750_A3 0x4003
Michael Chan52c0fd82006-06-29 20:15:54 -0700105#define CHIPREV_ID_5750_C2 0x4202
Michael Chanff645be2005-04-21 17:09:53 -0700106#define CHIPREV_ID_5752_A0_HW 0x5000
107#define CHIPREV_ID_5752_A0 0x6000
John W. Linville053d7802005-04-21 17:03:52 -0700108#define CHIPREV_ID_5752_A1 0x6001
Michael Chan7544b092007-05-05 13:08:32 -0700109#define CHIPREV_ID_5714_A2 0x9002
Michael Chanb5d37722006-09-27 16:06:21 -0700110#define CHIPREV_ID_5906_A1 0xc001
Matt Carlsond30cdd22007-10-07 23:28:35 -0700111#define CHIPREV_ID_5784_A0 0x5784000
Matt Carlsonb5af7122007-11-12 21:22:02 -0800112#define CHIPREV_ID_5784_A1 0x5784001
Matt Carlsonce057f02007-11-12 21:08:03 -0800113#define CHIPREV_ID_5761_A0 0x5761000
Matt Carlsonb5af7122007-11-12 21:22:02 -0800114#define CHIPREV_ID_5761_A1 0x5761001
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115#define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
116#define ASIC_REV_5700 0x07
117#define ASIC_REV_5701 0x00
118#define ASIC_REV_5703 0x01
119#define ASIC_REV_5704 0x02
120#define ASIC_REV_5705 0x03
121#define ASIC_REV_5750 0x04
Michael Chanff645be2005-04-21 17:09:53 -0700122#define ASIC_REV_5752 0x06
Michael Chan4cf78e42005-07-25 12:29:19 -0700123#define ASIC_REV_5780 0x08
Michael Chana4e2b342005-10-26 15:46:52 -0700124#define ASIC_REV_5714 0x09
Michael Chanaf36e6b2006-03-23 01:28:06 -0800125#define ASIC_REV_5755 0x0a
Michael Chand9ab5ad2006-03-20 22:27:35 -0800126#define ASIC_REV_5787 0x0b
Michael Chanb5d37722006-09-27 16:06:21 -0700127#define ASIC_REV_5906 0x0c
Matt Carlson795d01c2007-10-07 23:28:17 -0700128#define ASIC_REV_USE_PROD_ID_REG 0x0f
Matt Carlsond30cdd22007-10-07 23:28:35 -0700129#define ASIC_REV_5784 0x5784
Matt Carlson6b91fa02007-10-10 18:01:09 -0700130#define ASIC_REV_5761 0x5761
Matt Carlson57e69832008-05-25 23:48:31 -0700131#define ASIC_REV_5785 0x5785
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
133#define CHIPREV_5700_AX 0x70
134#define CHIPREV_5700_BX 0x71
135#define CHIPREV_5700_CX 0x72
136#define CHIPREV_5701_AX 0x00
137#define CHIPREV_5703_AX 0x10
138#define CHIPREV_5704_AX 0x20
139#define CHIPREV_5704_BX 0x21
140#define CHIPREV_5750_AX 0x40
141#define CHIPREV_5750_BX 0x41
Matt Carlsonb2a5c192008-04-03 21:44:44 -0700142#define CHIPREV_5784_AX 0x57840
143#define CHIPREV_5761_AX 0x57610
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144#define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
145#define METAL_REV_A0 0x00
146#define METAL_REV_A1 0x01
147#define METAL_REV_B0 0x00
148#define METAL_REV_B1 0x01
149#define METAL_REV_B2 0x02
150#define TG3PCI_DMA_RW_CTRL 0x0000006c
151#define DMA_RWCTRL_MIN_DMA 0x000000ff
152#define DMA_RWCTRL_MIN_DMA_SHIFT 0
153#define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
154#define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
155#define DMA_RWCTRL_READ_BNDRY_16 0x00000100
156#define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100
157#define DMA_RWCTRL_READ_BNDRY_32 0x00000200
158#define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200
159#define DMA_RWCTRL_READ_BNDRY_64 0x00000300
160#define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300
161#define DMA_RWCTRL_READ_BNDRY_128 0x00000400
162#define DMA_RWCTRL_READ_BNDRY_256 0x00000500
163#define DMA_RWCTRL_READ_BNDRY_512 0x00000600
164#define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
165#define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
166#define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
167#define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
168#define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
169#define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
170#define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
171#define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
172#define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
173#define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
174#define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
175#define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
176#define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
177#define DMA_RWCTRL_ONE_DMA 0x00004000
178#define DMA_RWCTRL_READ_WATER 0x00070000
179#define DMA_RWCTRL_READ_WATER_SHIFT 16
180#define DMA_RWCTRL_WRITE_WATER 0x00380000
181#define DMA_RWCTRL_WRITE_WATER_SHIFT 19
182#define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
183#define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
184#define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
185#define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
186#define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
187#define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
188#define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000
189#define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
190#define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
191#define TG3PCI_PCISTATE 0x00000070
192#define PCISTATE_FORCE_RESET 0x00000001
193#define PCISTATE_INT_NOT_ACTIVE 0x00000002
194#define PCISTATE_CONV_PCI_MODE 0x00000004
195#define PCISTATE_BUS_SPEED_HIGH 0x00000008
196#define PCISTATE_BUS_32BIT 0x00000010
197#define PCISTATE_ROM_ENABLE 0x00000020
198#define PCISTATE_ROM_RETRY_ENABLE 0x00000040
199#define PCISTATE_FLAT_VIEW 0x00000100
200#define PCISTATE_RETRY_SAME_DMA 0x00002000
Matt Carlson0d3031d2007-10-10 18:02:43 -0700201#define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000
202#define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203#define TG3PCI_CLOCK_CTRL 0x00000074
204#define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
205#define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
206#define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
207#define CLOCK_CTRL_ALTCLK 0x00001000
208#define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
209#define CLOCK_CTRL_44MHZ_CORE 0x00040000
210#define CLOCK_CTRL_625_CORE 0x00100000
211#define CLOCK_CTRL_FORCE_CLKRUN 0x00200000
212#define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000
213#define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
214#define TG3PCI_REG_BASE_ADDR 0x00000078
215#define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
216#define TG3PCI_REG_DATA 0x00000080
217#define TG3PCI_MEM_WIN_DATA 0x00000084
218#define TG3PCI_MODE_CTRL 0x00000088
219#define TG3PCI_MISC_CFG 0x0000008c
220#define TG3PCI_MISC_LOCAL_CTRL 0x00000090
221/* 0x94 --> 0x98 unused */
222#define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
223#define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
224#define TG3PCI_SND_PROD_IDX 0x000000a8 /* 64-bit */
225/* 0xb0 --> 0xb8 unused */
226#define TG3PCI_DUAL_MAC_CTRL 0x000000b8
227#define DUAL_MAC_CTRL_CH_MASK 0x00000003
228#define DUAL_MAC_CTRL_ID 0x00000004
Matt Carlson795d01c2007-10-07 23:28:17 -0700229#define TG3PCI_PRODID_ASICREV 0x000000bc
230#define PROD_ID_ASIC_REV_MASK 0x0fffffff
231/* 0xc0 --> 0x100 unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232
233/* 0x100 --> 0x200 unused */
234
235/* Mailbox registers */
236#define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
237#define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
238#define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
239#define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
240#define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
241#define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */
242#define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */
243#define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */
244#define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */
245#define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */
246#define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */
247#define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */
248#define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */
249#define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */
250#define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */
251#define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */
252#define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */
253#define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */
254#define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */
255#define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */
256#define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */
257#define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */
258#define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */
259#define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */
260#define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */
261#define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */
262#define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */
263#define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */
264#define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */
265#define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */
266#define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */
267#define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */
268#define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */
269#define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */
270#define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */
271#define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */
272#define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */
273#define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */
274#define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */
275#define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */
276#define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */
277#define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */
278#define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */
279#define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */
280#define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */
281#define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */
282#define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */
283#define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */
284#define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */
285#define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */
286#define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */
287#define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */
288#define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */
289#define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */
290#define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */
291#define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */
292#define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */
293#define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */
294#define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */
295#define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */
296#define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */
297#define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */
298#define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */
299#define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */
300
301/* MAC control registers */
302#define MAC_MODE 0x00000400
303#define MAC_MODE_RESET 0x00000001
304#define MAC_MODE_HALF_DUPLEX 0x00000002
305#define MAC_MODE_PORT_MODE_MASK 0x0000000c
306#define MAC_MODE_PORT_MODE_TBI 0x0000000c
307#define MAC_MODE_PORT_MODE_GMII 0x00000008
308#define MAC_MODE_PORT_MODE_MII 0x00000004
309#define MAC_MODE_PORT_MODE_NONE 0x00000000
310#define MAC_MODE_PORT_INT_LPBACK 0x00000010
311#define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
312#define MAC_MODE_TX_BURSTING 0x00000100
313#define MAC_MODE_MAX_DEFER 0x00000200
314#define MAC_MODE_LINK_POLARITY 0x00000400
315#define MAC_MODE_RXSTAT_ENABLE 0x00000800
316#define MAC_MODE_RXSTAT_CLEAR 0x00001000
317#define MAC_MODE_RXSTAT_FLUSH 0x00002000
318#define MAC_MODE_TXSTAT_ENABLE 0x00004000
319#define MAC_MODE_TXSTAT_CLEAR 0x00008000
320#define MAC_MODE_TXSTAT_FLUSH 0x00010000
321#define MAC_MODE_SEND_CONFIGS 0x00020000
322#define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
323#define MAC_MODE_ACPI_ENABLE 0x00080000
324#define MAC_MODE_MIP_ENABLE 0x00100000
325#define MAC_MODE_TDE_ENABLE 0x00200000
326#define MAC_MODE_RDE_ENABLE 0x00400000
327#define MAC_MODE_FHDE_ENABLE 0x00800000
328#define MAC_STATUS 0x00000404
329#define MAC_STATUS_PCS_SYNCED 0x00000001
330#define MAC_STATUS_SIGNAL_DET 0x00000002
331#define MAC_STATUS_RCVD_CFG 0x00000004
332#define MAC_STATUS_CFG_CHANGED 0x00000008
333#define MAC_STATUS_SYNC_CHANGED 0x00000010
334#define MAC_STATUS_PORT_DEC_ERR 0x00000400
335#define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
336#define MAC_STATUS_MI_COMPLETION 0x00400000
337#define MAC_STATUS_MI_INTERRUPT 0x00800000
338#define MAC_STATUS_AP_ERROR 0x01000000
339#define MAC_STATUS_ODI_ERROR 0x02000000
340#define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
341#define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
342#define MAC_EVENT 0x00000408
343#define MAC_EVENT_PORT_DECODE_ERR 0x00000400
344#define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
345#define MAC_EVENT_MI_COMPLETION 0x00400000
346#define MAC_EVENT_MI_INTERRUPT 0x00800000
347#define MAC_EVENT_AP_ERROR 0x01000000
348#define MAC_EVENT_ODI_ERROR 0x02000000
349#define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
350#define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
351#define MAC_LED_CTRL 0x0000040c
352#define LED_CTRL_LNKLED_OVERRIDE 0x00000001
353#define LED_CTRL_1000MBPS_ON 0x00000002
354#define LED_CTRL_100MBPS_ON 0x00000004
355#define LED_CTRL_10MBPS_ON 0x00000008
356#define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
357#define LED_CTRL_TRAFFIC_BLINK 0x00000020
358#define LED_CTRL_TRAFFIC_LED 0x00000040
359#define LED_CTRL_1000MBPS_STATUS 0x00000080
360#define LED_CTRL_100MBPS_STATUS 0x00000100
361#define LED_CTRL_10MBPS_STATUS 0x00000200
362#define LED_CTRL_TRAFFIC_STATUS 0x00000400
363#define LED_CTRL_MODE_MAC 0x00000000
364#define LED_CTRL_MODE_PHY_1 0x00000800
365#define LED_CTRL_MODE_PHY_2 0x00001000
366#define LED_CTRL_MODE_SHASTA_MAC 0x00002000
367#define LED_CTRL_MODE_SHARED 0x00004000
368#define LED_CTRL_MODE_COMBO 0x00008000
369#define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
370#define LED_CTRL_BLINK_RATE_SHIFT 19
371#define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
372#define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
373#define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */
374#define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */
375#define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */
376#define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */
377#define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */
378#define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */
379#define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */
380#define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */
381#define MAC_ACPI_MBUF_PTR 0x00000430
382#define MAC_ACPI_LEN_OFFSET 0x00000434
383#define ACPI_LENOFF_LEN_MASK 0x0000ffff
384#define ACPI_LENOFF_LEN_SHIFT 0
385#define ACPI_LENOFF_OFF_MASK 0x0fff0000
386#define ACPI_LENOFF_OFF_SHIFT 16
387#define MAC_TX_BACKOFF_SEED 0x00000438
388#define TX_BACKOFF_SEED_MASK 0x000003ff
389#define MAC_RX_MTU_SIZE 0x0000043c
390#define RX_MTU_SIZE_MASK 0x0000ffff
391#define MAC_PCS_TEST 0x00000440
392#define PCS_TEST_PATTERN_MASK 0x000fffff
393#define PCS_TEST_PATTERN_SHIFT 0
394#define PCS_TEST_ENABLE 0x00100000
395#define MAC_TX_AUTO_NEG 0x00000444
396#define TX_AUTO_NEG_MASK 0x0000ffff
397#define TX_AUTO_NEG_SHIFT 0
398#define MAC_RX_AUTO_NEG 0x00000448
399#define RX_AUTO_NEG_MASK 0x0000ffff
400#define RX_AUTO_NEG_SHIFT 0
401#define MAC_MI_COM 0x0000044c
402#define MI_COM_CMD_MASK 0x0c000000
403#define MI_COM_CMD_WRITE 0x04000000
404#define MI_COM_CMD_READ 0x08000000
405#define MI_COM_READ_FAILED 0x10000000
406#define MI_COM_START 0x20000000
407#define MI_COM_BUSY 0x20000000
408#define MI_COM_PHY_ADDR_MASK 0x03e00000
409#define MI_COM_PHY_ADDR_SHIFT 21
410#define MI_COM_REG_ADDR_MASK 0x001f0000
411#define MI_COM_REG_ADDR_SHIFT 16
412#define MI_COM_DATA_MASK 0x0000ffff
413#define MAC_MI_STAT 0x00000450
414#define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
415#define MAC_MI_MODE 0x00000454
416#define MAC_MI_MODE_CLK_10MHZ 0x00000001
417#define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
418#define MAC_MI_MODE_AUTO_POLL 0x00000010
Matt Carlson8ef21422008-05-02 16:47:53 -0700419#define MAC_MI_MODE_500KHZ_CONST 0x00008000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420#define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */
421#define MAC_AUTO_POLL_STATUS 0x00000458
422#define MAC_AUTO_POLL_ERROR 0x00000001
423#define MAC_TX_MODE 0x0000045c
424#define TX_MODE_RESET 0x00000001
425#define TX_MODE_ENABLE 0x00000002
426#define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
427#define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
428#define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
429#define MAC_TX_STATUS 0x00000460
430#define TX_STATUS_XOFFED 0x00000001
431#define TX_STATUS_SENT_XOFF 0x00000002
432#define TX_STATUS_SENT_XON 0x00000004
433#define TX_STATUS_LINK_UP 0x00000008
434#define TX_STATUS_ODI_UNDERRUN 0x00000010
435#define TX_STATUS_ODI_OVERRUN 0x00000020
436#define MAC_TX_LENGTHS 0x00000464
437#define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
438#define TX_LENGTHS_SLOT_TIME_SHIFT 0
439#define TX_LENGTHS_IPG_MASK 0x00000f00
440#define TX_LENGTHS_IPG_SHIFT 8
441#define TX_LENGTHS_IPG_CRS_MASK 0x00003000
442#define TX_LENGTHS_IPG_CRS_SHIFT 12
443#define MAC_RX_MODE 0x00000468
444#define RX_MODE_RESET 0x00000001
445#define RX_MODE_ENABLE 0x00000002
446#define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
447#define RX_MODE_KEEP_MAC_CTRL 0x00000008
448#define RX_MODE_KEEP_PAUSE 0x00000010
449#define RX_MODE_ACCEPT_OVERSIZED 0x00000020
450#define RX_MODE_ACCEPT_RUNTS 0x00000040
451#define RX_MODE_LEN_CHECK 0x00000080
452#define RX_MODE_PROMISC 0x00000100
453#define RX_MODE_NO_CRC_CHECK 0x00000200
454#define RX_MODE_KEEP_VLAN_TAG 0x00000400
Michael Chanaf36e6b2006-03-23 01:28:06 -0800455#define RX_MODE_IPV6_CSUM_ENABLE 0x01000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456#define MAC_RX_STATUS 0x0000046c
457#define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
458#define RX_STATUS_XOFF_RCVD 0x00000002
459#define RX_STATUS_XON_RCVD 0x00000004
460#define MAC_HASH_REG_0 0x00000470
461#define MAC_HASH_REG_1 0x00000474
462#define MAC_HASH_REG_2 0x00000478
463#define MAC_HASH_REG_3 0x0000047c
464#define MAC_RCV_RULE_0 0x00000480
465#define MAC_RCV_VALUE_0 0x00000484
466#define MAC_RCV_RULE_1 0x00000488
467#define MAC_RCV_VALUE_1 0x0000048c
468#define MAC_RCV_RULE_2 0x00000490
469#define MAC_RCV_VALUE_2 0x00000494
470#define MAC_RCV_RULE_3 0x00000498
471#define MAC_RCV_VALUE_3 0x0000049c
472#define MAC_RCV_RULE_4 0x000004a0
473#define MAC_RCV_VALUE_4 0x000004a4
474#define MAC_RCV_RULE_5 0x000004a8
475#define MAC_RCV_VALUE_5 0x000004ac
476#define MAC_RCV_RULE_6 0x000004b0
477#define MAC_RCV_VALUE_6 0x000004b4
478#define MAC_RCV_RULE_7 0x000004b8
479#define MAC_RCV_VALUE_7 0x000004bc
480#define MAC_RCV_RULE_8 0x000004c0
481#define MAC_RCV_VALUE_8 0x000004c4
482#define MAC_RCV_RULE_9 0x000004c8
483#define MAC_RCV_VALUE_9 0x000004cc
484#define MAC_RCV_RULE_10 0x000004d0
485#define MAC_RCV_VALUE_10 0x000004d4
486#define MAC_RCV_RULE_11 0x000004d8
487#define MAC_RCV_VALUE_11 0x000004dc
488#define MAC_RCV_RULE_12 0x000004e0
489#define MAC_RCV_VALUE_12 0x000004e4
490#define MAC_RCV_RULE_13 0x000004e8
491#define MAC_RCV_VALUE_13 0x000004ec
492#define MAC_RCV_RULE_14 0x000004f0
493#define MAC_RCV_VALUE_14 0x000004f4
494#define MAC_RCV_RULE_15 0x000004f8
495#define MAC_RCV_VALUE_15 0x000004fc
496#define RCV_RULE_DISABLE_MASK 0x7fffffff
497#define MAC_RCV_RULE_CFG 0x00000500
498#define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
499#define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
500/* 0x508 --> 0x520 unused */
501#define MAC_HASHREGU_0 0x00000520
502#define MAC_HASHREGU_1 0x00000524
503#define MAC_HASHREGU_2 0x00000528
504#define MAC_HASHREGU_3 0x0000052c
505#define MAC_EXTADDR_0_HIGH 0x00000530
506#define MAC_EXTADDR_0_LOW 0x00000534
507#define MAC_EXTADDR_1_HIGH 0x00000538
508#define MAC_EXTADDR_1_LOW 0x0000053c
509#define MAC_EXTADDR_2_HIGH 0x00000540
510#define MAC_EXTADDR_2_LOW 0x00000544
511#define MAC_EXTADDR_3_HIGH 0x00000548
512#define MAC_EXTADDR_3_LOW 0x0000054c
513#define MAC_EXTADDR_4_HIGH 0x00000550
514#define MAC_EXTADDR_4_LOW 0x00000554
515#define MAC_EXTADDR_5_HIGH 0x00000558
516#define MAC_EXTADDR_5_LOW 0x0000055c
517#define MAC_EXTADDR_6_HIGH 0x00000560
518#define MAC_EXTADDR_6_LOW 0x00000564
519#define MAC_EXTADDR_7_HIGH 0x00000568
520#define MAC_EXTADDR_7_LOW 0x0000056c
521#define MAC_EXTADDR_8_HIGH 0x00000570
522#define MAC_EXTADDR_8_LOW 0x00000574
523#define MAC_EXTADDR_9_HIGH 0x00000578
524#define MAC_EXTADDR_9_LOW 0x0000057c
525#define MAC_EXTADDR_10_HIGH 0x00000580
526#define MAC_EXTADDR_10_LOW 0x00000584
527#define MAC_EXTADDR_11_HIGH 0x00000588
528#define MAC_EXTADDR_11_LOW 0x0000058c
529#define MAC_SERDES_CFG 0x00000590
530#define MAC_SERDES_CFG_EDGE_SELECT 0x00001000
531#define MAC_SERDES_STAT 0x00000594
Matt Carlsona9daf362008-05-25 23:49:44 -0700532/* 0x598 --> 0x5a0 unused */
533#define MAC_PHYCFG1 0x000005a0
534#define MAC_PHYCFG1_RGMII_INT 0x00000001
535#define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000
536#define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000
537#define MAC_PHYCFG1_TXC_DRV 0x20000000
538#define MAC_PHYCFG2 0x000005a4
539#define MAC_PHYCFG2_INBAND_ENABLE 0x00000001
540#define MAC_EXT_RGMII_MODE 0x000005a8
541#define MAC_RGMII_MODE_TX_ENABLE 0x00000001
542#define MAC_RGMII_MODE_TX_LOWPWR 0x00000002
543#define MAC_RGMII_MODE_TX_RESET 0x00000004
544#define MAC_RGMII_MODE_RX_INT_B 0x00000100
545#define MAC_RGMII_MODE_RX_QUALITY 0x00000200
546#define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400
547#define MAC_RGMII_MODE_RX_ENG_DET 0x00000800
548/* 0x5ac --> 0x5b0 unused */
Michael Chana4e2b342005-10-26 15:46:52 -0700549#define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */
550#define SERDES_RX_SIG_DETECT 0x00000400
Linus Torvalds1da177e2005-04-16 15:20:36 -0700551#define SG_DIG_CTRL 0x000005b0
552#define SG_DIG_USING_HW_AUTONEG 0x80000000
553#define SG_DIG_SOFT_RESET 0x40000000
554#define SG_DIG_DISABLE_LINKRDY 0x20000000
555#define SG_DIG_CRC16_CLEAR_N 0x01000000
556#define SG_DIG_EN10B 0x00800000
557#define SG_DIG_CLEAR_STATUS 0x00400000
558#define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000
559#define SG_DIG_LOCAL_LINK_STATUS 0x00100000
560#define SG_DIG_SPEED_STATUS_MASK 0x000c0000
561#define SG_DIG_SPEED_STATUS_SHIFT 18
562#define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000
563#define SG_DIG_RESTART_AUTONEG 0x00010000
564#define SG_DIG_FIBER_MODE 0x00008000
565#define SG_DIG_REMOTE_FAULT_MASK 0x00006000
566#define SG_DIG_PAUSE_MASK 0x00001800
Matt Carlsonc98f6e32007-12-20 20:08:32 -0800567#define SG_DIG_PAUSE_CAP 0x00000800
568#define SG_DIG_ASYM_PAUSE 0x00001000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700569#define SG_DIG_GBIC_ENABLE 0x00000400
570#define SG_DIG_CHECK_END_ENABLE 0x00000200
571#define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100
572#define SG_DIG_CLOCK_PHASE_SELECT 0x00000080
573#define SG_DIG_GMII_INPUT_SELECT 0x00000040
574#define SG_DIG_MRADV_CRC16_SELECT 0x00000020
575#define SG_DIG_COMMA_DETECT_ENABLE 0x00000010
576#define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008
577#define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004
578#define SG_DIG_REMOTE_LOOPBACK 0x00000002
579#define SG_DIG_LOOPBACK 0x00000001
Matt Carlsonc98f6e32007-12-20 20:08:32 -0800580#define SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \
581 SG_DIG_LOCAL_DUPLEX_STATUS | \
582 SG_DIG_LOCAL_LINK_STATUS | \
583 (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \
584 SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700585#define SG_DIG_STATUS 0x000005b4
586#define SG_DIG_CRC16_BUS_MASK 0xffff0000
587#define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */
588#define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */
589#define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */
590#define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */
591#define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */
592#define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */
593#define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0
594#define SG_DIG_COMMA_DETECTOR 0x00000008
595#define SG_DIG_MAC_ACK_STATUS 0x00000004
596#define SG_DIG_AUTONEG_COMPLETE 0x00000002
597#define SG_DIG_AUTONEG_ERROR 0x00000001
598/* 0x5b8 --> 0x600 unused */
599#define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
600#define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
601/* 0x624 --> 0x800 unused */
602#define MAC_TX_STATS_OCTETS 0x00000800
603#define MAC_TX_STATS_RESV1 0x00000804
604#define MAC_TX_STATS_COLLISIONS 0x00000808
605#define MAC_TX_STATS_XON_SENT 0x0000080c
606#define MAC_TX_STATS_XOFF_SENT 0x00000810
607#define MAC_TX_STATS_RESV2 0x00000814
608#define MAC_TX_STATS_MAC_ERRORS 0x00000818
609#define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c
610#define MAC_TX_STATS_MULT_COLLISIONS 0x00000820
611#define MAC_TX_STATS_DEFERRED 0x00000824
612#define MAC_TX_STATS_RESV3 0x00000828
613#define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c
614#define MAC_TX_STATS_LATE_COL 0x00000830
615#define MAC_TX_STATS_RESV4_1 0x00000834
616#define MAC_TX_STATS_RESV4_2 0x00000838
617#define MAC_TX_STATS_RESV4_3 0x0000083c
618#define MAC_TX_STATS_RESV4_4 0x00000840
619#define MAC_TX_STATS_RESV4_5 0x00000844
620#define MAC_TX_STATS_RESV4_6 0x00000848
621#define MAC_TX_STATS_RESV4_7 0x0000084c
622#define MAC_TX_STATS_RESV4_8 0x00000850
623#define MAC_TX_STATS_RESV4_9 0x00000854
624#define MAC_TX_STATS_RESV4_10 0x00000858
625#define MAC_TX_STATS_RESV4_11 0x0000085c
626#define MAC_TX_STATS_RESV4_12 0x00000860
627#define MAC_TX_STATS_RESV4_13 0x00000864
628#define MAC_TX_STATS_RESV4_14 0x00000868
629#define MAC_TX_STATS_UCAST 0x0000086c
630#define MAC_TX_STATS_MCAST 0x00000870
631#define MAC_TX_STATS_BCAST 0x00000874
632#define MAC_TX_STATS_RESV5_1 0x00000878
633#define MAC_TX_STATS_RESV5_2 0x0000087c
634#define MAC_RX_STATS_OCTETS 0x00000880
635#define MAC_RX_STATS_RESV1 0x00000884
636#define MAC_RX_STATS_FRAGMENTS 0x00000888
637#define MAC_RX_STATS_UCAST 0x0000088c
638#define MAC_RX_STATS_MCAST 0x00000890
639#define MAC_RX_STATS_BCAST 0x00000894
640#define MAC_RX_STATS_FCS_ERRORS 0x00000898
641#define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c
642#define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0
643#define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4
644#define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8
645#define MAC_RX_STATS_XOFF_ENTERED 0x000008ac
646#define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0
647#define MAC_RX_STATS_JABBERS 0x000008b4
648#define MAC_RX_STATS_UNDERSIZE 0x000008b8
649/* 0x8bc --> 0xc00 unused */
650
651/* Send data initiator control registers */
652#define SNDDATAI_MODE 0x00000c00
653#define SNDDATAI_MODE_RESET 0x00000001
654#define SNDDATAI_MODE_ENABLE 0x00000002
655#define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
656#define SNDDATAI_STATUS 0x00000c04
657#define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
658#define SNDDATAI_STATSCTRL 0x00000c08
659#define SNDDATAI_SCTRL_ENABLE 0x00000001
660#define SNDDATAI_SCTRL_FASTUPD 0x00000002
661#define SNDDATAI_SCTRL_CLEAR 0x00000004
662#define SNDDATAI_SCTRL_FLUSH 0x00000008
663#define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
664#define SNDDATAI_STATSENAB 0x00000c0c
665#define SNDDATAI_STATSINCMASK 0x00000c10
Michael Chanb5d37722006-09-27 16:06:21 -0700666#define ISO_PKT_TX 0x00000c20
667/* 0xc24 --> 0xc80 unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700668#define SNDDATAI_COS_CNT_0 0x00000c80
669#define SNDDATAI_COS_CNT_1 0x00000c84
670#define SNDDATAI_COS_CNT_2 0x00000c88
671#define SNDDATAI_COS_CNT_3 0x00000c8c
672#define SNDDATAI_COS_CNT_4 0x00000c90
673#define SNDDATAI_COS_CNT_5 0x00000c94
674#define SNDDATAI_COS_CNT_6 0x00000c98
675#define SNDDATAI_COS_CNT_7 0x00000c9c
676#define SNDDATAI_COS_CNT_8 0x00000ca0
677#define SNDDATAI_COS_CNT_9 0x00000ca4
678#define SNDDATAI_COS_CNT_10 0x00000ca8
679#define SNDDATAI_COS_CNT_11 0x00000cac
680#define SNDDATAI_COS_CNT_12 0x00000cb0
681#define SNDDATAI_COS_CNT_13 0x00000cb4
682#define SNDDATAI_COS_CNT_14 0x00000cb8
683#define SNDDATAI_COS_CNT_15 0x00000cbc
684#define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
685#define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
686#define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
687#define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
688#define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
689#define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
690#define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
691#define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
692/* 0xce0 --> 0x1000 unused */
693
694/* Send data completion control registers */
695#define SNDDATAC_MODE 0x00001000
696#define SNDDATAC_MODE_RESET 0x00000001
697#define SNDDATAC_MODE_ENABLE 0x00000002
Matt Carlson9936bcf2007-10-10 18:03:07 -0700698#define SNDDATAC_MODE_CDELAY 0x00000010
Linus Torvalds1da177e2005-04-16 15:20:36 -0700699/* 0x1004 --> 0x1400 unused */
700
701/* Send BD ring selector */
702#define SNDBDS_MODE 0x00001400
703#define SNDBDS_MODE_RESET 0x00000001
704#define SNDBDS_MODE_ENABLE 0x00000002
705#define SNDBDS_MODE_ATTN_ENABLE 0x00000004
706#define SNDBDS_STATUS 0x00001404
707#define SNDBDS_STATUS_ERROR_ATTN 0x00000004
708#define SNDBDS_HWDIAG 0x00001408
709/* 0x140c --> 0x1440 */
710#define SNDBDS_SEL_CON_IDX_0 0x00001440
711#define SNDBDS_SEL_CON_IDX_1 0x00001444
712#define SNDBDS_SEL_CON_IDX_2 0x00001448
713#define SNDBDS_SEL_CON_IDX_3 0x0000144c
714#define SNDBDS_SEL_CON_IDX_4 0x00001450
715#define SNDBDS_SEL_CON_IDX_5 0x00001454
716#define SNDBDS_SEL_CON_IDX_6 0x00001458
717#define SNDBDS_SEL_CON_IDX_7 0x0000145c
718#define SNDBDS_SEL_CON_IDX_8 0x00001460
719#define SNDBDS_SEL_CON_IDX_9 0x00001464
720#define SNDBDS_SEL_CON_IDX_10 0x00001468
721#define SNDBDS_SEL_CON_IDX_11 0x0000146c
722#define SNDBDS_SEL_CON_IDX_12 0x00001470
723#define SNDBDS_SEL_CON_IDX_13 0x00001474
724#define SNDBDS_SEL_CON_IDX_14 0x00001478
725#define SNDBDS_SEL_CON_IDX_15 0x0000147c
726/* 0x1480 --> 0x1800 unused */
727
728/* Send BD initiator control registers */
729#define SNDBDI_MODE 0x00001800
730#define SNDBDI_MODE_RESET 0x00000001
731#define SNDBDI_MODE_ENABLE 0x00000002
732#define SNDBDI_MODE_ATTN_ENABLE 0x00000004
733#define SNDBDI_STATUS 0x00001804
734#define SNDBDI_STATUS_ERROR_ATTN 0x00000004
735#define SNDBDI_IN_PROD_IDX_0 0x00001808
736#define SNDBDI_IN_PROD_IDX_1 0x0000180c
737#define SNDBDI_IN_PROD_IDX_2 0x00001810
738#define SNDBDI_IN_PROD_IDX_3 0x00001814
739#define SNDBDI_IN_PROD_IDX_4 0x00001818
740#define SNDBDI_IN_PROD_IDX_5 0x0000181c
741#define SNDBDI_IN_PROD_IDX_6 0x00001820
742#define SNDBDI_IN_PROD_IDX_7 0x00001824
743#define SNDBDI_IN_PROD_IDX_8 0x00001828
744#define SNDBDI_IN_PROD_IDX_9 0x0000182c
745#define SNDBDI_IN_PROD_IDX_10 0x00001830
746#define SNDBDI_IN_PROD_IDX_11 0x00001834
747#define SNDBDI_IN_PROD_IDX_12 0x00001838
748#define SNDBDI_IN_PROD_IDX_13 0x0000183c
749#define SNDBDI_IN_PROD_IDX_14 0x00001840
750#define SNDBDI_IN_PROD_IDX_15 0x00001844
751/* 0x1848 --> 0x1c00 unused */
752
753/* Send BD completion control registers */
754#define SNDBDC_MODE 0x00001c00
755#define SNDBDC_MODE_RESET 0x00000001
756#define SNDBDC_MODE_ENABLE 0x00000002
757#define SNDBDC_MODE_ATTN_ENABLE 0x00000004
758/* 0x1c04 --> 0x2000 unused */
759
760/* Receive list placement control registers */
761#define RCVLPC_MODE 0x00002000
762#define RCVLPC_MODE_RESET 0x00000001
763#define RCVLPC_MODE_ENABLE 0x00000002
764#define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
765#define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
766#define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
767#define RCVLPC_STATUS 0x00002004
768#define RCVLPC_STATUS_CLASS0 0x00000004
769#define RCVLPC_STATUS_MAPOOR 0x00000008
770#define RCVLPC_STATUS_STAT_OFLOW 0x00000010
771#define RCVLPC_LOCK 0x00002008
772#define RCVLPC_LOCK_REQ_MASK 0x0000ffff
773#define RCVLPC_LOCK_REQ_SHIFT 0
774#define RCVLPC_LOCK_GRANT_MASK 0xffff0000
775#define RCVLPC_LOCK_GRANT_SHIFT 16
776#define RCVLPC_NON_EMPTY_BITS 0x0000200c
777#define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
778#define RCVLPC_CONFIG 0x00002010
779#define RCVLPC_STATSCTRL 0x00002014
780#define RCVLPC_STATSCTRL_ENABLE 0x00000001
781#define RCVLPC_STATSCTRL_FASTUPD 0x00000002
782#define RCVLPC_STATS_ENABLE 0x00002018
Michael Chan16613942006-06-29 20:15:13 -0700783#define RCVLPC_STATSENAB_DACK_FIX 0x00040000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700784#define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
785#define RCVLPC_STATS_INCMASK 0x0000201c
786/* 0x2020 --> 0x2100 unused */
787#define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */
788#define SELLST_TAIL 0x00000004
789#define SELLST_CONT 0x00000008
790#define SELLST_UNUSED 0x0000000c
791#define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */
792#define RCVLPC_DROP_FILTER_CNT 0x00002240
793#define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
794#define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
795#define RCVLPC_NO_RCV_BD_CNT 0x0000224c
796#define RCVLPC_IN_DISCARDS_CNT 0x00002250
797#define RCVLPC_IN_ERRORS_CNT 0x00002254
798#define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
799/* 0x225c --> 0x2400 unused */
800
801/* Receive Data and Receive BD Initiator Control */
802#define RCVDBDI_MODE 0x00002400
803#define RCVDBDI_MODE_RESET 0x00000001
804#define RCVDBDI_MODE_ENABLE 0x00000002
805#define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
806#define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
807#define RCVDBDI_MODE_INV_RING_SZ 0x00000010
808#define RCVDBDI_STATUS 0x00002404
809#define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
810#define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
811#define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
812#define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
813/* 0x240c --> 0x2440 unused */
814#define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */
815#define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */
816#define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */
817#define RCVDBDI_JUMBO_CON_IDX 0x00002470
818#define RCVDBDI_STD_CON_IDX 0x00002474
819#define RCVDBDI_MINI_CON_IDX 0x00002478
820/* 0x247c --> 0x2480 unused */
821#define RCVDBDI_BD_PROD_IDX_0 0x00002480
822#define RCVDBDI_BD_PROD_IDX_1 0x00002484
823#define RCVDBDI_BD_PROD_IDX_2 0x00002488
824#define RCVDBDI_BD_PROD_IDX_3 0x0000248c
825#define RCVDBDI_BD_PROD_IDX_4 0x00002490
826#define RCVDBDI_BD_PROD_IDX_5 0x00002494
827#define RCVDBDI_BD_PROD_IDX_6 0x00002498
828#define RCVDBDI_BD_PROD_IDX_7 0x0000249c
829#define RCVDBDI_BD_PROD_IDX_8 0x000024a0
830#define RCVDBDI_BD_PROD_IDX_9 0x000024a4
831#define RCVDBDI_BD_PROD_IDX_10 0x000024a8
832#define RCVDBDI_BD_PROD_IDX_11 0x000024ac
833#define RCVDBDI_BD_PROD_IDX_12 0x000024b0
834#define RCVDBDI_BD_PROD_IDX_13 0x000024b4
835#define RCVDBDI_BD_PROD_IDX_14 0x000024b8
836#define RCVDBDI_BD_PROD_IDX_15 0x000024bc
837#define RCVDBDI_HWDIAG 0x000024c0
838/* 0x24c4 --> 0x2800 unused */
839
840/* Receive Data Completion Control */
841#define RCVDCC_MODE 0x00002800
842#define RCVDCC_MODE_RESET 0x00000001
843#define RCVDCC_MODE_ENABLE 0x00000002
844#define RCVDCC_MODE_ATTN_ENABLE 0x00000004
845/* 0x2804 --> 0x2c00 unused */
846
847/* Receive BD Initiator Control Registers */
848#define RCVBDI_MODE 0x00002c00
849#define RCVBDI_MODE_RESET 0x00000001
850#define RCVBDI_MODE_ENABLE 0x00000002
851#define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
852#define RCVBDI_STATUS 0x00002c04
853#define RCVBDI_STATUS_RCB_ATTN 0x00000004
854#define RCVBDI_JUMBO_PROD_IDX 0x00002c08
855#define RCVBDI_STD_PROD_IDX 0x00002c0c
856#define RCVBDI_MINI_PROD_IDX 0x00002c10
857#define RCVBDI_MINI_THRESH 0x00002c14
858#define RCVBDI_STD_THRESH 0x00002c18
859#define RCVBDI_JUMBO_THRESH 0x00002c1c
860/* 0x2c20 --> 0x3000 unused */
861
862/* Receive BD Completion Control Registers */
863#define RCVCC_MODE 0x00003000
864#define RCVCC_MODE_RESET 0x00000001
865#define RCVCC_MODE_ENABLE 0x00000002
866#define RCVCC_MODE_ATTN_ENABLE 0x00000004
867#define RCVCC_STATUS 0x00003004
868#define RCVCC_STATUS_ERROR_ATTN 0x00000004
869#define RCVCC_JUMP_PROD_IDX 0x00003008
870#define RCVCC_STD_PROD_IDX 0x0000300c
871#define RCVCC_MINI_PROD_IDX 0x00003010
872/* 0x3014 --> 0x3400 unused */
873
874/* Receive list selector control registers */
875#define RCVLSC_MODE 0x00003400
876#define RCVLSC_MODE_RESET 0x00000001
877#define RCVLSC_MODE_ENABLE 0x00000002
878#define RCVLSC_MODE_ATTN_ENABLE 0x00000004
879#define RCVLSC_STATUS 0x00003404
880#define RCVLSC_STATUS_ERROR_ATTN 0x00000004
Matt Carlsond30cdd22007-10-07 23:28:35 -0700881/* 0x3408 --> 0x3600 unused */
882
883/* CPMU registers */
884#define TG3_CPMU_CTRL 0x00003600
885#define CPMU_CTRL_LINK_IDLE_MODE 0x00000200
886#define CPMU_CTRL_LINK_AWARE_MODE 0x00000400
Matt Carlson9936bcf2007-10-10 18:03:07 -0700887#define CPMU_CTRL_LINK_SPEED_MODE 0x00004000
Matt Carlsonb2a5c192008-04-03 21:44:44 -0700888#define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000
Matt Carlson9acb9612007-11-12 21:10:06 -0800889#define TG3_CPMU_LSPD_10MB_CLK 0x00003604
890#define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000
891#define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000
892/* 0x3608 --> 0x360c unused */
Matt Carlsonce057f02007-11-12 21:08:03 -0800893
894#define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c
895#define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000
896#define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000
897#define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000
Matt Carlson9acb9612007-11-12 21:10:06 -0800898#define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610
899#define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000
900#define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000
901/* 0x3614 --> 0x361c unused */
902
903#define TG3_CPMU_HST_ACC 0x0000361c
904#define CPMU_HST_ACC_MACCLK_MASK 0x001f0000
905#define CPMU_HST_ACC_MACCLK_6_25 0x00130000
Matt Carlsonaa6c91f2007-11-12 21:18:04 -0800906/* 0x3620 --> 0x3630 unused */
907
908#define TG3_CPMU_CLCK_STAT 0x00003630
909#define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000
910#define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
911#define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000
912#define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000
913/* 0x3634 --> 0x365c unused */
Matt Carlson9936bcf2007-10-10 18:03:07 -0700914
915#define TG3_CPMU_MUTEX_REQ 0x0000365c
916#define CPMU_MUTEX_REQ_DRIVER 0x00001000
917#define TG3_CPMU_MUTEX_GNT 0x00003660
918#define CPMU_MUTEX_GNT_DRIVER 0x00001000
919/* 0x3664 --> 0x3800 unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700920
921/* Mbuf cluster free registers */
922#define MBFREE_MODE 0x00003800
923#define MBFREE_MODE_RESET 0x00000001
924#define MBFREE_MODE_ENABLE 0x00000002
925#define MBFREE_STATUS 0x00003804
926/* 0x3808 --> 0x3c00 unused */
927
928/* Host coalescing control registers */
929#define HOSTCC_MODE 0x00003c00
930#define HOSTCC_MODE_RESET 0x00000001
931#define HOSTCC_MODE_ENABLE 0x00000002
932#define HOSTCC_MODE_ATTN 0x00000004
933#define HOSTCC_MODE_NOW 0x00000008
934#define HOSTCC_MODE_FULL_STATUS 0x00000000
935#define HOSTCC_MODE_64BYTE 0x00000080
936#define HOSTCC_MODE_32BYTE 0x00000100
937#define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
938#define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
939#define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
940#define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
941#define HOSTCC_STATUS 0x00003c04
942#define HOSTCC_STATUS_ERROR_ATTN 0x00000004
943#define HOSTCC_RXCOL_TICKS 0x00003c08
944#define LOW_RXCOL_TICKS 0x00000032
David S. Miller15f98502005-05-18 22:49:26 -0700945#define LOW_RXCOL_TICKS_CLRTCKS 0x00000014
Linus Torvalds1da177e2005-04-16 15:20:36 -0700946#define DEFAULT_RXCOL_TICKS 0x00000048
947#define HIGH_RXCOL_TICKS 0x00000096
Michael Chand244c892005-07-05 14:42:33 -0700948#define MAX_RXCOL_TICKS 0x000003ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700949#define HOSTCC_TXCOL_TICKS 0x00003c0c
950#define LOW_TXCOL_TICKS 0x00000096
David S. Miller15f98502005-05-18 22:49:26 -0700951#define LOW_TXCOL_TICKS_CLRTCKS 0x00000048
Linus Torvalds1da177e2005-04-16 15:20:36 -0700952#define DEFAULT_TXCOL_TICKS 0x0000012c
953#define HIGH_TXCOL_TICKS 0x00000145
Michael Chand244c892005-07-05 14:42:33 -0700954#define MAX_TXCOL_TICKS 0x000003ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700955#define HOSTCC_RXMAX_FRAMES 0x00003c10
956#define LOW_RXMAX_FRAMES 0x00000005
957#define DEFAULT_RXMAX_FRAMES 0x00000008
958#define HIGH_RXMAX_FRAMES 0x00000012
Michael Chand244c892005-07-05 14:42:33 -0700959#define MAX_RXMAX_FRAMES 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700960#define HOSTCC_TXMAX_FRAMES 0x00003c14
961#define LOW_TXMAX_FRAMES 0x00000035
962#define DEFAULT_TXMAX_FRAMES 0x0000004b
963#define HIGH_TXMAX_FRAMES 0x00000052
Michael Chand244c892005-07-05 14:42:33 -0700964#define MAX_TXMAX_FRAMES 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700965#define HOSTCC_RXCOAL_TICK_INT 0x00003c18
966#define DEFAULT_RXCOAL_TICK_INT 0x00000019
David S. Miller15f98502005-05-18 22:49:26 -0700967#define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
Michael Chand244c892005-07-05 14:42:33 -0700968#define MAX_RXCOAL_TICK_INT 0x000003ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700969#define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
970#define DEFAULT_TXCOAL_TICK_INT 0x00000019
David S. Miller15f98502005-05-18 22:49:26 -0700971#define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
Michael Chand244c892005-07-05 14:42:33 -0700972#define MAX_TXCOAL_TICK_INT 0x000003ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700973#define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
974#define DEFAULT_RXCOAL_MAXF_INT 0x00000005
Michael Chand244c892005-07-05 14:42:33 -0700975#define MAX_RXCOAL_MAXF_INT 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700976#define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
977#define DEFAULT_TXCOAL_MAXF_INT 0x00000005
Michael Chand244c892005-07-05 14:42:33 -0700978#define MAX_TXCOAL_MAXF_INT 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700979#define HOSTCC_STAT_COAL_TICKS 0x00003c28
980#define DEFAULT_STAT_COAL_TICKS 0x000f4240
Michael Chand244c892005-07-05 14:42:33 -0700981#define MAX_STAT_COAL_TICKS 0xd693d400
982#define MIN_STAT_COAL_TICKS 0x00000064
Linus Torvalds1da177e2005-04-16 15:20:36 -0700983/* 0x3c2c --> 0x3c30 unused */
984#define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */
985#define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */
986#define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
987#define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
988#define HOSTCC_FLOW_ATTN 0x00003c48
989/* 0x3c4c --> 0x3c50 unused */
990#define HOSTCC_JUMBO_CON_IDX 0x00003c50
991#define HOSTCC_STD_CON_IDX 0x00003c54
992#define HOSTCC_MINI_CON_IDX 0x00003c58
993/* 0x3c5c --> 0x3c80 unused */
994#define HOSTCC_RET_PROD_IDX_0 0x00003c80
995#define HOSTCC_RET_PROD_IDX_1 0x00003c84
996#define HOSTCC_RET_PROD_IDX_2 0x00003c88
997#define HOSTCC_RET_PROD_IDX_3 0x00003c8c
998#define HOSTCC_RET_PROD_IDX_4 0x00003c90
999#define HOSTCC_RET_PROD_IDX_5 0x00003c94
1000#define HOSTCC_RET_PROD_IDX_6 0x00003c98
1001#define HOSTCC_RET_PROD_IDX_7 0x00003c9c
1002#define HOSTCC_RET_PROD_IDX_8 0x00003ca0
1003#define HOSTCC_RET_PROD_IDX_9 0x00003ca4
1004#define HOSTCC_RET_PROD_IDX_10 0x00003ca8
1005#define HOSTCC_RET_PROD_IDX_11 0x00003cac
1006#define HOSTCC_RET_PROD_IDX_12 0x00003cb0
1007#define HOSTCC_RET_PROD_IDX_13 0x00003cb4
1008#define HOSTCC_RET_PROD_IDX_14 0x00003cb8
1009#define HOSTCC_RET_PROD_IDX_15 0x00003cbc
1010#define HOSTCC_SND_CON_IDX_0 0x00003cc0
1011#define HOSTCC_SND_CON_IDX_1 0x00003cc4
1012#define HOSTCC_SND_CON_IDX_2 0x00003cc8
1013#define HOSTCC_SND_CON_IDX_3 0x00003ccc
1014#define HOSTCC_SND_CON_IDX_4 0x00003cd0
1015#define HOSTCC_SND_CON_IDX_5 0x00003cd4
1016#define HOSTCC_SND_CON_IDX_6 0x00003cd8
1017#define HOSTCC_SND_CON_IDX_7 0x00003cdc
1018#define HOSTCC_SND_CON_IDX_8 0x00003ce0
1019#define HOSTCC_SND_CON_IDX_9 0x00003ce4
1020#define HOSTCC_SND_CON_IDX_10 0x00003ce8
1021#define HOSTCC_SND_CON_IDX_11 0x00003cec
1022#define HOSTCC_SND_CON_IDX_12 0x00003cf0
1023#define HOSTCC_SND_CON_IDX_13 0x00003cf4
1024#define HOSTCC_SND_CON_IDX_14 0x00003cf8
1025#define HOSTCC_SND_CON_IDX_15 0x00003cfc
1026/* 0x3d00 --> 0x4000 unused */
1027
1028/* Memory arbiter control registers */
1029#define MEMARB_MODE 0x00004000
1030#define MEMARB_MODE_RESET 0x00000001
1031#define MEMARB_MODE_ENABLE 0x00000002
1032#define MEMARB_STATUS 0x00004004
1033#define MEMARB_TRAP_ADDR_LOW 0x00004008
1034#define MEMARB_TRAP_ADDR_HIGH 0x0000400c
1035/* 0x4010 --> 0x4400 unused */
1036
1037/* Buffer manager control registers */
1038#define BUFMGR_MODE 0x00004400
1039#define BUFMGR_MODE_RESET 0x00000001
1040#define BUFMGR_MODE_ENABLE 0x00000002
1041#define BUFMGR_MODE_ATTN_ENABLE 0x00000004
1042#define BUFMGR_MODE_BM_TEST 0x00000008
1043#define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
1044#define BUFMGR_STATUS 0x00004404
1045#define BUFMGR_STATUS_ERROR 0x00000004
1046#define BUFMGR_STATUS_MBLOW 0x00000010
1047#define BUFMGR_MB_POOL_ADDR 0x00004408
1048#define BUFMGR_MB_POOL_SIZE 0x0000440c
1049#define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
1050#define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
1051#define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
1052#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
Michael Chanfdfec1722005-07-25 12:31:48 -07001053#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001054#define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
1055#define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
1056#define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
Michael Chanb5d37722006-09-27 16:06:21 -07001057#define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004
Linus Torvalds1da177e2005-04-16 15:20:36 -07001058#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
Michael Chanfdfec1722005-07-25 12:31:48 -07001059#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
Linus Torvalds1da177e2005-04-16 15:20:36 -07001060#define BUFMGR_MB_HIGH_WATER 0x00004418
1061#define DEFAULT_MB_HIGH_WATER 0x00000060
1062#define DEFAULT_MB_HIGH_WATER_5705 0x00000060
Michael Chanb5d37722006-09-27 16:06:21 -07001063#define DEFAULT_MB_HIGH_WATER_5906 0x00000010
Linus Torvalds1da177e2005-04-16 15:20:36 -07001064#define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
Michael Chanfdfec1722005-07-25 12:31:48 -07001065#define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
Linus Torvalds1da177e2005-04-16 15:20:36 -07001066#define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
1067#define BUFMGR_MB_ALLOC_BIT 0x10000000
1068#define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
1069#define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
1070#define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
1071#define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
1072#define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
1073#define BUFMGR_DMA_LOW_WATER 0x00004434
1074#define DEFAULT_DMA_LOW_WATER 0x00000005
1075#define BUFMGR_DMA_HIGH_WATER 0x00004438
1076#define DEFAULT_DMA_HIGH_WATER 0x0000000a
1077#define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
1078#define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
1079#define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
1080#define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
1081#define BUFMGR_HWDIAG_0 0x0000444c
1082#define BUFMGR_HWDIAG_1 0x00004450
1083#define BUFMGR_HWDIAG_2 0x00004454
1084/* 0x4458 --> 0x4800 unused */
1085
1086/* Read DMA control registers */
1087#define RDMAC_MODE 0x00004800
1088#define RDMAC_MODE_RESET 0x00000001
1089#define RDMAC_MODE_ENABLE 0x00000002
1090#define RDMAC_MODE_TGTABORT_ENAB 0x00000004
1091#define RDMAC_MODE_MSTABORT_ENAB 0x00000008
1092#define RDMAC_MODE_PARITYERR_ENAB 0x00000010
1093#define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1094#define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1095#define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
1096#define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1097#define RDMAC_MODE_LNGREAD_ENAB 0x00000200
1098#define RDMAC_MODE_SPLIT_ENABLE 0x00000800
Matt Carlsond30cdd22007-10-07 23:28:35 -07001099#define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800
Linus Torvalds1da177e2005-04-16 15:20:36 -07001100#define RDMAC_MODE_SPLIT_RESET 0x00001000
Matt Carlsond30cdd22007-10-07 23:28:35 -07001101#define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000
1102#define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001103#define RDMAC_MODE_FIFO_SIZE_128 0x00020000
1104#define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
1105#define RDMAC_STATUS 0x00004804
1106#define RDMAC_STATUS_TGTABORT 0x00000004
1107#define RDMAC_STATUS_MSTABORT 0x00000008
1108#define RDMAC_STATUS_PARITYERR 0x00000010
1109#define RDMAC_STATUS_ADDROFLOW 0x00000020
1110#define RDMAC_STATUS_FIFOOFLOW 0x00000040
1111#define RDMAC_STATUS_FIFOURUN 0x00000080
1112#define RDMAC_STATUS_FIFOOREAD 0x00000100
1113#define RDMAC_STATUS_LNGREAD 0x00000200
1114/* 0x4808 --> 0x4c00 unused */
1115
1116/* Write DMA control registers */
1117#define WDMAC_MODE 0x00004c00
1118#define WDMAC_MODE_RESET 0x00000001
1119#define WDMAC_MODE_ENABLE 0x00000002
1120#define WDMAC_MODE_TGTABORT_ENAB 0x00000004
1121#define WDMAC_MODE_MSTABORT_ENAB 0x00000008
1122#define WDMAC_MODE_PARITYERR_ENAB 0x00000010
1123#define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1124#define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1125#define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
1126#define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1127#define WDMAC_MODE_LNGREAD_ENAB 0x00000200
1128#define WDMAC_MODE_RX_ACCEL 0x00000400
Matt Carlsonf51f3562008-05-25 23:45:08 -07001129#define WDMAC_MODE_STATUS_TAG_FIX 0x20000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001130#define WDMAC_STATUS 0x00004c04
1131#define WDMAC_STATUS_TGTABORT 0x00000004
1132#define WDMAC_STATUS_MSTABORT 0x00000008
1133#define WDMAC_STATUS_PARITYERR 0x00000010
1134#define WDMAC_STATUS_ADDROFLOW 0x00000020
1135#define WDMAC_STATUS_FIFOOFLOW 0x00000040
1136#define WDMAC_STATUS_FIFOURUN 0x00000080
1137#define WDMAC_STATUS_FIFOOREAD 0x00000100
1138#define WDMAC_STATUS_LNGREAD 0x00000200
1139/* 0x4c08 --> 0x5000 unused */
1140
1141/* Per-cpu register offsets (arm9) */
1142#define CPU_MODE 0x00000000
1143#define CPU_MODE_RESET 0x00000001
1144#define CPU_MODE_HALT 0x00000400
1145#define CPU_STATE 0x00000004
1146#define CPU_EVTMASK 0x00000008
1147/* 0xc --> 0x1c reserved */
1148#define CPU_PC 0x0000001c
1149#define CPU_INSN 0x00000020
1150#define CPU_SPAD_UFLOW 0x00000024
1151#define CPU_WDOG_CLEAR 0x00000028
1152#define CPU_WDOG_VECTOR 0x0000002c
1153#define CPU_WDOG_PC 0x00000030
1154#define CPU_HW_BP 0x00000034
1155/* 0x38 --> 0x44 unused */
1156#define CPU_WDOG_SAVED_STATE 0x00000044
1157#define CPU_LAST_BRANCH_ADDR 0x00000048
1158#define CPU_SPAD_UFLOW_SET 0x0000004c
1159/* 0x50 --> 0x200 unused */
1160#define CPU_R0 0x00000200
1161#define CPU_R1 0x00000204
1162#define CPU_R2 0x00000208
1163#define CPU_R3 0x0000020c
1164#define CPU_R4 0x00000210
1165#define CPU_R5 0x00000214
1166#define CPU_R6 0x00000218
1167#define CPU_R7 0x0000021c
1168#define CPU_R8 0x00000220
1169#define CPU_R9 0x00000224
1170#define CPU_R10 0x00000228
1171#define CPU_R11 0x0000022c
1172#define CPU_R12 0x00000230
1173#define CPU_R13 0x00000234
1174#define CPU_R14 0x00000238
1175#define CPU_R15 0x0000023c
1176#define CPU_R16 0x00000240
1177#define CPU_R17 0x00000244
1178#define CPU_R18 0x00000248
1179#define CPU_R19 0x0000024c
1180#define CPU_R20 0x00000250
1181#define CPU_R21 0x00000254
1182#define CPU_R22 0x00000258
1183#define CPU_R23 0x0000025c
1184#define CPU_R24 0x00000260
1185#define CPU_R25 0x00000264
1186#define CPU_R26 0x00000268
1187#define CPU_R27 0x0000026c
1188#define CPU_R28 0x00000270
1189#define CPU_R29 0x00000274
1190#define CPU_R30 0x00000278
1191#define CPU_R31 0x0000027c
1192/* 0x280 --> 0x400 unused */
1193
1194#define RX_CPU_BASE 0x00005000
Chris Elmquist091465d2005-12-20 13:25:19 -08001195#define RX_CPU_MODE 0x00005000
1196#define RX_CPU_STATE 0x00005004
1197#define RX_CPU_PGMCTR 0x0000501c
1198#define RX_CPU_HWBKPT 0x00005034
Linus Torvalds1da177e2005-04-16 15:20:36 -07001199#define TX_CPU_BASE 0x00005400
Chris Elmquist091465d2005-12-20 13:25:19 -08001200#define TX_CPU_MODE 0x00005400
1201#define TX_CPU_STATE 0x00005404
1202#define TX_CPU_PGMCTR 0x0000541c
Linus Torvalds1da177e2005-04-16 15:20:36 -07001203
Michael Chanb5d37722006-09-27 16:06:21 -07001204#define VCPU_STATUS 0x00005100
1205#define VCPU_STATUS_INIT_DONE 0x04000000
1206#define VCPU_STATUS_DRV_RESET 0x08000000
1207
Matt Carlson8ed5d972007-05-07 00:25:49 -07001208#define VCPU_CFGSHDW 0x00005104
Matt Carlson0527ba32007-10-10 18:03:30 -07001209#define VCPU_CFGSHDW_WOL_ENABLE 0x00000001
1210#define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004
Matt Carlson8ed5d972007-05-07 00:25:49 -07001211#define VCPU_CFGSHDW_ASPM_DBNC 0x00001000
1212
Linus Torvalds1da177e2005-04-16 15:20:36 -07001213/* Mailboxes */
Michael Chanb5d37722006-09-27 16:06:21 -07001214#define GRCMBOX_BASE 0x00005600
Linus Torvalds1da177e2005-04-16 15:20:36 -07001215#define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
1216#define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */
1217#define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */
1218#define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */
1219#define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */
1220#define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */
1221#define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */
1222#define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */
1223#define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */
1224#define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */
1225#define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */
1226#define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */
1227#define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */
1228#define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */
1229#define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */
1230#define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */
1231#define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */
1232#define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */
1233#define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */
1234#define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */
1235#define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */
1236#define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */
1237#define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */
1238#define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */
1239#define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */
1240#define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */
1241#define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */
1242#define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */
1243#define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */
1244#define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */
1245#define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */
1246#define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */
1247#define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */
1248#define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */
1249#define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */
1250#define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */
1251#define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */
1252#define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */
1253#define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */
1254#define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */
1255#define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */
1256#define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */
1257#define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */
1258#define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */
1259#define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */
1260#define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */
1261#define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */
1262#define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */
1263#define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */
1264#define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */
1265#define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */
1266#define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */
1267#define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */
1268#define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */
1269#define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */
1270#define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */
1271#define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */
1272#define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */
1273#define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */
1274#define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */
1275#define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */
1276#define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */
1277#define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */
1278#define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */
1279#define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
1280#define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
1281#define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
1282#define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
1283/* 0x5a10 --> 0x5c00 */
1284
1285/* Flow Through queues */
1286#define FTQ_RESET 0x00005c00
1287/* 0x5c04 --> 0x5c10 unused */
1288#define FTQ_DMA_NORM_READ_CTL 0x00005c10
1289#define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
1290#define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
1291#define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
1292#define FTQ_DMA_HIGH_READ_CTL 0x00005c20
1293#define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
1294#define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
1295#define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
1296#define FTQ_DMA_COMP_DISC_CTL 0x00005c30
1297#define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
1298#define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
1299#define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
1300#define FTQ_SEND_BD_COMP_CTL 0x00005c40
1301#define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
1302#define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
1303#define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
1304#define FTQ_SEND_DATA_INIT_CTL 0x00005c50
1305#define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
1306#define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
1307#define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
1308#define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
1309#define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
1310#define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
1311#define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
1312#define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
1313#define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
1314#define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
1315#define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
1316#define FTQ_SWTYPE1_CTL 0x00005c80
1317#define FTQ_SWTYPE1_FULL_CNT 0x00005c84
1318#define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
1319#define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
1320#define FTQ_SEND_DATA_COMP_CTL 0x00005c90
1321#define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
1322#define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
1323#define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
1324#define FTQ_HOST_COAL_CTL 0x00005ca0
1325#define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
1326#define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
1327#define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
1328#define FTQ_MAC_TX_CTL 0x00005cb0
1329#define FTQ_MAC_TX_FULL_CNT 0x00005cb4
1330#define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
1331#define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
1332#define FTQ_MB_FREE_CTL 0x00005cc0
1333#define FTQ_MB_FREE_FULL_CNT 0x00005cc4
1334#define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
1335#define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
1336#define FTQ_RCVBD_COMP_CTL 0x00005cd0
1337#define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
1338#define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
1339#define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
1340#define FTQ_RCVLST_PLMT_CTL 0x00005ce0
1341#define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
1342#define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
1343#define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
1344#define FTQ_RCVDATA_INI_CTL 0x00005cf0
1345#define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
1346#define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
1347#define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
1348#define FTQ_RCVDATA_COMP_CTL 0x00005d00
1349#define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
1350#define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
1351#define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
1352#define FTQ_SWTYPE2_CTL 0x00005d10
1353#define FTQ_SWTYPE2_FULL_CNT 0x00005d14
1354#define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
1355#define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
1356/* 0x5d20 --> 0x6000 unused */
1357
1358/* Message signaled interrupt registers */
1359#define MSGINT_MODE 0x00006000
1360#define MSGINT_MODE_RESET 0x00000001
1361#define MSGINT_MODE_ENABLE 0x00000002
1362#define MSGINT_STATUS 0x00006004
1363#define MSGINT_FIFO 0x00006008
1364/* 0x600c --> 0x6400 unused */
1365
1366/* DMA completion registers */
1367#define DMAC_MODE 0x00006400
1368#define DMAC_MODE_RESET 0x00000001
1369#define DMAC_MODE_ENABLE 0x00000002
1370/* 0x6404 --> 0x6800 unused */
1371
1372/* GRC registers */
1373#define GRC_MODE 0x00006800
1374#define GRC_MODE_UPD_ON_COAL 0x00000001
1375#define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
1376#define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
1377#define GRC_MODE_BSWAP_DATA 0x00000010
1378#define GRC_MODE_WSWAP_DATA 0x00000020
1379#define GRC_MODE_SPLITHDR 0x00000100
1380#define GRC_MODE_NOFRM_CRACKING 0x00000200
1381#define GRC_MODE_INCL_CRC 0x00000400
1382#define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
1383#define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
1384#define GRC_MODE_NOIRQ_ON_RCV 0x00004000
1385#define GRC_MODE_FORCE_PCI32BIT 0x00008000
1386#define GRC_MODE_HOST_STACKUP 0x00010000
1387#define GRC_MODE_HOST_SENDBDS 0x00020000
1388#define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
1389#define GRC_MODE_NVRAM_WR_ENABLE 0x00200000
1390#define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
1391#define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
1392#define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
1393#define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
1394#define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
1395#define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
1396#define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
1397#define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
1398#define GRC_MISC_CFG 0x00006804
1399#define GRC_MISC_CFG_CORECLK_RESET 0x00000001
1400#define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
1401#define GRC_MISC_CFG_PRESCALAR_SHIFT 1
1402#define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
1403#define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
1404#define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
1405#define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
1406#define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
1407#define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
1408#define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
1409#define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1410#define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
1411#define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
1412#define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
1413#define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
Michael Chan60189dd2006-12-17 17:08:07 -08001414#define GRC_MISC_CFG_EPHY_IDDQ 0x00200000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001415#define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
1416#define GRC_LOCAL_CTRL 0x00006808
1417#define GRC_LCLCTRL_INT_ACTIVE 0x00000001
1418#define GRC_LCLCTRL_CLEARINT 0x00000002
1419#define GRC_LCLCTRL_SETINT 0x00000004
1420#define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
Michael Chanaf36e6b2006-03-23 01:28:06 -08001421#define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */
Michael Chana4e2b342005-10-26 15:46:52 -07001422#define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */
1423#define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */
Michael Chan3e7d83b2005-04-21 17:10:36 -07001424#define GRC_LCLCTRL_GPIO_INPUT3 0x00000020
1425#define GRC_LCLCTRL_GPIO_OE3 0x00000040
1426#define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080
Linus Torvalds1da177e2005-04-16 15:20:36 -07001427#define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
1428#define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
1429#define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
1430#define GRC_LCLCTRL_GPIO_OE0 0x00000800
1431#define GRC_LCLCTRL_GPIO_OE1 0x00001000
1432#define GRC_LCLCTRL_GPIO_OE2 0x00002000
1433#define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
1434#define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
1435#define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
1436#define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
1437#define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
1438#define GRC_LCLCTRL_MEMSZ_256K 0x00000000
1439#define GRC_LCLCTRL_MEMSZ_512K 0x00040000
1440#define GRC_LCLCTRL_MEMSZ_1M 0x00080000
1441#define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
1442#define GRC_LCLCTRL_MEMSZ_4M 0x00100000
1443#define GRC_LCLCTRL_MEMSZ_8M 0x00140000
1444#define GRC_LCLCTRL_MEMSZ_16M 0x00180000
1445#define GRC_LCLCTRL_BANK_SELECT 0x00200000
1446#define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
1447#define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
1448#define GRC_TIMER 0x0000680c
1449#define GRC_RX_CPU_EVENT 0x00006810
Matt Carlson7c5026a2008-05-02 16:49:29 -07001450#define GRC_RX_CPU_DRIVER_EVENT 0x00004000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001451#define GRC_RX_TIMER_REF 0x00006814
1452#define GRC_RX_CPU_SEM 0x00006818
1453#define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
1454#define GRC_TX_CPU_EVENT 0x00006820
1455#define GRC_TX_TIMER_REF 0x00006824
1456#define GRC_TX_CPU_SEM 0x00006828
1457#define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
1458#define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */
1459#define GRC_EEPROM_ADDR 0x00006838
1460#define EEPROM_ADDR_WRITE 0x00000000
1461#define EEPROM_ADDR_READ 0x80000000
1462#define EEPROM_ADDR_COMPLETE 0x40000000
1463#define EEPROM_ADDR_FSM_RESET 0x20000000
1464#define EEPROM_ADDR_DEVID_MASK 0x1c000000
1465#define EEPROM_ADDR_DEVID_SHIFT 26
1466#define EEPROM_ADDR_START 0x02000000
1467#define EEPROM_ADDR_CLKPERD_SHIFT 16
1468#define EEPROM_ADDR_ADDR_MASK 0x0000ffff
1469#define EEPROM_ADDR_ADDR_SHIFT 0
1470#define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
1471#define EEPROM_CHIP_SIZE (64 * 1024)
1472#define GRC_EEPROM_DATA 0x0000683c
1473#define GRC_EEPROM_CTRL 0x00006840
1474#define GRC_MDI_CTRL 0x00006844
1475#define GRC_SEEPROM_DELAY 0x00006848
Michael Chanb5d37722006-09-27 16:06:21 -07001476/* 0x684c --> 0x6890 unused */
1477#define GRC_VCPU_EXT_CTRL 0x00006890
1478#define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000
1479#define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
Michael Chand9ab5ad2006-03-20 22:27:35 -08001480#define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001481
1482/* 0x6c00 --> 0x7000 unused */
1483
1484/* NVRAM Control registers */
1485#define NVRAM_CMD 0x00007000
1486#define NVRAM_CMD_RESET 0x00000001
1487#define NVRAM_CMD_DONE 0x00000008
1488#define NVRAM_CMD_GO 0x00000010
1489#define NVRAM_CMD_WR 0x00000020
1490#define NVRAM_CMD_RD 0x00000000
1491#define NVRAM_CMD_ERASE 0x00000040
1492#define NVRAM_CMD_FIRST 0x00000080
1493#define NVRAM_CMD_LAST 0x00000100
1494#define NVRAM_CMD_WREN 0x00010000
1495#define NVRAM_CMD_WRDI 0x00020000
1496#define NVRAM_STAT 0x00007004
1497#define NVRAM_WRDATA 0x00007008
1498#define NVRAM_ADDR 0x0000700c
1499#define NVRAM_ADDR_MSK 0x00ffffff
1500#define NVRAM_RDDATA 0x00007010
1501#define NVRAM_CFG1 0x00007014
1502#define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
1503#define NVRAM_CFG1_BUFFERED_MODE 0x00000002
1504#define NVRAM_CFG1_PASS_THRU 0x00000004
1505#define NVRAM_CFG1_STATUS_BITS 0x00000070
1506#define NVRAM_CFG1_BIT_BANG 0x00000008
1507#define NVRAM_CFG1_FLASH_SIZE 0x02000000
1508#define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
1509#define NVRAM_CFG1_VENDOR_MASK 0x03000003
1510#define FLASH_VENDOR_ATMEL_EEPROM 0x02000000
1511#define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1512#define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003
1513#define FLASH_VENDOR_ST 0x03000001
1514#define FLASH_VENDOR_SAIFUN 0x01000003
1515#define FLASH_VENDOR_SST_SMALL 0x00000001
1516#define FLASH_VENDOR_SST_LARGE 0x02000001
Michael Chan361b4ac2005-04-21 17:11:21 -07001517#define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003
1518#define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000
1519#define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000
1520#define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1521#define FLASH_5752VENDOR_ST_M45PE10 0x02400000
1522#define FLASH_5752VENDOR_ST_M45PE20 0x02400002
1523#define FLASH_5752VENDOR_ST_M45PE40 0x02400001
Michael Chan1b277772006-03-20 22:27:48 -08001524#define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001
1525#define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002
1526#define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000
Michael Chand3c7b882006-03-23 01:28:25 -08001527#define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003
Matt Carlson70b65a22007-07-11 19:48:50 -07001528#define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003
Michael Chand3c7b882006-03-23 01:28:25 -08001529#define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003
1530#define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002
Michael Chan1b277772006-03-20 22:27:48 -08001531#define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003
1532#define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002
1533#define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000
1534#define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000
Matt Carlson6b91fa02007-10-10 18:01:09 -07001535#define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003
1536#define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000
1537#define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002
1538#define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001
1539#define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003
1540#define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000
1541#define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002
1542#define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001
1543#define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001
1544#define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000
1545#define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002
1546#define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003
1547#define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001
1548#define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000
1549#define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002
1550#define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003
Michael Chan361b4ac2005-04-21 17:11:21 -07001551#define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
1552#define FLASH_5752PAGE_SIZE_256 0x00000000
1553#define FLASH_5752PAGE_SIZE_512 0x10000000
1554#define FLASH_5752PAGE_SIZE_1K 0x20000000
1555#define FLASH_5752PAGE_SIZE_2K 0x30000000
1556#define FLASH_5752PAGE_SIZE_4K 0x40000000
1557#define FLASH_5752PAGE_SIZE_264 0x50000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001558#define NVRAM_CFG2 0x00007018
1559#define NVRAM_CFG3 0x0000701c
1560#define NVRAM_SWARB 0x00007020
1561#define SWARB_REQ_SET0 0x00000001
1562#define SWARB_REQ_SET1 0x00000002
1563#define SWARB_REQ_SET2 0x00000004
1564#define SWARB_REQ_SET3 0x00000008
1565#define SWARB_REQ_CLR0 0x00000010
1566#define SWARB_REQ_CLR1 0x00000020
1567#define SWARB_REQ_CLR2 0x00000040
1568#define SWARB_REQ_CLR3 0x00000080
1569#define SWARB_GNT0 0x00000100
1570#define SWARB_GNT1 0x00000200
1571#define SWARB_GNT2 0x00000400
1572#define SWARB_GNT3 0x00000800
1573#define SWARB_REQ0 0x00001000
1574#define SWARB_REQ1 0x00002000
1575#define SWARB_REQ2 0x00004000
1576#define SWARB_REQ3 0x00008000
1577#define NVRAM_ACCESS 0x00007024
1578#define ACCESS_ENABLE 0x00000001
1579#define ACCESS_WR_ENABLE 0x00000002
1580#define NVRAM_WRITE1 0x00007028
Matt Carlson6b91fa02007-10-10 18:01:09 -07001581/* 0x702c unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001582
Matt Carlson6b91fa02007-10-10 18:01:09 -07001583#define NVRAM_ADDR_LOCKOUT 0x00007030
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001584/* 0x7034 --> 0x7500 unused */
1585
1586#define OTP_MODE 0x00007500
1587#define OTP_MODE_OTP_THRU_GRC 0x00000001
1588#define OTP_CTRL 0x00007504
1589#define OTP_CTRL_OTP_PROG_ENABLE 0x00200000
1590#define OTP_CTRL_OTP_CMD_READ 0x00000000
1591#define OTP_CTRL_OTP_CMD_INIT 0x00000008
1592#define OTP_CTRL_OTP_CMD_START 0x00000001
1593#define OTP_STATUS 0x00007508
1594#define OTP_STATUS_CMD_DONE 0x00000001
1595#define OTP_ADDRESS 0x0000750c
1596#define OTP_ADDRESS_MAGIC1 0x000000a0
1597#define OTP_ADDRESS_MAGIC2 0x00000080
1598/* 0x7510 unused */
1599
1600#define OTP_READ_DATA 0x00007514
1601/* 0x7518 --> 0x7c04 unused */
Matt Carlson6b91fa02007-10-10 18:01:09 -07001602
Michael Chanb5d37722006-09-27 16:06:21 -07001603#define PCIE_TRANSACTION_CFG 0x00007c04
1604#define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000
1605#define PCIE_TRANS_CFG_LOM 0x00000020
1606
Matt Carlson8ed5d972007-05-07 00:25:49 -07001607#define PCIE_PWR_MGMT_THRESH 0x00007d28
1608#define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00
Linus Torvalds1da177e2005-04-16 15:20:36 -07001609
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001610
1611/* OTP bit definitions */
1612#define TG3_OTP_AGCTGT_MASK 0x000000e0
1613#define TG3_OTP_AGCTGT_SHIFT 1
1614#define TG3_OTP_HPFFLTR_MASK 0x00000300
1615#define TG3_OTP_HPFFLTR_SHIFT 1
1616#define TG3_OTP_HPFOVER_MASK 0x00000400
1617#define TG3_OTP_HPFOVER_SHIFT 1
1618#define TG3_OTP_LPFDIS_MASK 0x00000800
1619#define TG3_OTP_LPFDIS_SHIFT 11
1620#define TG3_OTP_VDAC_MASK 0xff000000
1621#define TG3_OTP_VDAC_SHIFT 24
1622#define TG3_OTP_10BTAMP_MASK 0x0000f000
1623#define TG3_OTP_10BTAMP_SHIFT 8
1624#define TG3_OTP_ROFF_MASK 0x00e00000
1625#define TG3_OTP_ROFF_SHIFT 11
1626#define TG3_OTP_RCOFF_MASK 0x001c0000
1627#define TG3_OTP_RCOFF_SHIFT 16
1628
1629#define TG3_OTP_DEFAULT 0x286c1640
1630
1631
Linus Torvalds1da177e2005-04-16 15:20:36 -07001632#define TG3_EEPROM_MAGIC 0x669955aa
Michael Chanb16250e2006-09-27 16:10:14 -07001633#define TG3_EEPROM_MAGIC_FW 0xa5000000
1634#define TG3_EEPROM_MAGIC_FW_MSK 0xff000000
Matt Carlsona5767de2007-11-12 21:10:58 -08001635#define TG3_EEPROM_SB_FORMAT_MASK 0x00e00000
1636#define TG3_EEPROM_SB_FORMAT_1 0x00200000
1637#define TG3_EEPROM_SB_REVISION_MASK 0x001f0000
1638#define TG3_EEPROM_SB_REVISION_0 0x00000000
1639#define TG3_EEPROM_SB_REVISION_2 0x00020000
1640#define TG3_EEPROM_SB_REVISION_3 0x00030000
Michael Chanb16250e2006-09-27 16:10:14 -07001641#define TG3_EEPROM_MAGIC_HW 0xabcd
1642#define TG3_EEPROM_MAGIC_HW_MSK 0xffff
Linus Torvalds1da177e2005-04-16 15:20:36 -07001643
Matt Carlson9c8a6202007-10-21 16:16:08 -07001644#define TG3_NVM_DIR_START 0x18
1645#define TG3_NVM_DIR_END 0x78
1646#define TG3_NVM_DIRENT_SIZE 0xc
1647#define TG3_NVM_DIRTYPE_SHIFT 24
1648#define TG3_NVM_DIRTYPE_ASFINI 1
1649
Linus Torvalds1da177e2005-04-16 15:20:36 -07001650/* 32K Window into NIC internal memory */
1651#define NIC_SRAM_WIN_BASE 0x00008000
1652
1653/* Offsets into first 32k of NIC internal memory. */
1654#define NIC_SRAM_PAGE_ZERO 0x00000000
1655#define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */
1656#define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */
1657#define NIC_SRAM_STATS_BLK 0x00000300
1658#define NIC_SRAM_STATUS_BLK 0x00000b00
1659
1660#define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
1661#define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
1662#define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */
1663
1664#define NIC_SRAM_DATA_SIG 0x00000b54
1665#define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */
1666
1667#define NIC_SRAM_DATA_CFG 0x00000b58
1668#define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
1669#define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000
1670#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004
1671#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008
1672#define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
1673#define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
1674#define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
1675#define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
1676#define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
1677#define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
1678#define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
1679#define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000
1680#define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
1681#define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000
Matt Carlson0d3031d2007-10-10 18:02:43 -07001682#define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001683
1684#define NIC_SRAM_DATA_VER 0x00000b5c
1685#define NIC_SRAM_DATA_VER_SHIFT 16
1686
1687#define NIC_SRAM_DATA_PHY_ID 0x00000b74
1688#define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
1689#define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
1690
1691#define NIC_SRAM_FW_CMD_MBOX 0x00000b78
1692#define FWCMD_NICDRV_ALIVE 0x00000001
1693#define FWCMD_NICDRV_PAUSE_FW 0x00000002
1694#define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
1695#define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
1696#define FWCMD_NICDRV_FIX_DMAR 0x00000005
1697#define FWCMD_NICDRV_FIX_DMAW 0x00000006
Matt Carlson7c5026a2008-05-02 16:49:29 -07001698#define FWCMD_NICDRV_LINK_UPDATE 0x0000000c
Michael Chan28fbef72005-10-26 15:48:35 -07001699#define FWCMD_NICDRV_ALIVE2 0x0000000d
Michael Chan130b8e42006-09-27 16:00:40 -07001700#define FWCMD_NICDRV_ALIVE3 0x0000000e
Linus Torvalds1da177e2005-04-16 15:20:36 -07001701#define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
1702#define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
1703#define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
1704#define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
1705#define DRV_STATE_START 0x00000001
1706#define DRV_STATE_START_DONE 0x80000001
1707#define DRV_STATE_UNLOAD 0x00000002
1708#define DRV_STATE_UNLOAD_DONE 0x80000002
1709#define DRV_STATE_WOL 0x00000003
1710#define DRV_STATE_SUSPEND 0x00000004
1711
1712#define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
1713
1714#define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
1715#define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
1716
Michael Chan6921d202005-12-13 21:15:53 -08001717#define NIC_SRAM_WOL_MBOX 0x00000d30
1718#define WOL_SIGNATURE 0x474c0000
1719#define WOL_DRV_STATE_SHUTDOWN 0x00000001
1720#define WOL_DRV_WOL 0x00000002
1721#define WOL_SET_MAGIC_PKT 0x00000004
1722
Linus Torvalds1da177e2005-04-16 15:20:36 -07001723#define NIC_SRAM_DATA_CFG_2 0x00000d38
1724
1725#define SHASTA_EXT_LED_MODE_MASK 0x00018000
1726#define SHASTA_EXT_LED_LEGACY 0x00000000
1727#define SHASTA_EXT_LED_SHARED 0x00008000
1728#define SHASTA_EXT_LED_MAC 0x00010000
1729#define SHASTA_EXT_LED_COMBO 0x00018000
1730
Matt Carlson8ed5d972007-05-07 00:25:49 -07001731#define NIC_SRAM_DATA_CFG_3 0x00000d3c
1732#define NIC_SRAM_ASPM_DEBOUNCE 0x00000002
1733
Matt Carlsona9daf362008-05-25 23:49:44 -07001734#define NIC_SRAM_DATA_CFG_4 0x00000d60
1735#define NIC_SRAM_GMII_MODE 0x00000002
1736#define NIC_SRAM_RGMII_STD_IBND_DISABLE 0x00000004
1737#define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
1738#define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
1739
Linus Torvalds1da177e2005-04-16 15:20:36 -07001740#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
1741
1742#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
1743#define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
1744#define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */
1745#define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */
1746#define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */
1747#define NIC_SRAM_MBUF_POOL_BASE 0x00008000
1748#define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
1749#define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
1750#define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
1751#define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
1752
1753/* Currently this is fixed. */
1754#define PHY_ADDR 0x01
1755
1756/* Tigon3 specific PHY MII registers. */
1757#define TG3_BMCR_SPEED1000 0x0040
1758
1759#define MII_TG3_CTRL 0x09 /* 1000-baseT control register */
1760#define MII_TG3_CTRL_ADV_1000_HALF 0x0100
1761#define MII_TG3_CTRL_ADV_1000_FULL 0x0200
1762#define MII_TG3_CTRL_AS_MASTER 0x0800
1763#define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
1764
1765#define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
1766#define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
1767#define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
Michael Chan6921d202005-12-13 21:15:53 -08001768#define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
Linus Torvalds1da177e2005-04-16 15:20:36 -07001769#define MII_TG3_EXT_CTRL_TBI 0x8000
1770
1771#define MII_TG3_EXT_STAT 0x11 /* Extended status register */
1772#define MII_TG3_EXT_STAT_LPASS 0x0100
1773
1774#define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
1775
Michael Chan715116a2006-09-27 16:09:25 -07001776#define MII_TG3_EPHY_PTEST 0x17 /* 5906 PHY register */
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001777#define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
1778
1779#define MII_TG3_DSP_TAP1 0x0001
1780#define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007
1781#define MII_TG3_DSP_AADJ1CH0 0x001f
1782#define MII_TG3_DSP_AADJ1CH3 0x601f
1783#define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002
1784#define MII_TG3_DSP_EXP8 0x0708
1785#define MII_TG3_DSP_EXP8_REJ2MHz 0x0001
1786#define MII_TG3_DSP_EXP8_AEDW 0x0200
1787#define MII_TG3_DSP_EXP75 0x0f75
1788#define MII_TG3_DSP_EXP96 0x0f96
1789#define MII_TG3_DSP_EXP97 0x0f97
Linus Torvalds1da177e2005-04-16 15:20:36 -07001790
1791#define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */
1792
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001793#define MII_TG3_AUXCTL_MISC_WREN 0x8000
1794#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
1795#define MII_TG3_AUXCTL_MISC_RDSEL_MISC 0x7000
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001796#define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007
1797
1798#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800
1799#define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400
1800#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001801
Linus Torvalds1da177e2005-04-16 15:20:36 -07001802#define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */
1803#define MII_TG3_AUX_STAT_LPASS 0x0004
1804#define MII_TG3_AUX_STAT_SPDMASK 0x0700
1805#define MII_TG3_AUX_STAT_10HALF 0x0100
1806#define MII_TG3_AUX_STAT_10FULL 0x0200
1807#define MII_TG3_AUX_STAT_100HALF 0x0300
1808#define MII_TG3_AUX_STAT_100_4 0x0400
1809#define MII_TG3_AUX_STAT_100FULL 0x0500
1810#define MII_TG3_AUX_STAT_1000HALF 0x0600
1811#define MII_TG3_AUX_STAT_1000FULL 0x0700
Michael Chan715116a2006-09-27 16:09:25 -07001812#define MII_TG3_AUX_STAT_100 0x0008
1813#define MII_TG3_AUX_STAT_FULL 0x0001
Linus Torvalds1da177e2005-04-16 15:20:36 -07001814
1815#define MII_TG3_ISTAT 0x1a /* IRQ status register */
1816#define MII_TG3_IMASK 0x1b /* IRQ mask register */
1817
Matt Carlson662f38d2007-11-12 21:16:17 -08001818#define MII_TG3_MISC_SHDW 0x1c
1819#define MII_TG3_MISC_SHDW_WREN 0x8000
1820#define MII_TG3_MISC_SHDW_APD_SEL 0x2800
1821
1822#define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
1823
Linus Torvalds1da177e2005-04-16 15:20:36 -07001824/* ISTAT/IMASK event bits */
1825#define MII_TG3_INT_LINKCHG 0x0002
1826#define MII_TG3_INT_SPEEDCHG 0x0004
1827#define MII_TG3_INT_DUPLEXCHG 0x0008
1828#define MII_TG3_INT_ANEG_PAGE_RX 0x0400
1829
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001830#define MII_TG3_MISC_SHDW 0x1c
1831#define MII_TG3_MISC_SHDW_WREN 0x8000
1832#define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400
1833#define MII_TG3_MISC_SHDW_APD_SEL 0x2800
1834
1835#define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001
1836#define MII_TG3_MISC_SHDW_SCR5_DLLAPD 0x0002
1837#define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004
1838#define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008
1839#define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010
1840
1841#define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
1842#define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020
1843
Michael Chan715116a2006-09-27 16:09:25 -07001844#define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */
1845#define MII_TG3_EPHY_SHADOW_EN 0x80
1846
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001847#define MII_TG3_EPHYTST_MISCCTRL 0x10 /* 5906 EPHY misc ctrl shadow register */
1848#define MII_TG3_EPHYTST_MISCCTRL_MDIX 0x4000
1849
Michael Chanc1d2a192007-01-08 19:57:20 -08001850#define MII_TG3_TEST1 0x1e
1851#define MII_TG3_TEST1_TRIM_EN 0x0010
Michael Chan569a5df2007-02-13 12:18:15 -08001852#define MII_TG3_TEST1_CRC_EN 0x8000
Michael Chanc1d2a192007-01-08 19:57:20 -08001853
Matt Carlson0d3031d2007-10-10 18:02:43 -07001854/* APE registers. Accessible through BAR1 */
1855#define TG3_APE_EVENT 0x000c
1856#define APE_EVENT_1 0x00000001
1857#define TG3_APE_LOCK_REQ 0x002c
1858#define APE_LOCK_REQ_DRIVER 0x00001000
1859#define TG3_APE_LOCK_GRANT 0x004c
1860#define APE_LOCK_GRANT_DRIVER 0x00001000
1861#define TG3_APE_SEG_SIG 0x4000
1862#define APE_SEG_SIG_MAGIC 0x41504521
1863
1864/* APE shared memory. Accessible through BAR1 */
1865#define TG3_APE_FW_STATUS 0x400c
1866#define APE_FW_STATUS_READY 0x00000100
1867#define TG3_APE_HOST_SEG_SIG 0x4200
1868#define APE_HOST_SEG_SIG_MAGIC 0x484f5354
1869#define TG3_APE_HOST_SEG_LEN 0x4204
1870#define APE_HOST_SEG_LEN_MAGIC 0x0000001c
1871#define TG3_APE_HOST_INIT_COUNT 0x4208
1872#define TG3_APE_HOST_DRIVER_ID 0x420c
1873#define APE_HOST_DRIVER_ID_MAGIC 0xf0035100
1874#define TG3_APE_HOST_BEHAVIOR 0x4210
1875#define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001
1876#define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214
1877#define APE_HOST_HEARTBEAT_INT_DISABLE 0
1878#define APE_HOST_HEARTBEAT_INT_5SEC 5000
1879#define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218
1880
1881#define TG3_APE_EVENT_STATUS 0x4300
1882
1883#define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010
1884#define APE_EVENT_STATUS_STATE_CHNGE 0x00000500
1885#define APE_EVENT_STATUS_STATE_START 0x00010000
1886#define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000
1887#define APE_EVENT_STATUS_STATE_WOL 0x00030000
1888#define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000
1889#define APE_EVENT_STATUS_EVENT_PENDING 0x80000000
1890
1891/* APE convenience enumerations. */
1892#define TG3_APE_LOCK_MEM 4
1893
Matt Carlsona5767de2007-11-12 21:10:58 -08001894#define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
1895
Matt Carlson0d3031d2007-10-10 18:02:43 -07001896
Linus Torvalds1da177e2005-04-16 15:20:36 -07001897/* There are two ways to manage the TX descriptors on the tigon3.
1898 * Either the descriptors are in host DMA'able memory, or they
1899 * exist only in the cards on-chip SRAM. All 16 send bds are under
1900 * the same mode, they may not be configured individually.
1901 *
1902 * This driver always uses host memory TX descriptors.
1903 *
1904 * To use host memory TX descriptors:
1905 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
1906 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
1907 * 2) Allocate DMA'able memory.
1908 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1909 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
1910 * obtained in step 2
1911 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
1912 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
1913 * of TX descriptors. Leave flags field clear.
1914 * 4) Access TX descriptors via host memory. The chip
1915 * will refetch into local SRAM as needed when producer
1916 * index mailboxes are updated.
1917 *
1918 * To use on-chip TX descriptors:
1919 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
1920 * Make sure GRC_MODE_HOST_SENDBDS is clear.
1921 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1922 * a) Set TG3_BDINFO_HOST_ADDR to zero.
1923 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
1924 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
1925 * 3) Access TX descriptors directly in on-chip SRAM
1926 * using normal {read,write}l(). (and not using
1927 * pointer dereferencing of ioremap()'d memory like
1928 * the broken Broadcom driver does)
1929 *
1930 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
1931 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
1932 */
1933struct tg3_tx_buffer_desc {
1934 u32 addr_hi;
1935 u32 addr_lo;
1936
1937 u32 len_flags;
1938#define TXD_FLAG_TCPUDP_CSUM 0x0001
1939#define TXD_FLAG_IP_CSUM 0x0002
1940#define TXD_FLAG_END 0x0004
1941#define TXD_FLAG_IP_FRAG 0x0008
1942#define TXD_FLAG_IP_FRAG_END 0x0010
1943#define TXD_FLAG_VLAN 0x0040
1944#define TXD_FLAG_COAL_NOW 0x0080
1945#define TXD_FLAG_CPU_PRE_DMA 0x0100
1946#define TXD_FLAG_CPU_POST_DMA 0x0200
1947#define TXD_FLAG_ADD_SRC_ADDR 0x1000
1948#define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
1949#define TXD_FLAG_NO_CRC 0x8000
1950#define TXD_LEN_SHIFT 16
1951
1952 u32 vlan_tag;
1953#define TXD_VLAN_TAG_SHIFT 0
1954#define TXD_MSS_SHIFT 16
1955};
1956
1957#define TXD_ADDR 0x00UL /* 64-bit */
1958#define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */
1959#define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */
1960#define TXD_SIZE 0x10UL
1961
1962struct tg3_rx_buffer_desc {
1963 u32 addr_hi;
1964 u32 addr_lo;
1965
1966 u32 idx_len;
1967#define RXD_IDX_MASK 0xffff0000
1968#define RXD_IDX_SHIFT 16
1969#define RXD_LEN_MASK 0x0000ffff
1970#define RXD_LEN_SHIFT 0
1971
1972 u32 type_flags;
1973#define RXD_TYPE_SHIFT 16
1974#define RXD_FLAGS_SHIFT 0
1975
1976#define RXD_FLAG_END 0x0004
1977#define RXD_FLAG_MINI 0x0800
1978#define RXD_FLAG_JUMBO 0x0020
1979#define RXD_FLAG_VLAN 0x0040
1980#define RXD_FLAG_ERROR 0x0400
1981#define RXD_FLAG_IP_CSUM 0x1000
1982#define RXD_FLAG_TCPUDP_CSUM 0x2000
1983#define RXD_FLAG_IS_TCP 0x4000
1984
1985 u32 ip_tcp_csum;
1986#define RXD_IPCSUM_MASK 0xffff0000
1987#define RXD_IPCSUM_SHIFT 16
1988#define RXD_TCPCSUM_MASK 0x0000ffff
1989#define RXD_TCPCSUM_SHIFT 0
1990
1991 u32 err_vlan;
1992
1993#define RXD_VLAN_MASK 0x0000ffff
1994
1995#define RXD_ERR_BAD_CRC 0x00010000
1996#define RXD_ERR_COLLISION 0x00020000
1997#define RXD_ERR_LINK_LOST 0x00040000
1998#define RXD_ERR_PHY_DECODE 0x00080000
1999#define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
2000#define RXD_ERR_MAC_ABRT 0x00200000
2001#define RXD_ERR_TOO_SMALL 0x00400000
2002#define RXD_ERR_NO_RESOURCES 0x00800000
2003#define RXD_ERR_HUGE_FRAME 0x01000000
2004#define RXD_ERR_MASK 0xffff0000
2005
2006 u32 reserved;
2007 u32 opaque;
2008#define RXD_OPAQUE_INDEX_MASK 0x0000ffff
2009#define RXD_OPAQUE_INDEX_SHIFT 0
2010#define RXD_OPAQUE_RING_STD 0x00010000
2011#define RXD_OPAQUE_RING_JUMBO 0x00020000
2012#define RXD_OPAQUE_RING_MINI 0x00040000
2013#define RXD_OPAQUE_RING_MASK 0x00070000
2014};
2015
2016struct tg3_ext_rx_buffer_desc {
2017 struct {
2018 u32 addr_hi;
2019 u32 addr_lo;
2020 } addrlist[3];
2021 u32 len2_len1;
2022 u32 resv_len3;
2023 struct tg3_rx_buffer_desc std;
2024};
2025
2026/* We only use this when testing out the DMA engine
2027 * at probe time. This is the internal format of buffer
2028 * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
2029 */
2030struct tg3_internal_buffer_desc {
2031 u32 addr_hi;
2032 u32 addr_lo;
2033 u32 nic_mbuf;
2034 /* XXX FIX THIS */
2035#ifdef __BIG_ENDIAN
2036 u16 cqid_sqid;
2037 u16 len;
2038#else
2039 u16 len;
2040 u16 cqid_sqid;
2041#endif
2042 u32 flags;
2043 u32 __cookie1;
2044 u32 __cookie2;
2045 u32 __cookie3;
2046};
2047
2048#define TG3_HW_STATUS_SIZE 0x50
2049struct tg3_hw_status {
2050 u32 status;
2051#define SD_STATUS_UPDATED 0x00000001
2052#define SD_STATUS_LINK_CHG 0x00000002
2053#define SD_STATUS_ERROR 0x00000004
2054
2055 u32 status_tag;
2056
2057#ifdef __BIG_ENDIAN
2058 u16 rx_consumer;
2059 u16 rx_jumbo_consumer;
2060#else
2061 u16 rx_jumbo_consumer;
2062 u16 rx_consumer;
2063#endif
2064
2065#ifdef __BIG_ENDIAN
2066 u16 reserved;
2067 u16 rx_mini_consumer;
2068#else
2069 u16 rx_mini_consumer;
2070 u16 reserved;
2071#endif
2072 struct {
2073#ifdef __BIG_ENDIAN
2074 u16 tx_consumer;
2075 u16 rx_producer;
2076#else
2077 u16 rx_producer;
2078 u16 tx_consumer;
2079#endif
2080 } idx[16];
2081};
2082
2083typedef struct {
2084 u32 high, low;
2085} tg3_stat64_t;
2086
2087struct tg3_hw_stats {
2088 u8 __reserved0[0x400-0x300];
2089
2090 /* Statistics maintained by Receive MAC. */
2091 tg3_stat64_t rx_octets;
2092 u64 __reserved1;
2093 tg3_stat64_t rx_fragments;
2094 tg3_stat64_t rx_ucast_packets;
2095 tg3_stat64_t rx_mcast_packets;
2096 tg3_stat64_t rx_bcast_packets;
2097 tg3_stat64_t rx_fcs_errors;
2098 tg3_stat64_t rx_align_errors;
2099 tg3_stat64_t rx_xon_pause_rcvd;
2100 tg3_stat64_t rx_xoff_pause_rcvd;
2101 tg3_stat64_t rx_mac_ctrl_rcvd;
2102 tg3_stat64_t rx_xoff_entered;
2103 tg3_stat64_t rx_frame_too_long_errors;
2104 tg3_stat64_t rx_jabbers;
2105 tg3_stat64_t rx_undersize_packets;
2106 tg3_stat64_t rx_in_length_errors;
2107 tg3_stat64_t rx_out_length_errors;
2108 tg3_stat64_t rx_64_or_less_octet_packets;
2109 tg3_stat64_t rx_65_to_127_octet_packets;
2110 tg3_stat64_t rx_128_to_255_octet_packets;
2111 tg3_stat64_t rx_256_to_511_octet_packets;
2112 tg3_stat64_t rx_512_to_1023_octet_packets;
2113 tg3_stat64_t rx_1024_to_1522_octet_packets;
2114 tg3_stat64_t rx_1523_to_2047_octet_packets;
2115 tg3_stat64_t rx_2048_to_4095_octet_packets;
2116 tg3_stat64_t rx_4096_to_8191_octet_packets;
2117 tg3_stat64_t rx_8192_to_9022_octet_packets;
2118
2119 u64 __unused0[37];
2120
2121 /* Statistics maintained by Transmit MAC. */
2122 tg3_stat64_t tx_octets;
2123 u64 __reserved2;
2124 tg3_stat64_t tx_collisions;
2125 tg3_stat64_t tx_xon_sent;
2126 tg3_stat64_t tx_xoff_sent;
2127 tg3_stat64_t tx_flow_control;
2128 tg3_stat64_t tx_mac_errors;
2129 tg3_stat64_t tx_single_collisions;
2130 tg3_stat64_t tx_mult_collisions;
2131 tg3_stat64_t tx_deferred;
2132 u64 __reserved3;
2133 tg3_stat64_t tx_excessive_collisions;
2134 tg3_stat64_t tx_late_collisions;
2135 tg3_stat64_t tx_collide_2times;
2136 tg3_stat64_t tx_collide_3times;
2137 tg3_stat64_t tx_collide_4times;
2138 tg3_stat64_t tx_collide_5times;
2139 tg3_stat64_t tx_collide_6times;
2140 tg3_stat64_t tx_collide_7times;
2141 tg3_stat64_t tx_collide_8times;
2142 tg3_stat64_t tx_collide_9times;
2143 tg3_stat64_t tx_collide_10times;
2144 tg3_stat64_t tx_collide_11times;
2145 tg3_stat64_t tx_collide_12times;
2146 tg3_stat64_t tx_collide_13times;
2147 tg3_stat64_t tx_collide_14times;
2148 tg3_stat64_t tx_collide_15times;
2149 tg3_stat64_t tx_ucast_packets;
2150 tg3_stat64_t tx_mcast_packets;
2151 tg3_stat64_t tx_bcast_packets;
2152 tg3_stat64_t tx_carrier_sense_errors;
2153 tg3_stat64_t tx_discards;
2154 tg3_stat64_t tx_errors;
2155
2156 u64 __unused1[31];
2157
2158 /* Statistics maintained by Receive List Placement. */
2159 tg3_stat64_t COS_rx_packets[16];
2160 tg3_stat64_t COS_rx_filter_dropped;
2161 tg3_stat64_t dma_writeq_full;
2162 tg3_stat64_t dma_write_prioq_full;
2163 tg3_stat64_t rxbds_empty;
2164 tg3_stat64_t rx_discards;
2165 tg3_stat64_t rx_errors;
2166 tg3_stat64_t rx_threshold_hit;
2167
2168 u64 __unused2[9];
2169
2170 /* Statistics maintained by Send Data Initiator. */
2171 tg3_stat64_t COS_out_packets[16];
2172 tg3_stat64_t dma_readq_full;
2173 tg3_stat64_t dma_read_prioq_full;
2174 tg3_stat64_t tx_comp_queue_full;
2175
2176 /* Statistics maintained by Host Coalescing. */
2177 tg3_stat64_t ring_set_send_prod_index;
2178 tg3_stat64_t ring_status_update;
2179 tg3_stat64_t nic_irqs;
2180 tg3_stat64_t nic_avoided_irqs;
2181 tg3_stat64_t nic_tx_threshold_hit;
2182
2183 u8 __reserved4[0xb00-0x9c0];
2184};
2185
2186/* 'mapping' is superfluous as the chip does not write into
2187 * the tx/rx post rings so we could just fetch it from there.
2188 * But the cache behavior is better how we are doing it now.
2189 */
2190struct ring_info {
2191 struct sk_buff *skb;
2192 DECLARE_PCI_UNMAP_ADDR(mapping)
2193};
2194
2195struct tx_ring_info {
2196 struct sk_buff *skb;
2197 DECLARE_PCI_UNMAP_ADDR(mapping)
2198 u32 prev_vlan_tag;
2199};
2200
2201struct tg3_config_info {
2202 u32 flags;
2203};
2204
2205struct tg3_link_config {
2206 /* Describes what we're trying to get. */
2207 u32 advertising;
2208 u16 speed;
2209 u8 duplex;
2210 u8 autoneg;
Matt Carlson8d018622007-12-20 20:05:44 -08002211 u8 flowctrl;
2212#define TG3_FLOW_CTRL_TX 0x01
2213#define TG3_FLOW_CTRL_RX 0x02
Linus Torvalds1da177e2005-04-16 15:20:36 -07002214
2215 /* Describes what we actually have. */
Matt Carlson8d018622007-12-20 20:05:44 -08002216 u8 active_flowctrl;
2217
Linus Torvalds1da177e2005-04-16 15:20:36 -07002218 u8 active_duplex;
2219#define SPEED_INVALID 0xffff
2220#define DUPLEX_INVALID 0xff
2221#define AUTONEG_INVALID 0xff
Matt Carlson8d018622007-12-20 20:05:44 -08002222 u16 active_speed;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002223
2224 /* When we go in and out of low power mode we need
2225 * to swap with this state.
2226 */
2227 int phy_is_low_power;
2228 u16 orig_speed;
2229 u8 orig_duplex;
2230 u8 orig_autoneg;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002231 u32 orig_advertising;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002232};
2233
2234struct tg3_bufmgr_config {
2235 u32 mbuf_read_dma_low_water;
2236 u32 mbuf_mac_rx_low_water;
2237 u32 mbuf_high_water;
2238
2239 u32 mbuf_read_dma_low_water_jumbo;
2240 u32 mbuf_mac_rx_low_water_jumbo;
2241 u32 mbuf_high_water_jumbo;
2242
2243 u32 dma_low_water;
2244 u32 dma_high_water;
2245};
2246
2247struct tg3_ethtool_stats {
2248 /* Statistics maintained by Receive MAC. */
2249 u64 rx_octets;
2250 u64 rx_fragments;
2251 u64 rx_ucast_packets;
2252 u64 rx_mcast_packets;
2253 u64 rx_bcast_packets;
2254 u64 rx_fcs_errors;
2255 u64 rx_align_errors;
2256 u64 rx_xon_pause_rcvd;
2257 u64 rx_xoff_pause_rcvd;
2258 u64 rx_mac_ctrl_rcvd;
2259 u64 rx_xoff_entered;
2260 u64 rx_frame_too_long_errors;
2261 u64 rx_jabbers;
2262 u64 rx_undersize_packets;
2263 u64 rx_in_length_errors;
2264 u64 rx_out_length_errors;
2265 u64 rx_64_or_less_octet_packets;
2266 u64 rx_65_to_127_octet_packets;
2267 u64 rx_128_to_255_octet_packets;
2268 u64 rx_256_to_511_octet_packets;
2269 u64 rx_512_to_1023_octet_packets;
2270 u64 rx_1024_to_1522_octet_packets;
2271 u64 rx_1523_to_2047_octet_packets;
2272 u64 rx_2048_to_4095_octet_packets;
2273 u64 rx_4096_to_8191_octet_packets;
2274 u64 rx_8192_to_9022_octet_packets;
2275
2276 /* Statistics maintained by Transmit MAC. */
2277 u64 tx_octets;
2278 u64 tx_collisions;
2279 u64 tx_xon_sent;
2280 u64 tx_xoff_sent;
2281 u64 tx_flow_control;
2282 u64 tx_mac_errors;
2283 u64 tx_single_collisions;
2284 u64 tx_mult_collisions;
2285 u64 tx_deferred;
2286 u64 tx_excessive_collisions;
2287 u64 tx_late_collisions;
2288 u64 tx_collide_2times;
2289 u64 tx_collide_3times;
2290 u64 tx_collide_4times;
2291 u64 tx_collide_5times;
2292 u64 tx_collide_6times;
2293 u64 tx_collide_7times;
2294 u64 tx_collide_8times;
2295 u64 tx_collide_9times;
2296 u64 tx_collide_10times;
2297 u64 tx_collide_11times;
2298 u64 tx_collide_12times;
2299 u64 tx_collide_13times;
2300 u64 tx_collide_14times;
2301 u64 tx_collide_15times;
2302 u64 tx_ucast_packets;
2303 u64 tx_mcast_packets;
2304 u64 tx_bcast_packets;
2305 u64 tx_carrier_sense_errors;
2306 u64 tx_discards;
2307 u64 tx_errors;
2308
2309 /* Statistics maintained by Receive List Placement. */
2310 u64 dma_writeq_full;
2311 u64 dma_write_prioq_full;
2312 u64 rxbds_empty;
2313 u64 rx_discards;
2314 u64 rx_errors;
2315 u64 rx_threshold_hit;
2316
2317 /* Statistics maintained by Send Data Initiator. */
2318 u64 dma_readq_full;
2319 u64 dma_read_prioq_full;
2320 u64 tx_comp_queue_full;
2321
2322 /* Statistics maintained by Host Coalescing. */
2323 u64 ring_set_send_prod_index;
2324 u64 ring_status_update;
2325 u64 nic_irqs;
2326 u64 nic_avoided_irqs;
2327 u64 nic_tx_threshold_hit;
2328};
2329
2330struct tg3 {
2331 /* begin "general, frequently-used members" cacheline section */
2332
David S. Millerf47c11e2005-06-24 20:18:35 -07002333 /* If the IRQ handler (which runs lockless) needs to be
2334 * quiesced, the following bitmask state is used. The
2335 * SYNC flag is set by non-IRQ context code to initiate
2336 * the quiescence.
2337 *
2338 * When the IRQ handler notices that SYNC is set, it
2339 * disables interrupts and returns.
2340 *
2341 * When all outstanding IRQ handlers have returned after
2342 * the SYNC flag has been set, the setter can be assured
2343 * that interrupts will no longer get run.
2344 *
2345 * In this way all SMP driver locks are never acquired
2346 * in hw IRQ context, only sw IRQ context or lower.
2347 */
2348 unsigned int irq_sync;
2349
Linus Torvalds1da177e2005-04-16 15:20:36 -07002350 /* SMP locking strategy:
2351 *
Michael Chan00b70502006-06-17 21:58:45 -07002352 * lock: Held during reset, PHY access, timer, and when
2353 * updating tg3_flags and tg3_flags2.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002354 *
Michael Chan1b2a7202006-08-07 21:46:02 -07002355 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
2356 * netif_tx_lock when it needs to call
2357 * netif_wake_queue.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002358 *
David S. Millerf47c11e2005-06-24 20:18:35 -07002359 * Both of these locks are to be held with BH safety.
Michael Chan00b70502006-06-17 21:58:45 -07002360 *
2361 * Because the IRQ handler, tg3_poll, and tg3_start_xmit
2362 * are running lockless, it is necessary to completely
2363 * quiesce the chip with tg3_netif_stop and tg3_full_lock
2364 * before reconfiguring the device.
2365 *
2366 * indirect_lock: Held when accessing registers indirectly
2367 * with IRQ disabling.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002368 */
2369 spinlock_t lock;
2370 spinlock_t indirect_lock;
2371
Michael Chan20094932005-08-09 20:16:32 -07002372 u32 (*read32) (struct tg3 *, u32);
2373 void (*write32) (struct tg3 *, u32, u32);
Michael Chan09ee9292005-08-09 20:17:00 -07002374 u32 (*read32_mbox) (struct tg3 *, u32);
Michael Chan20094932005-08-09 20:16:32 -07002375 void (*write32_mbox) (struct tg3 *, u32,
2376 u32);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002377 void __iomem *regs;
Matt Carlson0d3031d2007-10-10 18:02:43 -07002378 void __iomem *aperegs;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002379 struct net_device *dev;
2380 struct pci_dev *pdev;
2381
2382 struct tg3_hw_status *hw_status;
2383 dma_addr_t status_mapping;
David S. Millerfac9b832005-05-18 22:46:34 -07002384 u32 last_tag;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002385
2386 u32 msg_enable;
2387
2388 /* begin "tx thread" cacheline section */
Michael Chan20094932005-08-09 20:16:32 -07002389 void (*write32_tx_mbox) (struct tg3 *, u32,
2390 u32);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002391 u32 tx_prod;
2392 u32 tx_cons;
2393 u32 tx_pending;
2394
Linus Torvalds1da177e2005-04-16 15:20:36 -07002395 struct tg3_tx_buffer_desc *tx_ring;
2396 struct tx_ring_info *tx_buffers;
2397 dma_addr_t tx_desc_mapping;
2398
2399 /* begin "rx thread" cacheline section */
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002400 struct napi_struct napi;
Michael Chan20094932005-08-09 20:16:32 -07002401 void (*write32_rx_mbox) (struct tg3 *, u32,
2402 u32);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002403 u32 rx_rcb_ptr;
2404 u32 rx_std_ptr;
2405 u32 rx_jumbo_ptr;
2406 u32 rx_pending;
2407 u32 rx_jumbo_pending;
2408#if TG3_VLAN_TAG_USED
2409 struct vlan_group *vlgrp;
2410#endif
2411
2412 struct tg3_rx_buffer_desc *rx_std;
2413 struct ring_info *rx_std_buffers;
2414 dma_addr_t rx_std_mapping;
Michael Chanf92905d2006-06-29 20:14:29 -07002415 u32 rx_std_max_post;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002416
2417 struct tg3_rx_buffer_desc *rx_jumbo;
2418 struct ring_info *rx_jumbo_buffers;
2419 dma_addr_t rx_jumbo_mapping;
2420
2421 struct tg3_rx_buffer_desc *rx_rcb;
2422 dma_addr_t rx_rcb_mapping;
2423
Michael Chan7e72aad2005-07-25 12:31:17 -07002424 u32 rx_pkt_buf_sz;
2425
Linus Torvalds1da177e2005-04-16 15:20:36 -07002426 /* begin "everything else" cacheline(s) section */
2427 struct net_device_stats net_stats;
2428 struct net_device_stats net_stats_prev;
2429 struct tg3_ethtool_stats estats;
2430 struct tg3_ethtool_stats estats_prev;
2431
2432 unsigned long phy_crc_errors;
2433
2434 u32 rx_offset;
2435 u32 tg3_flags;
David S. Millerfac9b832005-05-18 22:46:34 -07002436#define TG3_FLAG_TAGGED_STATUS 0x00000001
Linus Torvalds1da177e2005-04-16 15:20:36 -07002437#define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002
2438#define TG3_FLAG_RX_CHECKSUMS 0x00000004
2439#define TG3_FLAG_USE_LINKCHG_REG 0x00000008
2440#define TG3_FLAG_USE_MI_INTERRUPT 0x00000010
2441#define TG3_FLAG_ENABLE_ASF 0x00000020
Matt Carlson8ed5d972007-05-07 00:25:49 -07002442#define TG3_FLAG_ASPM_WORKAROUND 0x00000040
Linus Torvalds1da177e2005-04-16 15:20:36 -07002443#define TG3_FLAG_POLL_SERDES 0x00000080
Linus Torvalds1da177e2005-04-16 15:20:36 -07002444#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
Linus Torvalds1da177e2005-04-16 15:20:36 -07002445#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
2446#define TG3_FLAG_WOL_SPEED_100MB 0x00000400
2447#define TG3_FLAG_WOL_ENABLE 0x00000800
2448#define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000
2449#define TG3_FLAG_NVRAM 0x00002000
2450#define TG3_FLAG_NVRAM_BUFFERED 0x00004000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002451#define TG3_FLAG_PCIX_MODE 0x00020000
2452#define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
2453#define TG3_FLAG_PCI_32BIT 0x00080000
Michael Chanbbadf502006-04-06 21:46:34 -07002454#define TG3_FLAG_SRAM_USE_CONFIG 0x00100000
Michael Chandf3e6542006-05-26 17:48:07 -07002455#define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000
Gary Zambranoa85feb82007-05-05 11:52:19 -07002456#define TG3_FLAG_WOL_CAP 0x00400000
Michael Chan0f893dc2005-07-25 12:30:38 -07002457#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002458#define TG3_FLAG_10_100_ONLY 0x01000000
2459#define TG3_FLAG_PAUSE_AUTONEG 0x02000000
Matt Carlson795d01c2007-10-07 23:28:17 -07002460#define TG3_FLAG_CPMU_PRESENT 0x04000000
Michael Chan4a29cc22006-03-19 13:21:12 -08002461#define TG3_FLAG_40BIT_DMA_BUG 0x08000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002462#define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
Michael Chan7544b092007-05-05 13:08:32 -07002463#define TG3_FLAG_SUPPORT_MSI 0x20000000
Michael Chand18edcb2007-03-24 20:57:11 -07002464#define TG3_FLAG_CHIP_RESETTING 0x40000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002465#define TG3_FLAG_INIT_COMPLETE 0x80000000
2466 u32 tg3_flags2;
2467#define TG3_FLG2_RESTART_TIMER 0x00000001
Michael Chan7f62ad52007-02-20 23:25:40 -08002468#define TG3_FLG2_TSO_BUG 0x00000002
Linus Torvalds1da177e2005-04-16 15:20:36 -07002469#define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004
2470#define TG3_FLG2_IS_5788 0x00000008
2471#define TG3_FLG2_MAX_RXPEND_64 0x00000010
2472#define TG3_FLG2_TSO_CAPABLE 0x00000020
2473#define TG3_FLG2_PHY_ADC_BUG 0x00000040
2474#define TG3_FLG2_PHY_5704_A0_BUG 0x00000080
2475#define TG3_FLG2_PHY_BER_BUG 0x00000100
2476#define TG3_FLG2_PCI_EXPRESS 0x00000200
2477#define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400
2478#define TG3_FLG2_HW_AUTONEG 0x00000800
Michael Chan9d26e212006-12-07 00:21:14 -08002479#define TG3_FLG2_IS_NIC 0x00001000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002480#define TG3_FLG2_PHY_SERDES 0x00002000
2481#define TG3_FLG2_CAPACITIVE_COUPLING 0x00004000
2482#define TG3_FLG2_FLASH 0x00008000
Michael Chan5a6f3072006-03-20 22:28:05 -08002483#define TG3_FLG2_HW_TSO_1 0x00010000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002484#define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000
2485#define TG3_FLG2_5705_PLUS 0x00040000
John W. Linville6708e5c2005-04-21 17:00:52 -07002486#define TG3_FLG2_5750_PLUS 0x00080000
Michael Chane6af3012005-04-21 17:12:05 -07002487#define TG3_FLG2_PROTECTED_NVRAM 0x00100000
Michael Chan88b06bc22005-04-21 17:13:25 -07002488#define TG3_FLG2_USING_MSI 0x00200000
Michael Chan0f893dc2005-07-25 12:30:38 -07002489#define TG3_FLG2_JUMBO_CAPABLE 0x00400000
Michael Chan747e8f82005-07-25 12:33:22 -07002490#define TG3_FLG2_MII_SERDES 0x00800000
2491#define TG3_FLG2_ANY_SERDES (TG3_FLG2_PHY_SERDES | \
2492 TG3_FLG2_MII_SERDES)
2493#define TG3_FLG2_PARALLEL_DETECT 0x01000000
Michael Chan68929142005-08-09 20:17:14 -07002494#define TG3_FLG2_ICH_WORKAROUND 0x02000000
Michael Chana4e2b342005-10-26 15:46:52 -07002495#define TG3_FLG2_5780_CLASS 0x04000000
Michael Chan5a6f3072006-03-20 22:28:05 -08002496#define TG3_FLG2_HW_TSO_2 0x08000000
2497#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
Michael Chanfcfa0a32006-03-20 22:28:41 -08002498#define TG3_FLG2_1SHOT_MSI 0x10000000
Michael Chanc424cb22006-04-29 18:56:34 -07002499#define TG3_FLG2_PHY_JITTER_BUG 0x20000000
David S. Millerf49639e2006-06-09 11:58:36 -07002500#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
Michael Chanc1d2a192007-01-08 19:57:20 -08002501#define TG3_FLG2_PHY_ADJUST_TRIM 0x80000000
Matt Carlson6b91fa02007-10-10 18:01:09 -07002502 u32 tg3_flags3;
2503#define TG3_FLG3_NO_NVRAM_ADDR_TRANS 0x00000001
Matt Carlson0d3031d2007-10-10 18:02:43 -07002504#define TG3_FLG3_ENABLE_APE 0x00000002
Matt Carlsonb5af7122007-11-12 21:22:02 -08002505#define TG3_FLG3_5761_5784_AX_FIXES 0x00000004
Matt Carlson41588ba2008-04-19 18:12:33 -07002506#define TG3_FLG3_5701_DMA_BUG 0x00000008
Matt Carlsondd477002008-05-25 23:45:58 -07002507#define TG3_FLG3_USE_PHYLIB 0x00000010
Matt Carlson158d7ab2008-05-29 01:37:54 -07002508#define TG3_FLG3_MDIOBUS_INITED 0x00000020
2509#define TG3_FLG3_MDIOBUS_PAUSED 0x00000040
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002510#define TG3_FLG3_PHY_CONNECTED 0x00000080
Matt Carlsona9daf362008-05-25 23:49:44 -07002511#define TG3_FLG3_RGMII_STD_IBND_DISABLE 0x00000100
2512#define TG3_FLG3_RGMII_EXT_IBND_RX_EN 0x00000200
2513#define TG3_FLG3_RGMII_EXT_IBND_TX_EN 0x00000400
Linus Torvalds1da177e2005-04-16 15:20:36 -07002514
Linus Torvalds1da177e2005-04-16 15:20:36 -07002515 struct timer_list timer;
2516 u16 timer_counter;
2517 u16 timer_multiplier;
2518 u32 timer_offset;
2519 u16 asf_counter;
2520 u16 asf_multiplier;
2521
Michael Chan3d3ebe72006-09-27 15:59:15 -07002522 /* 1 second counter for transient serdes link events */
2523 u32 serdes_counter;
2524#define SERDES_AN_TIMEOUT_5704S 2
2525#define SERDES_PARALLEL_DET_TIMEOUT 1
2526#define SERDES_AN_TIMEOUT_5714S 1
2527
Linus Torvalds1da177e2005-04-16 15:20:36 -07002528 struct tg3_link_config link_config;
2529 struct tg3_bufmgr_config bufmgr_config;
2530
2531 /* cache h/w values, often passed straight to h/w */
2532 u32 rx_mode;
2533 u32 tx_mode;
2534 u32 mac_mode;
2535 u32 mi_mode;
2536 u32 misc_host_ctrl;
2537 u32 grc_mode;
2538 u32 grc_local_ctrl;
2539 u32 dma_rwctrl;
2540 u32 coalesce_mode;
Matt Carlson8ed5d972007-05-07 00:25:49 -07002541 u32 pwrmgmt_thresh;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002542
2543 /* PCI block */
Matt Carlson795d01c2007-10-07 23:28:17 -07002544 u32 pci_chip_rev_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002545 u8 pci_cacheline_sz;
2546 u8 pci_lat_timer;
2547 u8 pci_hdr_type;
2548 u8 pci_bist;
2549
2550 int pm_cap;
Michael Chan4cf78e42005-07-25 12:29:19 -07002551 int msi_cap;
Matt Carlson9974a352007-10-07 23:27:28 -07002552 int pcix_cap;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002553
Matt Carlson158d7ab2008-05-29 01:37:54 -07002554 struct mii_bus mdio_bus;
2555 int mdio_irq[PHY_MAX_ADDR];
2556
Linus Torvalds1da177e2005-04-16 15:20:36 -07002557 /* PHY info */
2558 u32 phy_id;
2559#define PHY_ID_MASK 0xfffffff0
2560#define PHY_ID_BCM5400 0x60008040
2561#define PHY_ID_BCM5401 0x60008050
2562#define PHY_ID_BCM5411 0x60008070
2563#define PHY_ID_BCM5701 0x60008110
2564#define PHY_ID_BCM5703 0x60008160
2565#define PHY_ID_BCM5704 0x60008190
2566#define PHY_ID_BCM5705 0x600081a0
2567#define PHY_ID_BCM5750 0x60008180
Michael Chan85e94ce2005-04-21 17:05:28 -07002568#define PHY_ID_BCM5752 0x60008100
Michael Chana4e2b342005-10-26 15:46:52 -07002569#define PHY_ID_BCM5714 0x60008340
Michael Chan4cf78e42005-07-25 12:29:19 -07002570#define PHY_ID_BCM5780 0x60008350
Michael Chanaf36e6b2006-03-23 01:28:06 -08002571#define PHY_ID_BCM5755 0xbc050cc0
Michael Chand9ab5ad2006-03-20 22:27:35 -08002572#define PHY_ID_BCM5787 0xbc050ce0
Michael Chan126a3362006-09-27 16:03:07 -07002573#define PHY_ID_BCM5756 0xbc050ed0
Matt Carlsond30cdd22007-10-07 23:28:35 -07002574#define PHY_ID_BCM5784 0xbc050fa0
Matt Carlson9936bcf2007-10-10 18:03:07 -07002575#define PHY_ID_BCM5761 0xbc050fd0
Michael Chanb5d37722006-09-27 16:06:21 -07002576#define PHY_ID_BCM5906 0xdc00ac40
Linus Torvalds1da177e2005-04-16 15:20:36 -07002577#define PHY_ID_BCM8002 0x60010140
2578#define PHY_ID_INVALID 0xffffffff
2579#define PHY_ID_REV_MASK 0x0000000f
2580#define PHY_REV_BCM5401_B0 0x1
2581#define PHY_REV_BCM5401_B2 0x3
2582#define PHY_REV_BCM5401_C0 0x6
2583#define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
Matt Carlsona9daf362008-05-25 23:49:44 -07002584#define TG3_PHY_ID_BCM50610 0x143bd60
2585#define TG3_PHY_ID_BCMAC131 0x143bc70
2586
Linus Torvalds1da177e2005-04-16 15:20:36 -07002587
2588 u32 led_ctrl;
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002589 u32 phy_otp;
Matt Carlson8a6eac92007-10-21 16:17:55 -07002590 u16 pci_cmd;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002591
2592 char board_part_number[24];
Matt Carlson9c8a6202007-10-21 16:16:08 -07002593#define TG3_VER_SIZE 32
2594 char fw_ver[TG3_VER_SIZE];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002595 u32 nic_sram_data_cfg;
2596 u32 pci_clock_ctrl;
2597 struct pci_dev *pdev_peer;
2598
2599 /* This macro assumes the passed PHY ID is already masked
2600 * with PHY_ID_MASK.
2601 */
2602#define KNOWN_PHY_ID(X) \
2603 ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
2604 (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
2605 (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
2606 (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
Michael Chana4e2b342005-10-26 15:46:52 -07002607 (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
Michael Chand9ab5ad2006-03-20 22:27:35 -08002608 (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
Michael Chan126a3362006-09-27 16:03:07 -07002609 (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
Matt Carlson9936bcf2007-10-10 18:03:07 -07002610 (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
2611 (X) == PHY_ID_BCM8002)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002612
2613 struct tg3_hw_stats *hw_stats;
2614 dma_addr_t stats_mapping;
2615 struct work_struct reset_task;
2616
Michael Chanec41c7d2006-01-17 02:40:55 -08002617 int nvram_lock_cnt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002618 u32 nvram_size;
Matt Carlsonfd1122a2008-05-02 16:48:36 -07002619#define TG3_NVRAM_SIZE_64KB 0x00010000
2620#define TG3_NVRAM_SIZE_128KB 0x00020000
2621#define TG3_NVRAM_SIZE_256KB 0x00040000
2622#define TG3_NVRAM_SIZE_512KB 0x00080000
2623#define TG3_NVRAM_SIZE_1MB 0x00100000
2624#define TG3_NVRAM_SIZE_2MB 0x00200000
2625
Linus Torvalds1da177e2005-04-16 15:20:36 -07002626 u32 nvram_pagesize;
2627 u32 nvram_jedecnum;
2628
2629#define JEDEC_ATMEL 0x1f
2630#define JEDEC_ST 0x20
2631#define JEDEC_SAIFUN 0x4f
2632#define JEDEC_SST 0xbf
2633
Matt Carlsonfd1122a2008-05-02 16:48:36 -07002634#define ATMEL_AT24C64_CHIP_SIZE TG3_NVRAM_SIZE_64KB
Linus Torvalds1da177e2005-04-16 15:20:36 -07002635#define ATMEL_AT24C64_PAGE_SIZE (32)
2636
Matt Carlsonfd1122a2008-05-02 16:48:36 -07002637#define ATMEL_AT24C512_CHIP_SIZE TG3_NVRAM_SIZE_512KB
Linus Torvalds1da177e2005-04-16 15:20:36 -07002638#define ATMEL_AT24C512_PAGE_SIZE (128)
2639
2640#define ATMEL_AT45DB0X1B_PAGE_POS 9
2641#define ATMEL_AT45DB0X1B_PAGE_SIZE 264
2642
2643#define ATMEL_AT25F512_PAGE_SIZE 256
2644
2645#define ST_M45PEX0_PAGE_SIZE 256
2646
2647#define SAIFUN_SA25F0XX_PAGE_SIZE 256
2648
2649#define SST_25VF0X0_PAGE_SIZE 4098
2650
David S. Miller15f98502005-05-18 22:49:26 -07002651 struct ethtool_coalesce coal;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002652};
2653
2654#endif /* !(_T3_H) */