blob: 96dff04334b862d7d7410c091fc528212333550b [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
2/*
3 Written 1998-2001 by Donald Becker.
4
5 Current Maintainer: Roger Luethi <rl@hellgate.ch>
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
13
14 This driver is designed for the VIA VT86C100A Rhine-I.
15 It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
16 and management NIC 6105M).
17
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
21 Annapolis MD 21403
22
23
24 This driver contains some changes from the original Donald Becker
25 version. He may or may not be interested in bug reports on this
26 code. You can find his versions at:
27 http://www.scyld.com/network/via-rhine.html
Jeff Garzik03a8c662006-06-27 07:57:22 -040028 [link no longer provides useful info -jgarzik]
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30*/
31
32#define DRV_NAME "via-rhine"
Roger Luethie84df482007-03-06 19:57:37 +010033#define DRV_VERSION "1.4.3"
34#define DRV_RELDATE "2007-03-06"
Linus Torvalds1da177e2005-04-16 15:20:36 -070035
36
37/* A few user-configurable values.
38 These may be modified when a driver module is loaded. */
39
40static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
41static int max_interrupt_work = 20;
42
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1518 effectively disables this feature. */
Dustin Marquessb47157f2007-08-10 14:05:15 -070045#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \
46 || defined(CONFIG_SPARC) || defined(__ia64__) \
47 || defined(__sh__) || defined(__mips__)
48static int rx_copybreak = 1518;
49#else
Linus Torvalds1da177e2005-04-16 15:20:36 -070050static int rx_copybreak;
Dustin Marquessb47157f2007-08-10 14:05:15 -070051#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
Roger Luethib933b4d2006-08-14 23:00:21 -070053/* Work-around for broken BIOSes: they are unable to get the chip back out of
54 power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */
55static int avoid_D3;
56
Linus Torvalds1da177e2005-04-16 15:20:36 -070057/*
58 * In case you are looking for 'options[]' or 'full_duplex[]', they
59 * are gone. Use ethtool(8) instead.
60 */
61
62/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
63 The Rhine has a 64 element 8390-like hash table. */
64static const int multicast_filter_limit = 32;
65
66
67/* Operational parameters that are set at compile time. */
68
69/* Keep the ring sizes a power of two for compile efficiency.
70 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
71 Making the Tx ring too large decreases the effectiveness of channel
72 bonding and packet priority.
73 There are no ill effects from too-large receive rings. */
74#define TX_RING_SIZE 16
75#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
Roger Luethi633949a2006-08-14 23:00:17 -070076#define RX_RING_SIZE 64
Linus Torvalds1da177e2005-04-16 15:20:36 -070077
78/* Operational parameters that usually are not changed. */
79
80/* Time in jiffies before concluding the transmitter is hung. */
81#define TX_TIMEOUT (2*HZ)
82
83#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
84
85#include <linux/module.h>
86#include <linux/moduleparam.h>
87#include <linux/kernel.h>
88#include <linux/string.h>
89#include <linux/timer.h>
90#include <linux/errno.h>
91#include <linux/ioport.h>
92#include <linux/slab.h>
93#include <linux/interrupt.h>
94#include <linux/pci.h>
Domen Puncer1e7f0bd2005-06-26 18:22:14 -040095#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070096#include <linux/netdevice.h>
97#include <linux/etherdevice.h>
98#include <linux/skbuff.h>
99#include <linux/init.h>
100#include <linux/delay.h>
101#include <linux/mii.h>
102#include <linux/ethtool.h>
103#include <linux/crc32.h>
104#include <linux/bitops.h>
105#include <asm/processor.h> /* Processor type for cache alignment. */
106#include <asm/io.h>
107#include <asm/irq.h>
108#include <asm/uaccess.h>
Roger Luethie84df482007-03-06 19:57:37 +0100109#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110
111/* These identify the driver base version and may not be removed. */
112static char version[] __devinitdata =
113KERN_INFO DRV_NAME ".c:v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n";
114
115/* This driver was written to use PCI memory space. Some early versions
116 of the Rhine may only work correctly with I/O space accesses. */
117#ifdef CONFIG_VIA_RHINE_MMIO
118#define USE_MMIO
119#else
120#endif
121
122MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
123MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
124MODULE_LICENSE("GPL");
125
126module_param(max_interrupt_work, int, 0);
127module_param(debug, int, 0);
128module_param(rx_copybreak, int, 0);
Roger Luethib933b4d2006-08-14 23:00:21 -0700129module_param(avoid_D3, bool, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700130MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt");
131MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");
132MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
Roger Luethib933b4d2006-08-14 23:00:21 -0700133MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134
135/*
136 Theory of Operation
137
138I. Board Compatibility
139
140This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
141controller.
142
143II. Board-specific settings
144
145Boards with this chip are functional only in a bus-master PCI slot.
146
147Many operational settings are loaded from the EEPROM to the Config word at
148offset 0x78. For most of these settings, this driver assumes that they are
149correct.
150If this driver is compiled to use PCI memory space operations the EEPROM
151must be configured to enable memory ops.
152
153III. Driver operation
154
155IIIa. Ring buffers
156
157This driver uses two statically allocated fixed-size descriptor lists
158formed into rings by a branch from the final descriptor to the beginning of
159the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
160
161IIIb/c. Transmit/Receive Structure
162
163This driver attempts to use a zero-copy receive and transmit scheme.
164
165Alas, all data buffers are required to start on a 32 bit boundary, so
166the driver must often copy transmit packets into bounce buffers.
167
168The driver allocates full frame size skbuffs for the Rx ring buffers at
169open() time and passes the skb->data field to the chip as receive data
170buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
171a fresh skbuff is allocated and the frame is copied to the new skbuff.
172When the incoming frame is larger, the skbuff is passed directly up the
173protocol stack. Buffers consumed this way are replaced by newly allocated
174skbuffs in the last phase of rhine_rx().
175
176The RX_COPYBREAK value is chosen to trade-off the memory wasted by
177using a full-sized skbuff for small frames vs. the copying costs of larger
178frames. New boards are typically used in generously configured machines
179and the underfilled buffers have negligible impact compared to the benefit of
180a single allocation size, so the default value of zero results in never
181copying packets. When copying is done, the cost is usually mitigated by using
182a combined copy/checksum routine. Copying also preloads the cache, which is
183most useful with small frames.
184
185Since the VIA chips are only able to transfer data to buffers on 32 bit
186boundaries, the IP header at offset 14 in an ethernet frame isn't
187longword aligned for further processing. Copying these unaligned buffers
188has the beneficial effect of 16-byte aligning the IP header.
189
190IIId. Synchronization
191
192The driver runs as two independent, single-threaded flows of control. One
193is the send-packet routine, which enforces single-threaded use by the
194dev->priv->lock spinlock. The other thread is the interrupt handler, which
195is single threaded by the hardware and interrupt handling software.
196
197The send packet thread has partial control over the Tx ring. It locks the
198dev->priv->lock whenever it's queuing a Tx packet. If the next slot in the ring
199is not available it stops the transmit queue by calling netif_stop_queue.
200
201The interrupt handler has exclusive control over the Rx ring and records stats
202from the Tx ring. After reaping the stats, it marks the Tx queue entry as
203empty by incrementing the dirty_tx mark. If at least half of the entries in
204the Rx ring are available the transmit queue is woken up if it was stopped.
205
206IV. Notes
207
208IVb. References
209
210Preliminary VT86C100A manual from http://www.via.com.tw/
211http://www.scyld.com/expert/100mbps.html
212http://www.scyld.com/expert/NWay.html
213ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
214ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
215
216
217IVc. Errata
218
219The VT86C100A manual is not reliable information.
220The 3043 chip does not handle unaligned transmit or receive buffers, resulting
221in significant performance degradation for bounce buffer copies on transmit
222and unaligned IP headers on receive.
223The chip does not pad to minimum transmit length.
224
225*/
226
227
228/* This table drives the PCI probe routines. It's mostly boilerplate in all
229 of the drivers, and will likely be provided by some future kernel.
230 Note the matching code -- the first table entry matchs all 56** cards but
231 second only the 1234 card.
232*/
233
234enum rhine_revs {
235 VT86C100A = 0x00,
236 VTunknown0 = 0x20,
237 VT6102 = 0x40,
238 VT8231 = 0x50, /* Integrated MAC */
239 VT8233 = 0x60, /* Integrated MAC */
240 VT8235 = 0x74, /* Integrated MAC */
241 VT8237 = 0x78, /* Integrated MAC */
242 VTunknown1 = 0x7C,
243 VT6105 = 0x80,
244 VT6105_B0 = 0x83,
245 VT6105L = 0x8A,
246 VT6107 = 0x8C,
247 VTunknown2 = 0x8E,
248 VT6105M = 0x90, /* Management adapter */
249};
250
251enum rhine_quirks {
252 rqWOL = 0x0001, /* Wake-On-LAN support */
253 rqForceReset = 0x0002,
254 rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */
255 rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */
256 rqRhineI = 0x0100, /* See comment below */
257};
258/*
259 * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
260 * MMIO as well as for the collision counter and the Tx FIFO underflow
261 * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
262 */
263
264/* Beware of PCI posted writes */
265#define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
266
Jeff Garzik46009c82006-06-27 09:12:38 -0400267static const struct pci_device_id rhine_pci_tbl[] = {
268 { 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, }, /* VT86C100A */
269 { 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6102 */
270 { 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, }, /* 6105{,L,LOM} */
271 { 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6105M */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272 { } /* terminate list */
273};
274MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
275
276
277/* Offsets to the device registers. */
278enum register_offsets {
279 StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
280 ChipCmd1=0x09,
281 IntrStatus=0x0C, IntrEnable=0x0E,
282 MulticastFilter0=0x10, MulticastFilter1=0x14,
283 RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
284 MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E,
285 MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
286 ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
287 RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
288 StickyHW=0x83, IntrStatus2=0x84,
289 WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
290 WOLcrClr1=0xA6, WOLcgClr=0xA7,
291 PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
292};
293
294/* Bits in ConfigD */
295enum backoff_bits {
296 BackOptional=0x01, BackModify=0x02,
297 BackCaptureEffect=0x04, BackRandom=0x08
298};
299
300#ifdef USE_MMIO
301/* Registers we check that mmio and reg are the same. */
302static const int mmio_verify_registers[] = {
303 RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
304 0
305};
306#endif
307
308/* Bits in the interrupt status/mask registers. */
309enum intr_status_bits {
310 IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,
311 IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,
312 IntrPCIErr=0x0040,
313 IntrStatsMax=0x0080, IntrRxEarly=0x0100,
314 IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,
315 IntrTxAborted=0x2000, IntrLinkChange=0x4000,
316 IntrRxWakeUp=0x8000,
317 IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
318 IntrTxDescRace=0x080000, /* mapped from IntrStatus2 */
319 IntrTxErrSummary=0x082218,
320};
321
322/* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
323enum wol_bits {
324 WOLucast = 0x10,
325 WOLmagic = 0x20,
326 WOLbmcast = 0x30,
327 WOLlnkon = 0x40,
328 WOLlnkoff = 0x80,
329};
330
331/* The Rx and Tx buffer descriptors. */
332struct rx_desc {
Al Viro53c03f52007-08-23 02:33:30 -0400333 __le32 rx_status;
334 __le32 desc_length; /* Chain flag, Buffer/frame length */
335 __le32 addr;
336 __le32 next_desc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337};
338struct tx_desc {
Al Viro53c03f52007-08-23 02:33:30 -0400339 __le32 tx_status;
340 __le32 desc_length; /* Chain flag, Tx Config, Frame length */
341 __le32 addr;
342 __le32 next_desc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343};
344
345/* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
346#define TXDESC 0x00e08000
347
348enum rx_status_bits {
349 RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
350};
351
352/* Bits in *_desc.*_status */
353enum desc_status_bits {
354 DescOwn=0x80000000
355};
356
357/* Bits in ChipCmd. */
358enum chip_cmd_bits {
359 CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
360 CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
361 Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
362 Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
363};
364
365struct rhine_private {
366 /* Descriptor rings */
367 struct rx_desc *rx_ring;
368 struct tx_desc *tx_ring;
369 dma_addr_t rx_ring_dma;
370 dma_addr_t tx_ring_dma;
371
372 /* The addresses of receive-in-place skbuffs. */
373 struct sk_buff *rx_skbuff[RX_RING_SIZE];
374 dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
375
376 /* The saved address of a sent-in-place packet/buffer, for later free(). */
377 struct sk_buff *tx_skbuff[TX_RING_SIZE];
378 dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
379
Roger Luethi4be5de22006-04-04 20:49:16 +0200380 /* Tx bounce buffers (Rhine-I only) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700381 unsigned char *tx_buf[TX_RING_SIZE];
382 unsigned char *tx_bufs;
383 dma_addr_t tx_bufs_dma;
384
385 struct pci_dev *pdev;
386 long pioaddr;
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700387 struct net_device *dev;
388 struct napi_struct napi;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389 struct net_device_stats stats;
390 spinlock_t lock;
391
392 /* Frequently used values: keep some adjacent for cache effect. */
393 u32 quirks;
394 struct rx_desc *rx_head_desc;
395 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
396 unsigned int cur_tx, dirty_tx;
397 unsigned int rx_buf_sz; /* Based on MTU+slack. */
398 u8 wolopts;
399
400 u8 tx_thresh, rx_thresh;
401
402 struct mii_if_info mii_if;
403 void __iomem *base;
404};
405
406static int mdio_read(struct net_device *dev, int phy_id, int location);
407static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
408static int rhine_open(struct net_device *dev);
409static void rhine_tx_timeout(struct net_device *dev);
410static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev);
David Howells7d12e782006-10-05 14:55:46 +0100411static irqreturn_t rhine_interrupt(int irq, void *dev_instance);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412static void rhine_tx(struct net_device *dev);
Roger Luethi633949a2006-08-14 23:00:17 -0700413static int rhine_rx(struct net_device *dev, int limit);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700414static void rhine_error(struct net_device *dev, int intr_status);
415static void rhine_set_rx_mode(struct net_device *dev);
416static struct net_device_stats *rhine_get_stats(struct net_device *dev);
417static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
Jeff Garzik7282d492006-09-13 14:30:00 -0400418static const struct ethtool_ops netdev_ethtool_ops;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700419static int rhine_close(struct net_device *dev);
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -0700420static void rhine_shutdown (struct pci_dev *pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700421
422#define RHINE_WAIT_FOR(condition) do { \
423 int i=1024; \
424 while (!(condition) && --i) \
425 ; \
426 if (debug > 1 && i < 512) \
427 printk(KERN_INFO "%s: %4d cycles used @ %s:%d\n", \
428 DRV_NAME, 1024-i, __func__, __LINE__); \
429} while(0)
430
431static inline u32 get_intr_status(struct net_device *dev)
432{
433 struct rhine_private *rp = netdev_priv(dev);
434 void __iomem *ioaddr = rp->base;
435 u32 intr_status;
436
437 intr_status = ioread16(ioaddr + IntrStatus);
438 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
439 if (rp->quirks & rqStatusWBRace)
440 intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
441 return intr_status;
442}
443
444/*
445 * Get power related registers into sane state.
446 * Notify user about past WOL event.
447 */
448static void rhine_power_init(struct net_device *dev)
449{
450 struct rhine_private *rp = netdev_priv(dev);
451 void __iomem *ioaddr = rp->base;
452 u16 wolstat;
453
454 if (rp->quirks & rqWOL) {
455 /* Make sure chip is in power state D0 */
456 iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
457
458 /* Disable "force PME-enable" */
459 iowrite8(0x80, ioaddr + WOLcgClr);
460
461 /* Clear power-event config bits (WOL) */
462 iowrite8(0xFF, ioaddr + WOLcrClr);
463 /* More recent cards can manage two additional patterns */
464 if (rp->quirks & rq6patterns)
465 iowrite8(0x03, ioaddr + WOLcrClr1);
466
467 /* Save power-event status bits */
468 wolstat = ioread8(ioaddr + PwrcsrSet);
469 if (rp->quirks & rq6patterns)
470 wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
471
472 /* Clear power-event status bits */
473 iowrite8(0xFF, ioaddr + PwrcsrClr);
474 if (rp->quirks & rq6patterns)
475 iowrite8(0x03, ioaddr + PwrcsrClr1);
476
477 if (wolstat) {
478 char *reason;
479 switch (wolstat) {
480 case WOLmagic:
481 reason = "Magic packet";
482 break;
483 case WOLlnkon:
484 reason = "Link went up";
485 break;
486 case WOLlnkoff:
487 reason = "Link went down";
488 break;
489 case WOLucast:
490 reason = "Unicast packet";
491 break;
492 case WOLbmcast:
493 reason = "Multicast/broadcast packet";
494 break;
495 default:
496 reason = "Unknown";
497 }
498 printk(KERN_INFO "%s: Woke system up. Reason: %s.\n",
499 DRV_NAME, reason);
500 }
501 }
502}
503
504static void rhine_chip_reset(struct net_device *dev)
505{
506 struct rhine_private *rp = netdev_priv(dev);
507 void __iomem *ioaddr = rp->base;
508
509 iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
510 IOSYNC;
511
512 if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
513 printk(KERN_INFO "%s: Reset not complete yet. "
514 "Trying harder.\n", DRV_NAME);
515
516 /* Force reset */
517 if (rp->quirks & rqForceReset)
518 iowrite8(0x40, ioaddr + MiscCmd);
519
520 /* Reset can take somewhat longer (rare) */
521 RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset));
522 }
523
524 if (debug > 1)
525 printk(KERN_INFO "%s: Reset %s.\n", dev->name,
526 (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) ?
527 "failed" : "succeeded");
528}
529
530#ifdef USE_MMIO
531static void enable_mmio(long pioaddr, u32 quirks)
532{
533 int n;
534 if (quirks & rqRhineI) {
535 /* More recent docs say that this bit is reserved ... */
536 n = inb(pioaddr + ConfigA) | 0x20;
537 outb(n, pioaddr + ConfigA);
538 } else {
539 n = inb(pioaddr + ConfigD) | 0x80;
540 outb(n, pioaddr + ConfigD);
541 }
542}
543#endif
544
545/*
546 * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
547 * (plus 0x6C for Rhine-I/II)
548 */
549static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)
550{
551 struct rhine_private *rp = netdev_priv(dev);
552 void __iomem *ioaddr = rp->base;
553
554 outb(0x20, pioaddr + MACRegEEcsr);
555 RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20));
556
557#ifdef USE_MMIO
558 /*
559 * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
560 * MMIO. If reloading EEPROM was done first this could be avoided, but
561 * it is not known if that still works with the "win98-reboot" problem.
562 */
563 enable_mmio(pioaddr, rp->quirks);
564#endif
565
566 /* Turn off EEPROM-controlled wake-up (magic packet) */
567 if (rp->quirks & rqWOL)
568 iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
569
570}
571
572#ifdef CONFIG_NET_POLL_CONTROLLER
573static void rhine_poll(struct net_device *dev)
574{
575 disable_irq(dev->irq);
David Howells7d12e782006-10-05 14:55:46 +0100576 rhine_interrupt(dev->irq, (void *)dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700577 enable_irq(dev->irq);
578}
579#endif
580
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700581static int rhine_napipoll(struct napi_struct *napi, int budget)
Roger Luethi633949a2006-08-14 23:00:17 -0700582{
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700583 struct rhine_private *rp = container_of(napi, struct rhine_private, napi);
584 struct net_device *dev = rp->dev;
Roger Luethi633949a2006-08-14 23:00:17 -0700585 void __iomem *ioaddr = rp->base;
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700586 int work_done;
Roger Luethi633949a2006-08-14 23:00:17 -0700587
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700588 work_done = rhine_rx(dev, budget);
Roger Luethi633949a2006-08-14 23:00:17 -0700589
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700590 if (work_done < budget) {
591 netif_rx_complete(dev, napi);
Roger Luethi633949a2006-08-14 23:00:17 -0700592
593 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
594 IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
595 IntrTxDone | IntrTxError | IntrTxUnderrun |
596 IntrPCIErr | IntrStatsMax | IntrLinkChange,
597 ioaddr + IntrEnable);
Roger Luethi633949a2006-08-14 23:00:17 -0700598 }
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700599 return work_done;
Roger Luethi633949a2006-08-14 23:00:17 -0700600}
Roger Luethi633949a2006-08-14 23:00:17 -0700601
Adrian Bunkde4e7c82008-01-30 22:02:05 +0200602static void __devinit rhine_hw_init(struct net_device *dev, long pioaddr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700603{
604 struct rhine_private *rp = netdev_priv(dev);
605
606 /* Reset the chip to erase previous misconfiguration. */
607 rhine_chip_reset(dev);
608
609 /* Rhine-I needs extra time to recuperate before EEPROM reload */
610 if (rp->quirks & rqRhineI)
611 msleep(5);
612
613 /* Reload EEPROM controlled bytes cleared by soft reset */
614 rhine_reload_eeprom(pioaddr, dev);
615}
616
617static int __devinit rhine_init_one(struct pci_dev *pdev,
618 const struct pci_device_id *ent)
619{
620 struct net_device *dev;
621 struct rhine_private *rp;
622 int i, rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700623 u32 quirks;
624 long pioaddr;
625 long memaddr;
626 void __iomem *ioaddr;
627 int io_size, phy_id;
628 const char *name;
629#ifdef USE_MMIO
630 int bar = 1;
631#else
632 int bar = 0;
633#endif
Joe Perches0795af52007-10-03 17:59:30 -0700634 DECLARE_MAC_BUF(mac);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700635
636/* when built into the kernel, we only print version if device is found */
637#ifndef MODULE
638 static int printed_version;
639 if (!printed_version++)
640 printk(version);
641#endif
642
Linus Torvalds1da177e2005-04-16 15:20:36 -0700643 io_size = 256;
644 phy_id = 0;
645 quirks = 0;
646 name = "Rhine";
Auke Kok44c10132007-06-08 15:46:36 -0700647 if (pdev->revision < VTunknown0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648 quirks = rqRhineI;
649 io_size = 128;
650 }
Auke Kok44c10132007-06-08 15:46:36 -0700651 else if (pdev->revision >= VT6102) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700652 quirks = rqWOL | rqForceReset;
Auke Kok44c10132007-06-08 15:46:36 -0700653 if (pdev->revision < VT6105) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700654 name = "Rhine II";
655 quirks |= rqStatusWBRace; /* Rhine-II exclusive */
656 }
657 else {
658 phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */
Auke Kok44c10132007-06-08 15:46:36 -0700659 if (pdev->revision >= VT6105_B0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660 quirks |= rq6patterns;
Auke Kok44c10132007-06-08 15:46:36 -0700661 if (pdev->revision < VT6105M)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700662 name = "Rhine III";
663 else
664 name = "Rhine III (Management Adapter)";
665 }
666 }
667
668 rc = pci_enable_device(pdev);
669 if (rc)
670 goto err_out;
671
672 /* this should always be supported */
Domen Puncer1e7f0bd2005-06-26 18:22:14 -0400673 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700674 if (rc) {
675 printk(KERN_ERR "32-bit PCI DMA addresses not supported by "
676 "the card!?\n");
677 goto err_out;
678 }
679
680 /* sanity check */
681 if ((pci_resource_len(pdev, 0) < io_size) ||
682 (pci_resource_len(pdev, 1) < io_size)) {
683 rc = -EIO;
684 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
685 goto err_out;
686 }
687
688 pioaddr = pci_resource_start(pdev, 0);
689 memaddr = pci_resource_start(pdev, 1);
690
691 pci_set_master(pdev);
692
693 dev = alloc_etherdev(sizeof(struct rhine_private));
694 if (!dev) {
695 rc = -ENOMEM;
696 printk(KERN_ERR "alloc_etherdev failed\n");
697 goto err_out;
698 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700699 SET_NETDEV_DEV(dev, &pdev->dev);
700
701 rp = netdev_priv(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700702 rp->dev = dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700703 rp->quirks = quirks;
704 rp->pioaddr = pioaddr;
705 rp->pdev = pdev;
706
707 rc = pci_request_regions(pdev, DRV_NAME);
708 if (rc)
709 goto err_out_free_netdev;
710
711 ioaddr = pci_iomap(pdev, bar, io_size);
712 if (!ioaddr) {
713 rc = -EIO;
714 printk(KERN_ERR "ioremap failed for device %s, region 0x%X "
715 "@ 0x%lX\n", pci_name(pdev), io_size, memaddr);
716 goto err_out_free_res;
717 }
718
719#ifdef USE_MMIO
720 enable_mmio(pioaddr, quirks);
721
722 /* Check that selected MMIO registers match the PIO ones */
723 i = 0;
724 while (mmio_verify_registers[i]) {
725 int reg = mmio_verify_registers[i++];
726 unsigned char a = inb(pioaddr+reg);
727 unsigned char b = readb(ioaddr+reg);
728 if (a != b) {
729 rc = -EIO;
730 printk(KERN_ERR "MMIO do not match PIO [%02x] "
731 "(%02x != %02x)\n", reg, a, b);
732 goto err_out_unmap;
733 }
734 }
735#endif /* USE_MMIO */
736
737 dev->base_addr = (unsigned long)ioaddr;
738 rp->base = ioaddr;
739
740 /* Get chip registers into a sane state */
741 rhine_power_init(dev);
742 rhine_hw_init(dev, pioaddr);
743
744 for (i = 0; i < 6; i++)
745 dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
John W. Linvilleb81e8e12005-09-12 10:48:58 -0400746 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747
John W. Linvilleb81e8e12005-09-12 10:48:58 -0400748 if (!is_valid_ether_addr(dev->perm_addr)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700749 rc = -EIO;
750 printk(KERN_ERR "Invalid MAC address\n");
751 goto err_out_unmap;
752 }
753
754 /* For Rhine-I/II, phy_id is loaded from EEPROM */
755 if (!phy_id)
756 phy_id = ioread8(ioaddr + 0x6C);
757
758 dev->irq = pdev->irq;
759
760 spin_lock_init(&rp->lock);
761 rp->mii_if.dev = dev;
762 rp->mii_if.mdio_read = mdio_read;
763 rp->mii_if.mdio_write = mdio_write;
764 rp->mii_if.phy_id_mask = 0x1f;
765 rp->mii_if.reg_num_mask = 0x1f;
766
767 /* The chip-specific entries in the device structure. */
768 dev->open = rhine_open;
769 dev->hard_start_xmit = rhine_start_tx;
770 dev->stop = rhine_close;
771 dev->get_stats = rhine_get_stats;
772 dev->set_multicast_list = rhine_set_rx_mode;
773 dev->do_ioctl = netdev_ioctl;
774 dev->ethtool_ops = &netdev_ethtool_ops;
775 dev->tx_timeout = rhine_tx_timeout;
776 dev->watchdog_timeo = TX_TIMEOUT;
777#ifdef CONFIG_NET_POLL_CONTROLLER
778 dev->poll_controller = rhine_poll;
779#endif
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700780 netif_napi_add(dev, &rp->napi, rhine_napipoll, 64);
Francois Romieu32b0f532008-07-11 00:30:14 +0200781
Linus Torvalds1da177e2005-04-16 15:20:36 -0700782 if (rp->quirks & rqRhineI)
783 dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
784
785 /* dev->name not defined before register_netdev()! */
786 rc = register_netdev(dev);
787 if (rc)
788 goto err_out_unmap;
789
Joe Perches0795af52007-10-03 17:59:30 -0700790 printk(KERN_INFO "%s: VIA %s at 0x%lx, %s, IRQ %d.\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700791 dev->name, name,
792#ifdef USE_MMIO
Joe Perches0795af52007-10-03 17:59:30 -0700793 memaddr,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794#else
Joe Perches0795af52007-10-03 17:59:30 -0700795 (long)ioaddr,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700796#endif
Joe Perches0795af52007-10-03 17:59:30 -0700797 print_mac(mac, dev->dev_addr), pdev->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798
799 pci_set_drvdata(pdev, dev);
800
801 {
802 u16 mii_cmd;
803 int mii_status = mdio_read(dev, phy_id, 1);
804 mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
805 mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
806 if (mii_status != 0xffff && mii_status != 0x0000) {
807 rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
808 printk(KERN_INFO "%s: MII PHY found at address "
809 "%d, status 0x%4.4x advertising %4.4x "
810 "Link %4.4x.\n", dev->name, phy_id,
811 mii_status, rp->mii_if.advertising,
812 mdio_read(dev, phy_id, 5));
813
814 /* set IFF_RUNNING */
815 if (mii_status & BMSR_LSTATUS)
816 netif_carrier_on(dev);
817 else
818 netif_carrier_off(dev);
819
820 }
821 }
822 rp->mii_if.phy_id = phy_id;
Roger Luethib933b4d2006-08-14 23:00:21 -0700823 if (debug > 1 && avoid_D3)
824 printk(KERN_INFO "%s: No D3 power state at shutdown.\n",
825 dev->name);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700826
827 return 0;
828
829err_out_unmap:
830 pci_iounmap(pdev, ioaddr);
831err_out_free_res:
832 pci_release_regions(pdev);
833err_out_free_netdev:
834 free_netdev(dev);
835err_out:
836 return rc;
837}
838
839static int alloc_ring(struct net_device* dev)
840{
841 struct rhine_private *rp = netdev_priv(dev);
842 void *ring;
843 dma_addr_t ring_dma;
844
845 ring = pci_alloc_consistent(rp->pdev,
846 RX_RING_SIZE * sizeof(struct rx_desc) +
847 TX_RING_SIZE * sizeof(struct tx_desc),
848 &ring_dma);
849 if (!ring) {
850 printk(KERN_ERR "Could not allocate DMA memory.\n");
851 return -ENOMEM;
852 }
853 if (rp->quirks & rqRhineI) {
854 rp->tx_bufs = pci_alloc_consistent(rp->pdev,
855 PKT_BUF_SZ * TX_RING_SIZE,
856 &rp->tx_bufs_dma);
857 if (rp->tx_bufs == NULL) {
858 pci_free_consistent(rp->pdev,
859 RX_RING_SIZE * sizeof(struct rx_desc) +
860 TX_RING_SIZE * sizeof(struct tx_desc),
861 ring, ring_dma);
862 return -ENOMEM;
863 }
864 }
865
866 rp->rx_ring = ring;
867 rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
868 rp->rx_ring_dma = ring_dma;
869 rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
870
871 return 0;
872}
873
874static void free_ring(struct net_device* dev)
875{
876 struct rhine_private *rp = netdev_priv(dev);
877
878 pci_free_consistent(rp->pdev,
879 RX_RING_SIZE * sizeof(struct rx_desc) +
880 TX_RING_SIZE * sizeof(struct tx_desc),
881 rp->rx_ring, rp->rx_ring_dma);
882 rp->tx_ring = NULL;
883
884 if (rp->tx_bufs)
885 pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE,
886 rp->tx_bufs, rp->tx_bufs_dma);
887
888 rp->tx_bufs = NULL;
889
890}
891
892static void alloc_rbufs(struct net_device *dev)
893{
894 struct rhine_private *rp = netdev_priv(dev);
895 dma_addr_t next;
896 int i;
897
898 rp->dirty_rx = rp->cur_rx = 0;
899
900 rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
901 rp->rx_head_desc = &rp->rx_ring[0];
902 next = rp->rx_ring_dma;
903
904 /* Init the ring entries */
905 for (i = 0; i < RX_RING_SIZE; i++) {
906 rp->rx_ring[i].rx_status = 0;
907 rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
908 next += sizeof(struct rx_desc);
909 rp->rx_ring[i].next_desc = cpu_to_le32(next);
910 rp->rx_skbuff[i] = NULL;
911 }
912 /* Mark the last entry as wrapping the ring. */
913 rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
914
915 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
916 for (i = 0; i < RX_RING_SIZE; i++) {
917 struct sk_buff *skb = dev_alloc_skb(rp->rx_buf_sz);
918 rp->rx_skbuff[i] = skb;
919 if (skb == NULL)
920 break;
921 skb->dev = dev; /* Mark as being used by this device. */
922
923 rp->rx_skbuff_dma[i] =
David S. Miller689be432005-06-28 15:25:31 -0700924 pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700925 PCI_DMA_FROMDEVICE);
926
927 rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]);
928 rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
929 }
930 rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
931}
932
933static void free_rbufs(struct net_device* dev)
934{
935 struct rhine_private *rp = netdev_priv(dev);
936 int i;
937
938 /* Free all the skbuffs in the Rx queue. */
939 for (i = 0; i < RX_RING_SIZE; i++) {
940 rp->rx_ring[i].rx_status = 0;
941 rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
942 if (rp->rx_skbuff[i]) {
943 pci_unmap_single(rp->pdev,
944 rp->rx_skbuff_dma[i],
945 rp->rx_buf_sz, PCI_DMA_FROMDEVICE);
946 dev_kfree_skb(rp->rx_skbuff[i]);
947 }
948 rp->rx_skbuff[i] = NULL;
949 }
950}
951
952static void alloc_tbufs(struct net_device* dev)
953{
954 struct rhine_private *rp = netdev_priv(dev);
955 dma_addr_t next;
956 int i;
957
958 rp->dirty_tx = rp->cur_tx = 0;
959 next = rp->tx_ring_dma;
960 for (i = 0; i < TX_RING_SIZE; i++) {
961 rp->tx_skbuff[i] = NULL;
962 rp->tx_ring[i].tx_status = 0;
963 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
964 next += sizeof(struct tx_desc);
965 rp->tx_ring[i].next_desc = cpu_to_le32(next);
Roger Luethi4be5de22006-04-04 20:49:16 +0200966 if (rp->quirks & rqRhineI)
967 rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700968 }
969 rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
970
971}
972
973static void free_tbufs(struct net_device* dev)
974{
975 struct rhine_private *rp = netdev_priv(dev);
976 int i;
977
978 for (i = 0; i < TX_RING_SIZE; i++) {
979 rp->tx_ring[i].tx_status = 0;
980 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
981 rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
982 if (rp->tx_skbuff[i]) {
983 if (rp->tx_skbuff_dma[i]) {
984 pci_unmap_single(rp->pdev,
985 rp->tx_skbuff_dma[i],
986 rp->tx_skbuff[i]->len,
987 PCI_DMA_TODEVICE);
988 }
989 dev_kfree_skb(rp->tx_skbuff[i]);
990 }
991 rp->tx_skbuff[i] = NULL;
992 rp->tx_buf[i] = NULL;
993 }
994}
995
996static void rhine_check_media(struct net_device *dev, unsigned int init_media)
997{
998 struct rhine_private *rp = netdev_priv(dev);
999 void __iomem *ioaddr = rp->base;
1000
1001 mii_check_media(&rp->mii_if, debug, init_media);
1002
1003 if (rp->mii_if.full_duplex)
1004 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
1005 ioaddr + ChipCmd1);
1006 else
1007 iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
1008 ioaddr + ChipCmd1);
Roger Luethi00b428c2006-03-28 20:53:56 +02001009 if (debug > 1)
1010 printk(KERN_INFO "%s: force_media %d, carrier %d\n", dev->name,
1011 rp->mii_if.force_media, netif_carrier_ok(dev));
1012}
1013
1014/* Called after status of force_media possibly changed */
Adrian Bunk0761be42006-04-10 23:22:21 -07001015static void rhine_set_carrier(struct mii_if_info *mii)
Roger Luethi00b428c2006-03-28 20:53:56 +02001016{
1017 if (mii->force_media) {
1018 /* autoneg is off: Link is always assumed to be up */
1019 if (!netif_carrier_ok(mii->dev))
1020 netif_carrier_on(mii->dev);
1021 }
1022 else /* Let MMI library update carrier status */
1023 rhine_check_media(mii->dev, 0);
1024 if (debug > 1)
1025 printk(KERN_INFO "%s: force_media %d, carrier %d\n",
1026 mii->dev->name, mii->force_media,
1027 netif_carrier_ok(mii->dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001028}
1029
1030static void init_registers(struct net_device *dev)
1031{
1032 struct rhine_private *rp = netdev_priv(dev);
1033 void __iomem *ioaddr = rp->base;
1034 int i;
1035
1036 for (i = 0; i < 6; i++)
1037 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
1038
1039 /* Initialize other registers. */
1040 iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */
1041 /* Configure initial FIFO thresholds. */
1042 iowrite8(0x20, ioaddr + TxConfig);
1043 rp->tx_thresh = 0x20;
1044 rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */
1045
1046 iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
1047 iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
1048
1049 rhine_set_rx_mode(dev);
1050
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001051 napi_enable(&rp->napi);
Stephen Hemmingerab197662006-08-14 23:00:18 -07001052
Linus Torvalds1da177e2005-04-16 15:20:36 -07001053 /* Enable interrupts by setting the interrupt mask. */
1054 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
1055 IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
1056 IntrTxDone | IntrTxError | IntrTxUnderrun |
1057 IntrPCIErr | IntrStatsMax | IntrLinkChange,
1058 ioaddr + IntrEnable);
1059
1060 iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),
1061 ioaddr + ChipCmd);
1062 rhine_check_media(dev, 1);
1063}
1064
1065/* Enable MII link status auto-polling (required for IntrLinkChange) */
1066static void rhine_enable_linkmon(void __iomem *ioaddr)
1067{
1068 iowrite8(0, ioaddr + MIICmd);
1069 iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
1070 iowrite8(0x80, ioaddr + MIICmd);
1071
1072 RHINE_WAIT_FOR((ioread8(ioaddr + MIIRegAddr) & 0x20));
1073
1074 iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
1075}
1076
1077/* Disable MII link status auto-polling (required for MDIO access) */
1078static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks)
1079{
1080 iowrite8(0, ioaddr + MIICmd);
1081
1082 if (quirks & rqRhineI) {
1083 iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR
1084
John W. Linville38bb6b22006-05-19 10:51:21 -04001085 /* Can be called from ISR. Evil. */
1086 mdelay(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001087
1088 /* 0x80 must be set immediately before turning it off */
1089 iowrite8(0x80, ioaddr + MIICmd);
1090
1091 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x20);
1092
1093 /* Heh. Now clear 0x80 again. */
1094 iowrite8(0, ioaddr + MIICmd);
1095 }
1096 else
1097 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x80);
1098}
1099
1100/* Read and write over the MII Management Data I/O (MDIO) interface. */
1101
1102static int mdio_read(struct net_device *dev, int phy_id, int regnum)
1103{
1104 struct rhine_private *rp = netdev_priv(dev);
1105 void __iomem *ioaddr = rp->base;
1106 int result;
1107
1108 rhine_disable_linkmon(ioaddr, rp->quirks);
1109
1110 /* rhine_disable_linkmon already cleared MIICmd */
1111 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1112 iowrite8(regnum, ioaddr + MIIRegAddr);
1113 iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */
1114 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x40));
1115 result = ioread16(ioaddr + MIIData);
1116
1117 rhine_enable_linkmon(ioaddr);
1118 return result;
1119}
1120
1121static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)
1122{
1123 struct rhine_private *rp = netdev_priv(dev);
1124 void __iomem *ioaddr = rp->base;
1125
1126 rhine_disable_linkmon(ioaddr, rp->quirks);
1127
1128 /* rhine_disable_linkmon already cleared MIICmd */
1129 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1130 iowrite8(regnum, ioaddr + MIIRegAddr);
1131 iowrite16(value, ioaddr + MIIData);
1132 iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */
1133 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x20));
1134
1135 rhine_enable_linkmon(ioaddr);
1136}
1137
1138static int rhine_open(struct net_device *dev)
1139{
1140 struct rhine_private *rp = netdev_priv(dev);
1141 void __iomem *ioaddr = rp->base;
1142 int rc;
1143
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07001144 rc = request_irq(rp->pdev->irq, &rhine_interrupt, IRQF_SHARED, dev->name,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001145 dev);
1146 if (rc)
1147 return rc;
1148
1149 if (debug > 1)
1150 printk(KERN_DEBUG "%s: rhine_open() irq %d.\n",
1151 dev->name, rp->pdev->irq);
1152
1153 rc = alloc_ring(dev);
1154 if (rc) {
1155 free_irq(rp->pdev->irq, dev);
1156 return rc;
1157 }
1158 alloc_rbufs(dev);
1159 alloc_tbufs(dev);
1160 rhine_chip_reset(dev);
1161 init_registers(dev);
1162 if (debug > 2)
1163 printk(KERN_DEBUG "%s: Done rhine_open(), status %4.4x "
1164 "MII status: %4.4x.\n",
1165 dev->name, ioread16(ioaddr + ChipCmd),
1166 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1167
1168 netif_start_queue(dev);
1169
1170 return 0;
1171}
1172
1173static void rhine_tx_timeout(struct net_device *dev)
1174{
1175 struct rhine_private *rp = netdev_priv(dev);
1176 void __iomem *ioaddr = rp->base;
1177
1178 printk(KERN_WARNING "%s: Transmit timed out, status %4.4x, PHY status "
1179 "%4.4x, resetting...\n",
1180 dev->name, ioread16(ioaddr + IntrStatus),
1181 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1182
1183 /* protect against concurrent rx interrupts */
1184 disable_irq(rp->pdev->irq);
1185
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001186 napi_disable(&rp->napi);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001187
Linus Torvalds1da177e2005-04-16 15:20:36 -07001188 spin_lock(&rp->lock);
1189
1190 /* clear all descriptors */
1191 free_tbufs(dev);
1192 free_rbufs(dev);
1193 alloc_tbufs(dev);
1194 alloc_rbufs(dev);
1195
1196 /* Reinitialize the hardware. */
1197 rhine_chip_reset(dev);
1198 init_registers(dev);
1199
1200 spin_unlock(&rp->lock);
1201 enable_irq(rp->pdev->irq);
1202
1203 dev->trans_start = jiffies;
1204 rp->stats.tx_errors++;
1205 netif_wake_queue(dev);
1206}
1207
1208static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev)
1209{
1210 struct rhine_private *rp = netdev_priv(dev);
1211 void __iomem *ioaddr = rp->base;
1212 unsigned entry;
1213
1214 /* Caution: the write order is important here, set the field
1215 with the "ownership" bits last. */
1216
1217 /* Calculate the next Tx descriptor entry. */
1218 entry = rp->cur_tx % TX_RING_SIZE;
1219
Herbert Xu5b057c62006-06-23 02:06:41 -07001220 if (skb_padto(skb, ETH_ZLEN))
1221 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001222
1223 rp->tx_skbuff[entry] = skb;
1224
1225 if ((rp->quirks & rqRhineI) &&
Patrick McHardy84fa7932006-08-29 16:44:56 -07001226 (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001227 /* Must use alignment buffer. */
1228 if (skb->len > PKT_BUF_SZ) {
1229 /* packet too long, drop it */
1230 dev_kfree_skb(skb);
1231 rp->tx_skbuff[entry] = NULL;
1232 rp->stats.tx_dropped++;
1233 return 0;
1234 }
Craig Brind3e0d1672006-04-27 02:30:46 -07001235
1236 /* Padding is not copied and so must be redone. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001237 skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
Craig Brind3e0d1672006-04-27 02:30:46 -07001238 if (skb->len < ETH_ZLEN)
1239 memset(rp->tx_buf[entry] + skb->len, 0,
1240 ETH_ZLEN - skb->len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001241 rp->tx_skbuff_dma[entry] = 0;
1242 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
1243 (rp->tx_buf[entry] -
1244 rp->tx_bufs));
1245 } else {
1246 rp->tx_skbuff_dma[entry] =
1247 pci_map_single(rp->pdev, skb->data, skb->len,
1248 PCI_DMA_TODEVICE);
1249 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
1250 }
1251
1252 rp->tx_ring[entry].desc_length =
1253 cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1254
1255 /* lock eth irq */
1256 spin_lock_irq(&rp->lock);
1257 wmb();
1258 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1259 wmb();
1260
1261 rp->cur_tx++;
1262
1263 /* Non-x86 Todo: explicitly flush cache lines here. */
1264
1265 /* Wake the potentially-idle transmit channel */
1266 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1267 ioaddr + ChipCmd1);
1268 IOSYNC;
1269
1270 if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN)
1271 netif_stop_queue(dev);
1272
1273 dev->trans_start = jiffies;
1274
1275 spin_unlock_irq(&rp->lock);
1276
1277 if (debug > 4) {
1278 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
1279 dev->name, rp->cur_tx-1, entry);
1280 }
1281 return 0;
1282}
1283
1284/* The interrupt handler does all of the Rx thread work and cleans up
1285 after the Tx thread. */
David Howells7d12e782006-10-05 14:55:46 +01001286static irqreturn_t rhine_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001287{
1288 struct net_device *dev = dev_instance;
1289 struct rhine_private *rp = netdev_priv(dev);
1290 void __iomem *ioaddr = rp->base;
1291 u32 intr_status;
1292 int boguscnt = max_interrupt_work;
1293 int handled = 0;
1294
1295 while ((intr_status = get_intr_status(dev))) {
1296 handled = 1;
1297
1298 /* Acknowledge all of the current interrupt sources ASAP. */
1299 if (intr_status & IntrTxDescRace)
1300 iowrite8(0x08, ioaddr + IntrStatus2);
1301 iowrite16(intr_status & 0xffff, ioaddr + IntrStatus);
1302 IOSYNC;
1303
1304 if (debug > 4)
1305 printk(KERN_DEBUG "%s: Interrupt, status %8.8x.\n",
1306 dev->name, intr_status);
1307
1308 if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped |
Roger Luethi633949a2006-08-14 23:00:17 -07001309 IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf)) {
Roger Luethi633949a2006-08-14 23:00:17 -07001310 iowrite16(IntrTxAborted |
1311 IntrTxDone | IntrTxError | IntrTxUnderrun |
1312 IntrPCIErr | IntrStatsMax | IntrLinkChange,
1313 ioaddr + IntrEnable);
1314
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001315 netif_rx_schedule(dev, &rp->napi);
Roger Luethi633949a2006-08-14 23:00:17 -07001316 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001317
1318 if (intr_status & (IntrTxErrSummary | IntrTxDone)) {
1319 if (intr_status & IntrTxErrSummary) {
1320 /* Avoid scavenging before Tx engine turned off */
1321 RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn));
1322 if (debug > 2 &&
1323 ioread8(ioaddr+ChipCmd) & CmdTxOn)
1324 printk(KERN_WARNING "%s: "
Joe Perches24500222007-11-19 17:48:28 -08001325 "rhine_interrupt() Tx engine "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001326 "still on.\n", dev->name);
1327 }
1328 rhine_tx(dev);
1329 }
1330
1331 /* Abnormal error summary/uncommon events handlers. */
1332 if (intr_status & (IntrPCIErr | IntrLinkChange |
1333 IntrStatsMax | IntrTxError | IntrTxAborted |
1334 IntrTxUnderrun | IntrTxDescRace))
1335 rhine_error(dev, intr_status);
1336
1337 if (--boguscnt < 0) {
1338 printk(KERN_WARNING "%s: Too much work at interrupt, "
1339 "status=%#8.8x.\n",
1340 dev->name, intr_status);
1341 break;
1342 }
1343 }
1344
1345 if (debug > 3)
1346 printk(KERN_DEBUG "%s: exiting interrupt, status=%8.8x.\n",
1347 dev->name, ioread16(ioaddr + IntrStatus));
1348 return IRQ_RETVAL(handled);
1349}
1350
1351/* This routine is logically part of the interrupt handler, but isolated
1352 for clarity. */
1353static void rhine_tx(struct net_device *dev)
1354{
1355 struct rhine_private *rp = netdev_priv(dev);
1356 int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE;
1357
1358 spin_lock(&rp->lock);
1359
1360 /* find and cleanup dirty tx descriptors */
1361 while (rp->dirty_tx != rp->cur_tx) {
1362 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
1363 if (debug > 6)
Denis Vlasenkoed4030d2005-06-17 08:23:17 +03001364 printk(KERN_DEBUG "Tx scavenge %d status %8.8x.\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001365 entry, txstatus);
1366 if (txstatus & DescOwn)
1367 break;
1368 if (txstatus & 0x8000) {
1369 if (debug > 1)
1370 printk(KERN_DEBUG "%s: Transmit error, "
1371 "Tx status %8.8x.\n",
1372 dev->name, txstatus);
1373 rp->stats.tx_errors++;
1374 if (txstatus & 0x0400) rp->stats.tx_carrier_errors++;
1375 if (txstatus & 0x0200) rp->stats.tx_window_errors++;
1376 if (txstatus & 0x0100) rp->stats.tx_aborted_errors++;
1377 if (txstatus & 0x0080) rp->stats.tx_heartbeat_errors++;
1378 if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
1379 (txstatus & 0x0800) || (txstatus & 0x1000)) {
1380 rp->stats.tx_fifo_errors++;
1381 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1382 break; /* Keep the skb - we try again */
1383 }
1384 /* Transmitter restarted in 'abnormal' handler. */
1385 } else {
1386 if (rp->quirks & rqRhineI)
1387 rp->stats.collisions += (txstatus >> 3) & 0x0F;
1388 else
1389 rp->stats.collisions += txstatus & 0x0F;
1390 if (debug > 6)
1391 printk(KERN_DEBUG "collisions: %1.1x:%1.1x\n",
1392 (txstatus >> 3) & 0xF,
1393 txstatus & 0xF);
1394 rp->stats.tx_bytes += rp->tx_skbuff[entry]->len;
1395 rp->stats.tx_packets++;
1396 }
1397 /* Free the original skb. */
1398 if (rp->tx_skbuff_dma[entry]) {
1399 pci_unmap_single(rp->pdev,
1400 rp->tx_skbuff_dma[entry],
1401 rp->tx_skbuff[entry]->len,
1402 PCI_DMA_TODEVICE);
1403 }
1404 dev_kfree_skb_irq(rp->tx_skbuff[entry]);
1405 rp->tx_skbuff[entry] = NULL;
1406 entry = (++rp->dirty_tx) % TX_RING_SIZE;
1407 }
1408 if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4)
1409 netif_wake_queue(dev);
1410
1411 spin_unlock(&rp->lock);
1412}
1413
Roger Luethi633949a2006-08-14 23:00:17 -07001414/* Process up to limit frames from receive ring */
1415static int rhine_rx(struct net_device *dev, int limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001416{
1417 struct rhine_private *rp = netdev_priv(dev);
Roger Luethi633949a2006-08-14 23:00:17 -07001418 int count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001419 int entry = rp->cur_rx % RX_RING_SIZE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001420
1421 if (debug > 4) {
1422 printk(KERN_DEBUG "%s: rhine_rx(), entry %d status %8.8x.\n",
1423 dev->name, entry,
1424 le32_to_cpu(rp->rx_head_desc->rx_status));
1425 }
1426
1427 /* If EOP is set on the next entry, it's a new packet. Send it up. */
Roger Luethi633949a2006-08-14 23:00:17 -07001428 for (count = 0; count < limit; ++count) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001429 struct rx_desc *desc = rp->rx_head_desc;
1430 u32 desc_status = le32_to_cpu(desc->rx_status);
1431 int data_size = desc_status >> 16;
1432
Roger Luethi633949a2006-08-14 23:00:17 -07001433 if (desc_status & DescOwn)
1434 break;
1435
Linus Torvalds1da177e2005-04-16 15:20:36 -07001436 if (debug > 4)
Denis Vlasenkoed4030d2005-06-17 08:23:17 +03001437 printk(KERN_DEBUG "rhine_rx() status is %8.8x.\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001438 desc_status);
Roger Luethi633949a2006-08-14 23:00:17 -07001439
Linus Torvalds1da177e2005-04-16 15:20:36 -07001440 if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {
1441 if ((desc_status & RxWholePkt) != RxWholePkt) {
1442 printk(KERN_WARNING "%s: Oversized Ethernet "
1443 "frame spanned multiple buffers, entry "
1444 "%#x length %d status %8.8x!\n",
1445 dev->name, entry, data_size,
1446 desc_status);
1447 printk(KERN_WARNING "%s: Oversized Ethernet "
1448 "frame %p vs %p.\n", dev->name,
1449 rp->rx_head_desc, &rp->rx_ring[entry]);
1450 rp->stats.rx_length_errors++;
1451 } else if (desc_status & RxErr) {
1452 /* There was a error. */
1453 if (debug > 2)
Denis Vlasenkoed4030d2005-06-17 08:23:17 +03001454 printk(KERN_DEBUG "rhine_rx() Rx "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001455 "error was %8.8x.\n",
1456 desc_status);
1457 rp->stats.rx_errors++;
1458 if (desc_status & 0x0030) rp->stats.rx_length_errors++;
1459 if (desc_status & 0x0048) rp->stats.rx_fifo_errors++;
1460 if (desc_status & 0x0004) rp->stats.rx_frame_errors++;
1461 if (desc_status & 0x0002) {
1462 /* this can also be updated outside the interrupt handler */
1463 spin_lock(&rp->lock);
1464 rp->stats.rx_crc_errors++;
1465 spin_unlock(&rp->lock);
1466 }
1467 }
1468 } else {
1469 struct sk_buff *skb;
1470 /* Length should omit the CRC */
1471 int pkt_len = data_size - 4;
1472
1473 /* Check if the packet is long enough to accept without
1474 copying to a minimally-sized skbuff. */
1475 if (pkt_len < rx_copybreak &&
1476 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001477 skb_reserve(skb, 2); /* 16 byte align the IP header */
1478 pci_dma_sync_single_for_cpu(rp->pdev,
1479 rp->rx_skbuff_dma[entry],
1480 rp->rx_buf_sz,
1481 PCI_DMA_FROMDEVICE);
1482
David S. Miller8c7b7fa2007-07-10 22:08:12 -07001483 skb_copy_to_linear_data(skb,
David S. Miller689be432005-06-28 15:25:31 -07001484 rp->rx_skbuff[entry]->data,
David S. Miller8c7b7fa2007-07-10 22:08:12 -07001485 pkt_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001486 skb_put(skb, pkt_len);
1487 pci_dma_sync_single_for_device(rp->pdev,
1488 rp->rx_skbuff_dma[entry],
1489 rp->rx_buf_sz,
1490 PCI_DMA_FROMDEVICE);
1491 } else {
1492 skb = rp->rx_skbuff[entry];
1493 if (skb == NULL) {
1494 printk(KERN_ERR "%s: Inconsistent Rx "
1495 "descriptor chain.\n",
1496 dev->name);
1497 break;
1498 }
1499 rp->rx_skbuff[entry] = NULL;
1500 skb_put(skb, pkt_len);
1501 pci_unmap_single(rp->pdev,
1502 rp->rx_skbuff_dma[entry],
1503 rp->rx_buf_sz,
1504 PCI_DMA_FROMDEVICE);
1505 }
1506 skb->protocol = eth_type_trans(skb, dev);
Roger Luethi633949a2006-08-14 23:00:17 -07001507 netif_receive_skb(skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001508 dev->last_rx = jiffies;
1509 rp->stats.rx_bytes += pkt_len;
1510 rp->stats.rx_packets++;
1511 }
1512 entry = (++rp->cur_rx) % RX_RING_SIZE;
1513 rp->rx_head_desc = &rp->rx_ring[entry];
1514 }
1515
1516 /* Refill the Rx ring buffers. */
1517 for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) {
1518 struct sk_buff *skb;
1519 entry = rp->dirty_rx % RX_RING_SIZE;
1520 if (rp->rx_skbuff[entry] == NULL) {
1521 skb = dev_alloc_skb(rp->rx_buf_sz);
1522 rp->rx_skbuff[entry] = skb;
1523 if (skb == NULL)
1524 break; /* Better luck next round. */
1525 skb->dev = dev; /* Mark as being used by this device. */
1526 rp->rx_skbuff_dma[entry] =
David S. Miller689be432005-06-28 15:25:31 -07001527 pci_map_single(rp->pdev, skb->data,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001528 rp->rx_buf_sz,
1529 PCI_DMA_FROMDEVICE);
1530 rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]);
1531 }
1532 rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn);
1533 }
Roger Luethi633949a2006-08-14 23:00:17 -07001534
1535 return count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001536}
1537
1538/*
1539 * Clears the "tally counters" for CRC errors and missed frames(?).
1540 * It has been reported that some chips need a write of 0 to clear
1541 * these, for others the counters are set to 1 when written to and
1542 * instead cleared when read. So we clear them both ways ...
1543 */
1544static inline void clear_tally_counters(void __iomem *ioaddr)
1545{
1546 iowrite32(0, ioaddr + RxMissed);
1547 ioread16(ioaddr + RxCRCErrs);
1548 ioread16(ioaddr + RxMissed);
1549}
1550
1551static void rhine_restart_tx(struct net_device *dev) {
1552 struct rhine_private *rp = netdev_priv(dev);
1553 void __iomem *ioaddr = rp->base;
1554 int entry = rp->dirty_tx % TX_RING_SIZE;
1555 u32 intr_status;
1556
1557 /*
1558 * If new errors occured, we need to sort them out before doing Tx.
1559 * In that case the ISR will be back here RSN anyway.
1560 */
1561 intr_status = get_intr_status(dev);
1562
1563 if ((intr_status & IntrTxErrSummary) == 0) {
1564
1565 /* We know better than the chip where it should continue. */
1566 iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
1567 ioaddr + TxRingPtr);
1568
1569 iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
1570 ioaddr + ChipCmd);
1571 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1572 ioaddr + ChipCmd1);
1573 IOSYNC;
1574 }
1575 else {
1576 /* This should never happen */
1577 if (debug > 1)
1578 printk(KERN_WARNING "%s: rhine_restart_tx() "
1579 "Another error occured %8.8x.\n",
1580 dev->name, intr_status);
1581 }
1582
1583}
1584
1585static void rhine_error(struct net_device *dev, int intr_status)
1586{
1587 struct rhine_private *rp = netdev_priv(dev);
1588 void __iomem *ioaddr = rp->base;
1589
1590 spin_lock(&rp->lock);
1591
1592 if (intr_status & IntrLinkChange)
John W. Linville38bb6b22006-05-19 10:51:21 -04001593 rhine_check_media(dev, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001594 if (intr_status & IntrStatsMax) {
1595 rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1596 rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1597 clear_tally_counters(ioaddr);
1598 }
1599 if (intr_status & IntrTxAborted) {
1600 if (debug > 1)
1601 printk(KERN_INFO "%s: Abort %8.8x, frame dropped.\n",
1602 dev->name, intr_status);
1603 }
1604 if (intr_status & IntrTxUnderrun) {
1605 if (rp->tx_thresh < 0xE0)
1606 iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1607 if (debug > 1)
1608 printk(KERN_INFO "%s: Transmitter underrun, Tx "
1609 "threshold now %2.2x.\n",
1610 dev->name, rp->tx_thresh);
1611 }
1612 if (intr_status & IntrTxDescRace) {
1613 if (debug > 2)
1614 printk(KERN_INFO "%s: Tx descriptor write-back race.\n",
1615 dev->name);
1616 }
1617 if ((intr_status & IntrTxError) &&
1618 (intr_status & (IntrTxAborted |
1619 IntrTxUnderrun | IntrTxDescRace)) == 0) {
1620 if (rp->tx_thresh < 0xE0) {
1621 iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1622 }
1623 if (debug > 1)
1624 printk(KERN_INFO "%s: Unspecified error. Tx "
1625 "threshold now %2.2x.\n",
1626 dev->name, rp->tx_thresh);
1627 }
1628 if (intr_status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace |
1629 IntrTxError))
1630 rhine_restart_tx(dev);
1631
1632 if (intr_status & ~(IntrLinkChange | IntrStatsMax | IntrTxUnderrun |
1633 IntrTxError | IntrTxAborted | IntrNormalSummary |
1634 IntrTxDescRace)) {
1635 if (debug > 1)
1636 printk(KERN_ERR "%s: Something Wicked happened! "
1637 "%8.8x.\n", dev->name, intr_status);
1638 }
1639
1640 spin_unlock(&rp->lock);
1641}
1642
1643static struct net_device_stats *rhine_get_stats(struct net_device *dev)
1644{
1645 struct rhine_private *rp = netdev_priv(dev);
1646 void __iomem *ioaddr = rp->base;
1647 unsigned long flags;
1648
1649 spin_lock_irqsave(&rp->lock, flags);
1650 rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1651 rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1652 clear_tally_counters(ioaddr);
1653 spin_unlock_irqrestore(&rp->lock, flags);
1654
1655 return &rp->stats;
1656}
1657
1658static void rhine_set_rx_mode(struct net_device *dev)
1659{
1660 struct rhine_private *rp = netdev_priv(dev);
1661 void __iomem *ioaddr = rp->base;
1662 u32 mc_filter[2]; /* Multicast hash filter */
1663 u8 rx_mode; /* Note: 0x02=accept runt, 0x01=accept errs */
1664
1665 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001666 rx_mode = 0x1C;
1667 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1668 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1669 } else if ((dev->mc_count > multicast_filter_limit)
1670 || (dev->flags & IFF_ALLMULTI)) {
1671 /* Too many to match, or accept all multicasts. */
1672 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1673 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1674 rx_mode = 0x0C;
1675 } else {
1676 struct dev_mc_list *mclist;
1677 int i;
1678 memset(mc_filter, 0, sizeof(mc_filter));
1679 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1680 i++, mclist = mclist->next) {
1681 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1682
1683 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1684 }
1685 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
1686 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
1687 rx_mode = 0x0C;
1688 }
1689 iowrite8(rp->rx_thresh | rx_mode, ioaddr + RxConfig);
1690}
1691
1692static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1693{
1694 struct rhine_private *rp = netdev_priv(dev);
1695
1696 strcpy(info->driver, DRV_NAME);
1697 strcpy(info->version, DRV_VERSION);
1698 strcpy(info->bus_info, pci_name(rp->pdev));
1699}
1700
1701static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1702{
1703 struct rhine_private *rp = netdev_priv(dev);
1704 int rc;
1705
1706 spin_lock_irq(&rp->lock);
1707 rc = mii_ethtool_gset(&rp->mii_if, cmd);
1708 spin_unlock_irq(&rp->lock);
1709
1710 return rc;
1711}
1712
1713static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1714{
1715 struct rhine_private *rp = netdev_priv(dev);
1716 int rc;
1717
1718 spin_lock_irq(&rp->lock);
1719 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1720 spin_unlock_irq(&rp->lock);
Roger Luethi00b428c2006-03-28 20:53:56 +02001721 rhine_set_carrier(&rp->mii_if);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001722
1723 return rc;
1724}
1725
1726static int netdev_nway_reset(struct net_device *dev)
1727{
1728 struct rhine_private *rp = netdev_priv(dev);
1729
1730 return mii_nway_restart(&rp->mii_if);
1731}
1732
1733static u32 netdev_get_link(struct net_device *dev)
1734{
1735 struct rhine_private *rp = netdev_priv(dev);
1736
1737 return mii_link_ok(&rp->mii_if);
1738}
1739
1740static u32 netdev_get_msglevel(struct net_device *dev)
1741{
1742 return debug;
1743}
1744
1745static void netdev_set_msglevel(struct net_device *dev, u32 value)
1746{
1747 debug = value;
1748}
1749
1750static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1751{
1752 struct rhine_private *rp = netdev_priv(dev);
1753
1754 if (!(rp->quirks & rqWOL))
1755 return;
1756
1757 spin_lock_irq(&rp->lock);
1758 wol->supported = WAKE_PHY | WAKE_MAGIC |
1759 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1760 wol->wolopts = rp->wolopts;
1761 spin_unlock_irq(&rp->lock);
1762}
1763
1764static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1765{
1766 struct rhine_private *rp = netdev_priv(dev);
1767 u32 support = WAKE_PHY | WAKE_MAGIC |
1768 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1769
1770 if (!(rp->quirks & rqWOL))
1771 return -EINVAL;
1772
1773 if (wol->wolopts & ~support)
1774 return -EINVAL;
1775
1776 spin_lock_irq(&rp->lock);
1777 rp->wolopts = wol->wolopts;
1778 spin_unlock_irq(&rp->lock);
1779
1780 return 0;
1781}
1782
Jeff Garzik7282d492006-09-13 14:30:00 -04001783static const struct ethtool_ops netdev_ethtool_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001784 .get_drvinfo = netdev_get_drvinfo,
1785 .get_settings = netdev_get_settings,
1786 .set_settings = netdev_set_settings,
1787 .nway_reset = netdev_nway_reset,
1788 .get_link = netdev_get_link,
1789 .get_msglevel = netdev_get_msglevel,
1790 .set_msglevel = netdev_set_msglevel,
1791 .get_wol = rhine_get_wol,
1792 .set_wol = rhine_set_wol,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001793};
1794
1795static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1796{
1797 struct rhine_private *rp = netdev_priv(dev);
1798 int rc;
1799
1800 if (!netif_running(dev))
1801 return -EINVAL;
1802
1803 spin_lock_irq(&rp->lock);
1804 rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
1805 spin_unlock_irq(&rp->lock);
Roger Luethi00b428c2006-03-28 20:53:56 +02001806 rhine_set_carrier(&rp->mii_if);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001807
1808 return rc;
1809}
1810
1811static int rhine_close(struct net_device *dev)
1812{
1813 struct rhine_private *rp = netdev_priv(dev);
1814 void __iomem *ioaddr = rp->base;
1815
1816 spin_lock_irq(&rp->lock);
1817
1818 netif_stop_queue(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001819 napi_disable(&rp->napi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001820
1821 if (debug > 1)
1822 printk(KERN_DEBUG "%s: Shutting down ethercard, "
1823 "status was %4.4x.\n",
1824 dev->name, ioread16(ioaddr + ChipCmd));
1825
1826 /* Switch to loopback mode to avoid hardware races. */
1827 iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
1828
1829 /* Disable interrupts by clearing the interrupt mask. */
1830 iowrite16(0x0000, ioaddr + IntrEnable);
1831
1832 /* Stop the chip's Tx and Rx processes. */
1833 iowrite16(CmdStop, ioaddr + ChipCmd);
1834
1835 spin_unlock_irq(&rp->lock);
1836
1837 free_irq(rp->pdev->irq, dev);
1838 free_rbufs(dev);
1839 free_tbufs(dev);
1840 free_ring(dev);
1841
1842 return 0;
1843}
1844
1845
1846static void __devexit rhine_remove_one(struct pci_dev *pdev)
1847{
1848 struct net_device *dev = pci_get_drvdata(pdev);
1849 struct rhine_private *rp = netdev_priv(dev);
1850
1851 unregister_netdev(dev);
1852
1853 pci_iounmap(pdev, rp->base);
1854 pci_release_regions(pdev);
1855
1856 free_netdev(dev);
1857 pci_disable_device(pdev);
1858 pci_set_drvdata(pdev, NULL);
1859}
1860
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -07001861static void rhine_shutdown (struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001862{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001863 struct net_device *dev = pci_get_drvdata(pdev);
1864 struct rhine_private *rp = netdev_priv(dev);
1865 void __iomem *ioaddr = rp->base;
1866
1867 if (!(rp->quirks & rqWOL))
1868 return; /* Nothing to do for non-WOL adapters */
1869
1870 rhine_power_init(dev);
1871
1872 /* Make sure we use pattern 0, 1 and not 4, 5 */
1873 if (rp->quirks & rq6patterns)
Laura Garciaf11cf252008-02-23 18:56:35 +01001874 iowrite8(0x04, ioaddr + WOLcgClr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001875
1876 if (rp->wolopts & WAKE_MAGIC) {
1877 iowrite8(WOLmagic, ioaddr + WOLcrSet);
1878 /*
1879 * Turn EEPROM-controlled wake-up back on -- some hardware may
1880 * not cooperate otherwise.
1881 */
1882 iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
1883 }
1884
1885 if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
1886 iowrite8(WOLbmcast, ioaddr + WOLcgSet);
1887
1888 if (rp->wolopts & WAKE_PHY)
1889 iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
1890
1891 if (rp->wolopts & WAKE_UCAST)
1892 iowrite8(WOLucast, ioaddr + WOLcrSet);
1893
1894 if (rp->wolopts) {
1895 /* Enable legacy WOL (for old motherboards) */
1896 iowrite8(0x01, ioaddr + PwcfgSet);
1897 iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
1898 }
1899
1900 /* Hit power state D3 (sleep) */
Roger Luethib933b4d2006-08-14 23:00:21 -07001901 if (!avoid_D3)
1902 iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001903
1904 /* TODO: Check use of pci_enable_wake() */
1905
1906}
1907
1908#ifdef CONFIG_PM
1909static int rhine_suspend(struct pci_dev *pdev, pm_message_t state)
1910{
1911 struct net_device *dev = pci_get_drvdata(pdev);
1912 struct rhine_private *rp = netdev_priv(dev);
1913 unsigned long flags;
1914
1915 if (!netif_running(dev))
1916 return 0;
1917
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001918 napi_disable(&rp->napi);
Francois Romieu32b0f532008-07-11 00:30:14 +02001919
Linus Torvalds1da177e2005-04-16 15:20:36 -07001920 netif_device_detach(dev);
1921 pci_save_state(pdev);
1922
1923 spin_lock_irqsave(&rp->lock, flags);
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -07001924 rhine_shutdown(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001925 spin_unlock_irqrestore(&rp->lock, flags);
1926
1927 free_irq(dev->irq, dev);
1928 return 0;
1929}
1930
1931static int rhine_resume(struct pci_dev *pdev)
1932{
1933 struct net_device *dev = pci_get_drvdata(pdev);
1934 struct rhine_private *rp = netdev_priv(dev);
1935 unsigned long flags;
1936 int ret;
1937
1938 if (!netif_running(dev))
1939 return 0;
1940
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07001941 if (request_irq(dev->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001942 printk(KERN_ERR "via-rhine %s: request_irq failed\n", dev->name);
1943
1944 ret = pci_set_power_state(pdev, PCI_D0);
1945 if (debug > 1)
1946 printk(KERN_INFO "%s: Entering power state D0 %s (%d).\n",
1947 dev->name, ret ? "failed" : "succeeded", ret);
1948
1949 pci_restore_state(pdev);
1950
1951 spin_lock_irqsave(&rp->lock, flags);
1952#ifdef USE_MMIO
1953 enable_mmio(rp->pioaddr, rp->quirks);
1954#endif
1955 rhine_power_init(dev);
1956 free_tbufs(dev);
1957 free_rbufs(dev);
1958 alloc_tbufs(dev);
1959 alloc_rbufs(dev);
1960 init_registers(dev);
1961 spin_unlock_irqrestore(&rp->lock, flags);
1962
1963 netif_device_attach(dev);
1964
1965 return 0;
1966}
1967#endif /* CONFIG_PM */
1968
1969static struct pci_driver rhine_driver = {
1970 .name = DRV_NAME,
1971 .id_table = rhine_pci_tbl,
1972 .probe = rhine_init_one,
1973 .remove = __devexit_p(rhine_remove_one),
1974#ifdef CONFIG_PM
1975 .suspend = rhine_suspend,
1976 .resume = rhine_resume,
1977#endif /* CONFIG_PM */
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -07001978 .shutdown = rhine_shutdown,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001979};
1980
Roger Luethie84df482007-03-06 19:57:37 +01001981static struct dmi_system_id __initdata rhine_dmi_table[] = {
1982 {
1983 .ident = "EPIA-M",
1984 .matches = {
1985 DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."),
1986 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
1987 },
1988 },
1989 {
1990 .ident = "KV7",
1991 .matches = {
1992 DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
1993 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
1994 },
1995 },
1996 { NULL }
1997};
Linus Torvalds1da177e2005-04-16 15:20:36 -07001998
1999static int __init rhine_init(void)
2000{
2001/* when a module, this is printed whether or not devices are found in probe */
2002#ifdef MODULE
2003 printk(version);
2004#endif
Roger Luethie84df482007-03-06 19:57:37 +01002005 if (dmi_check_system(rhine_dmi_table)) {
2006 /* these BIOSes fail at PXE boot if chip is in D3 */
2007 avoid_D3 = 1;
2008 printk(KERN_WARNING "%s: Broken BIOS detected, avoid_D3 "
2009 "enabled.\n",
2010 DRV_NAME);
2011 }
2012 else if (avoid_D3)
2013 printk(KERN_INFO "%s: avoid_D3 set.\n", DRV_NAME);
2014
Jeff Garzik29917622006-08-19 17:48:59 -04002015 return pci_register_driver(&rhine_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002016}
2017
2018
2019static void __exit rhine_cleanup(void)
2020{
2021 pci_unregister_driver(&rhine_driver);
2022}
2023
2024
2025module_init(rhine_init);
2026module_exit(rhine_cleanup);