blob: efa6534a6593c2c3b361c247fbd9e2e206c13090 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
David Brownell75862692005-09-23 17:14:37 -070010 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
Len Brown25be5e62005-05-27 04:21:50 -040023#include <linux/acpi.h>
bjorn.helgaas@hp.com9f23ed32007-12-17 14:09:38 -070024#include <linux/kallsyms.h>
Andreas Petlund75e07fc2008-11-20 20:42:25 -080025#include <linux/dmi.h>
Alexander Duyck649426e2009-03-05 13:57:28 -050026#include <linux/pci-aspm.h>
Yuji Shimada32a9a6822009-03-16 17:13:39 +090027#include <linux/ioport.h>
Greg KHbc56b9e2005-04-08 14:53:31 +090028#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Thomas Petazzoni3d137312008-08-19 10:28:24 +020030int isa_dma_bridge_buggy;
31EXPORT_SYMBOL(isa_dma_bridge_buggy);
32int pci_pci_problems;
33EXPORT_SYMBOL(pci_pci_problems);
Thomas Petazzoni3d137312008-08-19 10:28:24 +020034
35#ifdef CONFIG_PCI_QUIRKS
Yuji Shimada32a9a6822009-03-16 17:13:39 +090036/*
Yuji Shimada0cdbe302009-04-06 10:24:21 +090037 * This quirk function disables memory decoding and releases memory resources
38 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
Yuji Shimada32a9a6822009-03-16 17:13:39 +090039 * It also rounds up size to specified alignment.
40 * Later on, the kernel will assign page-aligned memory resource back
Yuji Shimada0cdbe302009-04-06 10:24:21 +090041 * to the device.
Yuji Shimada32a9a6822009-03-16 17:13:39 +090042 */
43static void __devinit quirk_resource_alignment(struct pci_dev *dev)
44{
45 int i;
46 struct resource *r;
47 resource_size_t align, size;
Yuji Shimada0cdbe302009-04-06 10:24:21 +090048 u16 command;
Yuji Shimada32a9a6822009-03-16 17:13:39 +090049
50 if (!pci_is_reassigndev(dev))
51 return;
52
53 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
54 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
55 dev_warn(&dev->dev,
56 "Can't reassign resources to host bridge.\n");
57 return;
58 }
59
Yuji Shimada0cdbe302009-04-06 10:24:21 +090060 dev_info(&dev->dev,
61 "Disabling memory decoding and releasing memory resources.\n");
62 pci_read_config_word(dev, PCI_COMMAND, &command);
63 command &= ~PCI_COMMAND_MEMORY;
64 pci_write_config_word(dev, PCI_COMMAND, command);
Yuji Shimada32a9a6822009-03-16 17:13:39 +090065
66 align = pci_specified_resource_alignment(dev);
67 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) {
68 r = &dev->resource[i];
69 if (!(r->flags & IORESOURCE_MEM))
70 continue;
71 size = resource_size(r);
72 if (size < align) {
73 size = align;
74 dev_info(&dev->dev,
75 "Rounding up size of resource #%d to %#llx.\n",
76 i, (unsigned long long)size);
77 }
78 r->end = size - 1;
79 r->start = 0;
80 }
81 /* Need to disable bridge's resource window,
82 * to enable the kernel to reassign new resource
83 * window later on.
84 */
85 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
86 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
87 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
88 r = &dev->resource[i];
89 if (!(r->flags & IORESOURCE_MEM))
90 continue;
91 r->end = resource_size(r) - 1;
92 r->start = 0;
93 }
94 pci_disable_bridge_window(dev);
95 }
96}
97DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment);
98
Doug Thompsonbd8481e2006-05-08 17:06:09 -070099/* The Mellanox Tavor device gives false positive parity errors
100 * Mark this device with a broken_parity_status, to allow
101 * PCI scanning code to "skip" this now blacklisted device.
102 */
103static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
104{
105 dev->broken_parity_status = 1; /* This device gives false positives */
106}
107DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
108DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
109
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110/* Deal with broken BIOS'es that neglect to enable passive release,
111 which can cause problems in combination with the 82441FX/PPro MTRRs */
Alan Cox1597cac2006-12-04 15:14:45 -0800112static void quirk_passive_release(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113{
114 struct pci_dev *d = NULL;
115 unsigned char dlc;
116
117 /* We have to make sure a particular bit is set in the PIIX3
118 ISA bridge, so we have to go out and find it. */
119 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
120 pci_read_config_byte(d, 0x82, &dlc);
121 if (!(dlc & 1<<1)) {
Adam Jackson999da9f2008-12-01 14:30:29 -0800122 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123 dlc |= 1<<1;
124 pci_write_config_byte(d, 0x82, dlc);
125 }
126 }
127}
Andrew Morton652c5382007-11-21 15:07:13 -0800128DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
129DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700130
131/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
132 but VIA don't answer queries. If you happen to have good contacts at VIA
133 ask them for me please -- Alan
134
135 This appears to be BIOS not version dependent. So presumably there is a
136 chipset level fix */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137
138static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
139{
140 if (!isa_dma_bridge_buggy) {
141 isa_dma_bridge_buggy=1;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700142 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143 }
144}
145 /*
146 * Its not totally clear which chipsets are the problematic ones
147 * We know 82C586 and 82C596 variants are affected.
148 */
Andrew Morton652c5382007-11-21 15:07:13 -0800149DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
150DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
151DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
152DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
153DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
154DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
155DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700156
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157/*
158 * Chipsets where PCI->PCI transfers vanish or hang
159 */
160static void __devinit quirk_nopcipci(struct pci_dev *dev)
161{
162 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700163 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164 pci_pci_problems |= PCIPCI_FAIL;
165 }
166}
Andrew Morton652c5382007-11-21 15:07:13 -0800167DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
168DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
Alan Cox236561e2006-09-30 23:27:03 -0700169
170static void __devinit quirk_nopciamd(struct pci_dev *dev)
171{
172 u8 rev;
173 pci_read_config_byte(dev, 0x08, &rev);
174 if (rev == 0x13) {
175 /* Erratum 24 */
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700176 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
Alan Cox236561e2006-09-30 23:27:03 -0700177 pci_pci_problems |= PCIAGP_FAIL;
178 }
179}
Andrew Morton652c5382007-11-21 15:07:13 -0800180DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181
182/*
183 * Triton requires workarounds to be used by the drivers
184 */
185static void __devinit quirk_triton(struct pci_dev *dev)
186{
187 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700188 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189 pci_pci_problems |= PCIPCI_TRITON;
190 }
191}
Andrew Morton652c5382007-11-21 15:07:13 -0800192DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
193DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
194DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
195DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196
197/*
198 * VIA Apollo KT133 needs PCI latency patch
199 * Made according to a windows driver based patch by George E. Breese
200 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
201 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
202 * the info on which Mr Breese based his work.
203 *
204 * Updated based on further information from the site and also on
205 * information provided by VIA
206 */
Alan Cox1597cac2006-12-04 15:14:45 -0800207static void quirk_vialatency(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700208{
209 struct pci_dev *p;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700210 u8 busarb;
211 /* Ok we have a potential problem chipset here. Now see if we have
212 a buggy southbridge */
213
214 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
215 if (p!=NULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
217 /* Check for buggy part revisions */
Auke Kok2b1afa82007-10-29 14:55:02 -0700218 if (p->revision < 0x40 || p->revision > 0x42)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219 goto exit;
220 } else {
221 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
222 if (p==NULL) /* No problem parts */
223 goto exit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224 /* Check for buggy part revisions */
Auke Kok2b1afa82007-10-29 14:55:02 -0700225 if (p->revision < 0x10 || p->revision > 0x12)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226 goto exit;
227 }
228
229 /*
230 * Ok we have the problem. Now set the PCI master grant to
231 * occur every master grant. The apparent bug is that under high
232 * PCI load (quite common in Linux of course) you can get data
233 * loss when the CPU is held off the bus for 3 bus master requests
234 * This happens to include the IDE controllers....
235 *
236 * VIA only apply this fix when an SB Live! is present but under
237 * both Linux and Windows this isnt enough, and we have seen
238 * corruption without SB Live! but with things like 3 UDMA IDE
239 * controllers. So we ignore that bit of the VIA recommendation..
240 */
241
242 pci_read_config_byte(dev, 0x76, &busarb);
243 /* Set bit 4 and bi 5 of byte 76 to 0x01
244 "Master priority rotation on every PCI master grant */
245 busarb &= ~(1<<5);
246 busarb |= (1<<4);
247 pci_write_config_byte(dev, 0x76, busarb);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700248 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700249exit:
250 pci_dev_put(p);
251}
Andrew Morton652c5382007-11-21 15:07:13 -0800252DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
253DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
254DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
Alan Cox1597cac2006-12-04 15:14:45 -0800255/* Must restore this on a resume from RAM */
Andrew Morton652c5382007-11-21 15:07:13 -0800256DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
257DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
258DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259
260/*
261 * VIA Apollo VP3 needs ETBF on BT848/878
262 */
263static void __devinit quirk_viaetbf(struct pci_dev *dev)
264{
265 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700266 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267 pci_pci_problems |= PCIPCI_VIAETBF;
268 }
269}
Andrew Morton652c5382007-11-21 15:07:13 -0800270DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271
272static void __devinit quirk_vsfx(struct pci_dev *dev)
273{
274 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700275 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700276 pci_pci_problems |= PCIPCI_VSFX;
277 }
278}
Andrew Morton652c5382007-11-21 15:07:13 -0800279DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280
281/*
282 * Ali Magik requires workarounds to be used by the drivers
283 * that DMA to AGP space. Latency must be set to 0xA and triton
284 * workaround applied too
285 * [Info kindly provided by ALi]
286 */
287static void __init quirk_alimagik(struct pci_dev *dev)
288{
289 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700290 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700291 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
292 }
293}
Andrew Morton652c5382007-11-21 15:07:13 -0800294DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
295DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700296
297/*
298 * Natoma has some interesting boundary conditions with Zoran stuff
299 * at least
300 */
301static void __devinit quirk_natoma(struct pci_dev *dev)
302{
303 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700304 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700305 pci_pci_problems |= PCIPCI_NATOMA;
306 }
307}
Andrew Morton652c5382007-11-21 15:07:13 -0800308DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
309DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
310DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
311DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
312DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
313DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700314
315/*
316 * This chip can cause PCI parity errors if config register 0xA0 is read
317 * while DMAs are occurring.
318 */
319static void __devinit quirk_citrine(struct pci_dev *dev)
320{
321 dev->cfg_size = 0xA0;
322}
Andrew Morton652c5382007-11-21 15:07:13 -0800323DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700324
325/*
326 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
327 * If it's needed, re-allocate the region.
328 */
329static void __devinit quirk_s3_64M(struct pci_dev *dev)
330{
331 struct resource *r = &dev->resource[0];
332
333 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
334 r->start = 0;
335 r->end = 0x3ffffff;
336 }
337}
Andrew Morton652c5382007-11-21 15:07:13 -0800338DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
339DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340
Linus Torvalds6693e742005-10-25 20:40:09 -0700341static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
342 unsigned size, int nr, const char *name)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343{
344 region &= ~(size-1);
345 if (region) {
David S. Miller085ae412005-08-08 13:19:08 -0700346 struct pci_bus_region bus_region;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700347 struct resource *res = dev->resource + nr;
348
349 res->name = pci_name(dev);
350 res->start = region;
351 res->end = region + size - 1;
352 res->flags = IORESOURCE_IO;
David S. Miller085ae412005-08-08 13:19:08 -0700353
354 /* Convert from PCI bus to resource space. */
355 bus_region.start = res->start;
356 bus_region.end = res->end;
357 pcibios_bus_to_resource(dev, res, &bus_region);
358
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359 pci_claim_resource(dev, nr);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700360 dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361 }
362}
363
364/*
365 * ATI Northbridge setups MCE the processor if you even
366 * read somewhere between 0x3b0->0x3bb or read 0x3d3
367 */
368static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
369{
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700370 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700371 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
372 request_region(0x3b0, 0x0C, "RadeonIGP");
373 request_region(0x3d3, 0x01, "RadeonIGP");
374}
Andrew Morton652c5382007-11-21 15:07:13 -0800375DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376
377/*
378 * Let's make the southbridge information explicit instead
379 * of having to worry about people probing the ACPI areas,
380 * for example.. (Yes, it happens, and if you read the wrong
381 * ACPI register it will put the machine to sleep with no
382 * way of waking it up again. Bummer).
383 *
384 * ALI M7101: Two IO regions pointed to by words at
385 * 0xE0 (64 bytes of ACPI registers)
386 * 0xE2 (32 bytes of SMB registers)
387 */
388static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
389{
390 u16 region;
391
392 pci_read_config_word(dev, 0xE0, &region);
Linus Torvalds6693e742005-10-25 20:40:09 -0700393 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394 pci_read_config_word(dev, 0xE2, &region);
Linus Torvalds6693e742005-10-25 20:40:09 -0700395 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396}
Andrew Morton652c5382007-11-21 15:07:13 -0800397DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398
Linus Torvalds6693e742005-10-25 20:40:09 -0700399static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
400{
401 u32 devres;
402 u32 mask, size, base;
403
404 pci_read_config_dword(dev, port, &devres);
405 if ((devres & enable) != enable)
406 return;
407 mask = (devres >> 16) & 15;
408 base = devres & 0xffff;
409 size = 16;
410 for (;;) {
411 unsigned bit = size >> 1;
412 if ((bit & mask) == bit)
413 break;
414 size = bit;
415 }
416 /*
417 * For now we only print it out. Eventually we'll want to
418 * reserve it (at least if it's in the 0x1000+ range), but
419 * let's get enough confirmation reports first.
420 */
421 base &= -size;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700422 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
Linus Torvalds6693e742005-10-25 20:40:09 -0700423}
424
425static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
426{
427 u32 devres;
428 u32 mask, size, base;
429
430 pci_read_config_dword(dev, port, &devres);
431 if ((devres & enable) != enable)
432 return;
433 base = devres & 0xffff0000;
434 mask = (devres & 0x3f) << 16;
435 size = 128 << 16;
436 for (;;) {
437 unsigned bit = size >> 1;
438 if ((bit & mask) == bit)
439 break;
440 size = bit;
441 }
442 /*
443 * For now we only print it out. Eventually we'll want to
444 * reserve it, but let's get enough confirmation reports first.
445 */
446 base &= -size;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700447 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
Linus Torvalds6693e742005-10-25 20:40:09 -0700448}
449
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450/*
451 * PIIX4 ACPI: Two IO regions pointed to by longwords at
452 * 0x40 (64 bytes of ACPI registers)
Linus Torvalds08db2a72005-10-30 14:40:07 -0800453 * 0x90 (16 bytes of SMB registers)
Linus Torvalds6693e742005-10-25 20:40:09 -0700454 * and a few strange programmable PIIX4 device resources.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455 */
456static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
457{
Linus Torvalds6693e742005-10-25 20:40:09 -0700458 u32 region, res_a;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459
460 pci_read_config_dword(dev, 0x40, &region);
Linus Torvalds6693e742005-10-25 20:40:09 -0700461 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700462 pci_read_config_dword(dev, 0x90, &region);
Linus Torvalds08db2a72005-10-30 14:40:07 -0800463 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
Linus Torvalds6693e742005-10-25 20:40:09 -0700464
465 /* Device resource A has enables for some of the other ones */
466 pci_read_config_dword(dev, 0x5c, &res_a);
467
468 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
469 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
470
471 /* Device resource D is just bitfields for static resources */
472
473 /* Device 12 enabled? */
474 if (res_a & (1 << 29)) {
475 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
476 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
477 }
478 /* Device 13 enabled? */
479 if (res_a & (1 << 30)) {
480 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
481 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
482 }
483 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
484 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700485}
Andrew Morton652c5382007-11-21 15:07:13 -0800486DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
487DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488
489/*
490 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
491 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
492 * 0x58 (64 bytes of GPIO I/O space)
493 */
494static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
495{
496 u32 region;
497
498 pci_read_config_dword(dev, 0x40, &region);
Linus Torvalds6693e742005-10-25 20:40:09 -0700499 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700500
501 pci_read_config_dword(dev, 0x58, &region);
Linus Torvalds6693e742005-10-25 20:40:09 -0700502 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503}
Andrew Morton652c5382007-11-21 15:07:13 -0800504DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
505DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
506DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
507DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
508DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
509DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
510DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
511DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
512DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
513DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700514
Linus Torvalds894886e2008-12-06 10:10:10 -0800515static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000516{
517 u32 region;
518
519 pci_read_config_dword(dev, 0x40, &region);
520 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
521
522 pci_read_config_dword(dev, 0x48, &region);
523 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
524}
Linus Torvalds894886e2008-12-06 10:10:10 -0800525
526static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
527{
528 u32 val;
529 u32 size, base;
530
531 pci_read_config_dword(dev, reg, &val);
532
533 /* Enabled? */
534 if (!(val & 1))
535 return;
536 base = val & 0xfffc;
537 if (dynsize) {
538 /*
539 * This is not correct. It is 16, 32 or 64 bytes depending on
540 * register D31:F0:ADh bits 5:4.
541 *
542 * But this gets us at least _part_ of it.
543 */
544 size = 16;
545 } else {
546 size = 128;
547 }
548 base &= ~(size-1);
549
550 /* Just print it out for now. We should reserve it after more debugging */
551 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
552}
553
554static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
555{
556 /* Shared ACPI/GPIO decode with all ICH6+ */
557 ich6_lpc_acpi_gpio(dev);
558
559 /* ICH6-specific generic IO decode */
560 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
561 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
562}
563DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
564DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
565
566static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
567{
568 u32 val;
569 u32 mask, base;
570
571 pci_read_config_dword(dev, reg, &val);
572
573 /* Enabled? */
574 if (!(val & 1))
575 return;
576
577 /*
578 * IO base in bits 15:2, mask in bits 23:18, both
579 * are dword-based
580 */
581 base = val & 0xfffc;
582 mask = (val >> 16) & 0xfc;
583 mask |= 3;
584
585 /* Just print it out for now. We should reserve it after more debugging */
586 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
587}
588
589/* ICH7-10 has the same common LPC generic IO decode registers */
590static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
591{
592 /* We share the common ACPI/DPIO decode with ICH6 */
593 ich6_lpc_acpi_gpio(dev);
594
595 /* And have 4 ICH7+ generic decodes */
596 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
597 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
598 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
599 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
600}
601DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
602DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
603DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
604DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
605DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
606DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
607DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
608DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
609DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
610DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
611DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
612DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
613DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000614
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615/*
616 * VIA ACPI: One IO region pointed to by longword at
617 * 0x48 or 0x20 (256 bytes of ACPI registers)
618 */
619static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
620{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700621 u32 region;
622
Auke Kok651472f2007-08-27 16:18:10 -0700623 if (dev->revision & 0x10) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700624 pci_read_config_dword(dev, 0x48, &region);
625 region &= PCI_BASE_ADDRESS_IO_MASK;
Linus Torvalds6693e742005-10-25 20:40:09 -0700626 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627 }
628}
Andrew Morton652c5382007-11-21 15:07:13 -0800629DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700630
631/*
632 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
633 * 0x48 (256 bytes of ACPI registers)
634 * 0x70 (128 bytes of hardware monitoring register)
635 * 0x90 (16 bytes of SMB registers)
636 */
637static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
638{
639 u16 hm;
640 u32 smb;
641
642 quirk_vt82c586_acpi(dev);
643
644 pci_read_config_word(dev, 0x70, &hm);
645 hm &= PCI_BASE_ADDRESS_IO_MASK;
Meelis Roos02f313b2005-10-29 13:31:49 +0300646 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647
648 pci_read_config_dword(dev, 0x90, &smb);
649 smb &= PCI_BASE_ADDRESS_IO_MASK;
Meelis Roos02f313b2005-10-29 13:31:49 +0300650 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651}
Andrew Morton652c5382007-11-21 15:07:13 -0800652DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400654/*
655 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
656 * 0x88 (128 bytes of power management registers)
657 * 0xd0 (16 bytes of SMB registers)
658 */
659static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
660{
661 u16 pm, smb;
662
663 pci_read_config_word(dev, 0x88, &pm);
664 pm &= PCI_BASE_ADDRESS_IO_MASK;
Linus Torvalds6693e742005-10-25 20:40:09 -0700665 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400666
667 pci_read_config_word(dev, 0xd0, &smb);
668 smb &= PCI_BASE_ADDRESS_IO_MASK;
Linus Torvalds6693e742005-10-25 20:40:09 -0700669 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400670}
671DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
672
Gabe Black1f56f4a2009-10-06 09:19:45 -0500673/*
674 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
675 * Disable fast back-to-back on the secondary bus segment
676 */
677static void __devinit quirk_xio2000a(struct pci_dev *dev)
678{
679 struct pci_dev *pdev;
680 u16 command;
681
682 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
683 "secondary bus fast back-to-back transfers disabled\n");
684 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
685 pci_read_config_word(pdev, PCI_COMMAND, &command);
686 if (command & PCI_COMMAND_FAST_BACK)
687 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
688 }
689}
690DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
691 quirk_xio2000a);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692
693#ifdef CONFIG_X86_IO_APIC
694
695#include <asm/io_apic.h>
696
697/*
698 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
699 * devices to the external APIC.
700 *
701 * TODO: When we have device-specific interrupt routers,
702 * this code will go away from quirks.
703 */
Alan Cox1597cac2006-12-04 15:14:45 -0800704static void quirk_via_ioapic(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700705{
706 u8 tmp;
707
708 if (nr_ioapics < 1)
709 tmp = 0; /* nothing routed to external APIC */
710 else
711 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
712
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700713 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700714 tmp == 0 ? "Disa" : "Ena");
715
716 /* Offset 0x58: External APIC IRQ output control */
717 pci_write_config_byte (dev, 0x58, tmp);
718}
Andrew Morton652c5382007-11-21 15:07:13 -0800719DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200720DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700721
722/*
Karsten Wiesea1740912005-09-03 15:56:33 -0700723 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
724 * This leads to doubled level interrupt rates.
725 * Set this bit to get rid of cycle wastage.
726 * Otherwise uncritical.
727 */
Alan Cox1597cac2006-12-04 15:14:45 -0800728static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
Karsten Wiesea1740912005-09-03 15:56:33 -0700729{
730 u8 misc_control2;
731#define BYPASS_APIC_DEASSERT 8
732
733 pci_read_config_byte(dev, 0x5B, &misc_control2);
734 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700735 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
Karsten Wiesea1740912005-09-03 15:56:33 -0700736 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
737 }
738}
739DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200740DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
Karsten Wiesea1740912005-09-03 15:56:33 -0700741
742/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700743 * The AMD io apic can hang the box when an apic irq is masked.
744 * We check all revs >= B0 (yet not in the pre production!) as the bug
745 * is currently marked NoFix
746 *
747 * We have multiple reports of hangs with this chipset that went away with
Alan Cox236561e2006-09-30 23:27:03 -0700748 * noapic specified. For the moment we assume it's the erratum. We may be wrong
Linus Torvalds1da177e2005-04-16 15:20:36 -0700749 * of course. However the advice is demonstrably good even if so..
750 */
751static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
752{
Auke Kok44c10132007-06-08 15:46:36 -0700753 if (dev->revision >= 0x02) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700754 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
755 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700756 }
757}
Andrew Morton652c5382007-11-21 15:07:13 -0800758DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700759
760static void __init quirk_ioapic_rmw(struct pci_dev *dev)
761{
762 if (dev->devfn == 0 && dev->bus->number == 0)
763 sis_apic_bug = 1;
764}
Andrew Morton652c5382007-11-21 15:07:13 -0800765DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700766#endif /* CONFIG_X86_IO_APIC */
767
Peter Orubad556ad42007-05-15 13:59:13 +0200768/*
769 * Some settings of MMRBC can lead to data corruption so block changes.
770 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
771 */
772static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
773{
Auke Kokaa288d42007-08-27 16:17:47 -0700774 if (dev->subordinate && dev->revision <= 0x12) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700775 dev_info(&dev->dev, "AMD8131 rev %x detected; "
776 "disabling PCI-X MMRBC\n", dev->revision);
Peter Orubad556ad42007-05-15 13:59:13 +0200777 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
778 }
779}
780DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781
782/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700783 * FIXME: it is questionable that quirk_via_acpi
784 * is needed. It shows up as an ISA bridge, and does not
785 * support the PCI_INTERRUPT_LINE register at all. Therefore
786 * it seems like setting the pci_dev's 'irq' to the
787 * value of the ACPI SCI interrupt is only done for convenience.
788 * -jgarzik
789 */
790static void __devinit quirk_via_acpi(struct pci_dev *d)
791{
792 /*
793 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
794 */
795 u8 irq;
796 pci_read_config_byte(d, 0x42, &irq);
797 irq &= 0xf;
798 if (irq && (irq != 2))
799 d->irq = irq;
800}
Andrew Morton652c5382007-11-21 15:07:13 -0800801DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
802DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700803
Daniel Drake09d60292006-09-25 16:52:19 -0700804
805/*
Alan Cox1597cac2006-12-04 15:14:45 -0800806 * VIA bridges which have VLink
Daniel Drake09d60292006-09-25 16:52:19 -0700807 */
Alan Cox1597cac2006-12-04 15:14:45 -0800808
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800809static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
810
811static void quirk_via_bridge(struct pci_dev *dev)
812{
813 /* See what bridge we have and find the device ranges */
814 switch (dev->device) {
815 case PCI_DEVICE_ID_VIA_82C686:
Jean Delvarecb7468e2007-01-31 23:48:12 -0800816 /* The VT82C686 is special, it attaches to PCI and can have
817 any device number. All its subdevices are functions of
818 that single device. */
819 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
820 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800821 break;
822 case PCI_DEVICE_ID_VIA_8237:
823 case PCI_DEVICE_ID_VIA_8237A:
824 via_vlink_dev_lo = 15;
825 break;
826 case PCI_DEVICE_ID_VIA_8235:
827 via_vlink_dev_lo = 16;
828 break;
829 case PCI_DEVICE_ID_VIA_8231:
830 case PCI_DEVICE_ID_VIA_8233_0:
831 case PCI_DEVICE_ID_VIA_8233A:
832 case PCI_DEVICE_ID_VIA_8233C_0:
833 via_vlink_dev_lo = 17;
834 break;
835 }
836}
837DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
838DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
839DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
840DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
841DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
842DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
843DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
844DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
Daniel Drake09d60292006-09-25 16:52:19 -0700845
Alan Cox1597cac2006-12-04 15:14:45 -0800846/**
847 * quirk_via_vlink - VIA VLink IRQ number update
848 * @dev: PCI device
849 *
850 * If the device we are dealing with is on a PIC IRQ we need to
851 * ensure that the IRQ line register which usually is not relevant
852 * for PCI cards, is actually written so that interrupts get sent
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800853 * to the right place.
854 * We only do this on systems where a VIA south bridge was detected,
855 * and only for VIA devices on the motherboard (see quirk_via_bridge
856 * above).
Alan Cox1597cac2006-12-04 15:14:45 -0800857 */
858
859static void quirk_via_vlink(struct pci_dev *dev)
Len Brown25be5e62005-05-27 04:21:50 -0400860{
861 u8 irq, new_irq;
862
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800863 /* Check if we have VLink at all */
864 if (via_vlink_dev_lo == -1)
Daniel Drake09d60292006-09-25 16:52:19 -0700865 return;
866
867 new_irq = dev->irq;
868
869 /* Don't quirk interrupts outside the legacy IRQ range */
870 if (!new_irq || new_irq > 15)
871 return;
872
Alan Cox1597cac2006-12-04 15:14:45 -0800873 /* Internal device ? */
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800874 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
875 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
Alan Cox1597cac2006-12-04 15:14:45 -0800876 return;
877
878 /* This is an internal VLink device on a PIC interrupt. The BIOS
879 ought to have set this but may not have, so we redo it */
880
Len Brown25be5e62005-05-27 04:21:50 -0400881 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
882 if (new_irq != irq) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700883 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
884 irq, new_irq);
Len Brown25be5e62005-05-27 04:21:50 -0400885 udelay(15); /* unknown if delay really needed */
886 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
887 }
888}
Alan Cox1597cac2006-12-04 15:14:45 -0800889DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
Len Brown25be5e62005-05-27 04:21:50 -0400890
Linus Torvalds1da177e2005-04-16 15:20:36 -0700891/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700892 * VIA VT82C598 has its device ID settable and many BIOSes
893 * set it to the ID of VT82C597 for backward compatibility.
894 * We need to switch it off to be able to recognize the real
895 * type of the chip.
896 */
897static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
898{
899 pci_write_config_byte(dev, 0xfc, 0);
900 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
901}
Andrew Morton652c5382007-11-21 15:07:13 -0800902DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700903
904/*
905 * CardBus controllers have a legacy base address that enables them
906 * to respond as i82365 pcmcia controllers. We don't want them to
907 * do this even if the Linux CardBus driver is not loaded, because
908 * the Linux i82365 driver does not (and should not) handle CardBus.
909 */
Alan Cox1597cac2006-12-04 15:14:45 -0800910static void quirk_cardbus_legacy(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700911{
912 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
913 return;
914 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
915}
916DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200917DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700918
919/*
920 * Following the PCI ordering rules is optional on the AMD762. I'm not
921 * sure what the designers were smoking but let's not inhale...
922 *
923 * To be fair to AMD, it follows the spec by default, its BIOS people
924 * who turn it off!
925 */
Alan Cox1597cac2006-12-04 15:14:45 -0800926static void quirk_amd_ordering(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700927{
928 u32 pcic;
929 pci_read_config_dword(dev, 0x4C, &pcic);
930 if ((pcic&6)!=6) {
931 pcic |= 6;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700932 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700933 pci_write_config_dword(dev, 0x4C, pcic);
934 pci_read_config_dword(dev, 0x84, &pcic);
935 pcic |= (1<<23); /* Required in this mode */
936 pci_write_config_dword(dev, 0x84, pcic);
937 }
938}
Andrew Morton652c5382007-11-21 15:07:13 -0800939DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200940DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700941
942/*
943 * DreamWorks provided workaround for Dunord I-3000 problem
944 *
945 * This card decodes and responds to addresses not apparently
946 * assigned to it. We force a larger allocation to ensure that
947 * nothing gets put too close to it.
948 */
949static void __devinit quirk_dunord ( struct pci_dev * dev )
950{
951 struct resource *r = &dev->resource [1];
952 r->start = 0;
953 r->end = 0xffffff;
954}
Andrew Morton652c5382007-11-21 15:07:13 -0800955DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700956
957/*
958 * i82380FB mobile docking controller: its PCI-to-PCI bridge
959 * is subtractive decoding (transparent), and does indicate this
960 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
961 * instead of 0x01.
962 */
963static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
964{
965 dev->transparent = 1;
966}
Andrew Morton652c5382007-11-21 15:07:13 -0800967DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
968DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700969
970/*
971 * Common misconfiguration of the MediaGX/Geode PCI master that will
972 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
973 * datasheets found at http://www.national.com/ds/GX for info on what
974 * these bits do. <christer@weinigel.se>
975 */
Alan Cox1597cac2006-12-04 15:14:45 -0800976static void quirk_mediagx_master(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700977{
978 u8 reg;
979 pci_read_config_byte(dev, 0x41, &reg);
980 if (reg & 2) {
981 reg &= ~2;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700982 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700983 pci_write_config_byte(dev, 0x41, reg);
984 }
985}
Andrew Morton652c5382007-11-21 15:07:13 -0800986DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
987DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700988
989/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700990 * Ensure C0 rev restreaming is off. This is normally done by
991 * the BIOS but in the odd case it is not the results are corruption
992 * hence the presence of a Linux check
993 */
Alan Cox1597cac2006-12-04 15:14:45 -0800994static void quirk_disable_pxb(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700995{
996 u16 config;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700997
Auke Kok44c10132007-06-08 15:46:36 -0700998 if (pdev->revision != 0x04) /* Only C0 requires this */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700999 return;
1000 pci_read_config_word(pdev, 0x40, &config);
1001 if (config & (1<<6)) {
1002 config &= ~(1<<6);
1003 pci_write_config_word(pdev, 0x40, config);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001004 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001005 }
1006}
Andrew Morton652c5382007-11-21 15:07:13 -08001007DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001008DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001009
Crane Cai05a7d222008-02-02 13:56:56 +08001010static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
Conke Huab174432006-12-19 13:11:37 -08001011{
Shane Huange2dd90b2009-07-29 11:34:49 +08001012 /* set SBX00 SATA in IDE mode to AHCI mode */
Crane Cai05a7d222008-02-02 13:56:56 +08001013 u8 tmp;
Conke Huab174432006-12-19 13:11:37 -08001014
Crane Cai05a7d222008-02-02 13:56:56 +08001015 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1016 if (tmp == 0x01) {
Conke Huab174432006-12-19 13:11:37 -08001017 pci_read_config_byte(pdev, 0x40, &tmp);
1018 pci_write_config_byte(pdev, 0x40, tmp|1);
1019 pci_write_config_byte(pdev, 0x9, 1);
1020 pci_write_config_byte(pdev, 0xa, 6);
1021 pci_write_config_byte(pdev, 0x40, tmp);
1022
Conke Huc9f89472007-01-09 05:32:51 -05001023 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
Crane Cai05a7d222008-02-02 13:56:56 +08001024 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
Conke Huab174432006-12-19 13:11:37 -08001025 }
1026}
Crane Cai05a7d222008-02-02 13:56:56 +08001027DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001028DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
Crane Cai05a7d222008-02-02 13:56:56 +08001029DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001030DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
Shane Huange2dd90b2009-07-29 11:34:49 +08001031DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_SB900_SATA_IDE, quirk_amd_ide_mode);
1032DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_SB900_SATA_IDE, quirk_amd_ide_mode);
Conke Huab174432006-12-19 13:11:37 -08001033
Linus Torvalds1da177e2005-04-16 15:20:36 -07001034/*
1035 * Serverworks CSB5 IDE does not fully support native mode
1036 */
1037static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1038{
1039 u8 prog;
1040 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1041 if (prog & 5) {
1042 prog &= ~5;
1043 pdev->class &= ~5;
1044 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
Alan Cox368c73d2006-10-04 00:41:26 +01001045 /* PCI layer will sort out resources */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001046 }
1047}
Andrew Morton652c5382007-11-21 15:07:13 -08001048DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001049
1050/*
1051 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1052 */
1053static void __init quirk_ide_samemode(struct pci_dev *pdev)
1054{
1055 u8 prog;
1056
1057 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1058
1059 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001060 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001061 prog &= ~5;
1062 pdev->class &= ~5;
1063 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001064 }
1065}
Alan Cox368c73d2006-10-04 00:41:26 +01001066DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001067
Alan Cox979b1792008-07-24 17:18:38 +01001068/*
1069 * Some ATA devices break if put into D3
1070 */
1071
1072static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1073{
1074 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1075 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
1076 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1077}
1078DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
1079DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
Alan Cox7a661c62009-06-24 16:02:27 +01001080/* ALi loses some register settings that we cannot then restore */
1081DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, quirk_no_ata_d3);
1082/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1083 occur when mode detecting */
1084DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_no_ata_d3);
Alan Cox979b1792008-07-24 17:18:38 +01001085
Linus Torvalds1da177e2005-04-16 15:20:36 -07001086/* This was originally an Alpha specific thing, but it really fits here.
1087 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1088 */
1089static void __init quirk_eisa_bridge(struct pci_dev *dev)
1090{
1091 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1092}
Andrew Morton652c5382007-11-21 15:07:13 -08001093DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001094
Johannes Goecke7daa0c42006-04-20 02:43:17 -07001095
1096/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001097 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1098 * is not activated. The myth is that Asus said that they do not want the
1099 * users to be irritated by just another PCI Device in the Win98 device
1100 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1101 * package 2.7.0 for details)
1102 *
1103 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1104 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001105 * becomes necessary to do this tweak in two steps -- the chosen trigger
1106 * is either the Host bridge (preferred) or on-board VGA controller.
Jean Delvare9208ee82007-03-24 16:56:44 +01001107 *
1108 * Note that we used to unhide the SMBus that way on Toshiba laptops
1109 * (Satellite A40 and Tecra M2) but then found that the thermal management
1110 * was done by SMM code, which could cause unsynchronized concurrent
1111 * accesses to the SMBus registers, with potentially bad effects. Thus you
1112 * should be very careful when adding new entries: if SMM is accessing the
1113 * Intel SMBus, this is a very good reason to leave it hidden.
Jean Delvarea99acc82008-03-28 14:16:04 -07001114 *
1115 * Likewise, many recent laptops use ACPI for thermal management. If the
1116 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1117 * natively, and keeping the SMBus hidden is the right thing to do. If you
1118 * are about to add an entry in the table below, please first disassemble
1119 * the DSDT and double-check that there is no code accessing the SMBus.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001120 */
Vivek Goyal9d24a812007-01-11 01:52:44 +01001121static int asus_hides_smbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001122
1123static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1124{
1125 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1126 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1127 switch(dev->subsystem_device) {
Jean Delvarea00db372005-06-29 17:04:06 +02001128 case 0x8025: /* P4B-LX */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001129 case 0x8070: /* P4B */
1130 case 0x8088: /* P4B533 */
1131 case 0x1626: /* L3C notebook */
1132 asus_hides_smbus = 1;
1133 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001134 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001135 switch(dev->subsystem_device) {
1136 case 0x80b1: /* P4GE-V */
1137 case 0x80b2: /* P4PE */
1138 case 0x8093: /* P4B533-V */
1139 asus_hides_smbus = 1;
1140 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001141 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001142 switch(dev->subsystem_device) {
1143 case 0x8030: /* P4T533 */
1144 asus_hides_smbus = 1;
1145 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001146 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001147 switch (dev->subsystem_device) {
1148 case 0x8070: /* P4G8X Deluxe */
1149 asus_hides_smbus = 1;
1150 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001151 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
Jean Delvare321311a2006-07-31 08:53:15 +02001152 switch (dev->subsystem_device) {
1153 case 0x80c9: /* PU-DLS */
1154 asus_hides_smbus = 1;
1155 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001156 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001157 switch (dev->subsystem_device) {
1158 case 0x1751: /* M2N notebook */
1159 case 0x1821: /* M5N notebook */
Mats Erik Andersson4096ed02009-05-12 12:05:23 +02001160 case 0x1897: /* A6L notebook */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001161 asus_hides_smbus = 1;
1162 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001163 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001164 switch (dev->subsystem_device) {
1165 case 0x184b: /* W1N notebook */
1166 case 0x186a: /* M6Ne notebook */
1167 asus_hides_smbus = 1;
1168 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001169 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
Jean Delvare2e457852007-01-05 09:17:56 +01001170 switch (dev->subsystem_device) {
1171 case 0x80f2: /* P4P800-X */
1172 asus_hides_smbus = 1;
1173 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001174 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001175 switch (dev->subsystem_device) {
1176 case 0x1882: /* M6V notebook */
Jean Delvare2d1e1c72006-04-01 16:46:35 +02001177 case 0x1977: /* A6VA notebook */
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001178 asus_hides_smbus = 1;
1179 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001180 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1181 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1182 switch(dev->subsystem_device) {
1183 case 0x088C: /* HP Compaq nc8000 */
1184 case 0x0890: /* HP Compaq nc6000 */
1185 asus_hides_smbus = 1;
1186 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001187 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001188 switch (dev->subsystem_device) {
1189 case 0x12bc: /* HP D330L */
Jean Delvaree3b1bd52005-09-21 22:26:31 +02001190 case 0x12bd: /* HP D530 */
Michal Miroslaw74c57422009-05-12 13:49:25 -07001191 case 0x006a: /* HP Compaq nx9500 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001192 asus_hides_smbus = 1;
1193 }
Jean Delvare677cc642007-11-21 18:29:06 +01001194 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1195 switch (dev->subsystem_device) {
1196 case 0x12bf: /* HP xw4100 */
1197 asus_hides_smbus = 1;
1198 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001199 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1200 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1201 switch(dev->subsystem_device) {
1202 case 0xC00C: /* Samsung P35 notebook */
1203 asus_hides_smbus = 1;
1204 }
Rumen Ivanov Zarevc87f8832005-09-06 13:39:32 -07001205 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1206 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1207 switch(dev->subsystem_device) {
1208 case 0x0058: /* Compaq Evo N620c */
1209 asus_hides_smbus = 1;
1210 }
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001211 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1212 switch(dev->subsystem_device) {
1213 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1214 /* Motherboard doesn't have Host bridge
1215 * subvendor/subdevice IDs, therefore checking
1216 * its on-board VGA controller */
1217 asus_hides_smbus = 1;
1218 }
David O'Shea8293b0f2009-03-02 09:51:13 +01001219 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
Jean Delvare10260d92008-06-04 13:53:31 +02001220 switch(dev->subsystem_device) {
1221 case 0x00b8: /* Compaq Evo D510 CMT */
1222 case 0x00b9: /* Compaq Evo D510 SFF */
Jean Delvare6b5096e2009-07-28 11:49:19 +02001223 case 0x00ba: /* Compaq Evo D510 USDT */
David O'Shea8293b0f2009-03-02 09:51:13 +01001224 /* Motherboard doesn't have Host bridge
1225 * subvendor/subdevice IDs and on-board VGA
1226 * controller is disabled if an AGP card is
1227 * inserted, therefore checking USB UHCI
1228 * Controller #1 */
Jean Delvare10260d92008-06-04 13:53:31 +02001229 asus_hides_smbus = 1;
1230 }
Krzysztof Helt27e46852008-06-08 13:47:02 +02001231 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1232 switch (dev->subsystem_device) {
1233 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1234 /* Motherboard doesn't have host bridge
1235 * subvendor/subdevice IDs, therefore checking
1236 * its on-board VGA controller */
1237 asus_hides_smbus = 1;
1238 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001239 }
1240}
Andrew Morton652c5382007-11-21 15:07:13 -08001241DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1242DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1243DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1244DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
Jean Delvare677cc642007-11-21 18:29:06 +01001245DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
Andrew Morton652c5382007-11-21 15:07:13 -08001246DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1247DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1248DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1249DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1250DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001251
Andrew Morton652c5382007-11-21 15:07:13 -08001252DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
David O'Shea8293b0f2009-03-02 09:51:13 +01001253DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
Krzysztof Helt27e46852008-06-08 13:47:02 +02001254DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001255
Alan Cox1597cac2006-12-04 15:14:45 -08001256static void asus_hides_smbus_lpc(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001257{
1258 u16 val;
1259
1260 if (likely(!asus_hides_smbus))
1261 return;
1262
1263 pci_read_config_word(dev, 0xF2, &val);
1264 if (val & 0x8) {
1265 pci_write_config_word(dev, 0xF2, val & (~0x8));
1266 pci_read_config_word(dev, 0xF2, &val);
1267 if (val & 0x8)
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001268 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001269 else
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001270 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001271 }
1272}
Andrew Morton652c5382007-11-21 15:07:13 -08001273DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1274DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1275DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1276DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1277DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1278DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1279DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001280DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1281DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1282DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1283DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1284DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1285DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1286DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001287
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001288/* It appears we just have one such device. If not, we have a warning */
1289static void __iomem *asus_rcba_base;
1290static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001291{
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001292 u32 rcba;
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001293
1294 if (likely(!asus_hides_smbus))
1295 return;
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001296 WARN_ON(asus_rcba_base);
1297
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001298 pci_read_config_dword(dev, 0xF0, &rcba);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001299 /* use bits 31:14, 16 kB aligned */
1300 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1301 if (asus_rcba_base == NULL)
1302 return;
1303}
1304
1305static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1306{
1307 u32 val;
1308
1309 if (likely(!asus_hides_smbus || !asus_rcba_base))
1310 return;
1311 /* read the Function Disable register, dword mode only */
1312 val = readl(asus_rcba_base + 0x3418);
1313 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1314}
1315
1316static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1317{
1318 if (likely(!asus_hides_smbus || !asus_rcba_base))
1319 return;
1320 iounmap(asus_rcba_base);
1321 asus_rcba_base = NULL;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001322 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001323}
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001324
1325static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1326{
1327 asus_hides_smbus_lpc_ich6_suspend(dev);
1328 asus_hides_smbus_lpc_ich6_resume_early(dev);
1329 asus_hides_smbus_lpc_ich6_resume(dev);
1330}
Andrew Morton652c5382007-11-21 15:07:13 -08001331DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001332DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1333DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1334DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
Carl-Daniel Hailfingerce007ea2006-05-15 09:44:33 -07001335
Linus Torvalds1da177e2005-04-16 15:20:36 -07001336/*
1337 * SiS 96x south bridge: BIOS typically hides SMBus device...
1338 */
Alan Cox1597cac2006-12-04 15:14:45 -08001339static void quirk_sis_96x_smbus(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001340{
1341 u8 val = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001342 pci_read_config_byte(dev, 0x77, &val);
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001343 if (val & 0x10) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001344 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001345 pci_write_config_byte(dev, 0x77, val & ~0x10);
1346 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001347}
Andrew Morton652c5382007-11-21 15:07:13 -08001348DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1349DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1350DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1351DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001352DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1353DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1354DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1355DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001356
Linus Torvalds1da177e2005-04-16 15:20:36 -07001357/*
1358 * ... This is further complicated by the fact that some SiS96x south
1359 * bridges pretend to be 85C503/5513 instead. In that case see if we
1360 * spotted a compatible north bridge to make sure.
1361 * (pci_find_device doesn't work yet)
1362 *
1363 * We can also enable the sis96x bit in the discovery register..
1364 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001365#define SIS_DETECT_REGISTER 0x40
1366
Alan Cox1597cac2006-12-04 15:14:45 -08001367static void quirk_sis_503(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001368{
1369 u8 reg;
1370 u16 devid;
1371
1372 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1373 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1374 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1375 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1376 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1377 return;
1378 }
1379
Linus Torvalds1da177e2005-04-16 15:20:36 -07001380 /*
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001381 * Ok, it now shows up as a 96x.. run the 96x quirk by
1382 * hand in case it has already been processed.
1383 * (depends on link order, which is apparently not guaranteed)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001384 */
1385 dev->device = devid;
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001386 quirk_sis_96x_smbus(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001387}
Andrew Morton652c5382007-11-21 15:07:13 -08001388DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001389DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001390
Linus Torvalds1da177e2005-04-16 15:20:36 -07001391
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001392/*
1393 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1394 * and MC97 modem controller are disabled when a second PCI soundcard is
1395 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1396 * -- bjd
1397 */
Alan Cox1597cac2006-12-04 15:14:45 -08001398static void asus_hides_ac97_lpc(struct pci_dev *dev)
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001399{
1400 u8 val;
1401 int asus_hides_ac97 = 0;
1402
1403 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1404 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1405 asus_hides_ac97 = 1;
1406 }
1407
1408 if (!asus_hides_ac97)
1409 return;
1410
1411 pci_read_config_byte(dev, 0x50, &val);
1412 if (val & 0xc0) {
1413 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1414 pci_read_config_byte(dev, 0x50, &val);
1415 if (val & 0xc0)
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001416 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001417 else
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001418 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001419 }
1420}
Andrew Morton652c5382007-11-21 15:07:13 -08001421DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001422DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
Alan Cox1597cac2006-12-04 15:14:45 -08001423
Tejun Heo77967052006-08-19 03:54:39 +09001424#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
Alan Cox15e0c692006-07-12 15:05:41 +01001425
1426/*
1427 * If we are using libata we can drive this chip properly but must
1428 * do this early on to make the additional device appear during
1429 * the PCI scanning.
1430 */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001431static void quirk_jmicron_ata(struct pci_dev *pdev)
Alan Cox15e0c692006-07-12 15:05:41 +01001432{
Tejun Heoe34bb372007-02-26 20:24:03 +09001433 u32 conf1, conf5, class;
Alan Cox15e0c692006-07-12 15:05:41 +01001434 u8 hdr;
1435
1436 /* Only poke fn 0 */
1437 if (PCI_FUNC(pdev->devfn))
1438 return;
1439
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001440 pci_read_config_dword(pdev, 0x40, &conf1);
1441 pci_read_config_dword(pdev, 0x80, &conf5);
Alan Cox15e0c692006-07-12 15:05:41 +01001442
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001443 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1444 conf5 &= ~(1 << 24); /* Clear bit 24 */
Alan Cox15e0c692006-07-12 15:05:41 +01001445
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001446 switch (pdev->device) {
1447 case PCI_DEVICE_ID_JMICRON_JMB360:
1448 /* The controller should be in single function ahci mode */
1449 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1450 break;
Alan Cox15e0c692006-07-12 15:05:41 +01001451
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001452 case PCI_DEVICE_ID_JMICRON_JMB365:
1453 case PCI_DEVICE_ID_JMICRON_JMB366:
1454 /* Redirect IDE second PATA port to the right spot */
1455 conf5 |= (1 << 24);
1456 /* Fall through */
1457 case PCI_DEVICE_ID_JMICRON_JMB361:
1458 case PCI_DEVICE_ID_JMICRON_JMB363:
1459 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1460 /* Set the class codes correctly and then direct IDE 0 */
Tejun Heo3a9e3a52007-10-23 15:27:31 +09001461 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001462 break;
1463
1464 case PCI_DEVICE_ID_JMICRON_JMB368:
1465 /* The controller should be in single function IDE mode */
1466 conf1 |= 0x00C00000; /* Set 22, 23 */
1467 break;
Alan Cox15e0c692006-07-12 15:05:41 +01001468 }
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001469
1470 pci_write_config_dword(pdev, 0x40, conf1);
1471 pci_write_config_dword(pdev, 0x80, conf5);
1472
1473 /* Update pdev accordingly */
1474 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1475 pdev->hdr_type = hdr & 0x7f;
1476 pdev->multifunction = !!(hdr & 0x80);
Tejun Heoe34bb372007-02-26 20:24:03 +09001477
1478 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1479 pdev->class = class >> 8;
Alan Cox15e0c692006-07-12 15:05:41 +01001480}
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001481DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1482DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1483DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1484DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1485DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1486DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001487DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1488DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1489DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1490DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1491DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1492DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
Alan Cox15e0c692006-07-12 15:05:41 +01001493
1494#endif
1495
Linus Torvalds1da177e2005-04-16 15:20:36 -07001496#ifdef CONFIG_X86_IO_APIC
1497static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1498{
1499 int i;
1500
1501 if ((pdev->class >> 8) != 0xff00)
1502 return;
1503
1504 /* the first BAR is the location of the IO APIC...we must
1505 * not touch this (and it's already covered by the fixmap), so
1506 * forcibly insert it into the resource tree */
1507 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1508 insert_resource(&iomem_resource, &pdev->resource[0]);
1509
1510 /* The next five BARs all seem to be rubbish, so just clean
1511 * them out */
1512 for (i=1; i < 6; i++) {
1513 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1514 }
1515
1516}
Andrew Morton652c5382007-11-21 15:07:13 -08001517DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001518#endif
1519
Linus Torvalds1da177e2005-04-16 15:20:36 -07001520static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1521{
Eric W. Biederman0ba379e2009-09-06 21:48:35 -07001522 pci_msi_off(pdev);
1523 pdev->no_msi = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001524}
Andrew Morton652c5382007-11-21 15:07:13 -08001525DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1526DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1527DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001528
Kristen Accardi4602b882005-08-16 15:15:58 -07001529
1530/*
1531 * It's possible for the MSI to get corrupted if shpc and acpi
1532 * are used together on certain PXH-based systems.
1533 */
1534static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1535{
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08001536 pci_msi_off(dev);
Kristen Accardi4602b882005-08-16 15:15:58 -07001537 dev->no_msi = 1;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001538 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
Kristen Accardi4602b882005-08-16 15:15:58 -07001539}
1540DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1541DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1542DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1543DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1544DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1545
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -07001546/*
1547 * Some Intel PCI Express chipsets have trouble with downstream
1548 * device power management.
1549 */
1550static void quirk_intel_pcie_pm(struct pci_dev * dev)
1551{
1552 pci_pm_d3_delay = 120;
1553 dev->no_d1d2 = 1;
1554}
1555
1556DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1557DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1558DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1559DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1560DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1561DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1562DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1563DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1564DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1565DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1566DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1567DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1568DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1569DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1571DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1572DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1573DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1574DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1575DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1576DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
Kristen Accardi4602b882005-08-16 15:15:58 -07001577
Stefan Assmann426b3b82008-06-11 16:35:16 +02001578#ifdef CONFIG_X86_IO_APIC
1579/*
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001580 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1581 * remap the original interrupt in the linux kernel to the boot interrupt, so
1582 * that a PCI device's interrupt handler is installed on the boot interrupt
1583 * line instead.
1584 */
1585static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1586{
Stefan Assmann41b9eb22008-07-15 13:48:55 +02001587 if (noioapicquirk || noioapicreroute)
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001588 return;
1589
1590 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001591 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1592 dev->vendor, dev->device);
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001593}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001594DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1595DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1596DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1597DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1598DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1599DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1600DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1602DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1603DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1604DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1605DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1606DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1607DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1608DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1609DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001610
1611/*
Stefan Assmann426b3b82008-06-11 16:35:16 +02001612 * On some chipsets we can disable the generation of legacy INTx boot
1613 * interrupts.
1614 */
1615
1616/*
1617 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1618 * 300641-004US, section 5.7.3.
1619 */
1620#define INTEL_6300_IOAPIC_ABAR 0x40
1621#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1622
1623static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1624{
1625 u16 pci_config_word;
1626
1627 if (noioapicquirk)
1628 return;
1629
1630 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1631 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1632 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1633
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001634 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1635 dev->vendor, dev->device);
Stefan Assmann426b3b82008-06-11 16:35:16 +02001636}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001637DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1638DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
Olaf Dabrunz77251182008-07-08 15:59:47 +02001639
1640/*
1641 * disable boot interrupts on HT-1000
1642 */
1643#define BC_HT1000_FEATURE_REG 0x64
1644#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1645#define BC_HT1000_MAP_IDX 0xC00
1646#define BC_HT1000_MAP_DATA 0xC01
1647
1648static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1649{
1650 u32 pci_config_dword;
1651 u8 irq;
1652
1653 if (noioapicquirk)
1654 return;
1655
1656 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1657 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1658 BC_HT1000_PIC_REGS_ENABLE);
1659
1660 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1661 outb(irq, BC_HT1000_MAP_IDX);
1662 outb(0x00, BC_HT1000_MAP_DATA);
1663 }
1664
1665 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1666
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001667 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1668 dev->vendor, dev->device);
Olaf Dabrunz77251182008-07-08 15:59:47 +02001669}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001670DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1671DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001672
1673/*
1674 * disable boot interrupts on AMD and ATI chipsets
1675 */
1676/*
1677 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1678 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1679 * (due to an erratum).
1680 */
1681#define AMD_813X_MISC 0x40
1682#define AMD_813X_NOIOAMODE (1<<0)
Stefan Assmannbbe19442009-02-26 10:46:48 -08001683#define AMD_813X_REV_B2 0x13
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001684
1685static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1686{
1687 u32 pci_config_dword;
1688
1689 if (noioapicquirk)
1690 return;
Stefan Assmannbbe19442009-02-26 10:46:48 -08001691 if (dev->revision == AMD_813X_REV_B2)
1692 return;
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001693
1694 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1695 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1696 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1697
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001698 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1699 dev->vendor, dev->device);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001700}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001701DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1702DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001703
1704#define AMD_8111_PCI_IRQ_ROUTING 0x56
1705
1706static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1707{
1708 u16 pci_config_word;
1709
1710 if (noioapicquirk)
1711 return;
1712
1713 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1714 if (!pci_config_word) {
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001715 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1716 "already disabled\n", dev->vendor, dev->device);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001717 return;
1718 }
1719 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001720 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1721 dev->vendor, dev->device);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001722}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001723DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1724DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
Stefan Assmann426b3b82008-06-11 16:35:16 +02001725#endif /* CONFIG_X86_IO_APIC */
1726
Sergei Shtylyov33dced22007-02-07 18:18:45 +01001727/*
1728 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1729 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1730 * Re-allocate the region if needed...
1731 */
1732static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1733{
1734 struct resource *r = &dev->resource[0];
1735
1736 if (r->start & 0x8) {
1737 r->start = 0;
1738 r->end = 0xf;
1739 }
1740}
1741DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1742 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1743 quirk_tc86c001_ide);
1744
Linus Torvalds1da177e2005-04-16 15:20:36 -07001745static void __devinit quirk_netmos(struct pci_dev *dev)
1746{
1747 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1748 unsigned int num_serial = dev->subsystem_device & 0xf;
1749
1750 /*
1751 * These Netmos parts are multiport serial devices with optional
1752 * parallel ports. Even when parallel ports are present, they
1753 * are identified as class SERIAL, which means the serial driver
1754 * will claim them. To prevent this, mark them as class OTHER.
1755 * These combo devices should be claimed by parport_serial.
1756 *
1757 * The subdevice ID is of the form 0x00PS, where <P> is the number
1758 * of parallel ports and <S> is the number of serial ports.
1759 */
1760 switch (dev->device) {
Jiri Slaby4c9c1682008-12-08 16:19:14 +01001761 case PCI_DEVICE_ID_NETMOS_9835:
1762 /* Well, this rule doesn't hold for the following 9835 device */
1763 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1764 dev->subsystem_device == 0x0299)
1765 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001766 case PCI_DEVICE_ID_NETMOS_9735:
1767 case PCI_DEVICE_ID_NETMOS_9745:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001768 case PCI_DEVICE_ID_NETMOS_9845:
1769 case PCI_DEVICE_ID_NETMOS_9855:
1770 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1771 num_parallel) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001772 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001773 "%u serial); changing class SERIAL to OTHER "
1774 "(use parport_serial)\n",
1775 dev->device, num_parallel, num_serial);
1776 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1777 (dev->class & 0xff);
1778 }
1779 }
1780}
1781DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1782
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001783static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1784{
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001785 u16 command, pmcsr;
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001786 u8 __iomem *csr;
1787 u8 cmd_hi;
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001788 int pm;
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001789
1790 switch (dev->device) {
1791 /* PCI IDs taken from drivers/net/e100.c */
1792 case 0x1029:
1793 case 0x1030 ... 0x1034:
1794 case 0x1038 ... 0x103E:
1795 case 0x1050 ... 0x1057:
1796 case 0x1059:
1797 case 0x1064 ... 0x106B:
1798 case 0x1091 ... 0x1095:
1799 case 0x1209:
1800 case 0x1229:
1801 case 0x2449:
1802 case 0x2459:
1803 case 0x245D:
1804 case 0x27DC:
1805 break;
1806 default:
1807 return;
1808 }
1809
1810 /*
1811 * Some firmware hands off the e100 with interrupts enabled,
1812 * which can cause a flood of interrupts if packets are
1813 * received before the driver attaches to the device. So
1814 * disable all e100 interrupts here. The driver will
1815 * re-enable them when it's ready.
1816 */
1817 pci_read_config_word(dev, PCI_COMMAND, &command);
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001818
Benjamin Herrenschmidt1bef7dc2007-09-29 09:06:21 +10001819 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001820 return;
1821
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001822 /*
1823 * Check that the device is in the D0 power state. If it's not,
1824 * there is no point to look any further.
1825 */
1826 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1827 if (pm) {
1828 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1829 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1830 return;
1831 }
1832
Benjamin Herrenschmidt1bef7dc2007-09-29 09:06:21 +10001833 /* Convert from PCI bus to resource space. */
1834 csr = ioremap(pci_resource_start(dev, 0), 8);
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001835 if (!csr) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001836 dev_warn(&dev->dev, "Can't map e100 registers\n");
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001837 return;
1838 }
1839
1840 cmd_hi = readb(csr + 3);
1841 if (cmd_hi == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001842 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1843 "disabling\n");
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001844 writeb(1, csr + 3);
1845 }
1846
1847 iounmap(csr);
1848}
Marian Balakowicz4e68fc92007-07-03 11:03:18 +02001849DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03001850
Alexander Duyck649426e2009-03-05 13:57:28 -05001851/*
1852 * The 82575 and 82598 may experience data corruption issues when transitioning
1853 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1854 */
1855static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1856{
1857 dev_info(&dev->dev, "Disabling L0s\n");
1858 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1859}
1860DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1861DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1862DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1863DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1864DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1865DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1866DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1867DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1868DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1869DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1870DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1871DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1872DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1873DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1874
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03001875static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1876{
1877 /* rev 1 ncr53c810 chips don't set the class at all which means
1878 * they don't get their resources remapped. Fix that here.
1879 */
1880
1881 if (dev->class == PCI_CLASS_NOT_DEFINED) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001882 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03001883 dev->class = PCI_CLASS_STORAGE_SCSI;
1884 }
1885}
1886DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1887
Daniel Yeisley9d265122005-12-05 07:06:43 -05001888/* Enable 1k I/O space granularity on the Intel P64H2 */
1889static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1890{
1891 u16 en1k;
1892 u8 io_base_lo, io_limit_lo;
1893 unsigned long base, limit;
1894 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1895
1896 pci_read_config_word(dev, 0x40, &en1k);
1897
1898 if (en1k & 0x200) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001899 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
Daniel Yeisley9d265122005-12-05 07:06:43 -05001900
1901 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1902 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1903 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1904 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1905
1906 if (base <= limit) {
1907 res->start = base;
1908 res->end = limit + 0x3ff;
1909 }
1910 }
1911}
1912DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1913
Daniel Yeisley15a260d2006-12-21 14:34:57 -05001914/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1915 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1916 * in drivers/pci/setup-bus.c
1917 */
1918static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1919{
1920 u16 en1k, iobl_adr, iobl_adr_1k;
1921 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1922
1923 pci_read_config_word(dev, 0x40, &en1k);
1924
1925 if (en1k & 0x200) {
1926 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1927
1928 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1929
1930 if (iobl_adr != iobl_adr_1k) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001931 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
Daniel Yeisley15a260d2006-12-21 14:34:57 -05001932 iobl_adr,iobl_adr_1k);
1933 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1934 }
1935 }
1936}
1937DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1938
Brice Goglincf34a8e2006-06-13 14:35:42 -04001939/* Under some circumstances, AER is not linked with extended capabilities.
1940 * Force it to be linked by setting the corresponding control bit in the
1941 * config space.
1942 */
Alan Cox1597cac2006-12-04 15:14:45 -08001943static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
Brice Goglincf34a8e2006-06-13 14:35:42 -04001944{
1945 uint8_t b;
1946 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1947 if (!(b & 0x20)) {
1948 pci_write_config_byte(dev, 0xf41, b | 0x20);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001949 dev_info(&dev->dev,
1950 "Linking AER extended capability\n");
Brice Goglincf34a8e2006-06-13 14:35:42 -04001951 }
1952 }
1953}
1954DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1955 quirk_nvidia_ck804_pcie_aer_ext_cap);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001956DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
Alan Cox1597cac2006-12-04 15:14:45 -08001957 quirk_nvidia_ck804_pcie_aer_ext_cap);
Brice Goglincf34a8e2006-06-13 14:35:42 -04001958
Tim Yamin53a9bf42007-11-01 23:14:54 +00001959static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1960{
1961 /*
1962 * Disable PCI Bus Parking and PCI Master read caching on CX700
1963 * which causes unspecified timing errors with a VT6212L on the PCI
1964 * bus leading to USB2.0 packet loss. The defaults are that these
1965 * features are turned off but some BIOSes turn them on.
1966 */
1967
1968 uint8_t b;
1969 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1970 if (b & 0x40) {
1971 /* Turn off PCI Bus Parking */
1972 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1973
Tim Yaminbc043272008-03-30 20:58:59 +01001974 dev_info(&dev->dev,
1975 "Disabling VIA CX700 PCI parking\n");
1976 }
1977 }
1978
1979 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
1980 if (b != 0) {
Tim Yamin53a9bf42007-11-01 23:14:54 +00001981 /* Turn off PCI Master read caching */
1982 pci_write_config_byte(dev, 0x72, 0x0);
Tim Yaminbc043272008-03-30 20:58:59 +01001983
1984 /* Set PCI Master Bus time-out to "1x16 PCLK" */
Tim Yamin53a9bf42007-11-01 23:14:54 +00001985 pci_write_config_byte(dev, 0x75, 0x1);
Tim Yaminbc043272008-03-30 20:58:59 +01001986
1987 /* Disable "Read FIFO Timer" */
Tim Yamin53a9bf42007-11-01 23:14:54 +00001988 pci_write_config_byte(dev, 0x77, 0x0);
1989
Bjorn Helgaasd6505a52008-02-29 16:12:18 -07001990 dev_info(&dev->dev,
Tim Yaminbc043272008-03-30 20:58:59 +01001991 "Disabling VIA CX700 PCI caching\n");
Tim Yamin53a9bf42007-11-01 23:14:54 +00001992 }
1993 }
1994}
1995DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
1996
Benjamin Li99cb233d2008-07-02 10:59:04 -07001997/*
1998 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
1999 * VPD end tag will hang the device. This problem was initially
2000 * observed when a vpd entry was created in sysfs
2001 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2002 * will dump 32k of data. Reading a full 32k will cause an access
2003 * beyond the VPD end tag causing the device to hang. Once the device
2004 * is hung, the bnx2 driver will not be able to reset the device.
2005 * We believe that it is legal to read beyond the end tag and
2006 * therefore the solution is to limit the read/write length.
2007 */
2008static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2009{
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02002010 /*
Dean Hildebrand35405f22008-08-07 17:31:45 -07002011 * Only disable the VPD capability for 5706, 5706S, 5708,
2012 * 5708S and 5709 rev. A
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02002013 */
Benjamin Li99cb233d2008-07-02 10:59:04 -07002014 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
Dean Hildebrand35405f22008-08-07 17:31:45 -07002015 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
Benjamin Li99cb233d2008-07-02 10:59:04 -07002016 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02002017 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
Benjamin Li99cb233d2008-07-02 10:59:04 -07002018 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2019 (dev->revision & 0xf0) == 0x0)) {
2020 if (dev->vpd)
2021 dev->vpd->len = 0x80;
2022 }
2023}
2024
Yu Zhaobffadff2008-10-28 14:44:11 +08002025DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2026 PCI_DEVICE_ID_NX2_5706,
2027 quirk_brcm_570x_limit_vpd);
2028DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2029 PCI_DEVICE_ID_NX2_5706S,
2030 quirk_brcm_570x_limit_vpd);
2031DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2032 PCI_DEVICE_ID_NX2_5708,
2033 quirk_brcm_570x_limit_vpd);
2034DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2035 PCI_DEVICE_ID_NX2_5708S,
2036 quirk_brcm_570x_limit_vpd);
2037DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2038 PCI_DEVICE_ID_NX2_5709,
2039 quirk_brcm_570x_limit_vpd);
2040DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2041 PCI_DEVICE_ID_NX2_5709S,
2042 quirk_brcm_570x_limit_vpd);
Benjamin Li99cb233d2008-07-02 10:59:04 -07002043
Michal Miroslaw26c56dc2009-05-12 13:49:26 -07002044/* Originally in EDAC sources for i82875P:
2045 * Intel tells BIOS developers to hide device 6 which
2046 * configures the overflow device access containing
2047 * the DRBs - this is where we expose device 6.
2048 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2049 */
2050static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2051{
2052 u8 reg;
2053
2054 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2055 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2056 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2057 }
2058}
2059
2060DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2061 quirk_unhide_mch_dev6);
2062DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2063 quirk_unhide_mch_dev6);
2064
2065
Brice Goglin3f79e102006-08-31 01:54:56 -04002066#ifdef CONFIG_PCI_MSI
Tejun Heoebdf7d32007-05-31 00:40:48 -07002067/* Some chipsets do not support MSI. We cannot easily rely on setting
2068 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2069 * some other busses controlled by the chipset even if Linux is not
2070 * aware of it. Instead of setting the flag on all busses in the
2071 * machine, simply disable MSI globally.
Brice Goglin3f79e102006-08-31 01:54:56 -04002072 */
Tejun Heoebdf7d32007-05-31 00:40:48 -07002073static void __init quirk_disable_all_msi(struct pci_dev *dev)
Brice Goglin3f79e102006-08-31 01:54:56 -04002074{
Michael Ellerman88187df2007-01-25 19:34:07 +11002075 pci_no_msi();
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002076 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
Brice Goglin3f79e102006-08-31 01:54:56 -04002077}
Tejun Heoebdf7d32007-05-31 00:40:48 -07002078DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2079DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2080DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
Tejun Heo66d715c2008-07-04 09:59:32 -07002081DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
Jay Cliburn184b8122007-05-26 17:01:04 -05002082DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
Thomas Renninger162dedd2009-04-03 06:34:00 -07002083DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
Brice Goglin3f79e102006-08-31 01:54:56 -04002084
2085/* Disable MSI on chipsets that are known to not support it */
2086static void __devinit quirk_disable_msi(struct pci_dev *dev)
2087{
2088 if (dev->subordinate) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002089 dev_warn(&dev->dev, "MSI quirk detected; "
2090 "subordinate MSI disabled\n");
Brice Goglin3f79e102006-08-31 01:54:56 -04002091 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2092 }
2093}
2094DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
Brice Goglin6397c752006-08-31 01:55:32 -04002095
2096/* Go through the list of Hypertransport capabilities and
2097 * return 1 if a HT MSI capability is found and enabled */
2098static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2099{
Michael Ellerman7a380502006-11-22 18:26:21 +11002100 int pos, ttl = 48;
2101
2102 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2103 while (pos && ttl--) {
2104 u8 flags;
2105
2106 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2107 &flags) == 0)
2108 {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002109 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
Michael Ellerman7a380502006-11-22 18:26:21 +11002110 flags & HT_MSI_FLAGS_ENABLE ?
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002111 "enabled" : "disabled");
Michael Ellerman7a380502006-11-22 18:26:21 +11002112 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
Brice Goglin6397c752006-08-31 01:55:32 -04002113 }
Michael Ellerman7a380502006-11-22 18:26:21 +11002114
2115 pos = pci_find_next_ht_capability(dev, pos,
2116 HT_CAPTYPE_MSI_MAPPING);
Brice Goglin6397c752006-08-31 01:55:32 -04002117 }
2118 return 0;
2119}
2120
2121/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2122static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2123{
2124 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002125 dev_warn(&dev->dev, "MSI quirk detected; "
2126 "subordinate MSI disabled\n");
Brice Goglin6397c752006-08-31 01:55:32 -04002127 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2128 }
2129}
2130DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2131 quirk_msi_ht_cap);
Sebastien Dugue6bae1d92007-12-13 16:09:25 -08002132
Brice Goglin6397c752006-08-31 01:55:32 -04002133/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2134 * MSI are supported if the MSI capability set in any of these mappings.
2135 */
2136static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2137{
2138 struct pci_dev *pdev;
2139
2140 if (!dev->subordinate)
2141 return;
2142
2143 /* check HT MSI cap on this chipset and the root one.
2144 * a single one having MSI is enough to be sure that MSI are supported.
2145 */
Alan Cox11f242f2006-10-10 14:39:00 -07002146 pdev = pci_get_slot(dev->bus, 0);
Jesper Juhl9ac0ce82006-12-04 15:14:48 -08002147 if (!pdev)
2148 return;
David Rientjes0c875c22006-12-03 11:55:34 -08002149 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002150 dev_warn(&dev->dev, "MSI quirk detected; "
2151 "subordinate MSI disabled\n");
Brice Goglin6397c752006-08-31 01:55:32 -04002152 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2153 }
Alan Cox11f242f2006-10-10 14:39:00 -07002154 pci_dev_put(pdev);
Brice Goglin6397c752006-08-31 01:55:32 -04002155}
2156DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2157 quirk_nvidia_ck804_msi_ht_cap);
David Millerba698ad2007-10-25 01:16:30 -07002158
Bjorn Helgaas415b6d02008-02-29 16:04:39 -07002159/* Force enable MSI mapping capability on HT bridges */
2160static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
Peer Chen9dc625e2008-02-04 23:50:13 -08002161{
2162 int pos, ttl = 48;
2163
2164 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2165 while (pos && ttl--) {
2166 u8 flags;
2167
2168 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2169 &flags) == 0) {
2170 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2171
2172 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2173 flags | HT_MSI_FLAGS_ENABLE);
2174 }
2175 pos = pci_find_next_ht_capability(dev, pos,
2176 HT_CAPTYPE_MSI_MAPPING);
2177 }
2178}
Bjorn Helgaas415b6d02008-02-29 16:04:39 -07002179DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2180 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2181 ht_enable_msi_mapping);
Peer Chen9dc625e2008-02-04 23:50:13 -08002182
Yinghai Lue0ae4f52009-02-17 20:40:09 -08002183DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2184 ht_enable_msi_mapping);
2185
Andreas Petlund75e07fc2008-11-20 20:42:25 -08002186/* The P5N32-SLI Premium motherboard from Asus has a problem with msi
2187 * for the MCP55 NIC. It is not yet determined whether the msi problem
2188 * also affects other devices. As for now, turn off msi for this device.
2189 */
2190static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2191{
2192 if (dmi_name_in_vendors("P5N32-SLI PREMIUM")) {
2193 dev_info(&dev->dev,
2194 "Disabling msi for MCP55 NIC on P5N32-SLI Premium\n");
2195 dev->no_msi = 1;
2196 }
2197}
2198DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2199 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2200 nvenet_msi_disable);
2201
Yinghai Lude745302009-03-20 19:29:41 -07002202static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2203{
2204 int pos, ttl = 48;
2205 int found = 0;
2206
2207 /* check if there is HT MSI cap or enabled on this device */
2208 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2209 while (pos && ttl--) {
2210 u8 flags;
2211
2212 if (found < 1)
2213 found = 1;
2214 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2215 &flags) == 0) {
2216 if (flags & HT_MSI_FLAGS_ENABLE) {
2217 if (found < 2) {
2218 found = 2;
2219 break;
2220 }
2221 }
2222 }
2223 pos = pci_find_next_ht_capability(dev, pos,
2224 HT_CAPTYPE_MSI_MAPPING);
2225 }
2226
2227 return found;
2228}
2229
2230static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2231{
2232 struct pci_dev *dev;
2233 int pos;
2234 int i, dev_no;
2235 int found = 0;
2236
2237 dev_no = host_bridge->devfn >> 3;
2238 for (i = dev_no + 1; i < 0x20; i++) {
2239 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2240 if (!dev)
2241 continue;
2242
2243 /* found next host bridge ?*/
2244 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2245 if (pos != 0) {
2246 pci_dev_put(dev);
2247 break;
2248 }
2249
2250 if (ht_check_msi_mapping(dev)) {
2251 found = 1;
2252 pci_dev_put(dev);
2253 break;
2254 }
2255 pci_dev_put(dev);
2256 }
2257
2258 return found;
2259}
2260
Yinghai Lueeafda72009-03-29 12:30:05 -07002261#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2262#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2263
2264static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
2265{
2266 int pos, ctrl_off;
2267 int end = 0;
2268 u16 flags, ctrl;
2269
2270 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2271
2272 if (!pos)
2273 goto out;
2274
2275 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2276
2277 ctrl_off = ((flags >> 10) & 1) ?
2278 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2279 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2280
2281 if (ctrl & (1 << 6))
2282 end = 1;
2283
2284out:
2285 return end;
2286}
2287
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002288static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
2289{
2290 struct pci_dev *host_bridge;
2291 int pos;
2292 int i, dev_no;
2293 int found = 0;
2294
2295 dev_no = dev->devfn >> 3;
2296 for (i = dev_no; i >= 0; i--) {
2297 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2298 if (!host_bridge)
2299 continue;
2300
2301 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2302 if (pos != 0) {
2303 found = 1;
2304 break;
2305 }
2306 pci_dev_put(host_bridge);
2307 }
2308
2309 if (!found)
2310 return;
2311
Yinghai Lueeafda72009-03-29 12:30:05 -07002312 /* don't enable end_device/host_bridge with leaf directly here */
2313 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2314 host_bridge_with_leaf(host_bridge))
Yinghai Lude745302009-03-20 19:29:41 -07002315 goto out;
2316
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002317 /* root did that ! */
2318 if (msi_ht_cap_enabled(host_bridge))
2319 goto out;
2320
2321 ht_enable_msi_mapping(dev);
2322
2323out:
2324 pci_dev_put(host_bridge);
2325}
2326
2327static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2328{
2329 int pos, ttl = 48;
2330
2331 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2332 while (pos && ttl--) {
2333 u8 flags;
2334
2335 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2336 &flags) == 0) {
Prakash Punnoor6a958d52009-03-06 10:10:35 +01002337 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002338
2339 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2340 flags & ~HT_MSI_FLAGS_ENABLE);
2341 }
2342 pos = pci_find_next_ht_capability(dev, pos,
2343 HT_CAPTYPE_MSI_MAPPING);
2344 }
2345}
2346
Yinghai Lude745302009-03-20 19:29:41 -07002347static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
Peer Chen9dc625e2008-02-04 23:50:13 -08002348{
2349 struct pci_dev *host_bridge;
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002350 int pos;
2351 int found;
2352
2353 /* check if there is HT MSI cap or enabled on this device */
2354 found = ht_check_msi_mapping(dev);
2355
2356 /* no HT MSI CAP */
2357 if (found == 0)
2358 return;
Peer Chen9dc625e2008-02-04 23:50:13 -08002359
2360 /*
2361 * HT MSI mapping should be disabled on devices that are below
2362 * a non-Hypertransport host bridge. Locate the host bridge...
2363 */
2364 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2365 if (host_bridge == NULL) {
2366 dev_warn(&dev->dev,
2367 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2368 return;
2369 }
2370
2371 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2372 if (pos != 0) {
2373 /* Host bridge is to HT */
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002374 if (found == 1) {
2375 /* it is not enabled, try to enable it */
Yinghai Lude745302009-03-20 19:29:41 -07002376 if (all)
2377 ht_enable_msi_mapping(dev);
2378 else
2379 nv_ht_enable_msi_mapping(dev);
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002380 }
Peer Chen9dc625e2008-02-04 23:50:13 -08002381 return;
2382 }
2383
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002384 /* HT MSI is not enabled */
2385 if (found == 1)
2386 return;
Peer Chen9dc625e2008-02-04 23:50:13 -08002387
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002388 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2389 ht_disable_msi_mapping(dev);
Peer Chen9dc625e2008-02-04 23:50:13 -08002390}
Yinghai Lude745302009-03-20 19:29:41 -07002391
2392static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2393{
2394 return __nv_msi_ht_cap_quirk(dev, 1);
2395}
2396
2397static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2398{
2399 return __nv_msi_ht_cap_quirk(dev, 0);
2400}
2401
2402DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
Tejun Heo6dab62e2009-07-21 16:08:43 -07002403DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
Yinghai Lude745302009-03-20 19:29:41 -07002404
2405DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
Tejun Heo6dab62e2009-07-21 16:08:43 -07002406DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
Peer Chen9dc625e2008-02-04 23:50:13 -08002407
David Millerba698ad2007-10-25 01:16:30 -07002408static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2409{
2410 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2411}
Shane Huang4600c9d2008-01-25 15:46:24 +09002412static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2413{
2414 struct pci_dev *p;
2415
2416 /* SB700 MSI issue will be fixed at HW level from revision A21,
2417 * we need check PCI REVISION ID of SMBus controller to get SB700
2418 * revision.
2419 */
2420 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2421 NULL);
2422 if (!p)
2423 return;
2424
2425 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2426 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2427 pci_dev_put(p);
2428}
David Millerba698ad2007-10-25 01:16:30 -07002429DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2430 PCI_DEVICE_ID_TIGON3_5780,
2431 quirk_msi_intx_disable_bug);
2432DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2433 PCI_DEVICE_ID_TIGON3_5780S,
2434 quirk_msi_intx_disable_bug);
2435DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2436 PCI_DEVICE_ID_TIGON3_5714,
2437 quirk_msi_intx_disable_bug);
2438DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2439 PCI_DEVICE_ID_TIGON3_5714S,
2440 quirk_msi_intx_disable_bug);
2441DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2442 PCI_DEVICE_ID_TIGON3_5715,
2443 quirk_msi_intx_disable_bug);
2444DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2445 PCI_DEVICE_ID_TIGON3_5715S,
2446 quirk_msi_intx_disable_bug);
2447
David Millerbc38b412007-10-25 01:16:52 -07002448DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
Shane Huang4600c9d2008-01-25 15:46:24 +09002449 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002450DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
Shane Huang4600c9d2008-01-25 15:46:24 +09002451 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002452DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
Shane Huang4600c9d2008-01-25 15:46:24 +09002453 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002454DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
Shane Huang4600c9d2008-01-25 15:46:24 +09002455 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002456DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
Shane Huang4600c9d2008-01-25 15:46:24 +09002457 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002458
2459DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2460 quirk_msi_intx_disable_bug);
2461DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2462 quirk_msi_intx_disable_bug);
2463DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2464 quirk_msi_intx_disable_bug);
2465
Brice Goglin3f79e102006-08-31 01:54:56 -04002466#endif /* CONFIG_PCI_MSI */
Thomas Petazzoni3d137312008-08-19 10:28:24 +02002467
Yu Zhao7eb93b12009-04-03 15:18:11 +08002468#ifdef CONFIG_PCI_IOV
2469
2470/*
2471 * For Intel 82576 SR-IOV NIC, if BIOS doesn't allocate resources for the
2472 * SR-IOV BARs, zero the Flash BAR and program the SR-IOV BARs to use the
2473 * old Flash Memory Space.
2474 */
2475static void __devinit quirk_i82576_sriov(struct pci_dev *dev)
2476{
2477 int pos, flags;
2478 u32 bar, start, size;
2479
2480 if (PAGE_SIZE > 0x10000)
2481 return;
2482
2483 flags = pci_resource_flags(dev, 0);
2484 if ((flags & PCI_BASE_ADDRESS_SPACE) !=
2485 PCI_BASE_ADDRESS_SPACE_MEMORY ||
2486 (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) !=
2487 PCI_BASE_ADDRESS_MEM_TYPE_32)
2488 return;
2489
2490 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
2491 if (!pos)
2492 return;
2493
2494 pci_read_config_dword(dev, pos + PCI_SRIOV_BAR, &bar);
2495 if (bar & PCI_BASE_ADDRESS_MEM_MASK)
2496 return;
2497
2498 start = pci_resource_start(dev, 1);
2499 size = pci_resource_len(dev, 1);
2500 if (!start || size != 0x400000 || start & (size - 1))
2501 return;
2502
2503 pci_resource_flags(dev, 1) = 0;
2504 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
2505 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR, start);
2506 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR + 12, start + size / 2);
2507
2508 dev_info(&dev->dev, "use Flash Memory Space for SR-IOV BARs\n");
2509}
2510DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c9, quirk_i82576_sriov);
2511DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, quirk_i82576_sriov);
2512DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, quirk_i82576_sriov);
Alexander Duyckdcb4ea22009-05-06 10:25:42 +00002513DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e8, quirk_i82576_sriov);
2514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150a, quirk_i82576_sriov);
Alexander Duyck6f1186b2009-08-13 16:57:49 -07002515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150d, quirk_i82576_sriov);
Yu Zhao7eb93b12009-04-03 15:18:11 +08002516
2517#endif /* CONFIG_PCI_IOV */
2518
Jesse Barnesbfb0f332008-10-27 17:50:21 -07002519static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2520 struct pci_fixup *end)
Thomas Petazzoni3d137312008-08-19 10:28:24 +02002521{
2522 while (f < end) {
2523 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
Jesse Barnesbfb0f332008-10-27 17:50:21 -07002524 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
Yinghai Luc9bbb4a2008-09-24 19:04:33 -07002525 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
Thomas Petazzoni3d137312008-08-19 10:28:24 +02002526 f->hook(dev);
2527 }
2528 f++;
2529 }
2530}
2531
2532extern struct pci_fixup __start_pci_fixups_early[];
2533extern struct pci_fixup __end_pci_fixups_early[];
2534extern struct pci_fixup __start_pci_fixups_header[];
2535extern struct pci_fixup __end_pci_fixups_header[];
2536extern struct pci_fixup __start_pci_fixups_final[];
2537extern struct pci_fixup __end_pci_fixups_final[];
2538extern struct pci_fixup __start_pci_fixups_enable[];
2539extern struct pci_fixup __end_pci_fixups_enable[];
2540extern struct pci_fixup __start_pci_fixups_resume[];
2541extern struct pci_fixup __end_pci_fixups_resume[];
2542extern struct pci_fixup __start_pci_fixups_resume_early[];
2543extern struct pci_fixup __end_pci_fixups_resume_early[];
2544extern struct pci_fixup __start_pci_fixups_suspend[];
2545extern struct pci_fixup __end_pci_fixups_suspend[];
2546
2547
2548void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2549{
2550 struct pci_fixup *start, *end;
2551
2552 switch(pass) {
2553 case pci_fixup_early:
2554 start = __start_pci_fixups_early;
2555 end = __end_pci_fixups_early;
2556 break;
2557
2558 case pci_fixup_header:
2559 start = __start_pci_fixups_header;
2560 end = __end_pci_fixups_header;
2561 break;
2562
2563 case pci_fixup_final:
2564 start = __start_pci_fixups_final;
2565 end = __end_pci_fixups_final;
2566 break;
2567
2568 case pci_fixup_enable:
2569 start = __start_pci_fixups_enable;
2570 end = __end_pci_fixups_enable;
2571 break;
2572
2573 case pci_fixup_resume:
2574 start = __start_pci_fixups_resume;
2575 end = __end_pci_fixups_resume;
2576 break;
2577
2578 case pci_fixup_resume_early:
2579 start = __start_pci_fixups_resume_early;
2580 end = __end_pci_fixups_resume_early;
2581 break;
2582
2583 case pci_fixup_suspend:
2584 start = __start_pci_fixups_suspend;
2585 end = __end_pci_fixups_suspend;
2586 break;
2587
2588 default:
2589 /* stupid compiler warning, you would think with an enum... */
2590 return;
2591 }
2592 pci_do_fixups(dev, start, end);
2593}
2594#else
2595void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) {}
2596#endif
2597EXPORT_SYMBOL(pci_fixup_device);