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gerrit-public.fairphone.software / kernel / msm-4.9 / 2094dd82eddc468b53ee99d92c38b23a65efac03 / . / drivers / gpu / drm / nouveau / core / subdev / device / nv40.c
blob: c6005c27382e7a7e003ad4e0a49e573cf61ddead [file] [log] [blame]
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <subdev/device.h>
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]26#include <subdev/bios.h>
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]27#include <subdev/gpio.h>
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]28#include <subdev/i2c.h>
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]29#include <subdev/clock.h>
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]30#include <subdev/devinit.h>
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]31#include <subdev/mc.h>
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]32#include <subdev/timer.h>
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]33#include <subdev/fb.h>
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]34#include <subdev/instmem.h>
35#include <subdev/vm.h>
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]36
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]37#include <engine/dmaobj.h>
38#include <engine/fifo.h>
39#include <engine/software.h>
40#include <engine/graph.h>
41#include <engine/mpeg.h>
42#include <engine/disp.h>
43
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]44int
45nv40_identify(struct nouveau_device *device)
46{
47 switch (device->chipset) {
48 case 0x40:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame^]49 device->cname = "NV40";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]50 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]51 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]52 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]53 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]54 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]55 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]56 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]57 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]58 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
59 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]60 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
61 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
62 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
63 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
64 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
65 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]66 break;
67 case 0x41:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame^]68 device->cname = "NV41";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]69 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]70 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]71 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]72 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]73 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]74 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]75 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]76 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]77 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
78 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]79 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
80 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
81 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
82 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
83 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
84 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]85 break;
86 case 0x42:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame^]87 device->cname = "NV42";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]88 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]89 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]90 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]91 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]92 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]93 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]94 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]95 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]96 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
97 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]98 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
99 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
100 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
101 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
102 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
103 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]104 break;
105 case 0x43:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame^]106 device->cname = "NV43";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]107 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]108 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]109 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]110 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]111 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]112 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]113 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]114 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]115 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
116 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]117 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
118 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
119 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
120 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
121 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
122 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]123 break;
124 case 0x45:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame^]125 device->cname = "NV45";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]126 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]127 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]128 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]129 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]130 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]131 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]132 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]133 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]134 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
135 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]136 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
137 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
138 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
139 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
140 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
141 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]142 break;
143 case 0x47:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame^]144 device->cname = "G70";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]145 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]146 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]147 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]148 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]149 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]150 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]151 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]152 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]153 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
154 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]155 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
156 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
157 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
158 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
159 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
160 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]161 break;
162 case 0x49:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame^]163 device->cname = "G71";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]164 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]165 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]166 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]167 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]168 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]169 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]170 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]171 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]172 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
173 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]174 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
175 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
176 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
177 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
178 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
179 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]180 break;
181 case 0x4b:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame^]182 device->cname = "G73";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]183 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]184 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]185 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]186 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]187 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]188 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]189 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]190 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]191 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
192 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]193 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
194 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
195 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
196 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
197 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
198 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]199 break;
200 case 0x44:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame^]201 device->cname = "NV44";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]202 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]203 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]204 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]205 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]206 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]207 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]208 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]209 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]210 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
211 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]212 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
213 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
214 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
215 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
216 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
217 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]218 break;
219 case 0x46:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame^]220 device->cname = "G72";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]221 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]222 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]223 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]224 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]225 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]226 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]227 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]228 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]229 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
230 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]231 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
232 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
233 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
234 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
235 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
236 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]237 break;
238 case 0x4a:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame^]239 device->cname = "NV44A";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]240 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]241 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]242 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]243 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]244 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]245 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]246 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]247 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]248 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
249 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]250 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
251 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
252 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
253 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
254 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
255 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]256 break;
257 case 0x4c:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame^]258 device->cname = "C61";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]259 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]260 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]261 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]262 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]263 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]264 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]265 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]266 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]267 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
268 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]269 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
270 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
271 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
272 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
273 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
274 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]275 break;
276 case 0x4e:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame^]277 device->cname = "C51";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]278 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]279 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]280 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]281 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]282 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]283 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]284 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]285 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]286 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
287 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]288 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
289 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
290 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
291 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
292 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
293 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]294 break;
295 case 0x63:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame^]296 device->cname = "C73";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]297 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]298 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]299 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]300 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]301 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]302 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]303 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]304 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]305 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
306 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]307 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
308 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
309 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
310 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
311 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
312 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]313 break;
314 case 0x67:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame^]315 device->cname = "C67";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]316 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]317 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]318 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]319 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]320 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]321 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]322 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]323 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]324 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
325 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]326 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
327 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
328 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
329 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
330 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
331 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]332 break;
333 case 0x68:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame^]334 device->cname = "C68";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]335 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]336 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]337 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]338 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]339 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]340 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]341 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]342 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]343 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
344 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]345 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
346 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
347 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
348 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
349 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
350 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]351 break;
352 default:
353 nv_fatal(device, "unknown Curie chipset\n");
354 return -EINVAL;
355 }
356
357 return 0;
358}