Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 1 | /* |
Michal Simek | 968674b | 2013-08-27 10:48:29 +0200 | [diff] [blame] | 2 | * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu> |
| 3 | * Copyright (C) 2012-2013 Xilinx, Inc. |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 4 | * Copyright (C) 2007-2009 PetaLogix |
| 5 | * Copyright (C) 2006 Atmark Techno, Inc. |
| 6 | * |
| 7 | * This file is subject to the terms and conditions of the GNU General Public |
| 8 | * License. See the file "COPYING" in the main directory of this archive |
| 9 | * for more details. |
| 10 | */ |
| 11 | |
Grant Likely | 2462bac | 2012-01-26 14:10:13 -0700 | [diff] [blame] | 12 | #include <linux/irqdomain.h> |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 13 | #include <linux/irq.h> |
Michal Simek | bcff661 | 2013-08-27 10:49:00 +0200 | [diff] [blame] | 14 | #include <linux/of_address.h> |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 15 | #include <linux/io.h> |
John Williams | 892ee92 | 2009-07-29 22:08:40 +1000 | [diff] [blame] | 16 | #include <linux/bug.h> |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 17 | |
Michal Simek | 8a9e90a | 2013-08-27 10:49:00 +0200 | [diff] [blame] | 18 | #include "../../drivers/irqchip/irqchip.h" |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 19 | |
Michal Simek | bcff661 | 2013-08-27 10:49:00 +0200 | [diff] [blame] | 20 | static void __iomem *intc_baseaddr; |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 21 | |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 22 | /* No one else should require these constants, so define them locally here. */ |
| 23 | #define ISR 0x00 /* Interrupt Status Register */ |
| 24 | #define IPR 0x04 /* Interrupt Pending Register */ |
| 25 | #define IER 0x08 /* Interrupt Enable Register */ |
| 26 | #define IAR 0x0c /* Interrupt Acknowledge Register */ |
| 27 | #define SIE 0x10 /* Set Interrupt Enable bits */ |
| 28 | #define CIE 0x14 /* Clear Interrupt Enable bits */ |
| 29 | #define IVR 0x18 /* Interrupt Vector Register */ |
| 30 | #define MER 0x1c /* Master Enable Register */ |
| 31 | |
| 32 | #define MER_ME (1<<0) |
| 33 | #define MER_HIE (1<<1) |
| 34 | |
Michal Simek | 1aa1243 | 2014-02-24 14:56:32 +0100 | [diff] [blame] | 35 | static unsigned int (*read_fn)(void __iomem *); |
| 36 | static void (*write_fn)(u32, void __iomem *); |
| 37 | |
| 38 | static void intc_write32(u32 val, void __iomem *addr) |
| 39 | { |
| 40 | iowrite32(val, addr); |
| 41 | } |
| 42 | |
| 43 | static unsigned int intc_read32(void __iomem *addr) |
| 44 | { |
| 45 | return ioread32(addr); |
| 46 | } |
| 47 | |
| 48 | static void intc_write32_be(u32 val, void __iomem *addr) |
| 49 | { |
| 50 | iowrite32be(val, addr); |
| 51 | } |
| 52 | |
| 53 | static unsigned int intc_read32_be(void __iomem *addr) |
| 54 | { |
| 55 | return ioread32be(addr); |
| 56 | } |
| 57 | |
Thomas Gleixner | 6f205a4 | 2011-02-06 19:36:30 +0000 | [diff] [blame] | 58 | static void intc_enable_or_unmask(struct irq_data *d) |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 59 | { |
Michal Simek | 6c7a267 | 2011-12-09 10:45:20 +0100 | [diff] [blame] | 60 | unsigned long mask = 1 << d->hwirq; |
| 61 | |
| 62 | pr_debug("enable_or_unmask: %ld\n", d->hwirq); |
steve@digidescorp.com | 33d9ff5 | 2009-11-17 08:43:39 -0600 | [diff] [blame] | 63 | |
| 64 | /* ack level irqs because they can't be acked during |
| 65 | * ack function since the handle_level_irq function |
| 66 | * acks the irq before calling the interrupt handler |
| 67 | */ |
Thomas Gleixner | 4adc192 | 2011-03-24 14:52:04 +0100 | [diff] [blame] | 68 | if (irqd_is_level_type(d)) |
Michal Simek | 1aa1243 | 2014-02-24 14:56:32 +0100 | [diff] [blame] | 69 | write_fn(mask, intc_baseaddr + IAR); |
Michal Simek | 7958a68 | 2012-11-05 11:51:13 +0100 | [diff] [blame] | 70 | |
Michal Simek | 1aa1243 | 2014-02-24 14:56:32 +0100 | [diff] [blame] | 71 | write_fn(mask, intc_baseaddr + SIE); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 72 | } |
| 73 | |
Thomas Gleixner | 6f205a4 | 2011-02-06 19:36:30 +0000 | [diff] [blame] | 74 | static void intc_disable_or_mask(struct irq_data *d) |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 75 | { |
Michal Simek | 6c7a267 | 2011-12-09 10:45:20 +0100 | [diff] [blame] | 76 | pr_debug("disable: %ld\n", d->hwirq); |
Michal Simek | 1aa1243 | 2014-02-24 14:56:32 +0100 | [diff] [blame] | 77 | write_fn(1 << d->hwirq, intc_baseaddr + CIE); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 78 | } |
| 79 | |
Thomas Gleixner | 6f205a4 | 2011-02-06 19:36:30 +0000 | [diff] [blame] | 80 | static void intc_ack(struct irq_data *d) |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 81 | { |
Michal Simek | 6c7a267 | 2011-12-09 10:45:20 +0100 | [diff] [blame] | 82 | pr_debug("ack: %ld\n", d->hwirq); |
Michal Simek | 1aa1243 | 2014-02-24 14:56:32 +0100 | [diff] [blame] | 83 | write_fn(1 << d->hwirq, intc_baseaddr + IAR); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 84 | } |
| 85 | |
Thomas Gleixner | 6f205a4 | 2011-02-06 19:36:30 +0000 | [diff] [blame] | 86 | static void intc_mask_ack(struct irq_data *d) |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 87 | { |
Michal Simek | 6c7a267 | 2011-12-09 10:45:20 +0100 | [diff] [blame] | 88 | unsigned long mask = 1 << d->hwirq; |
| 89 | |
| 90 | pr_debug("disable_and_ack: %ld\n", d->hwirq); |
Michal Simek | 1aa1243 | 2014-02-24 14:56:32 +0100 | [diff] [blame] | 91 | write_fn(mask, intc_baseaddr + CIE); |
| 92 | write_fn(mask, intc_baseaddr + IAR); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 93 | } |
| 94 | |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 95 | static struct irq_chip intc_dev = { |
| 96 | .name = "Xilinx INTC", |
Thomas Gleixner | 6f205a4 | 2011-02-06 19:36:30 +0000 | [diff] [blame] | 97 | .irq_unmask = intc_enable_or_unmask, |
| 98 | .irq_mask = intc_disable_or_mask, |
| 99 | .irq_ack = intc_ack, |
| 100 | .irq_mask_ack = intc_mask_ack, |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 101 | }; |
| 102 | |
Grant Likely | 2462bac | 2012-01-26 14:10:13 -0700 | [diff] [blame] | 103 | static struct irq_domain *root_domain; |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 104 | |
Grant Likely | 2462bac | 2012-01-26 14:10:13 -0700 | [diff] [blame] | 105 | unsigned int get_irq(void) |
| 106 | { |
| 107 | unsigned int hwirq, irq = -1; |
| 108 | |
Michal Simek | 1aa1243 | 2014-02-24 14:56:32 +0100 | [diff] [blame] | 109 | hwirq = read_fn(intc_baseaddr + IVR); |
Grant Likely | 2462bac | 2012-01-26 14:10:13 -0700 | [diff] [blame] | 110 | if (hwirq != -1U) |
| 111 | irq = irq_find_mapping(root_domain, hwirq); |
| 112 | |
| 113 | pr_debug("get_irq: hwirq=%d, irq=%d\n", hwirq, irq); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 114 | |
| 115 | return irq; |
| 116 | } |
| 117 | |
Michal Simek | c0d997f | 2012-12-13 17:30:05 +0100 | [diff] [blame] | 118 | static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) |
Grant Likely | 2462bac | 2012-01-26 14:10:13 -0700 | [diff] [blame] | 119 | { |
| 120 | u32 intr_mask = (u32)d->host_data; |
| 121 | |
| 122 | if (intr_mask & (1 << hw)) { |
| 123 | irq_set_chip_and_handler_name(irq, &intc_dev, |
| 124 | handle_edge_irq, "edge"); |
| 125 | irq_clear_status_flags(irq, IRQ_LEVEL); |
| 126 | } else { |
| 127 | irq_set_chip_and_handler_name(irq, &intc_dev, |
| 128 | handle_level_irq, "level"); |
| 129 | irq_set_status_flags(irq, IRQ_LEVEL); |
| 130 | } |
| 131 | return 0; |
| 132 | } |
| 133 | |
| 134 | static const struct irq_domain_ops xintc_irq_domain_ops = { |
| 135 | .xlate = irq_domain_xlate_onetwocell, |
| 136 | .map = xintc_map, |
| 137 | }; |
| 138 | |
Michal Simek | 8a9e90a | 2013-08-27 10:49:00 +0200 | [diff] [blame] | 139 | static int __init xilinx_intc_of_init(struct device_node *intc, |
| 140 | struct device_node *parent) |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 141 | { |
Grant Likely | 2462bac | 2012-01-26 14:10:13 -0700 | [diff] [blame] | 142 | u32 nr_irq, intr_mask; |
Michal Simek | bcff661 | 2013-08-27 10:49:00 +0200 | [diff] [blame] | 143 | int ret; |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 144 | |
Michal Simek | bcff661 | 2013-08-27 10:49:00 +0200 | [diff] [blame] | 145 | intc_baseaddr = of_iomap(intc, 0); |
| 146 | BUG_ON(!intc_baseaddr); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 147 | |
Michal Simek | bcff661 | 2013-08-27 10:49:00 +0200 | [diff] [blame] | 148 | ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &nr_irq); |
| 149 | if (ret < 0) { |
| 150 | pr_err("%s: unable to read xlnx,num-intr-inputs\n", __func__); |
Soren Brinkmann | 2c80a07 | 2014-12-19 10:21:04 -0800 | [diff] [blame] | 151 | return ret; |
Michal Simek | bcff661 | 2013-08-27 10:49:00 +0200 | [diff] [blame] | 152 | } |
| 153 | |
| 154 | ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &intr_mask); |
| 155 | if (ret < 0) { |
| 156 | pr_err("%s: unable to read xlnx,kind-of-intr\n", __func__); |
Soren Brinkmann | 2c80a07 | 2014-12-19 10:21:04 -0800 | [diff] [blame] | 157 | return ret; |
Michal Simek | bcff661 | 2013-08-27 10:49:00 +0200 | [diff] [blame] | 158 | } |
| 159 | |
Soren Brinkmann | d50466c | 2014-12-19 10:21:05 -0800 | [diff] [blame] | 160 | if (intr_mask >> nr_irq) |
Soren Brinkmann | 231856a | 2014-12-19 10:21:06 -0800 | [diff] [blame^] | 161 | pr_warn("%s: mismatch in kind-of-intr param\n", __func__); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 162 | |
Michal Simek | bcff661 | 2013-08-27 10:49:00 +0200 | [diff] [blame] | 163 | pr_info("%s: num_irq=%d, edge=0x%x\n", |
| 164 | intc->full_name, nr_irq, intr_mask); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 165 | |
Michal Simek | 1aa1243 | 2014-02-24 14:56:32 +0100 | [diff] [blame] | 166 | write_fn = intc_write32; |
| 167 | read_fn = intc_read32; |
| 168 | |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 169 | /* |
| 170 | * Disable all external interrupts until they are |
| 171 | * explicity requested. |
| 172 | */ |
Michal Simek | 1aa1243 | 2014-02-24 14:56:32 +0100 | [diff] [blame] | 173 | write_fn(0, intc_baseaddr + IER); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 174 | |
| 175 | /* Acknowledge any pending interrupts just in case. */ |
Michal Simek | 1aa1243 | 2014-02-24 14:56:32 +0100 | [diff] [blame] | 176 | write_fn(0xffffffff, intc_baseaddr + IAR); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 177 | |
| 178 | /* Turn on the Master Enable. */ |
Michal Simek | 1aa1243 | 2014-02-24 14:56:32 +0100 | [diff] [blame] | 179 | write_fn(MER_HIE | MER_ME, intc_baseaddr + MER); |
| 180 | if (!(read_fn(intc_baseaddr + MER) & (MER_HIE | MER_ME))) { |
| 181 | write_fn = intc_write32_be; |
| 182 | read_fn = intc_read32_be; |
| 183 | write_fn(MER_HIE | MER_ME, intc_baseaddr + MER); |
| 184 | } |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 185 | |
Grant Likely | 2462bac | 2012-01-26 14:10:13 -0700 | [diff] [blame] | 186 | /* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm |
| 187 | * lazy and Michal can clean it up to something nicer when he tests |
| 188 | * and commits this patch. ~~gcl */ |
| 189 | root_domain = irq_domain_add_linear(intc, nr_irq, &xintc_irq_domain_ops, |
| 190 | (void *)intr_mask); |
Dan Christensen | 7c2c851 | 2013-03-17 04:48:56 -0500 | [diff] [blame] | 191 | |
| 192 | irq_set_default_host(root_domain); |
Michal Simek | 8a9e90a | 2013-08-27 10:49:00 +0200 | [diff] [blame] | 193 | |
| 194 | return 0; |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 195 | } |
Michal Simek | 8a9e90a | 2013-08-27 10:49:00 +0200 | [diff] [blame] | 196 | |
| 197 | IRQCHIP_DECLARE(xilinx_intc, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init); |