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Matt Porterc2dde5f2012-08-22 21:09:34 -04001/*
2 * TI EDMA DMA engine driver
3 *
4 * Copyright 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/dmaengine.h>
17#include <linux/dma-mapping.h>
Lad, Prabhakarb7a4fd52015-02-04 13:03:27 +000018#include <linux/edma.h>
Matt Porterc2dde5f2012-08-22 21:09:34 -040019#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/list.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/slab.h>
26#include <linux/spinlock.h>
Peter Ujfalusied646102014-07-31 13:12:38 +030027#include <linux/of.h>
Peter Ujfalusidc9b60552015-10-14 14:42:47 +030028#include <linux/of_dma.h>
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +030029#include <linux/of_irq.h>
30#include <linux/of_address.h>
31#include <linux/of_device.h>
32#include <linux/pm_runtime.h>
Matt Porterc2dde5f2012-08-22 21:09:34 -040033
Matt Porter3ad7a422013-03-06 11:15:31 -050034#include <linux/platform_data/edma.h>
Matt Porterc2dde5f2012-08-22 21:09:34 -040035
36#include "dmaengine.h"
37#include "virt-dma.h"
38
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +030039/* Offsets matching "struct edmacc_param" */
40#define PARM_OPT 0x00
41#define PARM_SRC 0x04
42#define PARM_A_B_CNT 0x08
43#define PARM_DST 0x0c
44#define PARM_SRC_DST_BIDX 0x10
45#define PARM_LINK_BCNTRLD 0x14
46#define PARM_SRC_DST_CIDX 0x18
47#define PARM_CCNT 0x1c
48
49#define PARM_SIZE 0x20
50
51/* Offsets for EDMA CC global channel registers and their shadows */
52#define SH_ER 0x00 /* 64 bits */
53#define SH_ECR 0x08 /* 64 bits */
54#define SH_ESR 0x10 /* 64 bits */
55#define SH_CER 0x18 /* 64 bits */
56#define SH_EER 0x20 /* 64 bits */
57#define SH_EECR 0x28 /* 64 bits */
58#define SH_EESR 0x30 /* 64 bits */
59#define SH_SER 0x38 /* 64 bits */
60#define SH_SECR 0x40 /* 64 bits */
61#define SH_IER 0x50 /* 64 bits */
62#define SH_IECR 0x58 /* 64 bits */
63#define SH_IESR 0x60 /* 64 bits */
64#define SH_IPR 0x68 /* 64 bits */
65#define SH_ICR 0x70 /* 64 bits */
66#define SH_IEVAL 0x78
67#define SH_QER 0x80
68#define SH_QEER 0x84
69#define SH_QEECR 0x88
70#define SH_QEESR 0x8c
71#define SH_QSER 0x90
72#define SH_QSECR 0x94
73#define SH_SIZE 0x200
74
75/* Offsets for EDMA CC global registers */
76#define EDMA_REV 0x0000
77#define EDMA_CCCFG 0x0004
78#define EDMA_QCHMAP 0x0200 /* 8 registers */
79#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
80#define EDMA_QDMAQNUM 0x0260
81#define EDMA_QUETCMAP 0x0280
82#define EDMA_QUEPRI 0x0284
83#define EDMA_EMR 0x0300 /* 64 bits */
84#define EDMA_EMCR 0x0308 /* 64 bits */
85#define EDMA_QEMR 0x0310
86#define EDMA_QEMCR 0x0314
87#define EDMA_CCERR 0x0318
88#define EDMA_CCERRCLR 0x031c
89#define EDMA_EEVAL 0x0320
90#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
91#define EDMA_QRAE 0x0380 /* 4 registers */
92#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
93#define EDMA_QSTAT 0x0600 /* 2 registers */
94#define EDMA_QWMTHRA 0x0620
95#define EDMA_QWMTHRB 0x0624
96#define EDMA_CCSTAT 0x0640
97
98#define EDMA_M 0x1000 /* global channel registers */
99#define EDMA_ECR 0x1008
100#define EDMA_ECRH 0x100C
101#define EDMA_SHADOW0 0x2000 /* 4 shadow regions */
102#define EDMA_PARM 0x4000 /* PaRAM entries */
103
104#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
105
106#define EDMA_DCHMAP 0x0100 /* 64 registers */
107
108/* CCCFG register */
109#define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
Peter Ujfalusi633e42b2015-10-16 10:18:04 +0300110#define GET_NUM_QDMACH(x) (x & 0x70 >> 4) /* bits 4-6 */
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300111#define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
112#define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
113#define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
114#define CHMAP_EXIST BIT(24)
115
Matt Porterc2dde5f2012-08-22 21:09:34 -0400116/*
Joel Fernandes2abd5f12013-09-23 18:05:15 -0500117 * Max of 20 segments per channel to conserve PaRAM slots
118 * Also note that MAX_NR_SG should be atleast the no.of periods
119 * that are required for ASoC, otherwise DMA prep calls will
120 * fail. Today davinci-pcm is the only user of this driver and
121 * requires atleast 17 slots, so we setup the default to 20.
122 */
123#define MAX_NR_SG 20
Matt Porterc2dde5f2012-08-22 21:09:34 -0400124#define EDMA_MAX_SLOTS MAX_NR_SG
125#define EDMA_DESCRIPTORS 16
126
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300127#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
128#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
129#define EDMA_CONT_PARAMS_ANY 1001
130#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
131#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
132
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300133/* PaRAM slots are laid out like this */
134struct edmacc_param {
135 u32 opt;
136 u32 src;
137 u32 a_b_cnt;
138 u32 dst;
139 u32 src_dst_bidx;
140 u32 link_bcntrld;
141 u32 src_dst_cidx;
142 u32 ccnt;
143} __packed;
144
145/* fields in edmacc_param.opt */
146#define SAM BIT(0)
147#define DAM BIT(1)
148#define SYNCDIM BIT(2)
149#define STATIC BIT(3)
150#define EDMA_FWID (0x07 << 8)
151#define TCCMODE BIT(11)
152#define EDMA_TCC(t) ((t) << 12)
153#define TCINTEN BIT(20)
154#define ITCINTEN BIT(21)
155#define TCCHEN BIT(22)
156#define ITCCHEN BIT(23)
157
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500158struct edma_pset {
Thomas Gleixnerc2da2342014-04-28 14:29:57 -0500159 u32 len;
160 dma_addr_t addr;
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500161 struct edmacc_param param;
162};
163
Matt Porterc2dde5f2012-08-22 21:09:34 -0400164struct edma_desc {
165 struct virt_dma_desc vdesc;
166 struct list_head node;
Thomas Gleixnerc2da2342014-04-28 14:29:57 -0500167 enum dma_transfer_direction direction;
Joel Fernandes50a9c702013-10-31 16:31:23 -0500168 int cyclic;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400169 int absync;
170 int pset_nr;
Thomas Gleixner740b41f2014-04-28 14:34:11 -0500171 struct edma_chan *echan;
Joel Fernandes04361d82014-04-28 15:19:31 -0500172 int processed;
173
174 /*
175 * The following 4 elements are used for residue accounting.
176 *
177 * - processed_stat: the number of SG elements we have traversed
178 * so far to cover accounting. This is updated directly to processed
179 * during edma_callback and is always <= processed, because processed
180 * refers to the number of pending transfer (programmed to EDMA
181 * controller), where as processed_stat tracks number of transfers
182 * accounted for so far.
183 *
184 * - residue: The amount of bytes we have left to transfer for this desc
185 *
186 * - residue_stat: The residue in bytes of data we have covered
187 * so far for accounting. This is updated directly to residue
188 * during callbacks to keep it current.
189 *
190 * - sg_len: Tracks the length of the current intermediate transfer,
191 * this is required to update the residue during intermediate transfer
192 * completion callback.
193 */
194 int processed_stat;
195 u32 sg_len;
196 u32 residue;
197 u32 residue_stat;
198
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500199 struct edma_pset pset[0];
Matt Porterc2dde5f2012-08-22 21:09:34 -0400200};
201
202struct edma_cc;
203
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300204struct edma_tc {
205 struct device_node *node;
206 u16 id;
207};
208
Matt Porterc2dde5f2012-08-22 21:09:34 -0400209struct edma_chan {
210 struct virt_dma_chan vchan;
211 struct list_head node;
212 struct edma_desc *edesc;
213 struct edma_cc *ecc;
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300214 struct edma_tc *tc;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400215 int ch_num;
216 bool alloced;
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300217 bool hw_triggered;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400218 int slot[EDMA_MAX_SLOTS];
Joel Fernandesc5f47992013-08-29 18:05:43 -0500219 int missed;
Matt Porter661f7cb2013-01-10 13:41:04 -0500220 struct dma_slave_config cfg;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400221};
222
223struct edma_cc {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300224 struct device *dev;
225 struct edma_soc_info *info;
226 void __iomem *base;
227 int id;
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300228 bool legacy_mode;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300229
230 /* eDMA3 resource information */
231 unsigned num_channels;
Peter Ujfalusi633e42b2015-10-16 10:18:04 +0300232 unsigned num_qchannels;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300233 unsigned num_region;
234 unsigned num_slots;
235 unsigned num_tc;
Peter Ujfalusi4ab54f62015-10-14 14:43:04 +0300236 bool chmap_exist;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300237 enum dma_event_q default_queue;
238
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300239 /*
240 * The slot_inuse bit for each PaRAM slot is clear unless the slot is
241 * in use by Linux or if it is allocated to be used by DSP.
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300242 */
Peter Ujfalusi7a73b132015-10-14 14:43:05 +0300243 unsigned long *slot_inuse;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300244
Matt Porterc2dde5f2012-08-22 21:09:34 -0400245 struct dma_device dma_slave;
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300246 struct dma_device *dma_memcpy;
Peter Ujfalusicb782052015-10-14 14:42:54 +0300247 struct edma_chan *slave_chans;
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300248 struct edma_tc *tc_list;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400249 int dummy_slot;
250};
251
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300252/* dummy param set used to (re)initialize parameter RAM slots */
253static const struct edmacc_param dummy_paramset = {
254 .link_bcntrld = 0xffff,
255 .ccnt = 1,
256};
257
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300258#define EDMA_BINDING_LEGACY 0
259#define EDMA_BINDING_TPCC 1
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300260static const struct of_device_id edma_of_ids[] = {
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300261 {
262 .compatible = "ti,edma3",
263 .data = (void *)EDMA_BINDING_LEGACY,
264 },
265 {
266 .compatible = "ti,edma3-tpcc",
267 .data = (void *)EDMA_BINDING_TPCC,
268 },
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300269 {}
270};
271
Peter Ujfalusi34635b1a2015-11-02 15:21:40 +0200272static const struct of_device_id edma_tptc_of_ids[] = {
273 { .compatible = "ti,edma3-tptc", },
274 {}
275};
276
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300277static inline unsigned int edma_read(struct edma_cc *ecc, int offset)
278{
279 return (unsigned int)__raw_readl(ecc->base + offset);
280}
281
282static inline void edma_write(struct edma_cc *ecc, int offset, int val)
283{
284 __raw_writel(val, ecc->base + offset);
285}
286
287static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and,
288 unsigned or)
289{
290 unsigned val = edma_read(ecc, offset);
291
292 val &= and;
293 val |= or;
294 edma_write(ecc, offset, val);
295}
296
297static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and)
298{
299 unsigned val = edma_read(ecc, offset);
300
301 val &= and;
302 edma_write(ecc, offset, val);
303}
304
305static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or)
306{
307 unsigned val = edma_read(ecc, offset);
308
309 val |= or;
310 edma_write(ecc, offset, val);
311}
312
313static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset,
314 int i)
315{
316 return edma_read(ecc, offset + (i << 2));
317}
318
319static inline void edma_write_array(struct edma_cc *ecc, int offset, int i,
320 unsigned val)
321{
322 edma_write(ecc, offset + (i << 2), val);
323}
324
325static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i,
326 unsigned and, unsigned or)
327{
328 edma_modify(ecc, offset + (i << 2), and, or);
329}
330
331static inline void edma_or_array(struct edma_cc *ecc, int offset, int i,
332 unsigned or)
333{
334 edma_or(ecc, offset + (i << 2), or);
335}
336
337static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j,
338 unsigned or)
339{
340 edma_or(ecc, offset + ((i * 2 + j) << 2), or);
341}
342
343static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i,
344 int j, unsigned val)
345{
346 edma_write(ecc, offset + ((i * 2 + j) << 2), val);
347}
348
349static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset)
350{
351 return edma_read(ecc, EDMA_SHADOW0 + offset);
352}
353
354static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc,
355 int offset, int i)
356{
357 return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2));
358}
359
360static inline void edma_shadow0_write(struct edma_cc *ecc, int offset,
361 unsigned val)
362{
363 edma_write(ecc, EDMA_SHADOW0 + offset, val);
364}
365
366static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset,
367 int i, unsigned val)
368{
369 edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val);
370}
371
Peter Ujfalusid9c345d2015-10-16 10:18:02 +0300372static inline unsigned int edma_param_read(struct edma_cc *ecc, int offset,
373 int param_no)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300374{
375 return edma_read(ecc, EDMA_PARM + offset + (param_no << 5));
376}
377
Peter Ujfalusid9c345d2015-10-16 10:18:02 +0300378static inline void edma_param_write(struct edma_cc *ecc, int offset,
379 int param_no, unsigned val)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300380{
381 edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val);
382}
383
Peter Ujfalusid9c345d2015-10-16 10:18:02 +0300384static inline void edma_param_modify(struct edma_cc *ecc, int offset,
385 int param_no, unsigned and, unsigned or)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300386{
387 edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or);
388}
389
Peter Ujfalusid9c345d2015-10-16 10:18:02 +0300390static inline void edma_param_and(struct edma_cc *ecc, int offset, int param_no,
391 unsigned and)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300392{
393 edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and);
394}
395
Peter Ujfalusid9c345d2015-10-16 10:18:02 +0300396static inline void edma_param_or(struct edma_cc *ecc, int offset, int param_no,
397 unsigned or)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300398{
399 edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or);
400}
401
402static inline void set_bits(int offset, int len, unsigned long *p)
403{
404 for (; len > 0; len--)
405 set_bit(offset + (len - 1), p);
406}
407
408static inline void clear_bits(int offset, int len, unsigned long *p)
409{
410 for (; len > 0; len--)
411 clear_bit(offset + (len - 1), p);
412}
413
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300414static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no,
415 int priority)
416{
417 int bit = queue_no * 4;
418
419 edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
420}
421
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300422static void edma_set_chmap(struct edma_chan *echan, int slot)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300423{
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300424 struct edma_cc *ecc = echan->ecc;
425 int channel = EDMA_CHAN_SLOT(echan->ch_num);
426
Peter Ujfalusie4e886c2015-10-14 14:43:06 +0300427 if (ecc->chmap_exist) {
Peter Ujfalusie4e886c2015-10-14 14:43:06 +0300428 slot = EDMA_CHAN_SLOT(slot);
429 edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5));
430 }
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300431}
432
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300433static void edma_setup_interrupt(struct edma_chan *echan, bool enable)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300434{
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300435 struct edma_cc *ecc = echan->ecc;
436 int channel = EDMA_CHAN_SLOT(echan->ch_num);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300437
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +0300438 if (enable) {
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300439 edma_shadow0_write_array(ecc, SH_ICR, channel >> 5,
440 BIT(channel & 0x1f));
441 edma_shadow0_write_array(ecc, SH_IESR, channel >> 5,
442 BIT(channel & 0x1f));
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +0300443 } else {
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300444 edma_shadow0_write_array(ecc, SH_IECR, channel >> 5,
445 BIT(channel & 0x1f));
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300446 }
447}
448
449/*
Peter Ujfalusi11c15732015-10-14 14:43:00 +0300450 * paRAM slot management functions
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300451 */
452static void edma_write_slot(struct edma_cc *ecc, unsigned slot,
453 const struct edmacc_param *param)
454{
455 slot = EDMA_CHAN_SLOT(slot);
456 if (slot >= ecc->num_slots)
457 return;
458 memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE);
459}
460
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300461static void edma_read_slot(struct edma_cc *ecc, unsigned slot,
462 struct edmacc_param *param)
463{
464 slot = EDMA_CHAN_SLOT(slot);
465 if (slot >= ecc->num_slots)
466 return;
467 memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE);
468}
469
470/**
471 * edma_alloc_slot - allocate DMA parameter RAM
472 * @ecc: pointer to edma_cc struct
473 * @slot: specific slot to allocate; negative for "any unused slot"
474 *
475 * This allocates a parameter RAM slot, initializing it to hold a
476 * dummy transfer. Slots allocated using this routine have not been
477 * mapped to a hardware DMA channel, and will normally be used by
478 * linking to them from a slot associated with a DMA channel.
479 *
480 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
481 * slots may be allocated on behalf of DSP firmware.
482 *
483 * Returns the number of the slot, else negative errno.
484 */
485static int edma_alloc_slot(struct edma_cc *ecc, int slot)
486{
Peter Ujfalusie4e886c2015-10-14 14:43:06 +0300487 if (slot > 0) {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300488 slot = EDMA_CHAN_SLOT(slot);
Peter Ujfalusie4e886c2015-10-14 14:43:06 +0300489 /* Requesting entry paRAM slot for a HW triggered channel. */
490 if (ecc->chmap_exist && slot < ecc->num_channels)
491 slot = EDMA_SLOT_ANY;
492 }
493
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300494 if (slot < 0) {
Peter Ujfalusie4e886c2015-10-14 14:43:06 +0300495 if (ecc->chmap_exist)
496 slot = 0;
497 else
498 slot = ecc->num_channels;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300499 for (;;) {
Peter Ujfalusi7a73b132015-10-14 14:43:05 +0300500 slot = find_next_zero_bit(ecc->slot_inuse,
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300501 ecc->num_slots,
502 slot);
503 if (slot == ecc->num_slots)
504 return -ENOMEM;
Peter Ujfalusi7a73b132015-10-14 14:43:05 +0300505 if (!test_and_set_bit(slot, ecc->slot_inuse))
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300506 break;
507 }
Peter Ujfalusie4e886c2015-10-14 14:43:06 +0300508 } else if (slot >= ecc->num_slots) {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300509 return -EINVAL;
Peter Ujfalusi7a73b132015-10-14 14:43:05 +0300510 } else if (test_and_set_bit(slot, ecc->slot_inuse)) {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300511 return -EBUSY;
512 }
513
514 edma_write_slot(ecc, slot, &dummy_paramset);
515
516 return EDMA_CTLR_CHAN(ecc->id, slot);
517}
518
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300519static void edma_free_slot(struct edma_cc *ecc, unsigned slot)
520{
521 slot = EDMA_CHAN_SLOT(slot);
Peter Ujfalusie4e886c2015-10-14 14:43:06 +0300522 if (slot >= ecc->num_slots)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300523 return;
524
525 edma_write_slot(ecc, slot, &dummy_paramset);
Peter Ujfalusi7a73b132015-10-14 14:43:05 +0300526 clear_bit(slot, ecc->slot_inuse);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300527}
528
529/**
530 * edma_link - link one parameter RAM slot to another
531 * @ecc: pointer to edma_cc struct
532 * @from: parameter RAM slot originating the link
533 * @to: parameter RAM slot which is the link target
534 *
535 * The originating slot should not be part of any active DMA transfer.
536 */
537static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to)
538{
Peter Ujfalusifc014092015-10-14 14:42:59 +0300539 if (unlikely(EDMA_CTLR(from) != EDMA_CTLR(to)))
540 dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n");
541
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300542 from = EDMA_CHAN_SLOT(from);
543 to = EDMA_CHAN_SLOT(to);
544 if (from >= ecc->num_slots || to >= ecc->num_slots)
545 return;
546
Peter Ujfalusid9c345d2015-10-16 10:18:02 +0300547 edma_param_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000,
548 PARM_OFFSET(to));
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300549}
550
551/**
552 * edma_get_position - returns the current transfer point
553 * @ecc: pointer to edma_cc struct
554 * @slot: parameter RAM slot being examined
555 * @dst: true selects the dest position, false the source
556 *
557 * Returns the position of the current active slot
558 */
559static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot,
560 bool dst)
561{
562 u32 offs;
563
564 slot = EDMA_CHAN_SLOT(slot);
565 offs = PARM_OFFSET(slot);
566 offs += dst ? PARM_DST : PARM_SRC;
567
568 return edma_read(ecc, offs);
569}
570
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300571/*
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300572 * Channels with event associations will be triggered by their hardware
573 * events, and channels without such associations will be triggered by
574 * software. (At this writing there is no interface for using software
575 * triggers except with channels that don't support hardware triggers.)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300576 */
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300577static void edma_start(struct edma_chan *echan)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300578{
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300579 struct edma_cc *ecc = echan->ecc;
580 int channel = EDMA_CHAN_SLOT(echan->ch_num);
581 int j = (channel >> 5);
582 unsigned int mask = BIT(channel & 0x1f);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300583
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300584 if (!echan->hw_triggered) {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300585 /* EDMA channels without event association */
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300586 dev_dbg(ecc->dev, "ESR%d %08x\n", j,
587 edma_shadow0_read_array(ecc, SH_ESR, j));
588 edma_shadow0_write_array(ecc, SH_ESR, j, mask);
589 } else {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300590 /* EDMA channel with event association */
Peter Ujfalusi3287fb42015-10-14 14:42:57 +0300591 dev_dbg(ecc->dev, "ER%d %08x\n", j,
592 edma_shadow0_read_array(ecc, SH_ER, j));
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300593 /* Clear any pending event or error */
594 edma_write_array(ecc, EDMA_ECR, j, mask);
595 edma_write_array(ecc, EDMA_EMCR, j, mask);
596 /* Clear any SER */
597 edma_shadow0_write_array(ecc, SH_SECR, j, mask);
598 edma_shadow0_write_array(ecc, SH_EESR, j, mask);
Peter Ujfalusi3287fb42015-10-14 14:42:57 +0300599 dev_dbg(ecc->dev, "EER%d %08x\n", j,
600 edma_shadow0_read_array(ecc, SH_EER, j));
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300601 }
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300602}
603
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300604static void edma_stop(struct edma_chan *echan)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300605{
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300606 struct edma_cc *ecc = echan->ecc;
607 int channel = EDMA_CHAN_SLOT(echan->ch_num);
608 int j = (channel >> 5);
609 unsigned int mask = BIT(channel & 0x1f);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300610
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300611 edma_shadow0_write_array(ecc, SH_EECR, j, mask);
612 edma_shadow0_write_array(ecc, SH_ECR, j, mask);
613 edma_shadow0_write_array(ecc, SH_SECR, j, mask);
614 edma_write_array(ecc, EDMA_EMCR, j, mask);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300615
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300616 /* clear possibly pending completion interrupt */
617 edma_shadow0_write_array(ecc, SH_ICR, j, mask);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300618
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300619 dev_dbg(ecc->dev, "EER%d %08x\n", j,
620 edma_shadow0_read_array(ecc, SH_EER, j));
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300621
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300622 /* REVISIT: consider guarding against inappropriate event
623 * chaining by overwriting with dummy_paramset.
624 */
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300625}
626
Peter Ujfalusi11c15732015-10-14 14:43:00 +0300627/*
628 * Temporarily disable EDMA hardware events on the specified channel,
629 * preventing them from triggering new transfers
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300630 */
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300631static void edma_pause(struct edma_chan *echan)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300632{
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300633 int channel = EDMA_CHAN_SLOT(echan->ch_num);
634 unsigned int mask = BIT(channel & 0x1f);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300635
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300636 edma_shadow0_write_array(echan->ecc, SH_EECR, channel >> 5, mask);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300637}
638
Peter Ujfalusi11c15732015-10-14 14:43:00 +0300639/* Re-enable EDMA hardware events on the specified channel. */
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300640static void edma_resume(struct edma_chan *echan)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300641{
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300642 int channel = EDMA_CHAN_SLOT(echan->ch_num);
643 unsigned int mask = BIT(channel & 0x1f);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300644
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300645 edma_shadow0_write_array(echan->ecc, SH_EESR, channel >> 5, mask);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300646}
647
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300648static void edma_trigger_channel(struct edma_chan *echan)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300649{
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300650 struct edma_cc *ecc = echan->ecc;
651 int channel = EDMA_CHAN_SLOT(echan->ch_num);
652 unsigned int mask = BIT(channel & 0x1f);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300653
654 edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask);
655
Peter Ujfalusi3287fb42015-10-14 14:42:57 +0300656 dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5),
657 edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5)));
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300658}
659
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300660static void edma_clean_channel(struct edma_chan *echan)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300661{
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300662 struct edma_cc *ecc = echan->ecc;
663 int channel = EDMA_CHAN_SLOT(echan->ch_num);
664 int j = (channel >> 5);
665 unsigned int mask = BIT(channel & 0x1f);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300666
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300667 dev_dbg(ecc->dev, "EMR%d %08x\n", j, edma_read_array(ecc, EDMA_EMR, j));
668 edma_shadow0_write_array(ecc, SH_ECR, j, mask);
669 /* Clear the corresponding EMR bits */
670 edma_write_array(ecc, EDMA_EMCR, j, mask);
671 /* Clear any SER */
672 edma_shadow0_write_array(ecc, SH_SECR, j, mask);
673 edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300674}
675
Peter Ujfalusif9425de2015-10-16 10:18:03 +0300676/* Move channel to a specific event queue */
677static void edma_assign_channel_eventq(struct edma_chan *echan,
678 enum dma_event_q eventq_no)
679{
680 struct edma_cc *ecc = echan->ecc;
681 int channel = EDMA_CHAN_SLOT(echan->ch_num);
682 int bit = (channel & 0x7) * 4;
683
684 /* default to low priority queue */
685 if (eventq_no == EVENTQ_DEFAULT)
686 eventq_no = ecc->default_queue;
687 if (eventq_no >= ecc->num_tc)
688 return;
689
690 eventq_no &= 7;
691 edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit),
692 eventq_no << bit);
693}
694
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300695static int edma_alloc_channel(struct edma_chan *echan,
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +0300696 enum dma_event_q eventq_no)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300697{
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300698 struct edma_cc *ecc = echan->ecc;
699 int channel = EDMA_CHAN_SLOT(echan->ch_num);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300700
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300701 /* ensure access through shadow region 0 */
702 edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
703
704 /* ensure no events are pending */
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300705 edma_stop(echan);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300706
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300707 edma_setup_interrupt(echan, true);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300708
Peter Ujfalusif9425de2015-10-16 10:18:03 +0300709 edma_assign_channel_eventq(echan, eventq_no);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300710
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300711 return 0;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300712}
713
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300714static void edma_free_channel(struct edma_chan *echan)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300715{
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300716 /* ensure no events are pending */
717 edma_stop(echan);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300718 /* REVISIT should probably take out of shadow region 0 */
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300719 edma_setup_interrupt(echan, false);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300720}
721
Matt Porterc2dde5f2012-08-22 21:09:34 -0400722static inline struct edma_cc *to_edma_cc(struct dma_device *d)
723{
724 return container_of(d, struct edma_cc, dma_slave);
725}
726
727static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
728{
729 return container_of(c, struct edma_chan, vchan.chan);
730}
731
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300732static inline struct edma_desc *to_edma_desc(struct dma_async_tx_descriptor *tx)
Matt Porterc2dde5f2012-08-22 21:09:34 -0400733{
734 return container_of(tx, struct edma_desc, vdesc.tx);
735}
736
737static void edma_desc_free(struct virt_dma_desc *vdesc)
738{
739 kfree(container_of(vdesc, struct edma_desc, vdesc));
740}
741
742/* Dispatch a queued descriptor to the controller (caller holds lock) */
743static void edma_execute(struct edma_chan *echan)
744{
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300745 struct edma_cc *ecc = echan->ecc;
Joel Fernandes53407062013-09-03 10:02:46 -0500746 struct virt_dma_desc *vdesc;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400747 struct edma_desc *edesc;
Joel Fernandes53407062013-09-03 10:02:46 -0500748 struct device *dev = echan->vchan.chan.device->dev;
749 int i, j, left, nslots;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400750
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +0300751 if (!echan->edesc) {
752 /* Setup is needed for the first transfer */
Joel Fernandes53407062013-09-03 10:02:46 -0500753 vdesc = vchan_next_desc(&echan->vchan);
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +0300754 if (!vdesc)
Joel Fernandes53407062013-09-03 10:02:46 -0500755 return;
Joel Fernandes53407062013-09-03 10:02:46 -0500756 list_del(&vdesc->node);
757 echan->edesc = to_edma_desc(&vdesc->tx);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400758 }
759
Joel Fernandes53407062013-09-03 10:02:46 -0500760 edesc = echan->edesc;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400761
Joel Fernandes53407062013-09-03 10:02:46 -0500762 /* Find out how many left */
763 left = edesc->pset_nr - edesc->processed;
764 nslots = min(MAX_NR_SG, left);
Thomas Gleixner740b41f2014-04-28 14:34:11 -0500765 edesc->sg_len = 0;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400766
767 /* Write descriptor PaRAM set(s) */
Joel Fernandes53407062013-09-03 10:02:46 -0500768 for (i = 0; i < nslots; i++) {
769 j = i + edesc->processed;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300770 edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param);
Thomas Gleixner740b41f2014-04-28 14:34:11 -0500771 edesc->sg_len += edesc->pset[j].len;
Peter Ujfalusi907f74a2015-10-14 14:42:56 +0300772 dev_vdbg(dev,
773 "\n pset[%d]:\n"
774 " chnum\t%d\n"
775 " slot\t%d\n"
776 " opt\t%08x\n"
777 " src\t%08x\n"
778 " dst\t%08x\n"
779 " abcnt\t%08x\n"
780 " ccnt\t%08x\n"
781 " bidx\t%08x\n"
782 " cidx\t%08x\n"
783 " lkrld\t%08x\n",
784 j, echan->ch_num, echan->slot[i],
785 edesc->pset[j].param.opt,
786 edesc->pset[j].param.src,
787 edesc->pset[j].param.dst,
788 edesc->pset[j].param.a_b_cnt,
789 edesc->pset[j].param.ccnt,
790 edesc->pset[j].param.src_dst_bidx,
791 edesc->pset[j].param.src_dst_cidx,
792 edesc->pset[j].param.link_bcntrld);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400793 /* Link to the previous slot if not the last set */
Joel Fernandes53407062013-09-03 10:02:46 -0500794 if (i != (nslots - 1))
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300795 edma_link(ecc, echan->slot[i], echan->slot[i + 1]);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400796 }
797
Joel Fernandes53407062013-09-03 10:02:46 -0500798 edesc->processed += nslots;
799
Joel Fernandesb267b3b2013-08-29 18:05:44 -0500800 /*
801 * If this is either the last set in a set of SG-list transactions
802 * then setup a link to the dummy slot, this results in all future
803 * events being absorbed and that's OK because we're done
804 */
Joel Fernandes50a9c702013-10-31 16:31:23 -0500805 if (edesc->processed == edesc->pset_nr) {
806 if (edesc->cyclic)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300807 edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500808 else
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300809 edma_link(ecc, echan->slot[nslots - 1],
Joel Fernandes50a9c702013-10-31 16:31:23 -0500810 echan->ecc->dummy_slot);
811 }
Joel Fernandesb267b3b2013-08-29 18:05:44 -0500812
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +0300813 if (echan->missed) {
814 /*
815 * This happens due to setup times between intermediate
816 * transfers in long SG lists which have to be broken up into
817 * transfers of MAX_NR_SG
818 */
819 dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300820 edma_clean_channel(echan);
821 edma_stop(echan);
822 edma_start(echan);
823 edma_trigger_channel(echan);
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +0300824 echan->missed = 0;
825 } else if (edesc->processed <= MAX_NR_SG) {
Peter Ujfalusi9aac9092014-04-24 10:29:50 +0300826 dev_dbg(dev, "first transfer starting on channel %d\n",
827 echan->ch_num);
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300828 edma_start(echan);
Sekhar Nori5fc68a62014-03-19 11:25:50 +0530829 } else {
830 dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
831 echan->ch_num, edesc->processed);
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300832 edma_resume(echan);
Joel Fernandes53407062013-09-03 10:02:46 -0500833 }
Matt Porterc2dde5f2012-08-22 21:09:34 -0400834}
835
Maxime Ripardaa7c09b2014-11-17 14:42:13 +0100836static int edma_terminate_all(struct dma_chan *chan)
Matt Porterc2dde5f2012-08-22 21:09:34 -0400837{
Maxime Ripardaa7c09b2014-11-17 14:42:13 +0100838 struct edma_chan *echan = to_edma_chan(chan);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400839 unsigned long flags;
840 LIST_HEAD(head);
841
842 spin_lock_irqsave(&echan->vchan.lock, flags);
843
844 /*
845 * Stop DMA activity: we assume the callback will not be called
846 * after edma_dma() returns (even if it does, it will see
847 * echan->edesc is NULL and exit.)
848 */
849 if (echan->edesc) {
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300850 edma_stop(echan);
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +0300851 /* Move the cyclic channel back to default queue */
Peter Ujfalusi1be53362015-10-16 10:18:10 +0300852 if (!echan->tc && echan->edesc->cyclic)
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300853 edma_assign_channel_eventq(echan, EVENTQ_DEFAULT);
Petr Kulhavy5ca9e7c2015-03-27 13:35:51 +0200854 /*
855 * free the running request descriptor
856 * since it is not in any of the vdesc lists
857 */
858 edma_desc_free(&echan->edesc->vdesc);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400859 echan->edesc = NULL;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400860 }
861
862 vchan_get_all_descriptors(&echan->vchan, &head);
863 spin_unlock_irqrestore(&echan->vchan.lock, flags);
864 vchan_dma_desc_free_list(&echan->vchan, &head);
865
866 return 0;
867}
868
Maxime Ripardaa7c09b2014-11-17 14:42:13 +0100869static int edma_slave_config(struct dma_chan *chan,
Matt Porter661f7cb2013-01-10 13:41:04 -0500870 struct dma_slave_config *cfg)
Matt Porterc2dde5f2012-08-22 21:09:34 -0400871{
Maxime Ripardaa7c09b2014-11-17 14:42:13 +0100872 struct edma_chan *echan = to_edma_chan(chan);
873
Matt Porter661f7cb2013-01-10 13:41:04 -0500874 if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
875 cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
Matt Porterc2dde5f2012-08-22 21:09:34 -0400876 return -EINVAL;
877
Matt Porter661f7cb2013-01-10 13:41:04 -0500878 memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
Matt Porterc2dde5f2012-08-22 21:09:34 -0400879
880 return 0;
881}
882
Maxime Ripardaa7c09b2014-11-17 14:42:13 +0100883static int edma_dma_pause(struct dma_chan *chan)
Peter Ujfalusi72c7b672014-04-14 14:41:59 +0300884{
Maxime Ripardaa7c09b2014-11-17 14:42:13 +0100885 struct edma_chan *echan = to_edma_chan(chan);
886
John Ogness02ec6042015-04-27 13:52:25 +0200887 if (!echan->edesc)
Peter Ujfalusi72c7b672014-04-14 14:41:59 +0300888 return -EINVAL;
889
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300890 edma_pause(echan);
Peter Ujfalusi72c7b672014-04-14 14:41:59 +0300891 return 0;
892}
893
Maxime Ripardaa7c09b2014-11-17 14:42:13 +0100894static int edma_dma_resume(struct dma_chan *chan)
Peter Ujfalusi72c7b672014-04-14 14:41:59 +0300895{
Maxime Ripardaa7c09b2014-11-17 14:42:13 +0100896 struct edma_chan *echan = to_edma_chan(chan);
897
Peter Ujfalusi34cf3012015-10-16 10:18:01 +0300898 edma_resume(echan);
Peter Ujfalusi72c7b672014-04-14 14:41:59 +0300899 return 0;
900}
901
Joel Fernandesfd009032013-09-23 18:05:13 -0500902/*
903 * A PaRAM set configuration abstraction used by other modes
904 * @chan: Channel who's PaRAM set we're configuring
905 * @pset: PaRAM set to initialize and setup.
906 * @src_addr: Source address of the DMA
907 * @dst_addr: Destination address of the DMA
908 * @burst: In units of dev_width, how much to send
909 * @dev_width: How much is the dev_width
910 * @dma_length: Total length of the DMA transfer
911 * @direction: Direction of the transfer
912 */
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500913static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset,
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300914 dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
Peter Ujfalusidf6694f2015-10-16 10:18:00 +0300915 unsigned int acnt, unsigned int dma_length,
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300916 enum dma_transfer_direction direction)
Joel Fernandesfd009032013-09-23 18:05:13 -0500917{
918 struct edma_chan *echan = to_edma_chan(chan);
919 struct device *dev = chan->device->dev;
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500920 struct edmacc_param *param = &epset->param;
Peter Ujfalusidf6694f2015-10-16 10:18:00 +0300921 int bcnt, ccnt, cidx;
Joel Fernandesfd009032013-09-23 18:05:13 -0500922 int src_bidx, dst_bidx, src_cidx, dst_cidx;
923 int absync;
924
Peter Ujfalusib2b617d2014-04-14 14:41:58 +0300925 /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */
926 if (!burst)
927 burst = 1;
Joel Fernandesfd009032013-09-23 18:05:13 -0500928 /*
929 * If the maxburst is equal to the fifo width, use
930 * A-synced transfers. This allows for large contiguous
931 * buffer transfers using only one PaRAM set.
932 */
933 if (burst == 1) {
934 /*
935 * For the A-sync case, bcnt and ccnt are the remainder
936 * and quotient respectively of the division of:
937 * (dma_length / acnt) by (SZ_64K -1). This is so
938 * that in case bcnt over flows, we have ccnt to use.
939 * Note: In A-sync tranfer only, bcntrld is used, but it
940 * only applies for sg_dma_len(sg) >= SZ_64K.
941 * In this case, the best way adopted is- bccnt for the
942 * first frame will be the remainder below. Then for
943 * every successive frame, bcnt will be SZ_64K-1. This
944 * is assured as bcntrld = 0xffff in end of function.
945 */
946 absync = false;
947 ccnt = dma_length / acnt / (SZ_64K - 1);
948 bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
949 /*
950 * If bcnt is non-zero, we have a remainder and hence an
951 * extra frame to transfer, so increment ccnt.
952 */
953 if (bcnt)
954 ccnt++;
955 else
956 bcnt = SZ_64K - 1;
957 cidx = acnt;
958 } else {
959 /*
960 * If maxburst is greater than the fifo address_width,
961 * use AB-synced transfers where A count is the fifo
962 * address_width and B count is the maxburst. In this
963 * case, we are limited to transfers of C count frames
964 * of (address_width * maxburst) where C count is limited
965 * to SZ_64K-1. This places an upper bound on the length
966 * of an SG segment that can be handled.
967 */
968 absync = true;
969 bcnt = burst;
970 ccnt = dma_length / (acnt * bcnt);
971 if (ccnt > (SZ_64K - 1)) {
972 dev_err(dev, "Exceeded max SG segment size\n");
973 return -EINVAL;
974 }
975 cidx = acnt * bcnt;
976 }
977
Thomas Gleixnerc2da2342014-04-28 14:29:57 -0500978 epset->len = dma_length;
979
Joel Fernandesfd009032013-09-23 18:05:13 -0500980 if (direction == DMA_MEM_TO_DEV) {
981 src_bidx = acnt;
982 src_cidx = cidx;
983 dst_bidx = 0;
984 dst_cidx = 0;
Thomas Gleixnerc2da2342014-04-28 14:29:57 -0500985 epset->addr = src_addr;
Joel Fernandesfd009032013-09-23 18:05:13 -0500986 } else if (direction == DMA_DEV_TO_MEM) {
987 src_bidx = 0;
988 src_cidx = 0;
989 dst_bidx = acnt;
990 dst_cidx = cidx;
Thomas Gleixnerc2da2342014-04-28 14:29:57 -0500991 epset->addr = dst_addr;
Joel Fernandes8cc3e302014-04-18 21:50:33 -0500992 } else if (direction == DMA_MEM_TO_MEM) {
993 src_bidx = acnt;
994 src_cidx = cidx;
995 dst_bidx = acnt;
996 dst_cidx = cidx;
Joel Fernandesfd009032013-09-23 18:05:13 -0500997 } else {
998 dev_err(dev, "%s: direction not implemented yet\n", __func__);
999 return -EINVAL;
1000 }
1001
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001002 param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
Joel Fernandesfd009032013-09-23 18:05:13 -05001003 /* Configure A or AB synchronized transfers */
1004 if (absync)
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001005 param->opt |= SYNCDIM;
Joel Fernandesfd009032013-09-23 18:05:13 -05001006
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001007 param->src = src_addr;
1008 param->dst = dst_addr;
Joel Fernandesfd009032013-09-23 18:05:13 -05001009
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001010 param->src_dst_bidx = (dst_bidx << 16) | src_bidx;
1011 param->src_dst_cidx = (dst_cidx << 16) | src_cidx;
Joel Fernandesfd009032013-09-23 18:05:13 -05001012
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001013 param->a_b_cnt = bcnt << 16 | acnt;
1014 param->ccnt = ccnt;
Joel Fernandesfd009032013-09-23 18:05:13 -05001015 /*
1016 * Only time when (bcntrld) auto reload is required is for
1017 * A-sync case, and in this case, a requirement of reload value
1018 * of SZ_64K-1 only is assured. 'link' is initially set to NULL
1019 * and then later will be populated by edma_execute.
1020 */
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001021 param->link_bcntrld = 0xffffffff;
Joel Fernandesfd009032013-09-23 18:05:13 -05001022 return absync;
1023}
1024
Matt Porterc2dde5f2012-08-22 21:09:34 -04001025static struct dma_async_tx_descriptor *edma_prep_slave_sg(
1026 struct dma_chan *chan, struct scatterlist *sgl,
1027 unsigned int sg_len, enum dma_transfer_direction direction,
1028 unsigned long tx_flags, void *context)
1029{
1030 struct edma_chan *echan = to_edma_chan(chan);
1031 struct device *dev = chan->device->dev;
1032 struct edma_desc *edesc;
Joel Fernandesfd009032013-09-23 18:05:13 -05001033 dma_addr_t src_addr = 0, dst_addr = 0;
Matt Porter661f7cb2013-01-10 13:41:04 -05001034 enum dma_slave_buswidth dev_width;
1035 u32 burst;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001036 struct scatterlist *sg;
Joel Fernandesfd009032013-09-23 18:05:13 -05001037 int i, nslots, ret;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001038
1039 if (unlikely(!echan || !sgl || !sg_len))
1040 return NULL;
1041
Matt Porter661f7cb2013-01-10 13:41:04 -05001042 if (direction == DMA_DEV_TO_MEM) {
Joel Fernandesfd009032013-09-23 18:05:13 -05001043 src_addr = echan->cfg.src_addr;
Matt Porter661f7cb2013-01-10 13:41:04 -05001044 dev_width = echan->cfg.src_addr_width;
1045 burst = echan->cfg.src_maxburst;
1046 } else if (direction == DMA_MEM_TO_DEV) {
Joel Fernandesfd009032013-09-23 18:05:13 -05001047 dst_addr = echan->cfg.dst_addr;
Matt Porter661f7cb2013-01-10 13:41:04 -05001048 dev_width = echan->cfg.dst_addr_width;
1049 burst = echan->cfg.dst_maxburst;
1050 } else {
Peter Ujfalusie6fad592014-04-14 14:42:05 +03001051 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
Matt Porter661f7cb2013-01-10 13:41:04 -05001052 return NULL;
1053 }
1054
1055 if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
Peter Ujfalusic594c892014-04-14 14:42:03 +03001056 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001057 return NULL;
1058 }
1059
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001060 edesc = kzalloc(sizeof(*edesc) + sg_len * sizeof(edesc->pset[0]),
1061 GFP_ATOMIC);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001062 if (!edesc) {
Peter Ujfalusic594c892014-04-14 14:42:03 +03001063 dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001064 return NULL;
1065 }
1066
1067 edesc->pset_nr = sg_len;
Thomas Gleixnerb6205c32014-04-28 14:18:45 -05001068 edesc->residue = 0;
Thomas Gleixnerc2da2342014-04-28 14:29:57 -05001069 edesc->direction = direction;
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001070 edesc->echan = echan;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001071
Joel Fernandes6fbe24d2013-08-29 18:05:40 -05001072 /* Allocate a PaRAM slot, if needed */
1073 nslots = min_t(unsigned, MAX_NR_SG, sg_len);
1074
1075 for (i = 0; i < nslots; i++) {
Matt Porterc2dde5f2012-08-22 21:09:34 -04001076 if (echan->slot[i] < 0) {
1077 echan->slot[i] =
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001078 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001079 if (echan->slot[i] < 0) {
Valentin Ilie4b6271a2013-10-24 16:14:22 +03001080 kfree(edesc);
Peter Ujfalusic594c892014-04-14 14:42:03 +03001081 dev_err(dev, "%s: Failed to allocate slot\n",
1082 __func__);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001083 return NULL;
1084 }
1085 }
Joel Fernandes6fbe24d2013-08-29 18:05:40 -05001086 }
1087
1088 /* Configure PaRAM sets for each SG */
1089 for_each_sg(sgl, sg, sg_len, i) {
Joel Fernandesfd009032013-09-23 18:05:13 -05001090 /* Get address for each SG */
1091 if (direction == DMA_DEV_TO_MEM)
1092 dst_addr = sg_dma_address(sg);
1093 else
1094 src_addr = sg_dma_address(sg);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001095
Joel Fernandesfd009032013-09-23 18:05:13 -05001096 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
1097 dst_addr, burst, dev_width,
1098 sg_dma_len(sg), direction);
Vinod Koulb967aec2013-10-30 13:07:18 +05301099 if (ret < 0) {
1100 kfree(edesc);
Joel Fernandesfd009032013-09-23 18:05:13 -05001101 return NULL;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001102 }
1103
Joel Fernandesfd009032013-09-23 18:05:13 -05001104 edesc->absync = ret;
Thomas Gleixnerb6205c32014-04-28 14:18:45 -05001105 edesc->residue += sg_dma_len(sg);
Joel Fernandes6fbe24d2013-08-29 18:05:40 -05001106
1107 /* If this is the last in a current SG set of transactions,
1108 enable interrupts so that next set is processed */
1109 if (!((i+1) % MAX_NR_SG))
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001110 edesc->pset[i].param.opt |= TCINTEN;
Joel Fernandes6fbe24d2013-08-29 18:05:40 -05001111
Matt Porterc2dde5f2012-08-22 21:09:34 -04001112 /* If this is the last set, enable completion interrupt flag */
1113 if (i == sg_len - 1)
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001114 edesc->pset[i].param.opt |= TCINTEN;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001115 }
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001116 edesc->residue_stat = edesc->residue;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001117
Matt Porterc2dde5f2012-08-22 21:09:34 -04001118 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1119}
Matt Porterc2dde5f2012-08-22 21:09:34 -04001120
Lad, Prabhakarb7a4fd52015-02-04 13:03:27 +00001121static struct dma_async_tx_descriptor *edma_prep_dma_memcpy(
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001122 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1123 size_t len, unsigned long tx_flags)
1124{
Peter Ujfalusidf6694f2015-10-16 10:18:00 +03001125 int ret, nslots;
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001126 struct edma_desc *edesc;
1127 struct device *dev = chan->device->dev;
1128 struct edma_chan *echan = to_edma_chan(chan);
Peter Ujfalusidf6694f2015-10-16 10:18:00 +03001129 unsigned int width, pset_len;
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001130
1131 if (unlikely(!echan || !len))
1132 return NULL;
1133
Peter Ujfalusidf6694f2015-10-16 10:18:00 +03001134 if (len < SZ_64K) {
1135 /*
1136 * Transfer size less than 64K can be handled with one paRAM
1137 * slot and with one burst.
1138 * ACNT = length
1139 */
1140 width = len;
1141 pset_len = len;
1142 nslots = 1;
1143 } else {
1144 /*
1145 * Transfer size bigger than 64K will be handled with maximum of
1146 * two paRAM slots.
1147 * slot1: (full_length / 32767) times 32767 bytes bursts.
1148 * ACNT = 32767, length1: (full_length / 32767) * 32767
1149 * slot2: the remaining amount of data after slot1.
1150 * ACNT = full_length - length1, length2 = ACNT
1151 *
1152 * When the full_length is multibple of 32767 one slot can be
1153 * used to complete the transfer.
1154 */
1155 width = SZ_32K - 1;
1156 pset_len = rounddown(len, width);
1157 /* One slot is enough for lengths multiple of (SZ_32K -1) */
1158 if (unlikely(pset_len == len))
1159 nslots = 1;
1160 else
1161 nslots = 2;
1162 }
1163
1164 edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]),
1165 GFP_ATOMIC);
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001166 if (!edesc) {
1167 dev_dbg(dev, "Failed to allocate a descriptor\n");
1168 return NULL;
1169 }
1170
Peter Ujfalusidf6694f2015-10-16 10:18:00 +03001171 edesc->pset_nr = nslots;
1172 edesc->residue = edesc->residue_stat = len;
1173 edesc->direction = DMA_MEM_TO_MEM;
1174 edesc->echan = echan;
Peter Ujfalusi21a31842015-10-16 10:17:59 +03001175
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001176 ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1,
Peter Ujfalusidf6694f2015-10-16 10:18:00 +03001177 width, pset_len, DMA_MEM_TO_MEM);
1178 if (ret < 0) {
1179 kfree(edesc);
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001180 return NULL;
Peter Ujfalusidf6694f2015-10-16 10:18:00 +03001181 }
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001182
1183 edesc->absync = ret;
1184
Joel Fernandesb0cce4c2014-04-28 15:30:32 -05001185 edesc->pset[0].param.opt |= ITCCHEN;
Peter Ujfalusidf6694f2015-10-16 10:18:00 +03001186 if (nslots == 1) {
1187 /* Enable transfer complete interrupt */
1188 edesc->pset[0].param.opt |= TCINTEN;
1189 } else {
1190 /* Enable transfer complete chaining for the first slot */
1191 edesc->pset[0].param.opt |= TCCHEN;
1192
1193 if (echan->slot[1] < 0) {
1194 echan->slot[1] = edma_alloc_slot(echan->ecc,
1195 EDMA_SLOT_ANY);
1196 if (echan->slot[1] < 0) {
1197 kfree(edesc);
1198 dev_err(dev, "%s: Failed to allocate slot\n",
1199 __func__);
1200 return NULL;
1201 }
1202 }
1203 dest += pset_len;
1204 src += pset_len;
1205 pset_len = width = len % (SZ_32K - 1);
1206
1207 ret = edma_config_pset(chan, &edesc->pset[1], src, dest, 1,
1208 width, pset_len, DMA_MEM_TO_MEM);
1209 if (ret < 0) {
1210 kfree(edesc);
1211 return NULL;
1212 }
1213
1214 edesc->pset[1].param.opt |= ITCCHEN;
1215 edesc->pset[1].param.opt |= TCINTEN;
1216 }
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001217
1218 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1219}
1220
Joel Fernandes50a9c702013-10-31 16:31:23 -05001221static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
1222 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
1223 size_t period_len, enum dma_transfer_direction direction,
Laurent Pinchart31c1e5a2014-08-01 12:20:10 +02001224 unsigned long tx_flags)
Joel Fernandes50a9c702013-10-31 16:31:23 -05001225{
1226 struct edma_chan *echan = to_edma_chan(chan);
1227 struct device *dev = chan->device->dev;
1228 struct edma_desc *edesc;
1229 dma_addr_t src_addr, dst_addr;
1230 enum dma_slave_buswidth dev_width;
1231 u32 burst;
1232 int i, ret, nslots;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001233
Joel Fernandes50a9c702013-10-31 16:31:23 -05001234 if (unlikely(!echan || !buf_len || !period_len))
1235 return NULL;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001236
Joel Fernandes50a9c702013-10-31 16:31:23 -05001237 if (direction == DMA_DEV_TO_MEM) {
1238 src_addr = echan->cfg.src_addr;
1239 dst_addr = buf_addr;
1240 dev_width = echan->cfg.src_addr_width;
1241 burst = echan->cfg.src_maxburst;
1242 } else if (direction == DMA_MEM_TO_DEV) {
1243 src_addr = buf_addr;
1244 dst_addr = echan->cfg.dst_addr;
1245 dev_width = echan->cfg.dst_addr_width;
1246 burst = echan->cfg.dst_maxburst;
1247 } else {
Peter Ujfalusie6fad592014-04-14 14:42:05 +03001248 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001249 return NULL;
1250 }
1251
1252 if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
Peter Ujfalusic594c892014-04-14 14:42:03 +03001253 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001254 return NULL;
1255 }
1256
1257 if (unlikely(buf_len % period_len)) {
1258 dev_err(dev, "Period should be multiple of Buffer length\n");
1259 return NULL;
1260 }
1261
1262 nslots = (buf_len / period_len) + 1;
1263
1264 /*
1265 * Cyclic DMA users such as audio cannot tolerate delays introduced
1266 * by cases where the number of periods is more than the maximum
1267 * number of SGs the EDMA driver can handle at a time. For DMA types
1268 * such as Slave SGs, such delays are tolerable and synchronized,
1269 * but the synchronization is difficult to achieve with Cyclic and
1270 * cannot be guaranteed, so we error out early.
1271 */
1272 if (nslots > MAX_NR_SG)
1273 return NULL;
1274
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001275 edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]),
1276 GFP_ATOMIC);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001277 if (!edesc) {
Peter Ujfalusic594c892014-04-14 14:42:03 +03001278 dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001279 return NULL;
1280 }
1281
1282 edesc->cyclic = 1;
1283 edesc->pset_nr = nslots;
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001284 edesc->residue = edesc->residue_stat = buf_len;
Thomas Gleixnerc2da2342014-04-28 14:29:57 -05001285 edesc->direction = direction;
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001286 edesc->echan = echan;
Joel Fernandes50a9c702013-10-31 16:31:23 -05001287
Peter Ujfalusi83bb3122014-04-14 14:42:02 +03001288 dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n",
1289 __func__, echan->ch_num, nslots, period_len, buf_len);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001290
1291 for (i = 0; i < nslots; i++) {
1292 /* Allocate a PaRAM slot, if needed */
1293 if (echan->slot[i] < 0) {
1294 echan->slot[i] =
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001295 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001296 if (echan->slot[i] < 0) {
Christian Engelmayere3ddc972013-12-30 20:48:39 +01001297 kfree(edesc);
Peter Ujfalusic594c892014-04-14 14:42:03 +03001298 dev_err(dev, "%s: Failed to allocate slot\n",
1299 __func__);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001300 return NULL;
1301 }
1302 }
1303
1304 if (i == nslots - 1) {
1305 memcpy(&edesc->pset[i], &edesc->pset[0],
1306 sizeof(edesc->pset[0]));
1307 break;
1308 }
1309
1310 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
1311 dst_addr, burst, dev_width, period_len,
1312 direction);
Christian Engelmayere3ddc972013-12-30 20:48:39 +01001313 if (ret < 0) {
1314 kfree(edesc);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001315 return NULL;
Christian Engelmayere3ddc972013-12-30 20:48:39 +01001316 }
Joel Fernandes50a9c702013-10-31 16:31:23 -05001317
1318 if (direction == DMA_DEV_TO_MEM)
1319 dst_addr += period_len;
1320 else
1321 src_addr += period_len;
1322
Peter Ujfalusi83bb3122014-04-14 14:42:02 +03001323 dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i);
1324 dev_vdbg(dev,
Joel Fernandes50a9c702013-10-31 16:31:23 -05001325 "\n pset[%d]:\n"
1326 " chnum\t%d\n"
1327 " slot\t%d\n"
1328 " opt\t%08x\n"
1329 " src\t%08x\n"
1330 " dst\t%08x\n"
1331 " abcnt\t%08x\n"
1332 " ccnt\t%08x\n"
1333 " bidx\t%08x\n"
1334 " cidx\t%08x\n"
1335 " lkrld\t%08x\n",
1336 i, echan->ch_num, echan->slot[i],
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001337 edesc->pset[i].param.opt,
1338 edesc->pset[i].param.src,
1339 edesc->pset[i].param.dst,
1340 edesc->pset[i].param.a_b_cnt,
1341 edesc->pset[i].param.ccnt,
1342 edesc->pset[i].param.src_dst_bidx,
1343 edesc->pset[i].param.src_dst_cidx,
1344 edesc->pset[i].param.link_bcntrld);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001345
1346 edesc->absync = ret;
1347
1348 /*
Peter Ujfalusia1f146f2014-07-16 15:29:21 +03001349 * Enable period interrupt only if it is requested
Joel Fernandes50a9c702013-10-31 16:31:23 -05001350 */
Peter Ujfalusia1f146f2014-07-16 15:29:21 +03001351 if (tx_flags & DMA_PREP_INTERRUPT)
1352 edesc->pset[i].param.opt |= TCINTEN;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001353 }
1354
Peter Ujfalusi8e8805d2014-07-08 13:46:38 +03001355 /* Place the cyclic channel to highest priority queue */
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001356 if (!echan->tc)
1357 edma_assign_channel_eventq(echan, EVENTQ_0);
Peter Ujfalusi8e8805d2014-07-08 13:46:38 +03001358
Matt Porterc2dde5f2012-08-22 21:09:34 -04001359 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1360}
1361
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001362static void edma_completion_handler(struct edma_chan *echan)
Matt Porterc2dde5f2012-08-22 21:09:34 -04001363{
Matt Porterc2dde5f2012-08-22 21:09:34 -04001364 struct device *dev = echan->vchan.chan.device->dev;
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001365 struct edma_desc *edesc = echan->edesc;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001366
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001367 if (!edesc)
1368 return;
Joel Fernandes50a9c702013-10-31 16:31:23 -05001369
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +03001370 spin_lock(&echan->vchan.lock);
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001371 if (edesc->cyclic) {
1372 vchan_cyclic_callback(&edesc->vdesc);
1373 spin_unlock(&echan->vchan.lock);
1374 return;
1375 } else if (edesc->processed == edesc->pset_nr) {
1376 edesc->residue = 0;
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03001377 edma_stop(echan);
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001378 vchan_cookie_complete(&edesc->vdesc);
1379 echan->edesc = NULL;
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001380
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001381 dev_dbg(dev, "Transfer completed on channel %d\n",
1382 echan->ch_num);
1383 } else {
1384 dev_dbg(dev, "Sub transfer completed on channel %d\n",
1385 echan->ch_num);
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +03001386
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03001387 edma_pause(echan);
Joel Fernandesc5f47992013-08-29 18:05:43 -05001388
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001389 /* Update statistics for tx_status */
1390 edesc->residue -= edesc->sg_len;
1391 edesc->residue_stat = edesc->residue;
1392 edesc->processed_stat = edesc->processed;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001393 }
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001394 edma_execute(echan);
1395
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +03001396 spin_unlock(&echan->vchan.lock);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001397}
1398
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001399/* eDMA interrupt handler */
1400static irqreturn_t dma_irq_handler(int irq, void *data)
1401{
1402 struct edma_cc *ecc = data;
1403 int ctlr;
1404 u32 sh_ier;
1405 u32 sh_ipr;
1406 u32 bank;
1407
1408 ctlr = ecc->id;
1409 if (ctlr < 0)
1410 return IRQ_NONE;
1411
1412 dev_vdbg(ecc->dev, "dma_irq_handler\n");
1413
1414 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0);
1415 if (!sh_ipr) {
1416 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1);
1417 if (!sh_ipr)
1418 return IRQ_NONE;
1419 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1);
1420 bank = 1;
1421 } else {
1422 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0);
1423 bank = 0;
1424 }
1425
1426 do {
1427 u32 slot;
1428 u32 channel;
1429
1430 slot = __ffs(sh_ipr);
1431 sh_ipr &= ~(BIT(slot));
1432
1433 if (sh_ier & BIT(slot)) {
1434 channel = (bank << 5) | slot;
1435 /* Clear the corresponding IPR bits */
1436 edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot));
1437 edma_completion_handler(&ecc->slave_chans[channel]);
1438 }
1439 } while (sh_ipr);
1440
1441 edma_shadow0_write(ecc, SH_IEVAL, 1);
1442 return IRQ_HANDLED;
1443}
1444
1445static void edma_error_handler(struct edma_chan *echan)
1446{
1447 struct edma_cc *ecc = echan->ecc;
1448 struct device *dev = echan->vchan.chan.device->dev;
1449 struct edmacc_param p;
1450
1451 if (!echan->edesc)
1452 return;
1453
1454 spin_lock(&echan->vchan.lock);
1455
1456 edma_read_slot(ecc, echan->slot[0], &p);
1457 /*
1458 * Issue later based on missed flag which will be sure
1459 * to happen as:
1460 * (1) we finished transmitting an intermediate slot and
1461 * edma_execute is coming up.
1462 * (2) or we finished current transfer and issue will
1463 * call edma_execute.
1464 *
1465 * Important note: issuing can be dangerous here and
1466 * lead to some nasty recursion when we are in a NULL
1467 * slot. So we avoid doing so and set the missed flag.
1468 */
1469 if (p.a_b_cnt == 0 && p.ccnt == 0) {
1470 dev_dbg(dev, "Error on null slot, setting miss\n");
1471 echan->missed = 1;
1472 } else {
1473 /*
1474 * The slot is already programmed but the event got
1475 * missed, so its safe to issue it here.
1476 */
1477 dev_dbg(dev, "Missed event, TRIGGERING\n");
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03001478 edma_clean_channel(echan);
1479 edma_stop(echan);
1480 edma_start(echan);
1481 edma_trigger_channel(echan);
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001482 }
1483 spin_unlock(&echan->vchan.lock);
1484}
1485
Peter Ujfalusi7c3b8b32015-10-14 14:43:02 +03001486static inline bool edma_error_pending(struct edma_cc *ecc)
1487{
1488 if (edma_read_array(ecc, EDMA_EMR, 0) ||
1489 edma_read_array(ecc, EDMA_EMR, 1) ||
1490 edma_read(ecc, EDMA_QEMR) || edma_read(ecc, EDMA_CCERR))
1491 return true;
1492
1493 return false;
1494}
1495
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001496/* eDMA error interrupt handler */
1497static irqreturn_t dma_ccerr_handler(int irq, void *data)
1498{
1499 struct edma_cc *ecc = data;
Peter Ujfalusie4402a12015-10-14 14:43:03 +03001500 int i, j;
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001501 int ctlr;
1502 unsigned int cnt = 0;
Peter Ujfalusie4402a12015-10-14 14:43:03 +03001503 unsigned int val;
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001504
1505 ctlr = ecc->id;
1506 if (ctlr < 0)
1507 return IRQ_NONE;
1508
1509 dev_vdbg(ecc->dev, "dma_ccerr_handler\n");
1510
Peter Ujfalusi7c3b8b32015-10-14 14:43:02 +03001511 if (!edma_error_pending(ecc))
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001512 return IRQ_NONE;
1513
1514 while (1) {
Peter Ujfalusie4402a12015-10-14 14:43:03 +03001515 /* Event missed register(s) */
1516 for (j = 0; j < 2; j++) {
1517 unsigned long emr;
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001518
Peter Ujfalusie4402a12015-10-14 14:43:03 +03001519 val = edma_read_array(ecc, EDMA_EMR, j);
1520 if (!val)
1521 continue;
1522
1523 dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val);
1524 emr = val;
1525 for (i = find_next_bit(&emr, 32, 0); i < 32;
1526 i = find_next_bit(&emr, 32, i + 1)) {
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001527 int k = (j << 5) + i;
1528
Peter Ujfalusie4402a12015-10-14 14:43:03 +03001529 /* Clear the corresponding EMR bits */
1530 edma_write_array(ecc, EDMA_EMCR, j, BIT(i));
1531 /* Clear any SER */
1532 edma_shadow0_write_array(ecc, SH_SECR, j,
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001533 BIT(i));
Peter Ujfalusie4402a12015-10-14 14:43:03 +03001534 edma_error_handler(&ecc->slave_chans[k]);
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001535 }
1536 }
Peter Ujfalusie4402a12015-10-14 14:43:03 +03001537
1538 val = edma_read(ecc, EDMA_QEMR);
1539 if (val) {
1540 dev_dbg(ecc->dev, "QEMR 0x%02x\n", val);
1541 /* Not reported, just clear the interrupt reason. */
1542 edma_write(ecc, EDMA_QEMCR, val);
1543 edma_shadow0_write(ecc, SH_QSECR, val);
1544 }
1545
1546 val = edma_read(ecc, EDMA_CCERR);
1547 if (val) {
1548 dev_warn(ecc->dev, "CCERR 0x%08x\n", val);
1549 /* Not reported, just clear the interrupt reason. */
1550 edma_write(ecc, EDMA_CCERRCLR, val);
1551 }
1552
Peter Ujfalusi7c3b8b32015-10-14 14:43:02 +03001553 if (!edma_error_pending(ecc))
Peter Ujfalusi79ad2e32015-10-14 14:43:01 +03001554 break;
1555 cnt++;
1556 if (cnt > 10)
1557 break;
1558 }
1559 edma_write(ecc, EDMA_EEVAL, 1);
1560 return IRQ_HANDLED;
1561}
1562
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001563static void edma_tc_set_pm_state(struct edma_tc *tc, bool enable)
1564{
1565 struct platform_device *tc_pdev;
1566 int ret;
1567
1568 if (!tc)
1569 return;
1570
1571 tc_pdev = of_find_device_by_node(tc->node);
1572 if (!tc_pdev) {
1573 pr_err("%s: TPTC device is not found\n", __func__);
1574 return;
1575 }
1576 if (!pm_runtime_enabled(&tc_pdev->dev))
1577 pm_runtime_enable(&tc_pdev->dev);
1578
1579 if (enable)
1580 ret = pm_runtime_get_sync(&tc_pdev->dev);
1581 else
1582 ret = pm_runtime_put_sync(&tc_pdev->dev);
1583
1584 if (ret < 0)
1585 pr_err("%s: pm_runtime_%s_sync() failed for %s\n", __func__,
1586 enable ? "get" : "put", dev_name(&tc_pdev->dev));
1587}
1588
Matt Porterc2dde5f2012-08-22 21:09:34 -04001589/* Alloc channel resources */
1590static int edma_alloc_chan_resources(struct dma_chan *chan)
1591{
1592 struct edma_chan *echan = to_edma_chan(chan);
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001593 struct edma_cc *ecc = echan->ecc;
1594 struct device *dev = ecc->dev;
1595 enum dma_event_q eventq_no = EVENTQ_DEFAULT;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001596 int ret;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001597
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001598 if (echan->tc) {
1599 eventq_no = echan->tc->id;
1600 } else if (ecc->tc_list) {
1601 /* memcpy channel */
1602 echan->tc = &ecc->tc_list[ecc->info->default_queue];
1603 eventq_no = echan->tc->id;
1604 }
1605
1606 ret = edma_alloc_channel(echan, eventq_no);
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03001607 if (ret)
1608 return ret;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001609
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001610 echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num);
Peter Ujfalusie4e886c2015-10-14 14:43:06 +03001611 if (echan->slot[0] < 0) {
1612 dev_err(dev, "Entry slot allocation failed for channel %u\n",
1613 EDMA_CHAN_SLOT(echan->ch_num));
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03001614 goto err_slot;
Peter Ujfalusie4e886c2015-10-14 14:43:06 +03001615 }
1616
1617 /* Set up channel -> slot mapping for the entry slot */
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03001618 edma_set_chmap(echan, echan->slot[0]);
1619 echan->alloced = true;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001620
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001621 dev_dbg(dev, "Got eDMA channel %d for virt channel %d (%s trigger)\n",
1622 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id,
1623 echan->hw_triggered ? "HW" : "SW");
1624
1625 edma_tc_set_pm_state(echan->tc, true);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001626
1627 return 0;
1628
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03001629err_slot:
1630 edma_free_channel(echan);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001631 return ret;
1632}
1633
1634/* Free channel resources */
1635static void edma_free_chan_resources(struct dma_chan *chan)
1636{
1637 struct edma_chan *echan = to_edma_chan(chan);
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001638 struct device *dev = echan->ecc->dev;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001639 int i;
1640
1641 /* Terminate transfers */
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03001642 edma_stop(echan);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001643
1644 vchan_free_chan_resources(&echan->vchan);
1645
1646 /* Free EDMA PaRAM slots */
Peter Ujfalusie4e886c2015-10-14 14:43:06 +03001647 for (i = 0; i < EDMA_MAX_SLOTS; i++) {
Matt Porterc2dde5f2012-08-22 21:09:34 -04001648 if (echan->slot[i] >= 0) {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001649 edma_free_slot(echan->ecc, echan->slot[i]);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001650 echan->slot[i] = -1;
1651 }
1652 }
1653
Peter Ujfalusie4e886c2015-10-14 14:43:06 +03001654 /* Set entry slot to the dummy slot */
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03001655 edma_set_chmap(echan, echan->ecc->dummy_slot);
Peter Ujfalusie4e886c2015-10-14 14:43:06 +03001656
Matt Porterc2dde5f2012-08-22 21:09:34 -04001657 /* Free EDMA channel */
1658 if (echan->alloced) {
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03001659 edma_free_channel(echan);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001660 echan->alloced = false;
1661 }
1662
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001663 edma_tc_set_pm_state(echan->tc, false);
1664 echan->tc = NULL;
1665 echan->hw_triggered = false;
1666
1667 dev_dbg(dev, "Free eDMA channel %d for virt channel %d\n",
1668 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001669}
1670
1671/* Send pending descriptor to hardware */
1672static void edma_issue_pending(struct dma_chan *chan)
1673{
1674 struct edma_chan *echan = to_edma_chan(chan);
1675 unsigned long flags;
1676
1677 spin_lock_irqsave(&echan->vchan.lock, flags);
1678 if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
1679 edma_execute(echan);
1680 spin_unlock_irqrestore(&echan->vchan.lock, flags);
1681}
1682
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001683static u32 edma_residue(struct edma_desc *edesc)
1684{
1685 bool dst = edesc->direction == DMA_DEV_TO_MEM;
1686 struct edma_pset *pset = edesc->pset;
1687 dma_addr_t done, pos;
1688 int i;
1689
1690 /*
1691 * We always read the dst/src position from the first RamPar
1692 * pset. That's the one which is active now.
1693 */
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001694 pos = edma_get_position(edesc->echan->ecc, edesc->echan->slot[0], dst);
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001695
1696 /*
1697 * Cyclic is simple. Just subtract pset[0].addr from pos.
1698 *
1699 * We never update edesc->residue in the cyclic case, so we
1700 * can tell the remaining room to the end of the circular
1701 * buffer.
1702 */
1703 if (edesc->cyclic) {
1704 done = pos - pset->addr;
1705 edesc->residue_stat = edesc->residue - done;
1706 return edesc->residue_stat;
1707 }
1708
1709 /*
1710 * For SG operation we catch up with the last processed
1711 * status.
1712 */
1713 pset += edesc->processed_stat;
1714
1715 for (i = edesc->processed_stat; i < edesc->processed; i++, pset++) {
1716 /*
1717 * If we are inside this pset address range, we know
1718 * this is the active one. Get the current delta and
1719 * stop walking the psets.
1720 */
1721 if (pos >= pset->addr && pos < pset->addr + pset->len)
1722 return edesc->residue_stat - (pos - pset->addr);
1723
1724 /* Otherwise mark it done and update residue_stat. */
1725 edesc->processed_stat++;
1726 edesc->residue_stat -= pset->len;
1727 }
1728 return edesc->residue_stat;
1729}
1730
Matt Porterc2dde5f2012-08-22 21:09:34 -04001731/* Check request completion status */
1732static enum dma_status edma_tx_status(struct dma_chan *chan,
1733 dma_cookie_t cookie,
1734 struct dma_tx_state *txstate)
1735{
1736 struct edma_chan *echan = to_edma_chan(chan);
1737 struct virt_dma_desc *vdesc;
1738 enum dma_status ret;
1739 unsigned long flags;
1740
1741 ret = dma_cookie_status(chan, cookie, txstate);
Vinod Koul9d386ec2013-10-16 13:42:15 +05301742 if (ret == DMA_COMPLETE || !txstate)
Matt Porterc2dde5f2012-08-22 21:09:34 -04001743 return ret;
1744
1745 spin_lock_irqsave(&echan->vchan.lock, flags);
Thomas Gleixnerde135932014-04-28 14:19:51 -05001746 if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie)
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001747 txstate->residue = edma_residue(echan->edesc);
Thomas Gleixnerde135932014-04-28 14:19:51 -05001748 else if ((vdesc = vchan_find_desc(&echan->vchan, cookie)))
1749 txstate->residue = to_edma_desc(&vdesc->tx)->residue;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001750 spin_unlock_irqrestore(&echan->vchan.lock, flags);
1751
1752 return ret;
1753}
1754
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001755static bool edma_is_memcpy_channel(int ch_num, u16 *memcpy_channels)
1756{
1757 s16 *memcpy_ch = memcpy_channels;
1758
1759 if (!memcpy_channels)
1760 return false;
1761 while (*memcpy_ch != -1) {
1762 if (*memcpy_ch == ch_num)
1763 return true;
1764 memcpy_ch++;
1765 }
1766 return false;
1767}
1768
Peter Ujfalusi2c88ee62014-04-14 14:42:01 +03001769#define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
1770 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
Peter Ujfalusie4a899d2014-07-03 07:51:56 +03001771 BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
Peter Ujfalusi2c88ee62014-04-14 14:42:01 +03001772 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
1773
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001774static void edma_dma_init(struct edma_cc *ecc, bool legacy_mode)
Matt Porterc2dde5f2012-08-22 21:09:34 -04001775{
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001776 struct dma_device *s_ddev = &ecc->dma_slave;
1777 struct dma_device *m_ddev = NULL;
1778 s16 *memcpy_channels = ecc->info->memcpy_channels;
Peter Ujfalusi02f77ef2015-10-16 10:18:05 +03001779 int i, j;
Maxime Ripard9f59cd02014-11-17 14:42:47 +01001780
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001781 dma_cap_zero(s_ddev->cap_mask);
1782 dma_cap_set(DMA_SLAVE, s_ddev->cap_mask);
1783 dma_cap_set(DMA_CYCLIC, s_ddev->cap_mask);
1784 if (ecc->legacy_mode && !memcpy_channels) {
1785 dev_warn(ecc->dev,
1786 "Legacy memcpy is enabled, things might not work\n");
Maxime Ripard9f59cd02014-11-17 14:42:47 +01001787
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001788 dma_cap_set(DMA_MEMCPY, s_ddev->cap_mask);
1789 s_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy;
1790 s_ddev->directions = BIT(DMA_MEM_TO_MEM);
1791 }
Matt Porterc2dde5f2012-08-22 21:09:34 -04001792
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001793 s_ddev->device_prep_slave_sg = edma_prep_slave_sg;
1794 s_ddev->device_prep_dma_cyclic = edma_prep_dma_cyclic;
1795 s_ddev->device_alloc_chan_resources = edma_alloc_chan_resources;
1796 s_ddev->device_free_chan_resources = edma_free_chan_resources;
1797 s_ddev->device_issue_pending = edma_issue_pending;
1798 s_ddev->device_tx_status = edma_tx_status;
1799 s_ddev->device_config = edma_slave_config;
1800 s_ddev->device_pause = edma_dma_pause;
1801 s_ddev->device_resume = edma_dma_resume;
1802 s_ddev->device_terminate_all = edma_terminate_all;
Peter Ujfalusi02f77ef2015-10-16 10:18:05 +03001803
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001804 s_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS;
1805 s_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS;
1806 s_ddev->directions |= (BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV));
1807 s_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
Peter Ujfalusi02f77ef2015-10-16 10:18:05 +03001808
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001809 s_ddev->dev = ecc->dev;
1810 INIT_LIST_HEAD(&s_ddev->channels);
1811
1812 if (memcpy_channels) {
1813 m_ddev = devm_kzalloc(ecc->dev, sizeof(*m_ddev), GFP_KERNEL);
1814 ecc->dma_memcpy = m_ddev;
1815
1816 dma_cap_zero(m_ddev->cap_mask);
1817 dma_cap_set(DMA_MEMCPY, m_ddev->cap_mask);
1818
1819 m_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy;
1820 m_ddev->device_alloc_chan_resources = edma_alloc_chan_resources;
1821 m_ddev->device_free_chan_resources = edma_free_chan_resources;
1822 m_ddev->device_issue_pending = edma_issue_pending;
1823 m_ddev->device_tx_status = edma_tx_status;
1824 m_ddev->device_config = edma_slave_config;
1825 m_ddev->device_pause = edma_dma_pause;
1826 m_ddev->device_resume = edma_dma_resume;
1827 m_ddev->device_terminate_all = edma_terminate_all;
1828
1829 m_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS;
1830 m_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS;
1831 m_ddev->directions = BIT(DMA_MEM_TO_MEM);
1832 m_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1833
1834 m_ddev->dev = ecc->dev;
1835 INIT_LIST_HEAD(&m_ddev->channels);
1836 } else if (!ecc->legacy_mode) {
1837 dev_info(ecc->dev, "memcpy is disabled\n");
1838 }
Peter Ujfalusi02f77ef2015-10-16 10:18:05 +03001839
1840 for (i = 0; i < ecc->num_channels; i++) {
1841 struct edma_chan *echan = &ecc->slave_chans[i];
1842 echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i);
1843 echan->ecc = ecc;
1844 echan->vchan.desc_free = edma_desc_free;
1845
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001846 if (m_ddev && edma_is_memcpy_channel(i, memcpy_channels))
1847 vchan_init(&echan->vchan, m_ddev);
1848 else
1849 vchan_init(&echan->vchan, s_ddev);
Peter Ujfalusi02f77ef2015-10-16 10:18:05 +03001850
1851 INIT_LIST_HEAD(&echan->node);
1852 for (j = 0; j < EDMA_MAX_SLOTS; j++)
1853 echan->slot[j] = -1;
1854 }
Matt Porterc2dde5f2012-08-22 21:09:34 -04001855}
1856
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001857static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
1858 struct edma_cc *ecc)
1859{
1860 int i;
1861 u32 value, cccfg;
1862 s8 (*queue_priority_map)[2];
1863
1864 /* Decode the eDMA3 configuration from CCCFG register */
1865 cccfg = edma_read(ecc, EDMA_CCCFG);
1866
1867 value = GET_NUM_REGN(cccfg);
1868 ecc->num_region = BIT(value);
1869
1870 value = GET_NUM_DMACH(cccfg);
1871 ecc->num_channels = BIT(value + 1);
1872
Peter Ujfalusi633e42b2015-10-16 10:18:04 +03001873 value = GET_NUM_QDMACH(cccfg);
1874 ecc->num_qchannels = value * 2;
1875
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001876 value = GET_NUM_PAENTRY(cccfg);
1877 ecc->num_slots = BIT(value + 4);
1878
1879 value = GET_NUM_EVQUE(cccfg);
1880 ecc->num_tc = value + 1;
1881
Peter Ujfalusi4ab54f62015-10-14 14:43:04 +03001882 ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false;
1883
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001884 dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg);
1885 dev_dbg(dev, "num_region: %u\n", ecc->num_region);
1886 dev_dbg(dev, "num_channels: %u\n", ecc->num_channels);
Peter Ujfalusi633e42b2015-10-16 10:18:04 +03001887 dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001888 dev_dbg(dev, "num_slots: %u\n", ecc->num_slots);
1889 dev_dbg(dev, "num_tc: %u\n", ecc->num_tc);
Peter Ujfalusi4ab54f62015-10-14 14:43:04 +03001890 dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no");
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001891
1892 /* Nothing need to be done if queue priority is provided */
1893 if (pdata->queue_priority_mapping)
1894 return 0;
1895
1896 /*
1897 * Configure TC/queue priority as follows:
1898 * Q0 - priority 0
1899 * Q1 - priority 1
1900 * Q2 - priority 2
1901 * ...
1902 * The meaning of priority numbers: 0 highest priority, 7 lowest
1903 * priority. So Q0 is the highest priority queue and the last queue has
1904 * the lowest priority.
1905 */
Peter Ujfalusi547c6e22015-10-14 14:42:55 +03001906 queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8),
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001907 GFP_KERNEL);
1908 if (!queue_priority_map)
1909 return -ENOMEM;
1910
1911 for (i = 0; i < ecc->num_tc; i++) {
1912 queue_priority_map[i][0] = i;
1913 queue_priority_map[i][1] = i;
1914 }
1915 queue_priority_map[i][0] = -1;
1916 queue_priority_map[i][1] = -1;
1917
1918 pdata->queue_priority_mapping = queue_priority_map;
1919 /* Default queue has the lowest priority */
1920 pdata->default_queue = i - 1;
1921
1922 return 0;
1923}
1924
1925#if IS_ENABLED(CONFIG_OF)
1926static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata,
1927 size_t sz)
1928{
1929 const char pname[] = "ti,edma-xbar-event-map";
1930 struct resource res;
1931 void __iomem *xbar;
1932 s16 (*xbar_chans)[2];
1933 size_t nelm = sz / sizeof(s16);
1934 u32 shift, offset, mux;
1935 int ret, i;
1936
Peter Ujfalusi547c6e22015-10-14 14:42:55 +03001937 xbar_chans = devm_kcalloc(dev, nelm + 2, sizeof(s16), GFP_KERNEL);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001938 if (!xbar_chans)
1939 return -ENOMEM;
1940
1941 ret = of_address_to_resource(dev->of_node, 1, &res);
1942 if (ret)
1943 return -ENOMEM;
1944
1945 xbar = devm_ioremap(dev, res.start, resource_size(&res));
1946 if (!xbar)
1947 return -ENOMEM;
1948
1949 ret = of_property_read_u16_array(dev->of_node, pname, (u16 *)xbar_chans,
1950 nelm);
1951 if (ret)
1952 return -EIO;
1953
1954 /* Invalidate last entry for the other user of this mess */
1955 nelm >>= 1;
1956 xbar_chans[nelm][0] = -1;
1957 xbar_chans[nelm][1] = -1;
1958
1959 for (i = 0; i < nelm; i++) {
1960 shift = (xbar_chans[i][1] & 0x03) << 3;
1961 offset = xbar_chans[i][1] & 0xfffffffc;
1962 mux = readl(xbar + offset);
1963 mux &= ~(0xff << shift);
1964 mux |= xbar_chans[i][0] << shift;
1965 writel(mux, (xbar + offset));
1966 }
1967
1968 pdata->xbar_chans = (const s16 (*)[2]) xbar_chans;
1969 return 0;
1970}
1971
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001972static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
1973 bool legacy_mode)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001974{
1975 struct edma_soc_info *info;
Peter Ujfalusi966a87b2015-10-16 10:18:07 +03001976 struct property *prop;
1977 size_t sz;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001978 int ret;
1979
1980 info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
1981 if (!info)
1982 return ERR_PTR(-ENOMEM);
1983
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001984 if (legacy_mode) {
1985 prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map",
1986 &sz);
1987 if (prop) {
1988 ret = edma_xbar_event_map(dev, info, sz);
1989 if (ret)
1990 return ERR_PTR(ret);
1991 }
1992 return info;
1993 }
1994
1995 /* Get the list of channels allocated to be used for memcpy */
1996 prop = of_find_property(dev->of_node, "ti,edma-memcpy-channels", &sz);
Peter Ujfalusi966a87b2015-10-16 10:18:07 +03001997 if (prop) {
Peter Ujfalusi1be53362015-10-16 10:18:10 +03001998 const char pname[] = "ti,edma-memcpy-channels";
1999 size_t nelm = sz / sizeof(s16);
2000 s16 *memcpy_ch;
2001
2002 memcpy_ch = devm_kcalloc(dev, nelm + 1, sizeof(s16),
2003 GFP_KERNEL);
2004 if (!memcpy_ch)
2005 return ERR_PTR(-ENOMEM);
2006
2007 ret = of_property_read_u16_array(dev->of_node, pname,
2008 (u16 *)memcpy_ch, nelm);
Peter Ujfalusi966a87b2015-10-16 10:18:07 +03002009 if (ret)
2010 return ERR_PTR(ret);
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002011
2012 memcpy_ch[nelm] = -1;
2013 info->memcpy_channels = memcpy_ch;
2014 }
2015
2016 prop = of_find_property(dev->of_node, "ti,edma-reserved-slot-ranges",
2017 &sz);
2018 if (prop) {
2019 const char pname[] = "ti,edma-reserved-slot-ranges";
2020 s16 (*rsv_slots)[2];
2021 size_t nelm = sz / sizeof(*rsv_slots);
2022 struct edma_rsv_info *rsv_info;
2023
2024 if (!nelm)
2025 return info;
2026
2027 rsv_info = devm_kzalloc(dev, sizeof(*rsv_info), GFP_KERNEL);
2028 if (!rsv_info)
2029 return ERR_PTR(-ENOMEM);
2030
2031 rsv_slots = devm_kcalloc(dev, nelm + 1, sizeof(*rsv_slots),
2032 GFP_KERNEL);
2033 if (!rsv_slots)
2034 return ERR_PTR(-ENOMEM);
2035
2036 ret = of_property_read_u16_array(dev->of_node, pname,
2037 (u16 *)rsv_slots, nelm * 2);
2038 if (ret)
2039 return ERR_PTR(ret);
2040
2041 rsv_slots[nelm][0] = -1;
2042 rsv_slots[nelm][1] = -1;
2043 info->rsv = rsv_info;
2044 info->rsv->rsv_slots = (const s16 (*)[2])rsv_slots;
Peter Ujfalusi966a87b2015-10-16 10:18:07 +03002045 }
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002046
2047 return info;
2048}
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002049
2050static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec,
2051 struct of_dma *ofdma)
2052{
2053 struct edma_cc *ecc = ofdma->of_dma_data;
2054 struct dma_chan *chan = NULL;
2055 struct edma_chan *echan;
2056 int i;
2057
2058 if (!ecc || dma_spec->args_count < 1)
2059 return NULL;
2060
2061 for (i = 0; i < ecc->num_channels; i++) {
2062 echan = &ecc->slave_chans[i];
2063 if (echan->ch_num == dma_spec->args[0]) {
2064 chan = &echan->vchan.chan;
2065 break;
2066 }
2067 }
2068
2069 if (!chan)
2070 return NULL;
2071
2072 if (echan->ecc->legacy_mode && dma_spec->args_count == 1)
2073 goto out;
2074
2075 if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 &&
2076 dma_spec->args[1] < echan->ecc->num_tc) {
2077 echan->tc = &echan->ecc->tc_list[dma_spec->args[1]];
2078 goto out;
2079 }
2080
2081 return NULL;
2082out:
2083 /* The channel is going to be used as HW synchronized */
2084 echan->hw_triggered = true;
2085 return dma_get_slave_channel(chan);
2086}
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002087#else
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002088static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
2089 bool legacy_mode)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002090{
2091 return ERR_PTR(-EINVAL);
2092}
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002093
2094static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec,
2095 struct of_dma *ofdma)
2096{
2097 return NULL;
2098}
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002099#endif
2100
Bill Pemberton463a1f82012-11-19 13:22:55 -05002101static int edma_probe(struct platform_device *pdev)
Matt Porterc2dde5f2012-08-22 21:09:34 -04002102{
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002103 struct edma_soc_info *info = pdev->dev.platform_data;
2104 s8 (*queue_priority_mapping)[2];
2105 int i, off, ln;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002106 const s16 (*rsv_slots)[2];
2107 const s16 (*xbar_chans)[2];
2108 int irq;
2109 char *irq_name;
2110 struct resource *mem;
2111 struct device_node *node = pdev->dev.of_node;
2112 struct device *dev = &pdev->dev;
2113 struct edma_cc *ecc;
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002114 bool legacy_mode = true;
Matt Porterc2dde5f2012-08-22 21:09:34 -04002115 int ret;
2116
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002117 if (node) {
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002118 const struct of_device_id *match;
2119
2120 match = of_match_node(edma_of_ids, node);
2121 if (match && (u32)match->data == EDMA_BINDING_TPCC)
2122 legacy_mode = false;
2123
2124 info = edma_setup_info_from_dt(dev, legacy_mode);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002125 if (IS_ERR(info)) {
2126 dev_err(dev, "failed to get DT data\n");
2127 return PTR_ERR(info);
2128 }
2129 }
2130
2131 if (!info)
2132 return -ENODEV;
2133
2134 pm_runtime_enable(dev);
2135 ret = pm_runtime_get_sync(dev);
2136 if (ret < 0) {
2137 dev_err(dev, "pm_runtime_get_sync() failed\n");
2138 return ret;
2139 }
2140
Peter Ujfalusi907f74a2015-10-14 14:42:56 +03002141 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
Russell King94cb0e72013-06-27 13:45:16 +01002142 if (ret)
2143 return ret;
2144
Peter Ujfalusi907f74a2015-10-14 14:42:56 +03002145 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002146 if (!ecc) {
Peter Ujfalusi907f74a2015-10-14 14:42:56 +03002147 dev_err(dev, "Can't allocate controller\n");
Matt Porterc2dde5f2012-08-22 21:09:34 -04002148 return -ENOMEM;
2149 }
2150
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002151 ecc->dev = dev;
2152 ecc->id = pdev->id;
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002153 ecc->legacy_mode = legacy_mode;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002154 /* When booting with DT the pdev->id is -1 */
2155 if (ecc->id < 0)
2156 ecc->id = 0;
Peter Ujfalusica304fa2015-10-14 14:42:49 +03002157
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002158 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc");
2159 if (!mem) {
2160 dev_dbg(dev, "mem resource not found, using index 0\n");
2161 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2162 if (!mem) {
2163 dev_err(dev, "no mem resource?\n");
2164 return -ENODEV;
2165 }
2166 }
2167 ecc->base = devm_ioremap_resource(dev, mem);
2168 if (IS_ERR(ecc->base))
2169 return PTR_ERR(ecc->base);
Peter Ujfalusib2c843a2015-10-14 14:42:50 +03002170
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002171 platform_set_drvdata(pdev, ecc);
2172
2173 /* Get eDMA3 configuration from IP */
2174 ret = edma_setup_from_hw(dev, info, ecc);
2175 if (ret)
2176 return ret;
2177
Peter Ujfalusicb782052015-10-14 14:42:54 +03002178 /* Allocate memory based on the information we got from the IP */
2179 ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels,
2180 sizeof(*ecc->slave_chans), GFP_KERNEL);
2181 if (!ecc->slave_chans)
2182 return -ENOMEM;
2183
Peter Ujfalusi7a73b132015-10-14 14:43:05 +03002184 ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots),
Peter Ujfalusicb782052015-10-14 14:42:54 +03002185 sizeof(unsigned long), GFP_KERNEL);
Peter Ujfalusi7a73b132015-10-14 14:43:05 +03002186 if (!ecc->slot_inuse)
Peter Ujfalusicb782052015-10-14 14:42:54 +03002187 return -ENOMEM;
2188
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002189 ecc->default_queue = info->default_queue;
2190
2191 for (i = 0; i < ecc->num_slots; i++)
2192 edma_write_slot(ecc, i, &dummy_paramset);
2193
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002194 if (info->rsv) {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002195 /* Set the reserved slots in inuse list */
2196 rsv_slots = info->rsv->rsv_slots;
2197 if (rsv_slots) {
2198 for (i = 0; rsv_slots[i][0] != -1; i++) {
2199 off = rsv_slots[i][0];
2200 ln = rsv_slots[i][1];
Peter Ujfalusi7a73b132015-10-14 14:43:05 +03002201 set_bits(off, ln, ecc->slot_inuse);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002202 }
2203 }
2204 }
2205
2206 /* Clear the xbar mapped channels in unused list */
2207 xbar_chans = info->xbar_chans;
2208 if (xbar_chans) {
2209 for (i = 0; xbar_chans[i][1] != -1; i++) {
2210 off = xbar_chans[i][1];
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002211 }
2212 }
2213
2214 irq = platform_get_irq_byname(pdev, "edma3_ccint");
2215 if (irq < 0 && node)
2216 irq = irq_of_parse_and_map(node, 0);
2217
2218 if (irq >= 0) {
2219 irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint",
2220 dev_name(dev));
2221 ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name,
2222 ecc);
2223 if (ret) {
2224 dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret);
2225 return ret;
2226 }
2227 }
2228
2229 irq = platform_get_irq_byname(pdev, "edma3_ccerrint");
2230 if (irq < 0 && node)
2231 irq = irq_of_parse_and_map(node, 2);
2232
2233 if (irq >= 0) {
2234 irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint",
2235 dev_name(dev));
2236 ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name,
2237 ecc);
2238 if (ret) {
2239 dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret);
2240 return ret;
2241 }
2242 }
2243
Peter Ujfalusie4e886c2015-10-14 14:43:06 +03002244 ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY);
2245 if (ecc->dummy_slot < 0) {
2246 dev_err(dev, "Can't allocate PaRAM dummy slot\n");
2247 return ecc->dummy_slot;
2248 }
2249
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002250 queue_priority_mapping = info->queue_priority_mapping;
2251
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002252 if (!ecc->legacy_mode) {
2253 int lowest_priority = 0;
2254 struct of_phandle_args tc_args;
2255
2256 ecc->tc_list = devm_kcalloc(dev, ecc->num_tc,
2257 sizeof(*ecc->tc_list), GFP_KERNEL);
2258 if (!ecc->tc_list)
2259 return -ENOMEM;
2260
2261 for (i = 0;; i++) {
2262 ret = of_parse_phandle_with_fixed_args(node, "ti,tptcs",
2263 1, i, &tc_args);
2264 if (ret || i == ecc->num_tc)
2265 break;
2266
2267 ecc->tc_list[i].node = tc_args.np;
2268 ecc->tc_list[i].id = i;
2269 queue_priority_mapping[i][1] = tc_args.args[0];
2270 if (queue_priority_mapping[i][1] > lowest_priority) {
2271 lowest_priority = queue_priority_mapping[i][1];
2272 info->default_queue = i;
2273 }
2274 }
2275 }
2276
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002277 /* Event queue priority mapping */
2278 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
2279 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
2280 queue_priority_mapping[i][1]);
2281
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002282 for (i = 0; i < ecc->num_region; i++) {
2283 edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0);
2284 edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0);
2285 edma_write_array(ecc, EDMA_QRAE, i, 0x0);
2286 }
2287 ecc->info = info;
2288
Peter Ujfalusi02f77ef2015-10-16 10:18:05 +03002289 /* Init the dma device and channels */
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002290 edma_dma_init(ecc, legacy_mode);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002291
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03002292 for (i = 0; i < ecc->num_channels; i++) {
2293 /* Assign all channels to the default queue */
Peter Ujfalusif9425de2015-10-16 10:18:03 +03002294 edma_assign_channel_eventq(&ecc->slave_chans[i],
2295 info->default_queue);
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03002296 /* Set entry slot to the dummy slot */
2297 edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot);
2298 }
2299
Matt Porterc2dde5f2012-08-22 21:09:34 -04002300 ret = dma_async_device_register(&ecc->dma_slave);
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002301 if (ret) {
2302 dev_err(dev, "slave ddev registration failed (%d)\n", ret);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002303 goto err_reg1;
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002304 }
2305
2306 if (ecc->dma_memcpy) {
2307 ret = dma_async_device_register(ecc->dma_memcpy);
2308 if (ret) {
2309 dev_err(dev, "memcpy ddev registration failed (%d)\n",
2310 ret);
2311 dma_async_device_unregister(&ecc->dma_slave);
2312 goto err_reg1;
2313 }
2314 }
Matt Porterc2dde5f2012-08-22 21:09:34 -04002315
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002316 if (node)
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002317 of_dma_controller_register(node, of_edma_xlate, ecc);
Peter Ujfalusidc9b60552015-10-14 14:42:47 +03002318
Peter Ujfalusi907f74a2015-10-14 14:42:56 +03002319 dev_info(dev, "TI EDMA DMA engine driver\n");
Matt Porterc2dde5f2012-08-22 21:09:34 -04002320
2321 return 0;
2322
2323err_reg1:
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002324 edma_free_slot(ecc, ecc->dummy_slot);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002325 return ret;
2326}
2327
Greg Kroah-Hartman4bf27b82012-12-21 15:09:59 -08002328static int edma_remove(struct platform_device *pdev)
Matt Porterc2dde5f2012-08-22 21:09:34 -04002329{
2330 struct device *dev = &pdev->dev;
2331 struct edma_cc *ecc = dev_get_drvdata(dev);
2332
Peter Ujfalusi907f74a2015-10-14 14:42:56 +03002333 if (dev->of_node)
2334 of_dma_controller_free(dev->of_node);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002335 dma_async_device_unregister(&ecc->dma_slave);
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002336 if (ecc->dma_memcpy)
2337 dma_async_device_unregister(ecc->dma_memcpy);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002338 edma_free_slot(ecc, ecc->dummy_slot);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002339
2340 return 0;
2341}
2342
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002343#ifdef CONFIG_PM_SLEEP
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002344static int edma_pm_suspend(struct device *dev)
2345{
2346 struct edma_cc *ecc = dev_get_drvdata(dev);
2347 struct edma_chan *echan = ecc->slave_chans;
2348 int i;
2349
2350 for (i = 0; i < ecc->num_channels; i++) {
2351 if (echan[i].alloced) {
2352 edma_setup_interrupt(&echan[i], false);
2353 edma_tc_set_pm_state(echan[i].tc, false);
2354 }
2355 }
2356
2357 return 0;
2358}
2359
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002360static int edma_pm_resume(struct device *dev)
2361{
2362 struct edma_cc *ecc = dev_get_drvdata(dev);
Peter Ujfalusie4e886c2015-10-14 14:43:06 +03002363 struct edma_chan *echan = ecc->slave_chans;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002364 int i;
2365 s8 (*queue_priority_mapping)[2];
2366
2367 queue_priority_mapping = ecc->info->queue_priority_mapping;
2368
2369 /* Event queue priority mapping */
2370 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
2371 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
2372 queue_priority_mapping[i][1]);
2373
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002374 for (i = 0; i < ecc->num_channels; i++) {
Peter Ujfalusie4e886c2015-10-14 14:43:06 +03002375 if (echan[i].alloced) {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002376 /* ensure access through shadow region 0 */
2377 edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5,
2378 BIT(i & 0x1f));
2379
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03002380 edma_setup_interrupt(&echan[i], true);
Peter Ujfalusie4e886c2015-10-14 14:43:06 +03002381
2382 /* Set up channel -> slot mapping for the entry slot */
Peter Ujfalusi34cf3012015-10-16 10:18:01 +03002383 edma_set_chmap(&echan[i], echan[i].slot[0]);
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002384
2385 edma_tc_set_pm_state(echan[i].tc, true);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002386 }
2387 }
2388
2389 return 0;
2390}
2391#endif
2392
2393static const struct dev_pm_ops edma_pm_ops = {
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002394 SET_LATE_SYSTEM_SLEEP_PM_OPS(edma_pm_suspend, edma_pm_resume)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002395};
2396
Matt Porterc2dde5f2012-08-22 21:09:34 -04002397static struct platform_driver edma_driver = {
2398 .probe = edma_probe,
Bill Pembertona7d6e3e2012-11-19 13:20:04 -05002399 .remove = edma_remove,
Matt Porterc2dde5f2012-08-22 21:09:34 -04002400 .driver = {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002401 .name = "edma",
2402 .pm = &edma_pm_ops,
2403 .of_match_table = edma_of_ids,
Matt Porterc2dde5f2012-08-22 21:09:34 -04002404 },
2405};
2406
Peter Ujfalusi34635b1a2015-11-02 15:21:40 +02002407static struct platform_driver edma_tptc_driver = {
2408 .driver = {
2409 .name = "edma3-tptc",
2410 .of_match_table = edma_tptc_of_ids,
2411 },
2412};
2413
Matt Porterc2dde5f2012-08-22 21:09:34 -04002414bool edma_filter_fn(struct dma_chan *chan, void *param)
2415{
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002416 bool match = false;
2417
Matt Porterc2dde5f2012-08-22 21:09:34 -04002418 if (chan->device->dev->driver == &edma_driver.driver) {
2419 struct edma_chan *echan = to_edma_chan(chan);
2420 unsigned ch_req = *(unsigned *)param;
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002421 if (ch_req == echan->ch_num) {
2422 /* The channel is going to be used as HW synchronized */
2423 echan->hw_triggered = true;
2424 match = true;
2425 }
Matt Porterc2dde5f2012-08-22 21:09:34 -04002426 }
Peter Ujfalusi1be53362015-10-16 10:18:10 +03002427 return match;
Matt Porterc2dde5f2012-08-22 21:09:34 -04002428}
2429EXPORT_SYMBOL(edma_filter_fn);
2430
Matt Porterc2dde5f2012-08-22 21:09:34 -04002431static int edma_init(void)
2432{
Peter Ujfalusi34635b1a2015-11-02 15:21:40 +02002433 int ret;
2434
2435 ret = platform_driver_register(&edma_tptc_driver);
2436 if (ret)
2437 return ret;
2438
Arnd Bergmann5305e4d2014-10-24 18:14:01 +02002439 return platform_driver_register(&edma_driver);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002440}
2441subsys_initcall(edma_init);
2442
2443static void __exit edma_exit(void)
2444{
Matt Porterc2dde5f2012-08-22 21:09:34 -04002445 platform_driver_unregister(&edma_driver);
Peter Ujfalusi34635b1a2015-11-02 15:21:40 +02002446 platform_driver_unregister(&edma_tptc_driver);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002447}
2448module_exit(edma_exit);
2449
Josh Boyerd71505b2013-09-04 10:32:50 -04002450MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
Matt Porterc2dde5f2012-08-22 21:09:34 -04002451MODULE_DESCRIPTION("TI EDMA DMA engine driver");
2452MODULE_LICENSE("GPL v2");