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Matt Porterc2dde5f2012-08-22 21:09:34 -04001/*
2 * TI EDMA DMA engine driver
3 *
4 * Copyright 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/dmaengine.h>
17#include <linux/dma-mapping.h>
18#include <linux/err.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/list.h>
22#include <linux/module.h>
23#include <linux/platform_device.h>
24#include <linux/slab.h>
25#include <linux/spinlock.h>
Peter Ujfalusied646102014-07-31 13:12:38 +030026#include <linux/of.h>
Matt Porterc2dde5f2012-08-22 21:09:34 -040027
Matt Porter3ad7a422013-03-06 11:15:31 -050028#include <linux/platform_data/edma.h>
Matt Porterc2dde5f2012-08-22 21:09:34 -040029
30#include "dmaengine.h"
31#include "virt-dma.h"
32
33/*
34 * This will go away when the private EDMA API is folded
35 * into this driver and the platform device(s) are
36 * instantiated in the arch code. We can only get away
37 * with this simplification because DA8XX may not be built
38 * in the same kernel image with other DaVinci parts. This
39 * avoids having to sprinkle dmaengine driver platform devices
40 * and data throughout all the existing board files.
41 */
42#ifdef CONFIG_ARCH_DAVINCI_DA8XX
43#define EDMA_CTLRS 2
44#define EDMA_CHANS 32
45#else
46#define EDMA_CTLRS 1
47#define EDMA_CHANS 64
48#endif /* CONFIG_ARCH_DAVINCI_DA8XX */
49
Joel Fernandes2abd5f12013-09-23 18:05:15 -050050/*
51 * Max of 20 segments per channel to conserve PaRAM slots
52 * Also note that MAX_NR_SG should be atleast the no.of periods
53 * that are required for ASoC, otherwise DMA prep calls will
54 * fail. Today davinci-pcm is the only user of this driver and
55 * requires atleast 17 slots, so we setup the default to 20.
56 */
57#define MAX_NR_SG 20
Matt Porterc2dde5f2012-08-22 21:09:34 -040058#define EDMA_MAX_SLOTS MAX_NR_SG
59#define EDMA_DESCRIPTORS 16
60
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -050061struct edma_pset {
Thomas Gleixnerc2da2342014-04-28 14:29:57 -050062 u32 len;
63 dma_addr_t addr;
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -050064 struct edmacc_param param;
65};
66
Matt Porterc2dde5f2012-08-22 21:09:34 -040067struct edma_desc {
68 struct virt_dma_desc vdesc;
69 struct list_head node;
Thomas Gleixnerc2da2342014-04-28 14:29:57 -050070 enum dma_transfer_direction direction;
Joel Fernandes50a9c702013-10-31 16:31:23 -050071 int cyclic;
Matt Porterc2dde5f2012-08-22 21:09:34 -040072 int absync;
73 int pset_nr;
Thomas Gleixner740b41f2014-04-28 14:34:11 -050074 struct edma_chan *echan;
Joel Fernandes04361d82014-04-28 15:19:31 -050075 int processed;
76
77 /*
78 * The following 4 elements are used for residue accounting.
79 *
80 * - processed_stat: the number of SG elements we have traversed
81 * so far to cover accounting. This is updated directly to processed
82 * during edma_callback and is always <= processed, because processed
83 * refers to the number of pending transfer (programmed to EDMA
84 * controller), where as processed_stat tracks number of transfers
85 * accounted for so far.
86 *
87 * - residue: The amount of bytes we have left to transfer for this desc
88 *
89 * - residue_stat: The residue in bytes of data we have covered
90 * so far for accounting. This is updated directly to residue
91 * during callbacks to keep it current.
92 *
93 * - sg_len: Tracks the length of the current intermediate transfer,
94 * this is required to update the residue during intermediate transfer
95 * completion callback.
96 */
97 int processed_stat;
98 u32 sg_len;
99 u32 residue;
100 u32 residue_stat;
101
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500102 struct edma_pset pset[0];
Matt Porterc2dde5f2012-08-22 21:09:34 -0400103};
104
105struct edma_cc;
106
107struct edma_chan {
108 struct virt_dma_chan vchan;
109 struct list_head node;
110 struct edma_desc *edesc;
111 struct edma_cc *ecc;
112 int ch_num;
113 bool alloced;
114 int slot[EDMA_MAX_SLOTS];
Joel Fernandesc5f47992013-08-29 18:05:43 -0500115 int missed;
Matt Porter661f7cb2013-01-10 13:41:04 -0500116 struct dma_slave_config cfg;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400117};
118
119struct edma_cc {
120 int ctlr;
121 struct dma_device dma_slave;
122 struct edma_chan slave_chans[EDMA_CHANS];
123 int num_slave_chans;
124 int dummy_slot;
125};
126
127static inline struct edma_cc *to_edma_cc(struct dma_device *d)
128{
129 return container_of(d, struct edma_cc, dma_slave);
130}
131
132static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
133{
134 return container_of(c, struct edma_chan, vchan.chan);
135}
136
137static inline struct edma_desc
138*to_edma_desc(struct dma_async_tx_descriptor *tx)
139{
140 return container_of(tx, struct edma_desc, vdesc.tx);
141}
142
143static void edma_desc_free(struct virt_dma_desc *vdesc)
144{
145 kfree(container_of(vdesc, struct edma_desc, vdesc));
146}
147
148/* Dispatch a queued descriptor to the controller (caller holds lock) */
149static void edma_execute(struct edma_chan *echan)
150{
Joel Fernandes53407062013-09-03 10:02:46 -0500151 struct virt_dma_desc *vdesc;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400152 struct edma_desc *edesc;
Joel Fernandes53407062013-09-03 10:02:46 -0500153 struct device *dev = echan->vchan.chan.device->dev;
154 int i, j, left, nslots;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400155
Joel Fernandes53407062013-09-03 10:02:46 -0500156 /* If either we processed all psets or we're still not started */
157 if (!echan->edesc ||
158 echan->edesc->pset_nr == echan->edesc->processed) {
159 /* Get next vdesc */
160 vdesc = vchan_next_desc(&echan->vchan);
161 if (!vdesc) {
162 echan->edesc = NULL;
163 return;
164 }
165 list_del(&vdesc->node);
166 echan->edesc = to_edma_desc(&vdesc->tx);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400167 }
168
Joel Fernandes53407062013-09-03 10:02:46 -0500169 edesc = echan->edesc;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400170
Joel Fernandes53407062013-09-03 10:02:46 -0500171 /* Find out how many left */
172 left = edesc->pset_nr - edesc->processed;
173 nslots = min(MAX_NR_SG, left);
Thomas Gleixner740b41f2014-04-28 14:34:11 -0500174 edesc->sg_len = 0;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400175
176 /* Write descriptor PaRAM set(s) */
Joel Fernandes53407062013-09-03 10:02:46 -0500177 for (i = 0; i < nslots; i++) {
178 j = i + edesc->processed;
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500179 edma_write_slot(echan->slot[i], &edesc->pset[j].param);
Thomas Gleixner740b41f2014-04-28 14:34:11 -0500180 edesc->sg_len += edesc->pset[j].len;
Peter Ujfalusi83bb3122014-04-14 14:42:02 +0300181 dev_vdbg(echan->vchan.chan.device->dev,
Matt Porterc2dde5f2012-08-22 21:09:34 -0400182 "\n pset[%d]:\n"
183 " chnum\t%d\n"
184 " slot\t%d\n"
185 " opt\t%08x\n"
186 " src\t%08x\n"
187 " dst\t%08x\n"
188 " abcnt\t%08x\n"
189 " ccnt\t%08x\n"
190 " bidx\t%08x\n"
191 " cidx\t%08x\n"
192 " lkrld\t%08x\n",
Joel Fernandes53407062013-09-03 10:02:46 -0500193 j, echan->ch_num, echan->slot[i],
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500194 edesc->pset[j].param.opt,
195 edesc->pset[j].param.src,
196 edesc->pset[j].param.dst,
197 edesc->pset[j].param.a_b_cnt,
198 edesc->pset[j].param.ccnt,
199 edesc->pset[j].param.src_dst_bidx,
200 edesc->pset[j].param.src_dst_cidx,
201 edesc->pset[j].param.link_bcntrld);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400202 /* Link to the previous slot if not the last set */
Joel Fernandes53407062013-09-03 10:02:46 -0500203 if (i != (nslots - 1))
Matt Porterc2dde5f2012-08-22 21:09:34 -0400204 edma_link(echan->slot[i], echan->slot[i+1]);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400205 }
206
Joel Fernandes53407062013-09-03 10:02:46 -0500207 edesc->processed += nslots;
208
Joel Fernandesb267b3b2013-08-29 18:05:44 -0500209 /*
210 * If this is either the last set in a set of SG-list transactions
211 * then setup a link to the dummy slot, this results in all future
212 * events being absorbed and that's OK because we're done
213 */
Joel Fernandes50a9c702013-10-31 16:31:23 -0500214 if (edesc->processed == edesc->pset_nr) {
215 if (edesc->cyclic)
216 edma_link(echan->slot[nslots-1], echan->slot[1]);
217 else
218 edma_link(echan->slot[nslots-1],
219 echan->ecc->dummy_slot);
220 }
Joel Fernandesb267b3b2013-08-29 18:05:44 -0500221
Joel Fernandes53407062013-09-03 10:02:46 -0500222 if (edesc->processed <= MAX_NR_SG) {
Peter Ujfalusi9aac9092014-04-24 10:29:50 +0300223 dev_dbg(dev, "first transfer starting on channel %d\n",
224 echan->ch_num);
Joel Fernandes53407062013-09-03 10:02:46 -0500225 edma_start(echan->ch_num);
Sekhar Nori5fc68a62014-03-19 11:25:50 +0530226 } else {
227 dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
228 echan->ch_num, edesc->processed);
229 edma_resume(echan->ch_num);
Joel Fernandes53407062013-09-03 10:02:46 -0500230 }
Joel Fernandesc5f47992013-08-29 18:05:43 -0500231
232 /*
233 * This happens due to setup times between intermediate transfers
234 * in long SG lists which have to be broken up into transfers of
235 * MAX_NR_SG
236 */
237 if (echan->missed) {
Peter Ujfalusi9aac9092014-04-24 10:29:50 +0300238 dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
Joel Fernandesc5f47992013-08-29 18:05:43 -0500239 edma_clean_channel(echan->ch_num);
240 edma_stop(echan->ch_num);
241 edma_start(echan->ch_num);
242 edma_trigger_channel(echan->ch_num);
243 echan->missed = 0;
244 }
Matt Porterc2dde5f2012-08-22 21:09:34 -0400245}
246
247static int edma_terminate_all(struct edma_chan *echan)
248{
249 unsigned long flags;
250 LIST_HEAD(head);
251
252 spin_lock_irqsave(&echan->vchan.lock, flags);
253
254 /*
255 * Stop DMA activity: we assume the callback will not be called
256 * after edma_dma() returns (even if it does, it will see
257 * echan->edesc is NULL and exit.)
258 */
259 if (echan->edesc) {
Peter Ujfalusi8e8805d2014-07-08 13:46:38 +0300260 int cyclic = echan->edesc->cyclic;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400261 echan->edesc = NULL;
262 edma_stop(echan->ch_num);
Peter Ujfalusi8e8805d2014-07-08 13:46:38 +0300263 /* Move the cyclic channel back to default queue */
264 if (cyclic)
265 edma_assign_channel_eventq(echan->ch_num,
266 EVENTQ_DEFAULT);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400267 }
268
269 vchan_get_all_descriptors(&echan->vchan, &head);
270 spin_unlock_irqrestore(&echan->vchan.lock, flags);
271 vchan_dma_desc_free_list(&echan->vchan, &head);
272
273 return 0;
274}
275
Matt Porterc2dde5f2012-08-22 21:09:34 -0400276static int edma_slave_config(struct edma_chan *echan,
Matt Porter661f7cb2013-01-10 13:41:04 -0500277 struct dma_slave_config *cfg)
Matt Porterc2dde5f2012-08-22 21:09:34 -0400278{
Matt Porter661f7cb2013-01-10 13:41:04 -0500279 if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
280 cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
Matt Porterc2dde5f2012-08-22 21:09:34 -0400281 return -EINVAL;
282
Matt Porter661f7cb2013-01-10 13:41:04 -0500283 memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
Matt Porterc2dde5f2012-08-22 21:09:34 -0400284
285 return 0;
286}
287
Peter Ujfalusi72c7b672014-04-14 14:41:59 +0300288static int edma_dma_pause(struct edma_chan *echan)
289{
290 /* Pause/Resume only allowed with cyclic mode */
Sebastian Andrzej Siewior639559a2014-09-29 20:06:45 +0200291 if (!echan->edesc || !echan->edesc->cyclic)
Peter Ujfalusi72c7b672014-04-14 14:41:59 +0300292 return -EINVAL;
293
294 edma_pause(echan->ch_num);
295 return 0;
296}
297
298static int edma_dma_resume(struct edma_chan *echan)
299{
300 /* Pause/Resume only allowed with cyclic mode */
301 if (!echan->edesc->cyclic)
302 return -EINVAL;
303
304 edma_resume(echan->ch_num);
305 return 0;
306}
307
Matt Porterc2dde5f2012-08-22 21:09:34 -0400308static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
309 unsigned long arg)
310{
311 int ret = 0;
312 struct dma_slave_config *config;
313 struct edma_chan *echan = to_edma_chan(chan);
314
315 switch (cmd) {
316 case DMA_TERMINATE_ALL:
317 edma_terminate_all(echan);
318 break;
319 case DMA_SLAVE_CONFIG:
320 config = (struct dma_slave_config *)arg;
321 ret = edma_slave_config(echan, config);
322 break;
Peter Ujfalusi72c7b672014-04-14 14:41:59 +0300323 case DMA_PAUSE:
324 ret = edma_dma_pause(echan);
325 break;
326
327 case DMA_RESUME:
328 ret = edma_dma_resume(echan);
329 break;
330
Matt Porterc2dde5f2012-08-22 21:09:34 -0400331 default:
332 ret = -ENOSYS;
333 }
334
335 return ret;
336}
337
Joel Fernandesfd009032013-09-23 18:05:13 -0500338/*
339 * A PaRAM set configuration abstraction used by other modes
340 * @chan: Channel who's PaRAM set we're configuring
341 * @pset: PaRAM set to initialize and setup.
342 * @src_addr: Source address of the DMA
343 * @dst_addr: Destination address of the DMA
344 * @burst: In units of dev_width, how much to send
345 * @dev_width: How much is the dev_width
346 * @dma_length: Total length of the DMA transfer
347 * @direction: Direction of the transfer
348 */
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500349static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset,
Joel Fernandesfd009032013-09-23 18:05:13 -0500350 dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
351 enum dma_slave_buswidth dev_width, unsigned int dma_length,
352 enum dma_transfer_direction direction)
353{
354 struct edma_chan *echan = to_edma_chan(chan);
355 struct device *dev = chan->device->dev;
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500356 struct edmacc_param *param = &epset->param;
Joel Fernandesfd009032013-09-23 18:05:13 -0500357 int acnt, bcnt, ccnt, cidx;
358 int src_bidx, dst_bidx, src_cidx, dst_cidx;
359 int absync;
360
361 acnt = dev_width;
Peter Ujfalusib2b617d2014-04-14 14:41:58 +0300362
363 /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */
364 if (!burst)
365 burst = 1;
Joel Fernandesfd009032013-09-23 18:05:13 -0500366 /*
367 * If the maxburst is equal to the fifo width, use
368 * A-synced transfers. This allows for large contiguous
369 * buffer transfers using only one PaRAM set.
370 */
371 if (burst == 1) {
372 /*
373 * For the A-sync case, bcnt and ccnt are the remainder
374 * and quotient respectively of the division of:
375 * (dma_length / acnt) by (SZ_64K -1). This is so
376 * that in case bcnt over flows, we have ccnt to use.
377 * Note: In A-sync tranfer only, bcntrld is used, but it
378 * only applies for sg_dma_len(sg) >= SZ_64K.
379 * In this case, the best way adopted is- bccnt for the
380 * first frame will be the remainder below. Then for
381 * every successive frame, bcnt will be SZ_64K-1. This
382 * is assured as bcntrld = 0xffff in end of function.
383 */
384 absync = false;
385 ccnt = dma_length / acnt / (SZ_64K - 1);
386 bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
387 /*
388 * If bcnt is non-zero, we have a remainder and hence an
389 * extra frame to transfer, so increment ccnt.
390 */
391 if (bcnt)
392 ccnt++;
393 else
394 bcnt = SZ_64K - 1;
395 cidx = acnt;
396 } else {
397 /*
398 * If maxburst is greater than the fifo address_width,
399 * use AB-synced transfers where A count is the fifo
400 * address_width and B count is the maxburst. In this
401 * case, we are limited to transfers of C count frames
402 * of (address_width * maxburst) where C count is limited
403 * to SZ_64K-1. This places an upper bound on the length
404 * of an SG segment that can be handled.
405 */
406 absync = true;
407 bcnt = burst;
408 ccnt = dma_length / (acnt * bcnt);
409 if (ccnt > (SZ_64K - 1)) {
410 dev_err(dev, "Exceeded max SG segment size\n");
411 return -EINVAL;
412 }
413 cidx = acnt * bcnt;
414 }
415
Thomas Gleixnerc2da2342014-04-28 14:29:57 -0500416 epset->len = dma_length;
417
Joel Fernandesfd009032013-09-23 18:05:13 -0500418 if (direction == DMA_MEM_TO_DEV) {
419 src_bidx = acnt;
420 src_cidx = cidx;
421 dst_bidx = 0;
422 dst_cidx = 0;
Thomas Gleixnerc2da2342014-04-28 14:29:57 -0500423 epset->addr = src_addr;
Joel Fernandesfd009032013-09-23 18:05:13 -0500424 } else if (direction == DMA_DEV_TO_MEM) {
425 src_bidx = 0;
426 src_cidx = 0;
427 dst_bidx = acnt;
428 dst_cidx = cidx;
Thomas Gleixnerc2da2342014-04-28 14:29:57 -0500429 epset->addr = dst_addr;
Joel Fernandes8cc3e302014-04-18 21:50:33 -0500430 } else if (direction == DMA_MEM_TO_MEM) {
431 src_bidx = acnt;
432 src_cidx = cidx;
433 dst_bidx = acnt;
434 dst_cidx = cidx;
Joel Fernandesfd009032013-09-23 18:05:13 -0500435 } else {
436 dev_err(dev, "%s: direction not implemented yet\n", __func__);
437 return -EINVAL;
438 }
439
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500440 param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
Joel Fernandesfd009032013-09-23 18:05:13 -0500441 /* Configure A or AB synchronized transfers */
442 if (absync)
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500443 param->opt |= SYNCDIM;
Joel Fernandesfd009032013-09-23 18:05:13 -0500444
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500445 param->src = src_addr;
446 param->dst = dst_addr;
Joel Fernandesfd009032013-09-23 18:05:13 -0500447
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500448 param->src_dst_bidx = (dst_bidx << 16) | src_bidx;
449 param->src_dst_cidx = (dst_cidx << 16) | src_cidx;
Joel Fernandesfd009032013-09-23 18:05:13 -0500450
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500451 param->a_b_cnt = bcnt << 16 | acnt;
452 param->ccnt = ccnt;
Joel Fernandesfd009032013-09-23 18:05:13 -0500453 /*
454 * Only time when (bcntrld) auto reload is required is for
455 * A-sync case, and in this case, a requirement of reload value
456 * of SZ_64K-1 only is assured. 'link' is initially set to NULL
457 * and then later will be populated by edma_execute.
458 */
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500459 param->link_bcntrld = 0xffffffff;
Joel Fernandesfd009032013-09-23 18:05:13 -0500460 return absync;
461}
462
Matt Porterc2dde5f2012-08-22 21:09:34 -0400463static struct dma_async_tx_descriptor *edma_prep_slave_sg(
464 struct dma_chan *chan, struct scatterlist *sgl,
465 unsigned int sg_len, enum dma_transfer_direction direction,
466 unsigned long tx_flags, void *context)
467{
468 struct edma_chan *echan = to_edma_chan(chan);
469 struct device *dev = chan->device->dev;
470 struct edma_desc *edesc;
Joel Fernandesfd009032013-09-23 18:05:13 -0500471 dma_addr_t src_addr = 0, dst_addr = 0;
Matt Porter661f7cb2013-01-10 13:41:04 -0500472 enum dma_slave_buswidth dev_width;
473 u32 burst;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400474 struct scatterlist *sg;
Joel Fernandesfd009032013-09-23 18:05:13 -0500475 int i, nslots, ret;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400476
477 if (unlikely(!echan || !sgl || !sg_len))
478 return NULL;
479
Matt Porter661f7cb2013-01-10 13:41:04 -0500480 if (direction == DMA_DEV_TO_MEM) {
Joel Fernandesfd009032013-09-23 18:05:13 -0500481 src_addr = echan->cfg.src_addr;
Matt Porter661f7cb2013-01-10 13:41:04 -0500482 dev_width = echan->cfg.src_addr_width;
483 burst = echan->cfg.src_maxburst;
484 } else if (direction == DMA_MEM_TO_DEV) {
Joel Fernandesfd009032013-09-23 18:05:13 -0500485 dst_addr = echan->cfg.dst_addr;
Matt Porter661f7cb2013-01-10 13:41:04 -0500486 dev_width = echan->cfg.dst_addr_width;
487 burst = echan->cfg.dst_maxburst;
488 } else {
Peter Ujfalusie6fad592014-04-14 14:42:05 +0300489 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
Matt Porter661f7cb2013-01-10 13:41:04 -0500490 return NULL;
491 }
492
493 if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
Peter Ujfalusic594c892014-04-14 14:42:03 +0300494 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400495 return NULL;
496 }
497
Matt Porterc2dde5f2012-08-22 21:09:34 -0400498 edesc = kzalloc(sizeof(*edesc) + sg_len *
499 sizeof(edesc->pset[0]), GFP_ATOMIC);
500 if (!edesc) {
Peter Ujfalusic594c892014-04-14 14:42:03 +0300501 dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400502 return NULL;
503 }
504
505 edesc->pset_nr = sg_len;
Thomas Gleixnerb6205c32014-04-28 14:18:45 -0500506 edesc->residue = 0;
Thomas Gleixnerc2da2342014-04-28 14:29:57 -0500507 edesc->direction = direction;
Thomas Gleixner740b41f2014-04-28 14:34:11 -0500508 edesc->echan = echan;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400509
Joel Fernandes6fbe24d2013-08-29 18:05:40 -0500510 /* Allocate a PaRAM slot, if needed */
511 nslots = min_t(unsigned, MAX_NR_SG, sg_len);
512
513 for (i = 0; i < nslots; i++) {
Matt Porterc2dde5f2012-08-22 21:09:34 -0400514 if (echan->slot[i] < 0) {
515 echan->slot[i] =
516 edma_alloc_slot(EDMA_CTLR(echan->ch_num),
517 EDMA_SLOT_ANY);
518 if (echan->slot[i] < 0) {
Valentin Ilie4b6271a2013-10-24 16:14:22 +0300519 kfree(edesc);
Peter Ujfalusic594c892014-04-14 14:42:03 +0300520 dev_err(dev, "%s: Failed to allocate slot\n",
521 __func__);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400522 return NULL;
523 }
524 }
Joel Fernandes6fbe24d2013-08-29 18:05:40 -0500525 }
526
527 /* Configure PaRAM sets for each SG */
528 for_each_sg(sgl, sg, sg_len, i) {
Joel Fernandesfd009032013-09-23 18:05:13 -0500529 /* Get address for each SG */
530 if (direction == DMA_DEV_TO_MEM)
531 dst_addr = sg_dma_address(sg);
532 else
533 src_addr = sg_dma_address(sg);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400534
Joel Fernandesfd009032013-09-23 18:05:13 -0500535 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
536 dst_addr, burst, dev_width,
537 sg_dma_len(sg), direction);
Vinod Koulb967aec2013-10-30 13:07:18 +0530538 if (ret < 0) {
539 kfree(edesc);
Joel Fernandesfd009032013-09-23 18:05:13 -0500540 return NULL;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400541 }
542
Joel Fernandesfd009032013-09-23 18:05:13 -0500543 edesc->absync = ret;
Thomas Gleixnerb6205c32014-04-28 14:18:45 -0500544 edesc->residue += sg_dma_len(sg);
Joel Fernandes6fbe24d2013-08-29 18:05:40 -0500545
546 /* If this is the last in a current SG set of transactions,
547 enable interrupts so that next set is processed */
548 if (!((i+1) % MAX_NR_SG))
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500549 edesc->pset[i].param.opt |= TCINTEN;
Joel Fernandes6fbe24d2013-08-29 18:05:40 -0500550
Matt Porterc2dde5f2012-08-22 21:09:34 -0400551 /* If this is the last set, enable completion interrupt flag */
552 if (i == sg_len - 1)
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500553 edesc->pset[i].param.opt |= TCINTEN;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400554 }
Thomas Gleixner740b41f2014-04-28 14:34:11 -0500555 edesc->residue_stat = edesc->residue;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400556
Matt Porterc2dde5f2012-08-22 21:09:34 -0400557 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
558}
Matt Porterc2dde5f2012-08-22 21:09:34 -0400559
Joel Fernandes8cc3e302014-04-18 21:50:33 -0500560struct dma_async_tx_descriptor *edma_prep_dma_memcpy(
561 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
562 size_t len, unsigned long tx_flags)
563{
564 int ret;
565 struct edma_desc *edesc;
566 struct device *dev = chan->device->dev;
567 struct edma_chan *echan = to_edma_chan(chan);
568
569 if (unlikely(!echan || !len))
570 return NULL;
571
572 edesc = kzalloc(sizeof(*edesc) + sizeof(edesc->pset[0]), GFP_ATOMIC);
573 if (!edesc) {
574 dev_dbg(dev, "Failed to allocate a descriptor\n");
575 return NULL;
576 }
577
578 edesc->pset_nr = 1;
579
580 ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1,
581 DMA_SLAVE_BUSWIDTH_4_BYTES, len, DMA_MEM_TO_MEM);
582 if (ret < 0)
583 return NULL;
584
585 edesc->absync = ret;
586
587 /*
588 * Enable intermediate transfer chaining to re-trigger channel
589 * on completion of every TR, and enable transfer-completion
590 * interrupt on completion of the whole transfer.
591 */
Joel Fernandesb0cce4c2014-04-28 15:30:32 -0500592 edesc->pset[0].param.opt |= ITCCHEN;
593 edesc->pset[0].param.opt |= TCINTEN;
Joel Fernandes8cc3e302014-04-18 21:50:33 -0500594
595 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
596}
597
Joel Fernandes50a9c702013-10-31 16:31:23 -0500598static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
599 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
600 size_t period_len, enum dma_transfer_direction direction,
Laurent Pinchart31c1e5a2014-08-01 12:20:10 +0200601 unsigned long tx_flags)
Joel Fernandes50a9c702013-10-31 16:31:23 -0500602{
603 struct edma_chan *echan = to_edma_chan(chan);
604 struct device *dev = chan->device->dev;
605 struct edma_desc *edesc;
606 dma_addr_t src_addr, dst_addr;
607 enum dma_slave_buswidth dev_width;
608 u32 burst;
609 int i, ret, nslots;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400610
Joel Fernandes50a9c702013-10-31 16:31:23 -0500611 if (unlikely(!echan || !buf_len || !period_len))
612 return NULL;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400613
Joel Fernandes50a9c702013-10-31 16:31:23 -0500614 if (direction == DMA_DEV_TO_MEM) {
615 src_addr = echan->cfg.src_addr;
616 dst_addr = buf_addr;
617 dev_width = echan->cfg.src_addr_width;
618 burst = echan->cfg.src_maxburst;
619 } else if (direction == DMA_MEM_TO_DEV) {
620 src_addr = buf_addr;
621 dst_addr = echan->cfg.dst_addr;
622 dev_width = echan->cfg.dst_addr_width;
623 burst = echan->cfg.dst_maxburst;
624 } else {
Peter Ujfalusie6fad592014-04-14 14:42:05 +0300625 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500626 return NULL;
627 }
628
629 if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
Peter Ujfalusic594c892014-04-14 14:42:03 +0300630 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500631 return NULL;
632 }
633
634 if (unlikely(buf_len % period_len)) {
635 dev_err(dev, "Period should be multiple of Buffer length\n");
636 return NULL;
637 }
638
639 nslots = (buf_len / period_len) + 1;
640
641 /*
642 * Cyclic DMA users such as audio cannot tolerate delays introduced
643 * by cases where the number of periods is more than the maximum
644 * number of SGs the EDMA driver can handle at a time. For DMA types
645 * such as Slave SGs, such delays are tolerable and synchronized,
646 * but the synchronization is difficult to achieve with Cyclic and
647 * cannot be guaranteed, so we error out early.
648 */
649 if (nslots > MAX_NR_SG)
650 return NULL;
651
652 edesc = kzalloc(sizeof(*edesc) + nslots *
653 sizeof(edesc->pset[0]), GFP_ATOMIC);
654 if (!edesc) {
Peter Ujfalusic594c892014-04-14 14:42:03 +0300655 dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500656 return NULL;
657 }
658
659 edesc->cyclic = 1;
660 edesc->pset_nr = nslots;
Thomas Gleixner740b41f2014-04-28 14:34:11 -0500661 edesc->residue = edesc->residue_stat = buf_len;
Thomas Gleixnerc2da2342014-04-28 14:29:57 -0500662 edesc->direction = direction;
Thomas Gleixner740b41f2014-04-28 14:34:11 -0500663 edesc->echan = echan;
Joel Fernandes50a9c702013-10-31 16:31:23 -0500664
Peter Ujfalusi83bb3122014-04-14 14:42:02 +0300665 dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n",
666 __func__, echan->ch_num, nslots, period_len, buf_len);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500667
668 for (i = 0; i < nslots; i++) {
669 /* Allocate a PaRAM slot, if needed */
670 if (echan->slot[i] < 0) {
671 echan->slot[i] =
672 edma_alloc_slot(EDMA_CTLR(echan->ch_num),
673 EDMA_SLOT_ANY);
674 if (echan->slot[i] < 0) {
Christian Engelmayere3ddc972013-12-30 20:48:39 +0100675 kfree(edesc);
Peter Ujfalusic594c892014-04-14 14:42:03 +0300676 dev_err(dev, "%s: Failed to allocate slot\n",
677 __func__);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500678 return NULL;
679 }
680 }
681
682 if (i == nslots - 1) {
683 memcpy(&edesc->pset[i], &edesc->pset[0],
684 sizeof(edesc->pset[0]));
685 break;
686 }
687
688 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
689 dst_addr, burst, dev_width, period_len,
690 direction);
Christian Engelmayere3ddc972013-12-30 20:48:39 +0100691 if (ret < 0) {
692 kfree(edesc);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500693 return NULL;
Christian Engelmayere3ddc972013-12-30 20:48:39 +0100694 }
Joel Fernandes50a9c702013-10-31 16:31:23 -0500695
696 if (direction == DMA_DEV_TO_MEM)
697 dst_addr += period_len;
698 else
699 src_addr += period_len;
700
Peter Ujfalusi83bb3122014-04-14 14:42:02 +0300701 dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i);
702 dev_vdbg(dev,
Joel Fernandes50a9c702013-10-31 16:31:23 -0500703 "\n pset[%d]:\n"
704 " chnum\t%d\n"
705 " slot\t%d\n"
706 " opt\t%08x\n"
707 " src\t%08x\n"
708 " dst\t%08x\n"
709 " abcnt\t%08x\n"
710 " ccnt\t%08x\n"
711 " bidx\t%08x\n"
712 " cidx\t%08x\n"
713 " lkrld\t%08x\n",
714 i, echan->ch_num, echan->slot[i],
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500715 edesc->pset[i].param.opt,
716 edesc->pset[i].param.src,
717 edesc->pset[i].param.dst,
718 edesc->pset[i].param.a_b_cnt,
719 edesc->pset[i].param.ccnt,
720 edesc->pset[i].param.src_dst_bidx,
721 edesc->pset[i].param.src_dst_cidx,
722 edesc->pset[i].param.link_bcntrld);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500723
724 edesc->absync = ret;
725
726 /*
Peter Ujfalusia1f146f2014-07-16 15:29:21 +0300727 * Enable period interrupt only if it is requested
Joel Fernandes50a9c702013-10-31 16:31:23 -0500728 */
Peter Ujfalusia1f146f2014-07-16 15:29:21 +0300729 if (tx_flags & DMA_PREP_INTERRUPT)
730 edesc->pset[i].param.opt |= TCINTEN;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400731 }
732
Peter Ujfalusi8e8805d2014-07-08 13:46:38 +0300733 /* Place the cyclic channel to highest priority queue */
734 edma_assign_channel_eventq(echan->ch_num, EVENTQ_0);
735
Matt Porterc2dde5f2012-08-22 21:09:34 -0400736 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
737}
738
739static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
740{
741 struct edma_chan *echan = data;
742 struct device *dev = echan->vchan.chan.device->dev;
743 struct edma_desc *edesc;
Joel Fernandesc5f47992013-08-29 18:05:43 -0500744 struct edmacc_param p;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400745
Joel Fernandes50a9c702013-10-31 16:31:23 -0500746 edesc = echan->edesc;
747
748 /* Pause the channel for non-cyclic */
749 if (!edesc || (edesc && !edesc->cyclic))
750 edma_pause(echan->ch_num);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400751
752 switch (ch_status) {
Vinod Kouldb60d8d2013-10-30 18:22:30 +0530753 case EDMA_DMA_COMPLETE:
Joel Fernandes406efb12014-04-17 00:58:33 -0500754 spin_lock(&echan->vchan.lock);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400755
Matt Porterc2dde5f2012-08-22 21:09:34 -0400756 if (edesc) {
Joel Fernandes50a9c702013-10-31 16:31:23 -0500757 if (edesc->cyclic) {
758 vchan_cyclic_callback(&edesc->vdesc);
759 } else if (edesc->processed == edesc->pset_nr) {
Joel Fernandes53407062013-09-03 10:02:46 -0500760 dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num);
Thomas Gleixnerb6205c32014-04-28 14:18:45 -0500761 edesc->residue = 0;
Joel Fernandes53407062013-09-03 10:02:46 -0500762 edma_stop(echan->ch_num);
763 vchan_cookie_complete(&edesc->vdesc);
Joel Fernandes50a9c702013-10-31 16:31:23 -0500764 edma_execute(echan);
Joel Fernandes53407062013-09-03 10:02:46 -0500765 } else {
766 dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num);
Thomas Gleixner740b41f2014-04-28 14:34:11 -0500767
768 /* Update statistics for tx_status */
769 edesc->residue -= edesc->sg_len;
770 edesc->residue_stat = edesc->residue;
771 edesc->processed_stat = edesc->processed;
772
Joel Fernandes50a9c702013-10-31 16:31:23 -0500773 edma_execute(echan);
Joel Fernandes53407062013-09-03 10:02:46 -0500774 }
Matt Porterc2dde5f2012-08-22 21:09:34 -0400775 }
776
Joel Fernandes406efb12014-04-17 00:58:33 -0500777 spin_unlock(&echan->vchan.lock);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400778
779 break;
Vinod Kouldb60d8d2013-10-30 18:22:30 +0530780 case EDMA_DMA_CC_ERROR:
Joel Fernandes406efb12014-04-17 00:58:33 -0500781 spin_lock(&echan->vchan.lock);
Joel Fernandesc5f47992013-08-29 18:05:43 -0500782
783 edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p);
784
785 /*
786 * Issue later based on missed flag which will be sure
787 * to happen as:
788 * (1) we finished transmitting an intermediate slot and
789 * edma_execute is coming up.
790 * (2) or we finished current transfer and issue will
791 * call edma_execute.
792 *
793 * Important note: issuing can be dangerous here and
794 * lead to some nasty recursion when we are in a NULL
795 * slot. So we avoid doing so and set the missed flag.
796 */
797 if (p.a_b_cnt == 0 && p.ccnt == 0) {
798 dev_dbg(dev, "Error occurred, looks like slot is null, just setting miss\n");
799 echan->missed = 1;
800 } else {
801 /*
802 * The slot is already programmed but the event got
803 * missed, so its safe to issue it here.
804 */
805 dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n");
806 edma_clean_channel(echan->ch_num);
807 edma_stop(echan->ch_num);
808 edma_start(echan->ch_num);
809 edma_trigger_channel(echan->ch_num);
810 }
811
Joel Fernandes406efb12014-04-17 00:58:33 -0500812 spin_unlock(&echan->vchan.lock);
Joel Fernandesc5f47992013-08-29 18:05:43 -0500813
Matt Porterc2dde5f2012-08-22 21:09:34 -0400814 break;
815 default:
816 break;
817 }
818}
819
820/* Alloc channel resources */
821static int edma_alloc_chan_resources(struct dma_chan *chan)
822{
823 struct edma_chan *echan = to_edma_chan(chan);
824 struct device *dev = chan->device->dev;
825 int ret;
826 int a_ch_num;
827 LIST_HEAD(descs);
828
829 a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
830 chan, EVENTQ_DEFAULT);
831
832 if (a_ch_num < 0) {
833 ret = -ENODEV;
834 goto err_no_chan;
835 }
836
837 if (a_ch_num != echan->ch_num) {
838 dev_err(dev, "failed to allocate requested channel %u:%u\n",
839 EDMA_CTLR(echan->ch_num),
840 EDMA_CHAN_SLOT(echan->ch_num));
841 ret = -ENODEV;
842 goto err_wrong_chan;
843 }
844
845 echan->alloced = true;
846 echan->slot[0] = echan->ch_num;
847
Peter Ujfalusi9aac9092014-04-24 10:29:50 +0300848 dev_dbg(dev, "allocated channel %d for %u:%u\n", echan->ch_num,
Ezequiel Garcia0e772c62013-12-13 11:06:18 -0300849 EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num));
Matt Porterc2dde5f2012-08-22 21:09:34 -0400850
851 return 0;
852
853err_wrong_chan:
854 edma_free_channel(a_ch_num);
855err_no_chan:
856 return ret;
857}
858
859/* Free channel resources */
860static void edma_free_chan_resources(struct dma_chan *chan)
861{
862 struct edma_chan *echan = to_edma_chan(chan);
863 struct device *dev = chan->device->dev;
864 int i;
865
866 /* Terminate transfers */
867 edma_stop(echan->ch_num);
868
869 vchan_free_chan_resources(&echan->vchan);
870
871 /* Free EDMA PaRAM slots */
872 for (i = 1; i < EDMA_MAX_SLOTS; i++) {
873 if (echan->slot[i] >= 0) {
874 edma_free_slot(echan->slot[i]);
875 echan->slot[i] = -1;
876 }
877 }
878
879 /* Free EDMA channel */
880 if (echan->alloced) {
881 edma_free_channel(echan->ch_num);
882 echan->alloced = false;
883 }
884
Ezequiel Garcia0e772c62013-12-13 11:06:18 -0300885 dev_dbg(dev, "freeing channel for %u\n", echan->ch_num);
Matt Porterc2dde5f2012-08-22 21:09:34 -0400886}
887
888/* Send pending descriptor to hardware */
889static void edma_issue_pending(struct dma_chan *chan)
890{
891 struct edma_chan *echan = to_edma_chan(chan);
892 unsigned long flags;
893
894 spin_lock_irqsave(&echan->vchan.lock, flags);
895 if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
896 edma_execute(echan);
897 spin_unlock_irqrestore(&echan->vchan.lock, flags);
898}
899
Thomas Gleixner740b41f2014-04-28 14:34:11 -0500900static u32 edma_residue(struct edma_desc *edesc)
901{
902 bool dst = edesc->direction == DMA_DEV_TO_MEM;
903 struct edma_pset *pset = edesc->pset;
904 dma_addr_t done, pos;
905 int i;
906
907 /*
908 * We always read the dst/src position from the first RamPar
909 * pset. That's the one which is active now.
910 */
911 pos = edma_get_position(edesc->echan->slot[0], dst);
912
913 /*
914 * Cyclic is simple. Just subtract pset[0].addr from pos.
915 *
916 * We never update edesc->residue in the cyclic case, so we
917 * can tell the remaining room to the end of the circular
918 * buffer.
919 */
920 if (edesc->cyclic) {
921 done = pos - pset->addr;
922 edesc->residue_stat = edesc->residue - done;
923 return edesc->residue_stat;
924 }
925
926 /*
927 * For SG operation we catch up with the last processed
928 * status.
929 */
930 pset += edesc->processed_stat;
931
932 for (i = edesc->processed_stat; i < edesc->processed; i++, pset++) {
933 /*
934 * If we are inside this pset address range, we know
935 * this is the active one. Get the current delta and
936 * stop walking the psets.
937 */
938 if (pos >= pset->addr && pos < pset->addr + pset->len)
939 return edesc->residue_stat - (pos - pset->addr);
940
941 /* Otherwise mark it done and update residue_stat. */
942 edesc->processed_stat++;
943 edesc->residue_stat -= pset->len;
944 }
945 return edesc->residue_stat;
946}
947
Matt Porterc2dde5f2012-08-22 21:09:34 -0400948/* Check request completion status */
949static enum dma_status edma_tx_status(struct dma_chan *chan,
950 dma_cookie_t cookie,
951 struct dma_tx_state *txstate)
952{
953 struct edma_chan *echan = to_edma_chan(chan);
954 struct virt_dma_desc *vdesc;
955 enum dma_status ret;
956 unsigned long flags;
957
958 ret = dma_cookie_status(chan, cookie, txstate);
Vinod Koul9d386ec2013-10-16 13:42:15 +0530959 if (ret == DMA_COMPLETE || !txstate)
Matt Porterc2dde5f2012-08-22 21:09:34 -0400960 return ret;
961
962 spin_lock_irqsave(&echan->vchan.lock, flags);
Thomas Gleixnerde135932014-04-28 14:19:51 -0500963 if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie)
Thomas Gleixner740b41f2014-04-28 14:34:11 -0500964 txstate->residue = edma_residue(echan->edesc);
Thomas Gleixnerde135932014-04-28 14:19:51 -0500965 else if ((vdesc = vchan_find_desc(&echan->vchan, cookie)))
966 txstate->residue = to_edma_desc(&vdesc->tx)->residue;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400967 spin_unlock_irqrestore(&echan->vchan.lock, flags);
968
969 return ret;
970}
971
972static void __init edma_chan_init(struct edma_cc *ecc,
973 struct dma_device *dma,
974 struct edma_chan *echans)
975{
976 int i, j;
977
978 for (i = 0; i < EDMA_CHANS; i++) {
979 struct edma_chan *echan = &echans[i];
980 echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i);
981 echan->ecc = ecc;
982 echan->vchan.desc_free = edma_desc_free;
983
984 vchan_init(&echan->vchan, dma);
985
986 INIT_LIST_HEAD(&echan->node);
987 for (j = 0; j < EDMA_MAX_SLOTS; j++)
988 echan->slot[j] = -1;
989 }
990}
991
Peter Ujfalusi2c88ee62014-04-14 14:42:01 +0300992#define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
993 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
Peter Ujfalusie4a899d2014-07-03 07:51:56 +0300994 BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
Peter Ujfalusi2c88ee62014-04-14 14:42:01 +0300995 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
996
997static int edma_dma_device_slave_caps(struct dma_chan *dchan,
998 struct dma_slave_caps *caps)
999{
1000 caps->src_addr_widths = EDMA_DMA_BUSWIDTHS;
1001 caps->dstn_addr_widths = EDMA_DMA_BUSWIDTHS;
1002 caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1003 caps->cmd_pause = true;
1004 caps->cmd_terminate = true;
Peter Ujfalusib7f9bc52014-07-16 15:29:20 +03001005 caps->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
Peter Ujfalusi2c88ee62014-04-14 14:42:01 +03001006
1007 return 0;
1008}
1009
Matt Porterc2dde5f2012-08-22 21:09:34 -04001010static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
1011 struct device *dev)
1012{
1013 dma->device_prep_slave_sg = edma_prep_slave_sg;
Joel Fernandes50a9c702013-10-31 16:31:23 -05001014 dma->device_prep_dma_cyclic = edma_prep_dma_cyclic;
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001015 dma->device_prep_dma_memcpy = edma_prep_dma_memcpy;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001016 dma->device_alloc_chan_resources = edma_alloc_chan_resources;
1017 dma->device_free_chan_resources = edma_free_chan_resources;
1018 dma->device_issue_pending = edma_issue_pending;
1019 dma->device_tx_status = edma_tx_status;
1020 dma->device_control = edma_control;
Peter Ujfalusi2c88ee62014-04-14 14:42:01 +03001021 dma->device_slave_caps = edma_dma_device_slave_caps;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001022 dma->dev = dev;
1023
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001024 /*
1025 * code using dma memcpy must make sure alignment of
1026 * length is at dma->copy_align boundary.
1027 */
1028 dma->copy_align = DMA_SLAVE_BUSWIDTH_4_BYTES;
1029
Matt Porterc2dde5f2012-08-22 21:09:34 -04001030 INIT_LIST_HEAD(&dma->channels);
1031}
1032
Bill Pemberton463a1f82012-11-19 13:22:55 -05001033static int edma_probe(struct platform_device *pdev)
Matt Porterc2dde5f2012-08-22 21:09:34 -04001034{
1035 struct edma_cc *ecc;
1036 int ret;
1037
Russell King94cb0e72013-06-27 13:45:16 +01001038 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1039 if (ret)
1040 return ret;
1041
Matt Porterc2dde5f2012-08-22 21:09:34 -04001042 ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL);
1043 if (!ecc) {
1044 dev_err(&pdev->dev, "Can't allocate controller\n");
1045 return -ENOMEM;
1046 }
1047
1048 ecc->ctlr = pdev->id;
1049 ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY);
1050 if (ecc->dummy_slot < 0) {
1051 dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
Peter Ujfalusi04d537d2014-07-31 13:12:37 +03001052 return ecc->dummy_slot;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001053 }
1054
1055 dma_cap_zero(ecc->dma_slave.cap_mask);
1056 dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
Peter Ujfalusi232b223d2014-04-14 14:42:00 +03001057 dma_cap_set(DMA_CYCLIC, ecc->dma_slave.cap_mask);
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001058 dma_cap_set(DMA_MEMCPY, ecc->dma_slave.cap_mask);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001059
1060 edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev);
1061
1062 edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans);
1063
1064 ret = dma_async_device_register(&ecc->dma_slave);
1065 if (ret)
1066 goto err_reg1;
1067
1068 platform_set_drvdata(pdev, ecc);
1069
1070 dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
1071
1072 return 0;
1073
1074err_reg1:
1075 edma_free_slot(ecc->dummy_slot);
1076 return ret;
1077}
1078
Greg Kroah-Hartman4bf27b82012-12-21 15:09:59 -08001079static int edma_remove(struct platform_device *pdev)
Matt Porterc2dde5f2012-08-22 21:09:34 -04001080{
1081 struct device *dev = &pdev->dev;
1082 struct edma_cc *ecc = dev_get_drvdata(dev);
1083
1084 dma_async_device_unregister(&ecc->dma_slave);
1085 edma_free_slot(ecc->dummy_slot);
1086
1087 return 0;
1088}
1089
1090static struct platform_driver edma_driver = {
1091 .probe = edma_probe,
Bill Pembertona7d6e3e2012-11-19 13:20:04 -05001092 .remove = edma_remove,
Matt Porterc2dde5f2012-08-22 21:09:34 -04001093 .driver = {
1094 .name = "edma-dma-engine",
1095 .owner = THIS_MODULE,
1096 },
1097};
1098
1099bool edma_filter_fn(struct dma_chan *chan, void *param)
1100{
1101 if (chan->device->dev->driver == &edma_driver.driver) {
1102 struct edma_chan *echan = to_edma_chan(chan);
1103 unsigned ch_req = *(unsigned *)param;
1104 return ch_req == echan->ch_num;
1105 }
1106 return false;
1107}
1108EXPORT_SYMBOL(edma_filter_fn);
1109
Matt Porterc2dde5f2012-08-22 21:09:34 -04001110static int edma_init(void)
1111{
Arnd Bergmann5305e4d2014-10-24 18:14:01 +02001112 return platform_driver_register(&edma_driver);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001113}
1114subsys_initcall(edma_init);
1115
1116static void __exit edma_exit(void)
1117{
Matt Porterc2dde5f2012-08-22 21:09:34 -04001118 platform_driver_unregister(&edma_driver);
1119}
1120module_exit(edma_exit);
1121
Josh Boyerd71505b2013-09-04 10:32:50 -04001122MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
Matt Porterc2dde5f2012-08-22 21:09:34 -04001123MODULE_DESCRIPTION("TI EDMA DMA engine driver");
1124MODULE_LICENSE("GPL v2");