Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 1 | /* |
Robert Richter | 6852fd9 | 2008-07-22 21:09:08 +0200 | [diff] [blame] | 2 | * @file op_model_amd.c |
Barry Kasindorf | bd87f1f | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 3 | * athlon / K7 / K8 / Family 10h model-specific MSR operations |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * |
Robert Richter | ae735e9 | 2008-12-25 17:26:07 +0100 | [diff] [blame] | 5 | * @remark Copyright 2002-2009 OProfile authors |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * @remark Read the file COPYING |
| 7 | * |
| 8 | * @author John Levon |
| 9 | * @author Philippe Elie |
| 10 | * @author Graydon Hoare |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 11 | * @author Robert Richter <robert.richter@amd.com> |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 12 | * @author Barry Kasindorf <barry.kasindorf@amd.com> |
| 13 | * @author Jason Yeh <jason.yeh@amd.com> |
| 14 | * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> |
Robert Richter | ae735e9 | 2008-12-25 17:26:07 +0100 | [diff] [blame] | 15 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | |
| 17 | #include <linux/oprofile.h> |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 18 | #include <linux/device.h> |
| 19 | #include <linux/pci.h> |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 20 | #include <linux/percpu.h> |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 21 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | #include <asm/ptrace.h> |
| 23 | #include <asm/msr.h> |
Don Zickus | 3e4ff11 | 2006-06-26 13:57:01 +0200 | [diff] [blame] | 24 | #include <asm/nmi.h> |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 25 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 26 | #include "op_x86_model.h" |
| 27 | #include "op_counter.h" |
| 28 | |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 29 | #define NUM_COUNTERS 4 |
| 30 | #define NUM_CONTROLS 4 |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 31 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
| 32 | #define NUM_VIRT_COUNTERS 32 |
| 33 | #define NUM_VIRT_CONTROLS 32 |
| 34 | #else |
| 35 | #define NUM_VIRT_COUNTERS NUM_COUNTERS |
| 36 | #define NUM_VIRT_CONTROLS NUM_CONTROLS |
| 37 | #endif |
| 38 | |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 39 | #define OP_EVENT_MASK 0x0FFF |
Robert Richter | 42399ad | 2009-05-25 17:59:06 +0200 | [diff] [blame] | 40 | #define OP_CTR_OVERFLOW (1ULL<<31) |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 41 | |
| 42 | #define MSR_AMD_EVENTSEL_RESERVED ((0xFFFFFCF0ULL<<32)|(1ULL<<21)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 44 | static unsigned long reset_value[NUM_VIRT_COUNTERS]; |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 45 | |
| 46 | #ifdef CONFIG_OPROFILE_IBS |
| 47 | |
Robert Richter | 87f0bac | 2008-07-22 21:09:03 +0200 | [diff] [blame] | 48 | /* IbsFetchCtl bits/masks */ |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 49 | #define IBS_FETCH_RAND_EN (1ULL<<57) |
| 50 | #define IBS_FETCH_VAL (1ULL<<49) |
| 51 | #define IBS_FETCH_ENABLE (1ULL<<48) |
| 52 | #define IBS_FETCH_CNT_MASK 0xFFFF0000ULL |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 53 | |
Robert Richter | 87f0bac | 2008-07-22 21:09:03 +0200 | [diff] [blame] | 54 | /*IbsOpCtl bits */ |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 55 | #define IBS_OP_CNT_CTL (1ULL<<19) |
| 56 | #define IBS_OP_VAL (1ULL<<18) |
| 57 | #define IBS_OP_ENABLE (1ULL<<17) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 58 | |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 59 | #define IBS_FETCH_SIZE 6 |
| 60 | #define IBS_OP_SIZE 12 |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 61 | |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 62 | static int has_ibs; /* AMD Family10h and later */ |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 63 | |
| 64 | struct op_ibs_config { |
| 65 | unsigned long op_enabled; |
| 66 | unsigned long fetch_enabled; |
| 67 | unsigned long max_cnt_fetch; |
| 68 | unsigned long max_cnt_op; |
| 69 | unsigned long rand_en; |
| 70 | unsigned long dispatched_ops; |
| 71 | }; |
| 72 | |
| 73 | static struct op_ibs_config ibs_config; |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 74 | |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 75 | #endif |
| 76 | |
Robert Richter | 7e7478c | 2009-07-16 13:09:53 +0200 | [diff] [blame] | 77 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
| 78 | |
| 79 | static void op_mux_fill_in_addresses(struct op_msrs * const msrs) |
| 80 | { |
| 81 | int i; |
| 82 | |
| 83 | for (i = 0; i < NUM_VIRT_COUNTERS; i++) { |
| 84 | int hw_counter = i % NUM_COUNTERS; |
| 85 | if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i)) |
| 86 | msrs->multiplex[i].addr = MSR_K7_PERFCTR0 + hw_counter; |
| 87 | else |
| 88 | msrs->multiplex[i].addr = 0; |
| 89 | } |
| 90 | } |
| 91 | |
| 92 | static void op_mux_switch_ctrl(struct op_x86_model_spec const *model, |
| 93 | struct op_msrs const * const msrs) |
| 94 | { |
| 95 | u64 val; |
| 96 | int i; |
| 97 | |
| 98 | /* enable active counters */ |
| 99 | for (i = 0; i < NUM_COUNTERS; ++i) { |
| 100 | int virt = op_x86_phys_to_virt(i); |
| 101 | if (!counter_config[virt].enabled) |
| 102 | continue; |
| 103 | rdmsrl(msrs->controls[i].addr, val); |
| 104 | val &= model->reserved; |
| 105 | val |= op_x86_get_ctrl(model, &counter_config[virt]); |
| 106 | wrmsrl(msrs->controls[i].addr, val); |
| 107 | } |
| 108 | } |
| 109 | |
| 110 | #else |
| 111 | |
| 112 | static inline void op_mux_fill_in_addresses(struct op_msrs * const msrs) { } |
| 113 | |
| 114 | #endif |
| 115 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 116 | /* functions for op_amd_spec */ |
Robert Richter | dfa1542 | 2008-07-22 21:08:49 +0200 | [diff] [blame] | 117 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 118 | static void op_amd_fill_in_addresses(struct op_msrs * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 119 | { |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 120 | int i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 121 | |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 122 | for (i = 0; i < NUM_COUNTERS; i++) { |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 123 | if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i)) |
| 124 | msrs->counters[i].addr = MSR_K7_PERFCTR0 + i; |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 125 | else |
| 126 | msrs->counters[i].addr = 0; |
| 127 | } |
| 128 | |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 129 | for (i = 0; i < NUM_CONTROLS; i++) { |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 130 | if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) |
| 131 | msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i; |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 132 | else |
| 133 | msrs->controls[i].addr = 0; |
| 134 | } |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 135 | |
Robert Richter | 7e7478c | 2009-07-16 13:09:53 +0200 | [diff] [blame] | 136 | op_mux_fill_in_addresses(msrs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 137 | } |
| 138 | |
Robert Richter | ef8828d | 2009-05-25 19:31:44 +0200 | [diff] [blame] | 139 | static void op_amd_setup_ctrs(struct op_x86_model_spec const *model, |
| 140 | struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 141 | { |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 142 | u64 val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 143 | int i; |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 144 | |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 145 | /* setup reset_value */ |
| 146 | for (i = 0; i < NUM_VIRT_COUNTERS; ++i) { |
| 147 | if (counter_config[i].enabled) { |
| 148 | reset_value[i] = counter_config[i].count; |
| 149 | } else { |
| 150 | reset_value[i] = 0; |
| 151 | } |
| 152 | } |
| 153 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 154 | /* clear all counters */ |
Robert Richter | 6e63ea4 | 2009-07-07 19:25:39 +0200 | [diff] [blame] | 155 | for (i = 0; i < NUM_CONTROLS; ++i) { |
Robert Richter | 217d3cf | 2009-06-04 02:36:44 +0200 | [diff] [blame] | 156 | if (unlikely(!msrs->controls[i].addr)) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 157 | continue; |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 158 | rdmsrl(msrs->controls[i].addr, val); |
| 159 | val &= model->reserved; |
| 160 | wrmsrl(msrs->controls[i].addr, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 161 | } |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 162 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 163 | /* avoid a false detection of ctr overflows in NMI handler */ |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 164 | for (i = 0; i < NUM_COUNTERS; ++i) { |
Robert Richter | 217d3cf | 2009-06-04 02:36:44 +0200 | [diff] [blame] | 165 | if (unlikely(!msrs->counters[i].addr)) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 166 | continue; |
Robert Richter | bbc5986 | 2009-05-25 17:38:19 +0200 | [diff] [blame] | 167 | wrmsrl(msrs->counters[i].addr, -1LL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 168 | } |
| 169 | |
| 170 | /* enable active counters */ |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 171 | for (i = 0; i < NUM_COUNTERS; ++i) { |
Robert Richter | d8471ad | 2009-07-16 13:04:43 +0200 | [diff] [blame] | 172 | int virt = op_x86_phys_to_virt(i); |
| 173 | if (!counter_config[virt].enabled) |
| 174 | continue; |
| 175 | if (!msrs->counters[i].addr) |
| 176 | continue; |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 177 | |
Robert Richter | d8471ad | 2009-07-16 13:04:43 +0200 | [diff] [blame] | 178 | /* setup counter registers */ |
| 179 | wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]); |
| 180 | |
| 181 | /* setup control registers */ |
| 182 | rdmsrl(msrs->controls[i].addr, val); |
| 183 | val &= model->reserved; |
| 184 | val |= op_x86_get_ctrl(model, &counter_config[virt]); |
| 185 | wrmsrl(msrs->controls[i].addr, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 186 | } |
| 187 | } |
| 188 | |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 189 | #ifdef CONFIG_OPROFILE_IBS |
| 190 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 191 | static inline int |
| 192 | op_amd_handle_ibs(struct pt_regs * const regs, |
| 193 | struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 194 | { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 195 | u64 val, ctl; |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 196 | struct op_entry entry; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 197 | |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 198 | if (!has_ibs) |
Jaswinder Singh Rajput | 21e7087 | 2009-06-18 17:09:27 +0530 | [diff] [blame] | 199 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 200 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 201 | if (ibs_config.fetch_enabled) { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 202 | rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl); |
| 203 | if (ctl & IBS_FETCH_VAL) { |
| 204 | rdmsrl(MSR_AMD64_IBSFETCHLINAD, val); |
| 205 | oprofile_write_reserve(&entry, regs, val, |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 206 | IBS_FETCH_CODE, IBS_FETCH_SIZE); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 207 | oprofile_add_data64(&entry, val); |
| 208 | oprofile_add_data64(&entry, ctl); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 209 | rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 210 | oprofile_add_data64(&entry, val); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 211 | oprofile_write_commit(&entry); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 212 | |
Robert Richter | fd13f6c | 2008-10-19 21:00:09 +0200 | [diff] [blame] | 213 | /* reenable the IRQ */ |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 214 | ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT_MASK); |
| 215 | ctl |= IBS_FETCH_ENABLE; |
| 216 | wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 217 | } |
| 218 | } |
| 219 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 220 | if (ibs_config.op_enabled) { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 221 | rdmsrl(MSR_AMD64_IBSOPCTL, ctl); |
| 222 | if (ctl & IBS_OP_VAL) { |
| 223 | rdmsrl(MSR_AMD64_IBSOPRIP, val); |
| 224 | oprofile_write_reserve(&entry, regs, val, |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 225 | IBS_OP_CODE, IBS_OP_SIZE); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 226 | oprofile_add_data64(&entry, val); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 227 | rdmsrl(MSR_AMD64_IBSOPDATA, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 228 | oprofile_add_data64(&entry, val); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 229 | rdmsrl(MSR_AMD64_IBSOPDATA2, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 230 | oprofile_add_data64(&entry, val); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 231 | rdmsrl(MSR_AMD64_IBSOPDATA3, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 232 | oprofile_add_data64(&entry, val); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 233 | rdmsrl(MSR_AMD64_IBSDCLINAD, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 234 | oprofile_add_data64(&entry, val); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 235 | rdmsrl(MSR_AMD64_IBSDCPHYSAD, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 236 | oprofile_add_data64(&entry, val); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 237 | oprofile_write_commit(&entry); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 238 | |
| 239 | /* reenable the IRQ */ |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 240 | ctl &= ~IBS_OP_VAL & 0xFFFFFFFF; |
| 241 | ctl |= IBS_OP_ENABLE; |
| 242 | wrmsrl(MSR_AMD64_IBSOPCTL, ctl); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 243 | } |
| 244 | } |
| 245 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 246 | return 1; |
| 247 | } |
| 248 | |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 249 | static inline void op_amd_start_ibs(void) |
| 250 | { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 251 | u64 val; |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 252 | if (has_ibs && ibs_config.fetch_enabled) { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 253 | val = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF; |
| 254 | val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0; |
| 255 | val |= IBS_FETCH_ENABLE; |
| 256 | wrmsrl(MSR_AMD64_IBSFETCHCTL, val); |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 257 | } |
| 258 | |
| 259 | if (has_ibs && ibs_config.op_enabled) { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 260 | val = (ibs_config.max_cnt_op >> 4) & 0xFFFF; |
| 261 | val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0; |
| 262 | val |= IBS_OP_ENABLE; |
| 263 | wrmsrl(MSR_AMD64_IBSOPCTL, val); |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 264 | } |
| 265 | } |
| 266 | |
| 267 | static void op_amd_stop_ibs(void) |
| 268 | { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 269 | if (has_ibs && ibs_config.fetch_enabled) |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 270 | /* clear max count and enable */ |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 271 | wrmsrl(MSR_AMD64_IBSFETCHCTL, 0); |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 272 | |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 273 | if (has_ibs && ibs_config.op_enabled) |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 274 | /* clear max count and enable */ |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 275 | wrmsrl(MSR_AMD64_IBSOPCTL, 0); |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 276 | } |
| 277 | |
| 278 | #else |
| 279 | |
| 280 | static inline int op_amd_handle_ibs(struct pt_regs * const regs, |
Jaswinder Singh Rajput | 21e7087 | 2009-06-18 17:09:27 +0530 | [diff] [blame] | 281 | struct op_msrs const * const msrs) |
| 282 | { |
| 283 | return 0; |
| 284 | } |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 285 | static inline void op_amd_start_ibs(void) { } |
| 286 | static inline void op_amd_stop_ibs(void) { } |
| 287 | |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 288 | #endif |
| 289 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 290 | static int op_amd_check_ctrs(struct pt_regs * const regs, |
| 291 | struct op_msrs const * const msrs) |
| 292 | { |
Robert Richter | 42399ad | 2009-05-25 17:59:06 +0200 | [diff] [blame] | 293 | u64 val; |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 294 | int i; |
| 295 | |
Robert Richter | 6e63ea4 | 2009-07-07 19:25:39 +0200 | [diff] [blame] | 296 | for (i = 0; i < NUM_COUNTERS; ++i) { |
Robert Richter | d8471ad | 2009-07-16 13:04:43 +0200 | [diff] [blame] | 297 | int virt = op_x86_phys_to_virt(i); |
| 298 | if (!reset_value[virt]) |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 299 | continue; |
Robert Richter | 42399ad | 2009-05-25 17:59:06 +0200 | [diff] [blame] | 300 | rdmsrl(msrs->counters[i].addr, val); |
| 301 | /* bit is clear if overflowed: */ |
| 302 | if (val & OP_CTR_OVERFLOW) |
| 303 | continue; |
Robert Richter | d8471ad | 2009-07-16 13:04:43 +0200 | [diff] [blame] | 304 | oprofile_add_sample(regs, virt); |
| 305 | wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]); |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 306 | } |
| 307 | |
| 308 | op_amd_handle_ibs(regs, msrs); |
| 309 | |
| 310 | /* See op_model_ppro.c */ |
| 311 | return 1; |
| 312 | } |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 313 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 314 | static void op_amd_start(struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 315 | { |
Robert Richter | dea3766 | 2009-05-25 18:11:52 +0200 | [diff] [blame] | 316 | u64 val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 317 | int i; |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 318 | |
Robert Richter | 6e63ea4 | 2009-07-07 19:25:39 +0200 | [diff] [blame] | 319 | for (i = 0; i < NUM_COUNTERS; ++i) { |
Robert Richter | d8471ad | 2009-07-16 13:04:43 +0200 | [diff] [blame] | 320 | if (!reset_value[op_x86_phys_to_virt(i)]) |
| 321 | continue; |
| 322 | rdmsrl(msrs->controls[i].addr, val); |
| 323 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; |
| 324 | wrmsrl(msrs->controls[i].addr, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 325 | } |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 326 | |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 327 | op_amd_start_ibs(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 328 | } |
| 329 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 330 | static void op_amd_stop(struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 331 | { |
Robert Richter | dea3766 | 2009-05-25 18:11:52 +0200 | [diff] [blame] | 332 | u64 val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 333 | int i; |
| 334 | |
Robert Richter | fd13f6c | 2008-10-19 21:00:09 +0200 | [diff] [blame] | 335 | /* |
| 336 | * Subtle: stop on all counters to avoid race with setting our |
| 337 | * pm callback |
| 338 | */ |
Robert Richter | 6e63ea4 | 2009-07-07 19:25:39 +0200 | [diff] [blame] | 339 | for (i = 0; i < NUM_COUNTERS; ++i) { |
Robert Richter | d8471ad | 2009-07-16 13:04:43 +0200 | [diff] [blame] | 340 | if (!reset_value[op_x86_phys_to_virt(i)]) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 341 | continue; |
Robert Richter | dea3766 | 2009-05-25 18:11:52 +0200 | [diff] [blame] | 342 | rdmsrl(msrs->controls[i].addr, val); |
| 343 | val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; |
| 344 | wrmsrl(msrs->controls[i].addr, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 345 | } |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 346 | |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 347 | op_amd_stop_ibs(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 348 | } |
| 349 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 350 | static void op_amd_shutdown(struct op_msrs const * const msrs) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 351 | { |
| 352 | int i; |
| 353 | |
Robert Richter | 6e63ea4 | 2009-07-07 19:25:39 +0200 | [diff] [blame] | 354 | for (i = 0; i < NUM_COUNTERS; ++i) { |
Robert Richter | 217d3cf | 2009-06-04 02:36:44 +0200 | [diff] [blame] | 355 | if (msrs->counters[i].addr) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 356 | release_perfctr_nmi(MSR_K7_PERFCTR0 + i); |
| 357 | } |
Robert Richter | 5e766e3 | 2009-07-08 14:54:17 +0200 | [diff] [blame] | 358 | for (i = 0; i < NUM_CONTROLS; ++i) { |
Robert Richter | 217d3cf | 2009-06-04 02:36:44 +0200 | [diff] [blame] | 359 | if (msrs->controls[i].addr) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 360 | release_evntsel_nmi(MSR_K7_EVNTSEL0 + i); |
| 361 | } |
| 362 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 363 | |
Robert Richter | 9fa6812 | 2008-11-24 14:21:03 +0100 | [diff] [blame] | 364 | #ifdef CONFIG_OPROFILE_IBS |
Robert Richter | a4c408a | 2008-07-22 21:09:02 +0200 | [diff] [blame] | 365 | |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 366 | static u8 ibs_eilvt_off; |
| 367 | |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 368 | static inline void apic_init_ibs_nmi_per_cpu(void *arg) |
| 369 | { |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 370 | ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 371 | } |
| 372 | |
| 373 | static inline void apic_clear_ibs_nmi_per_cpu(void *arg) |
| 374 | { |
| 375 | setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1); |
| 376 | } |
| 377 | |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 378 | static int init_ibs_nmi(void) |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 379 | { |
| 380 | #define IBSCTL_LVTOFFSETVAL (1 << 8) |
| 381 | #define IBSCTL 0x1cc |
| 382 | struct pci_dev *cpu_cfg; |
| 383 | int nodes; |
| 384 | u32 value = 0; |
| 385 | |
| 386 | /* per CPU setup */ |
Robert Richter | ebb535d | 2008-07-22 21:08:59 +0200 | [diff] [blame] | 387 | on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1); |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 388 | |
| 389 | nodes = 0; |
| 390 | cpu_cfg = NULL; |
| 391 | do { |
| 392 | cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD, |
| 393 | PCI_DEVICE_ID_AMD_10H_NB_MISC, |
| 394 | cpu_cfg); |
| 395 | if (!cpu_cfg) |
| 396 | break; |
| 397 | ++nodes; |
| 398 | pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off |
| 399 | | IBSCTL_LVTOFFSETVAL); |
| 400 | pci_read_config_dword(cpu_cfg, IBSCTL, &value); |
| 401 | if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) { |
Robert Richter | 83bd924 | 2008-12-15 15:09:50 +0100 | [diff] [blame] | 402 | pci_dev_put(cpu_cfg); |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 403 | printk(KERN_DEBUG "Failed to setup IBS LVT offset, " |
| 404 | "IBSCTL = 0x%08x", value); |
| 405 | return 1; |
| 406 | } |
| 407 | } while (1); |
| 408 | |
| 409 | if (!nodes) { |
| 410 | printk(KERN_DEBUG "No CPU node configured for IBS"); |
| 411 | return 1; |
| 412 | } |
| 413 | |
| 414 | #ifdef CONFIG_NUMA |
| 415 | /* Sanity check */ |
| 416 | /* Works only for 64bit with proper numa implementation. */ |
| 417 | if (nodes != num_possible_nodes()) { |
| 418 | printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, " |
| 419 | "found: %d, expected %d", |
| 420 | nodes, num_possible_nodes()); |
| 421 | return 1; |
| 422 | } |
| 423 | #endif |
| 424 | return 0; |
| 425 | } |
| 426 | |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 427 | /* uninitialize the APIC for the IBS interrupts if needed */ |
| 428 | static void clear_ibs_nmi(void) |
| 429 | { |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 430 | if (has_ibs) |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 431 | on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1); |
| 432 | } |
| 433 | |
Robert Richter | fd13f6c | 2008-10-19 21:00:09 +0200 | [diff] [blame] | 434 | /* initialize the APIC for the IBS interrupts if available */ |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 435 | static void ibs_init(void) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 436 | { |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 437 | has_ibs = boot_cpu_has(X86_FEATURE_IBS); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 438 | |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 439 | if (!has_ibs) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 440 | return; |
| 441 | |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 442 | if (init_ibs_nmi()) { |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 443 | has_ibs = 0; |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 444 | return; |
| 445 | } |
| 446 | |
| 447 | printk(KERN_INFO "oprofile: AMD IBS detected\n"); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 448 | } |
| 449 | |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 450 | static void ibs_exit(void) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 451 | { |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 452 | if (!has_ibs) |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 453 | return; |
| 454 | |
| 455 | clear_ibs_nmi(); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 456 | } |
| 457 | |
Robert Richter | 25ad2913 | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 458 | static int (*create_arch_files)(struct super_block *sb, struct dentry *root); |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 459 | |
Robert Richter | 25ad2913 | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 460 | static int setup_ibs_files(struct super_block *sb, struct dentry *root) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 461 | { |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 462 | struct dentry *dir; |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 463 | int ret = 0; |
| 464 | |
| 465 | /* architecture specific files */ |
| 466 | if (create_arch_files) |
| 467 | ret = create_arch_files(sb, root); |
| 468 | |
| 469 | if (ret) |
| 470 | return ret; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 471 | |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 472 | if (!has_ibs) |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 473 | return ret; |
| 474 | |
| 475 | /* model specific files */ |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 476 | |
| 477 | /* setup some reasonable defaults */ |
| 478 | ibs_config.max_cnt_fetch = 250000; |
| 479 | ibs_config.fetch_enabled = 0; |
| 480 | ibs_config.max_cnt_op = 250000; |
| 481 | ibs_config.op_enabled = 0; |
| 482 | ibs_config.dispatched_ops = 1; |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 483 | |
| 484 | dir = oprofilefs_mkdir(sb, root, "ibs_fetch"); |
| 485 | oprofilefs_create_ulong(sb, dir, "enable", |
| 486 | &ibs_config.fetch_enabled); |
| 487 | oprofilefs_create_ulong(sb, dir, "max_count", |
| 488 | &ibs_config.max_cnt_fetch); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 489 | oprofilefs_create_ulong(sb, dir, "rand_enable", |
| 490 | &ibs_config.rand_en); |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 491 | |
Robert Richter | ccd755c | 2008-07-29 16:57:10 +0200 | [diff] [blame] | 492 | dir = oprofilefs_mkdir(sb, root, "ibs_op"); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 493 | oprofilefs_create_ulong(sb, dir, "enable", |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 494 | &ibs_config.op_enabled); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 495 | oprofilefs_create_ulong(sb, dir, "max_count", |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 496 | &ibs_config.max_cnt_op); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 497 | oprofilefs_create_ulong(sb, dir, "dispatched_ops", |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 498 | &ibs_config.dispatched_ops); |
Robert Richter | fc2bd73 | 2008-07-22 21:09:00 +0200 | [diff] [blame] | 499 | |
| 500 | return 0; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 501 | } |
| 502 | |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 503 | static int op_amd_init(struct oprofile_operations *ops) |
| 504 | { |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 505 | ibs_init(); |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 506 | create_arch_files = ops->create_files; |
| 507 | ops->create_files = setup_ibs_files; |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 508 | return 0; |
| 509 | } |
| 510 | |
| 511 | static void op_amd_exit(void) |
| 512 | { |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 513 | ibs_exit(); |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 514 | } |
| 515 | |
Robert Richter | 9fa6812 | 2008-11-24 14:21:03 +0100 | [diff] [blame] | 516 | #else |
| 517 | |
| 518 | /* no IBS support */ |
| 519 | |
| 520 | static int op_amd_init(struct oprofile_operations *ops) |
| 521 | { |
| 522 | return 0; |
| 523 | } |
| 524 | |
| 525 | static void op_amd_exit(void) {} |
| 526 | |
| 527 | #endif /* CONFIG_OPROFILE_IBS */ |
Robert Richter | a4c408a | 2008-07-22 21:09:02 +0200 | [diff] [blame] | 528 | |
Robert Richter | 259a83a | 2009-07-09 15:12:35 +0200 | [diff] [blame^] | 529 | struct op_x86_model_spec op_amd_spec = { |
Robert Richter | c92960f | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 530 | .num_counters = NUM_COUNTERS, |
| 531 | .num_controls = NUM_CONTROLS, |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 532 | .num_virt_counters = NUM_VIRT_COUNTERS, |
| 533 | .num_virt_controls = NUM_VIRT_CONTROLS, |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 534 | .reserved = MSR_AMD_EVENTSEL_RESERVED, |
| 535 | .event_mask = OP_EVENT_MASK, |
| 536 | .init = op_amd_init, |
| 537 | .exit = op_amd_exit, |
Robert Richter | c92960f | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 538 | .fill_in_addresses = &op_amd_fill_in_addresses, |
| 539 | .setup_ctrs = &op_amd_setup_ctrs, |
| 540 | .check_ctrs = &op_amd_check_ctrs, |
| 541 | .start = &op_amd_start, |
| 542 | .stop = &op_amd_stop, |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 543 | .shutdown = &op_amd_shutdown, |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 544 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
Robert Richter | 7e7478c | 2009-07-16 13:09:53 +0200 | [diff] [blame] | 545 | .switch_ctrl = &op_mux_switch_ctrl, |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 546 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 547 | }; |