blob: 73fe71f5555d2de36d59bef4ae4be1f80bc25201 [file] [log] [blame]
Linus Walleij2744e8a2011-05-02 20:50:54 +02001PINCTRL (PIN CONTROL) subsystem
2This document outlines the pin control subsystem in Linux
3
4This subsystem deals with:
5
6- Enumerating and naming controllable pins
7
8- Multiplexing of pins, pads, fingers (etc) see below for details
9
Linus Walleijae6b4d82011-10-19 18:14:33 +020010- Configuration of pins, pads, fingers (etc), such as software-controlled
11 biasing and driving mode specific pins, such as pull-up/down, open drain,
12 load capacitance etc.
Linus Walleij2744e8a2011-05-02 20:50:54 +020013
14Top-level interface
15===================
16
17Definition of PIN CONTROLLER:
18
19- A pin controller is a piece of hardware, usually a set of registers, that
20 can control PINs. It may be able to multiplex, bias, set load capacitance,
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +000021 set drive strength, etc. for individual pins or groups of pins.
Linus Walleij2744e8a2011-05-02 20:50:54 +020022
23Definition of PIN:
24
25- PINS are equal to pads, fingers, balls or whatever packaging input or
26 output line you want to control and these are denoted by unsigned integers
27 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
28 there may be several such number spaces in a system. This pin space may
29 be sparse - i.e. there may be gaps in the space with numbers where no
30 pin exists.
31
Linus Walleij336cdba02011-11-10 09:27:41 +010032When a PIN CONTROLLER is instantiated, it will register a descriptor to the
Linus Walleij2744e8a2011-05-02 20:50:54 +020033pin control framework, and this descriptor contains an array of pin descriptors
34describing the pins handled by this specific pin controller.
35
36Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
37
38 A B C D E F G H
39
40 8 o o o o o o o o
41
42 7 o o o o o o o o
43
44 6 o o o o o o o o
45
46 5 o o o o o o o o
47
48 4 o o o o o o o o
49
50 3 o o o o o o o o
51
52 2 o o o o o o o o
53
54 1 o o o o o o o o
55
56To register a pin controller and name all the pins on this package we can do
57this in our driver:
58
59#include <linux/pinctrl/pinctrl.h>
60
Linus Walleij336cdba02011-11-10 09:27:41 +010061const struct pinctrl_pin_desc foo_pins[] = {
62 PINCTRL_PIN(0, "A8"),
63 PINCTRL_PIN(1, "B8"),
64 PINCTRL_PIN(2, "C8"),
Linus Walleij2744e8a2011-05-02 20:50:54 +020065 ...
Linus Walleij336cdba02011-11-10 09:27:41 +010066 PINCTRL_PIN(61, "F1"),
67 PINCTRL_PIN(62, "G1"),
68 PINCTRL_PIN(63, "H1"),
Linus Walleij2744e8a2011-05-02 20:50:54 +020069};
70
71static struct pinctrl_desc foo_desc = {
72 .name = "foo",
73 .pins = foo_pins,
74 .npins = ARRAY_SIZE(foo_pins),
Linus Walleij2744e8a2011-05-02 20:50:54 +020075 .owner = THIS_MODULE,
76};
77
78int __init foo_probe(void)
79{
80 struct pinctrl_dev *pctl;
81
82 pctl = pinctrl_register(&foo_desc, <PARENT>, NULL);
Axel Line2b86b82013-08-18 20:43:33 +080083 if (!pctl)
Linus Walleij2744e8a2011-05-02 20:50:54 +020084 pr_err("could not register foo pin driver\n");
85}
86
Linus Walleijae6b4d82011-10-19 18:14:33 +020087To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
88selected drivers, you need to select them from your machine's Kconfig entry,
89since these are so tightly integrated with the machines they are used on.
90See for example arch/arm/mach-u300/Kconfig for an example.
91
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +000092Pins usually have fancier names than this. You can find these in the datasheet
Linus Walleij2744e8a2011-05-02 20:50:54 +020093for your chip. Notice that the core pinctrl.h file provides a fancy macro
94called PINCTRL_PIN() to create the struct entries. As you can see I enumerated
Linus Walleij336cdba02011-11-10 09:27:41 +010095the pins from 0 in the upper left corner to 63 in the lower right corner.
96This enumeration was arbitrarily chosen, in practice you need to think
Linus Walleij2744e8a2011-05-02 20:50:54 +020097through your numbering system so that it matches the layout of registers
98and such things in your driver, or the code may become complicated. You must
99also consider matching of offsets to the GPIO ranges that may be handled by
100the pin controller.
101
102For a padring with 467 pads, as opposed to actual pins, I used an enumeration
103like this, walking around the edge of the chip, which seems to be industry
104standard too (all these pads had names, too):
105
106
107 0 ..... 104
108 466 105
109 . .
110 . .
111 358 224
112 357 .... 225
113
114
115Pin groups
116==========
117
118Many controllers need to deal with groups of pins, so the pin controller
119subsystem has a mechanism for enumerating groups of pins and retrieving the
120actual enumerated pins that are part of a certain group.
121
122For example, say that we have a group of pins dealing with an SPI interface
123on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
124on { 24, 25 }.
125
126These two groups are presented to the pin control subsystem by implementing
127some generic pinctrl_ops like this:
128
129#include <linux/pinctrl/pinctrl.h>
130
131struct foo_group {
132 const char *name;
133 const unsigned int *pins;
134 const unsigned num_pins;
135};
136
Linus Walleij336cdba02011-11-10 09:27:41 +0100137static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
138static const unsigned int i2c0_pins[] = { 24, 25 };
Linus Walleij2744e8a2011-05-02 20:50:54 +0200139
140static const struct foo_group foo_groups[] = {
141 {
142 .name = "spi0_grp",
143 .pins = spi0_pins,
144 .num_pins = ARRAY_SIZE(spi0_pins),
145 },
146 {
147 .name = "i2c0_grp",
148 .pins = i2c0_pins,
149 .num_pins = ARRAY_SIZE(i2c0_pins),
150 },
151};
152
153
Viresh Kumard1e90e92012-03-30 11:25:40 +0530154static int foo_get_groups_count(struct pinctrl_dev *pctldev)
Linus Walleij2744e8a2011-05-02 20:50:54 +0200155{
Viresh Kumard1e90e92012-03-30 11:25:40 +0530156 return ARRAY_SIZE(foo_groups);
Linus Walleij2744e8a2011-05-02 20:50:54 +0200157}
158
159static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
160 unsigned selector)
161{
162 return foo_groups[selector].name;
163}
164
165static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
166 unsigned ** const pins,
167 unsigned * const num_pins)
168{
169 *pins = (unsigned *) foo_groups[selector].pins;
170 *num_pins = foo_groups[selector].num_pins;
171 return 0;
172}
173
174static struct pinctrl_ops foo_pctrl_ops = {
Viresh Kumard1e90e92012-03-30 11:25:40 +0530175 .get_groups_count = foo_get_groups_count,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200176 .get_group_name = foo_get_group_name,
177 .get_group_pins = foo_get_group_pins,
178};
179
180
181static struct pinctrl_desc foo_desc = {
182 ...
183 .pctlops = &foo_pctrl_ops,
184};
185
Viresh Kumard1e90e92012-03-30 11:25:40 +0530186The pin control subsystem will call the .get_groups_count() function to
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000187determine the total number of legal selectors, then it will call the other functions
Viresh Kumard1e90e92012-03-30 11:25:40 +0530188to retrieve the name and pins of the group. Maintaining the data structure of
189the groups is up to the driver, this is just a simple example - in practice you
190may need more entries in your group structure, for example specific register
191ranges associated with each group and so on.
Linus Walleij2744e8a2011-05-02 20:50:54 +0200192
193
Linus Walleijae6b4d82011-10-19 18:14:33 +0200194Pin configuration
195=================
196
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000197Pins can sometimes be software-configured in various ways, mostly related
Linus Walleijae6b4d82011-10-19 18:14:33 +0200198to their electronic properties when used as inputs or outputs. For example you
199may be able to make an output pin high impedance, or "tristate" meaning it is
200effectively disconnected. You may be able to connect an input pin to VDD or GND
201using a certain resistor value - pull up and pull down - so that the pin has a
202stable value when nothing is driving the rail it is connected to, or when it's
203unconnected.
204
Linus Walleijad42fc62013-06-24 15:06:19 +0200205Pin configuration can be programmed by adding configuration entries into the
206mapping table; see section "Board/machine configuration" below.
Linus Walleijae6b4d82011-10-19 18:14:33 +0200207
Stephen Warren1e2082b2012-03-02 13:05:48 -0700208The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
209above, is entirely defined by the pin controller driver.
210
211The pin configuration driver implements callbacks for changing pin
212configuration in the pin controller ops like this:
Linus Walleijae6b4d82011-10-19 18:14:33 +0200213
214#include <linux/pinctrl/pinctrl.h>
215#include <linux/pinctrl/pinconf.h>
216#include "platform_x_pindefs.h"
217
Dong Aishenge6337c32011-12-20 17:51:59 +0800218static int foo_pin_config_get(struct pinctrl_dev *pctldev,
Linus Walleijae6b4d82011-10-19 18:14:33 +0200219 unsigned offset,
220 unsigned long *config)
221{
222 struct my_conftype conf;
223
224 ... Find setting for pin @ offset ...
225
226 *config = (unsigned long) conf;
227}
228
Dong Aishenge6337c32011-12-20 17:51:59 +0800229static int foo_pin_config_set(struct pinctrl_dev *pctldev,
Linus Walleijae6b4d82011-10-19 18:14:33 +0200230 unsigned offset,
231 unsigned long config)
232{
233 struct my_conftype *conf = (struct my_conftype *) config;
234
235 switch (conf) {
236 case PLATFORM_X_PULL_UP:
237 ...
238 }
239 }
240}
241
Dong Aishenge6337c32011-12-20 17:51:59 +0800242static int foo_pin_config_group_get (struct pinctrl_dev *pctldev,
Linus Walleijae6b4d82011-10-19 18:14:33 +0200243 unsigned selector,
244 unsigned long *config)
245{
246 ...
247}
248
Dong Aishenge6337c32011-12-20 17:51:59 +0800249static int foo_pin_config_group_set (struct pinctrl_dev *pctldev,
Linus Walleijae6b4d82011-10-19 18:14:33 +0200250 unsigned selector,
251 unsigned long config)
252{
253 ...
254}
255
256static struct pinconf_ops foo_pconf_ops = {
257 .pin_config_get = foo_pin_config_get,
258 .pin_config_set = foo_pin_config_set,
259 .pin_config_group_get = foo_pin_config_group_get,
260 .pin_config_group_set = foo_pin_config_group_set,
261};
262
263/* Pin config operations are handled by some pin controller */
264static struct pinctrl_desc foo_desc = {
265 ...
266 .confops = &foo_pconf_ops,
267};
268
269Since some controllers have special logic for handling entire groups of pins
270they can exploit the special whole-group pin control function. The
271pin_config_group_set() callback is allowed to return the error code -EAGAIN,
272for groups it does not want to handle, or if it just wants to do some
273group-level handling and then fall through to iterate over all pins, in which
274case each individual pin will be treated by separate pin_config_set() calls as
275well.
276
277
Linus Walleij2744e8a2011-05-02 20:50:54 +0200278Interaction with the GPIO subsystem
279===================================
280
281The GPIO drivers may want to perform operations of various types on the same
282physical pins that are also registered as pin controller pins.
283
Linus Walleijc31a00c2012-09-10 17:22:00 +0200284First and foremost, the two subsystems can be used as completely orthogonal,
285see the section named "pin control requests from drivers" and
286"drivers needing both pin control and GPIOs" below for details. But in some
287situations a cross-subsystem mapping between pins and GPIOs is needed.
288
Linus Walleij2744e8a2011-05-02 20:50:54 +0200289Since the pin controller subsystem have its pinspace local to the pin
290controller we need a mapping so that the pin control subsystem can figure out
291which pin controller handles control of a certain GPIO pin. Since a single
292pin controller may be muxing several GPIO ranges (typically SoCs that have
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000293one set of pins, but internally several GPIO silicon blocks, each modelled as
Linus Walleij2744e8a2011-05-02 20:50:54 +0200294a struct gpio_chip) any number of GPIO ranges can be added to a pin controller
295instance like this:
296
297struct gpio_chip chip_a;
298struct gpio_chip chip_b;
299
300static struct pinctrl_gpio_range gpio_range_a = {
301 .name = "chip a",
302 .id = 0,
303 .base = 32,
Chanho Park3c739ad2011-11-11 18:47:58 +0900304 .pin_base = 32,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200305 .npins = 16,
306 .gc = &chip_a;
307};
308
Chanho Park3c739ad2011-11-11 18:47:58 +0900309static struct pinctrl_gpio_range gpio_range_b = {
Linus Walleij2744e8a2011-05-02 20:50:54 +0200310 .name = "chip b",
311 .id = 0,
312 .base = 48,
Chanho Park3c739ad2011-11-11 18:47:58 +0900313 .pin_base = 64,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200314 .npins = 8,
315 .gc = &chip_b;
316};
317
Linus Walleij2744e8a2011-05-02 20:50:54 +0200318{
319 struct pinctrl_dev *pctl;
320 ...
321 pinctrl_add_gpio_range(pctl, &gpio_range_a);
322 pinctrl_add_gpio_range(pctl, &gpio_range_b);
323}
324
325So this complex system has one pin controller handling two different
Chanho Park3c739ad2011-11-11 18:47:58 +0900326GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
327"chip b" have different .pin_base, which means a start pin number of the
328GPIO range.
Linus Walleij2744e8a2011-05-02 20:50:54 +0200329
Chanho Park3c739ad2011-11-11 18:47:58 +0900330The GPIO range of "chip a" starts from the GPIO base of 32 and actual
331pin range also starts from 32. However "chip b" has different starting
332offset for the GPIO range and pin range. The GPIO range of "chip b" starts
333from GPIO number 48, while the pin range of "chip b" starts from 64.
334
335We can convert a gpio number to actual pin number using this "pin_base".
336They are mapped in the global GPIO pin space at:
337
338chip a:
339 - GPIO range : [32 .. 47]
340 - pin range : [32 .. 47]
341chip b:
342 - GPIO range : [48 .. 55]
343 - pin range : [64 .. 71]
Linus Walleij2744e8a2011-05-02 20:50:54 +0200344
Linus Walleij30cf8212013-06-16 12:15:36 +0200345The above examples assume the mapping between the GPIOs and pins is
346linear. If the mapping is sparse or haphazard, an array of arbitrary pin
347numbers can be encoded in the range like this:
348
349static const unsigned range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 };
350
351static struct pinctrl_gpio_range gpio_range = {
352 .name = "chip",
353 .id = 0,
354 .base = 32,
355 .pins = &range_pins,
356 .npins = ARRAY_SIZE(range_pins),
357 .gc = &chip;
358};
359
Christian Ruppertfe610522013-10-16 14:56:54 +0200360In this case the pin_base property will be ignored. If the name of a pin
361group is known, the pins and npins elements of the above structure can be
362initialised using the function pinctrl_get_group_pins(), e.g. for pin
363group "foo":
364
365pinctrl_get_group_pins(pctl, "foo", &gpio_range.pins, &gpio_range.npins);
Linus Walleij30cf8212013-06-16 12:15:36 +0200366
Linus Walleij2744e8a2011-05-02 20:50:54 +0200367When GPIO-specific functions in the pin control subsystem are called, these
Linus Walleij336cdba02011-11-10 09:27:41 +0100368ranges will be used to look up the appropriate pin controller by inspecting
Linus Walleij2744e8a2011-05-02 20:50:54 +0200369and matching the pin to the pin ranges across all controllers. When a
370pin controller handling the matching range is found, GPIO-specific functions
371will be called on that specific pin controller.
372
373For all functionalities dealing with pin biasing, pin muxing etc, the pin
Linus Walleij30cf8212013-06-16 12:15:36 +0200374controller subsystem will look up the corresponding pin number from the passed
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000375in gpio number, and use the range's internals to retrieve a pin number. After
Linus Walleij30cf8212013-06-16 12:15:36 +0200376that, the subsystem passes it on to the pin control driver, so the driver
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000377will get a pin number into its handled number range. Further it is also passed
Linus Walleij2744e8a2011-05-02 20:50:54 +0200378the range ID value, so that the pin controller knows which range it should
379deal with.
380
Shiraz Hashimf23f1512012-10-27 15:21:36 +0530381Calling pinctrl_add_gpio_range from pinctrl driver is DEPRECATED. Please see
382section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind
383pinctrl and gpio drivers.
Linus Walleijc31a00c2012-09-10 17:22:00 +0200384
Linus Walleij30cf8212013-06-16 12:15:36 +0200385
Linus Walleij2744e8a2011-05-02 20:50:54 +0200386PINMUX interfaces
387=================
388
389These calls use the pinmux_* naming prefix. No other calls should use that
390prefix.
391
392
393What is pinmuxing?
394==================
395
396PINMUX, also known as padmux, ballmux, alternate functions or mission modes
397is a way for chip vendors producing some kind of electrical packages to use
398a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
399functions, depending on the application. By "application" in this context
400we usually mean a way of soldering or wiring the package into an electronic
401system, even though the framework makes it possible to also change the function
402at runtime.
403
404Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
405
406 A B C D E F G H
407 +---+
408 8 | o | o o o o o o o
409 | |
410 7 | o | o o o o o o o
411 | |
412 6 | o | o o o o o o o
413 +---+---+
414 5 | o | o | o o o o o o
415 +---+---+ +---+
416 4 o o o o o o | o | o
417 | |
418 3 o o o o o o | o | o
419 | |
420 2 o o o o o o | o | o
421 +-------+-------+-------+---+---+
422 1 | o o | o o | o o | o | o |
423 +-------+-------+-------+---+---+
424
425This is not tetris. The game to think of is chess. Not all PGA/BGA packages
426are chessboard-like, big ones have "holes" in some arrangement according to
427different design patterns, but we're using this as a simple example. Of the
428pins you see some will be taken by things like a few VCC and GND to feed power
429to the chip, and quite a few will be taken by large ports like an external
430memory interface. The remaining pins will often be subject to pin multiplexing.
431
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000432The example 8x8 PGA package above will have pin numbers 0 through 63 assigned
433to its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
Linus Walleij2744e8a2011-05-02 20:50:54 +0200434pinctrl_register_pins() and a suitable data set as shown earlier.
435
436In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
437(these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
438some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
439be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
440we cannot use the SPI port and I2C port at the same time. However in the inside
441of the package the silicon performing the SPI logic can alternatively be routed
442out on pins { G4, G3, G2, G1 }.
443
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000444On the bottom row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
Linus Walleij2744e8a2011-05-02 20:50:54 +0200445special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
446consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
447{ A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
448port on pins { G4, G3, G2, G1 } of course.
449
450This way the silicon blocks present inside the chip can be multiplexed "muxed"
451out on different pin ranges. Often contemporary SoC (systems on chip) will
452contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
453different pins by pinmux settings.
454
455Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
456common to be able to use almost any pin as a GPIO pin if it is not currently
457in use by some other I/O port.
458
459
460Pinmux conventions
461==================
462
463The purpose of the pinmux functionality in the pin controller subsystem is to
464abstract and provide pinmux settings to the devices you choose to instantiate
465in your machine configuration. It is inspired by the clk, GPIO and regulator
466subsystems, so devices will request their mux setting, but it's also possible
467to request a single pin for e.g. GPIO.
468
469Definitions:
470
471- FUNCTIONS can be switched in and out by a driver residing with the pin
472 control subsystem in the drivers/pinctrl/* directory of the kernel. The
473 pin control driver knows the possible functions. In the example above you can
474 identify three pinmux functions, one for spi, one for i2c and one for mmc.
475
476- FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
477 In this case the array could be something like: { spi0, i2c0, mmc0 }
478 for the three available functions.
479
480- FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
481 function is *always* associated with a certain set of pin groups, could
482 be just a single one, but could also be many. In the example above the
483 function i2c is associated with the pins { A5, B5 }, enumerated as
484 { 24, 25 } in the controller pin space.
485
486 The Function spi is associated with pin groups { A8, A7, A6, A5 }
487 and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
488 { 38, 46, 54, 62 } respectively.
489
490 Group names must be unique per pin controller, no two groups on the same
491 controller may have the same name.
492
493- The combination of a FUNCTION and a PIN GROUP determine a certain function
494 for a certain set of pins. The knowledge of the functions and pin groups
495 and their machine-specific particulars are kept inside the pinmux driver,
496 from the outside only the enumerators are known, and the driver core can:
497
498 - Request the name of a function with a certain selector (>= 0)
499 - A list of groups associated with a certain function
500 - Request that a certain group in that list to be activated for a certain
501 function
502
503 As already described above, pin groups are in turn self-descriptive, so
504 the core will retrieve the actual pin range in a certain group from the
505 driver.
506
507- FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
508 device by the board file, device tree or similar machine setup configuration
509 mechanism, similar to how regulators are connected to devices, usually by
510 name. Defining a pin controller, function and group thus uniquely identify
511 the set of pins to be used by a certain device. (If only one possible group
512 of pins is available for the function, no group name need to be supplied -
513 the core will simply select the first and only group available.)
514
515 In the example case we can define that this particular machine shall
516 use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
517 fi2c0 group gi2c0, on the primary pin controller, we get mappings
518 like these:
519
520 {
521 {"map-spi0", spi0, pinctrl0, fspi0, gspi0},
522 {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0}
523 }
524
Stephen Warren1681f5a2012-02-22 14:25:58 -0700525 Every map must be assigned a state name, pin controller, device and
526 function. The group is not compulsory - if it is omitted the first group
527 presented by the driver as applicable for the function will be selected,
528 which is useful for simple cases.
Linus Walleij2744e8a2011-05-02 20:50:54 +0200529
530 It is possible to map several groups to the same combination of device,
531 pin controller and function. This is for cases where a certain function on
532 a certain pin controller may use different sets of pins in different
533 configurations.
534
535- PINS for a certain FUNCTION using a certain PIN GROUP on a certain
536 PIN CONTROLLER are provided on a first-come first-serve basis, so if some
537 other device mux setting or GPIO pin request has already taken your physical
538 pin, you will be denied the use of it. To get (activate) a new setting, the
539 old one has to be put (deactivated) first.
540
541Sometimes the documentation and hardware registers will be oriented around
542pads (or "fingers") rather than pins - these are the soldering surfaces on the
543silicon inside the package, and may or may not match the actual number of
544pins/balls underneath the capsule. Pick some enumeration that makes sense to
545you. Define enumerators only for the pins you can control if that makes sense.
546
547Assumptions:
548
Linus Walleij336cdba02011-11-10 09:27:41 +0100549We assume that the number of possible function maps to pin groups is limited by
Linus Walleij2744e8a2011-05-02 20:50:54 +0200550the hardware. I.e. we assume that there is no system where any function can be
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000551mapped to any pin, like in a phone exchange. So the available pin groups for
Linus Walleij2744e8a2011-05-02 20:50:54 +0200552a certain function will be limited to a few choices (say up to eight or so),
553not hundreds or any amount of choices. This is the characteristic we have found
554by inspecting available pinmux hardware, and a necessary assumption since we
555expect pinmux drivers to present *all* possible function vs pin group mappings
556to the subsystem.
557
558
559Pinmux drivers
560==============
561
562The pinmux core takes care of preventing conflicts on pins and calling
563the pin controller driver to execute different settings.
564
565It is the responsibility of the pinmux driver to impose further restrictions
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000566(say for example infer electronic limitations due to load, etc.) to determine
Linus Walleij2744e8a2011-05-02 20:50:54 +0200567whether or not the requested function can actually be allowed, and in case it
568is possible to perform the requested mux setting, poke the hardware so that
569this happens.
570
571Pinmux drivers are required to supply a few callback functions, some are
Baruch Siach260463d2015-03-08 10:51:45 +0200572optional. Usually the set_mux() function is implemented, writing values into
573some certain registers to activate a certain mux setting for a certain pin.
Linus Walleij2744e8a2011-05-02 20:50:54 +0200574
575A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4
576into some register named MUX to select a certain function with a certain
577group of pins would work something like this:
578
579#include <linux/pinctrl/pinctrl.h>
580#include <linux/pinctrl/pinmux.h>
581
582struct foo_group {
583 const char *name;
584 const unsigned int *pins;
585 const unsigned num_pins;
586};
587
588static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 };
589static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 };
590static const unsigned i2c0_pins[] = { 24, 25 };
591static const unsigned mmc0_1_pins[] = { 56, 57 };
592static const unsigned mmc0_2_pins[] = { 58, 59 };
593static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 };
594
595static const struct foo_group foo_groups[] = {
596 {
597 .name = "spi0_0_grp",
598 .pins = spi0_0_pins,
599 .num_pins = ARRAY_SIZE(spi0_0_pins),
600 },
601 {
602 .name = "spi0_1_grp",
603 .pins = spi0_1_pins,
604 .num_pins = ARRAY_SIZE(spi0_1_pins),
605 },
606 {
607 .name = "i2c0_grp",
608 .pins = i2c0_pins,
609 .num_pins = ARRAY_SIZE(i2c0_pins),
610 },
611 {
612 .name = "mmc0_1_grp",
613 .pins = mmc0_1_pins,
614 .num_pins = ARRAY_SIZE(mmc0_1_pins),
615 },
616 {
617 .name = "mmc0_2_grp",
618 .pins = mmc0_2_pins,
619 .num_pins = ARRAY_SIZE(mmc0_2_pins),
620 },
621 {
622 .name = "mmc0_3_grp",
623 .pins = mmc0_3_pins,
624 .num_pins = ARRAY_SIZE(mmc0_3_pins),
625 },
626};
627
628
Viresh Kumard1e90e92012-03-30 11:25:40 +0530629static int foo_get_groups_count(struct pinctrl_dev *pctldev)
Linus Walleij2744e8a2011-05-02 20:50:54 +0200630{
Viresh Kumard1e90e92012-03-30 11:25:40 +0530631 return ARRAY_SIZE(foo_groups);
Linus Walleij2744e8a2011-05-02 20:50:54 +0200632}
633
634static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
635 unsigned selector)
636{
637 return foo_groups[selector].name;
638}
639
640static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
641 unsigned ** const pins,
642 unsigned * const num_pins)
643{
644 *pins = (unsigned *) foo_groups[selector].pins;
645 *num_pins = foo_groups[selector].num_pins;
646 return 0;
647}
648
649static struct pinctrl_ops foo_pctrl_ops = {
Viresh Kumard1e90e92012-03-30 11:25:40 +0530650 .get_groups_count = foo_get_groups_count,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200651 .get_group_name = foo_get_group_name,
652 .get_group_pins = foo_get_group_pins,
653};
654
655struct foo_pmx_func {
656 const char *name;
657 const char * const *groups;
658 const unsigned num_groups;
659};
660
Viresh Kumareb181c32012-03-29 11:03:27 +0530661static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
Linus Walleij2744e8a2011-05-02 20:50:54 +0200662static const char * const i2c0_groups[] = { "i2c0_grp" };
663static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
664 "mmc0_3_grp" };
665
666static const struct foo_pmx_func foo_functions[] = {
667 {
668 .name = "spi0",
669 .groups = spi0_groups,
670 .num_groups = ARRAY_SIZE(spi0_groups),
671 },
672 {
673 .name = "i2c0",
674 .groups = i2c0_groups,
675 .num_groups = ARRAY_SIZE(i2c0_groups),
676 },
677 {
678 .name = "mmc0",
679 .groups = mmc0_groups,
680 .num_groups = ARRAY_SIZE(mmc0_groups),
681 },
682};
683
Viresh Kumard1e90e92012-03-30 11:25:40 +0530684int foo_get_functions_count(struct pinctrl_dev *pctldev)
Linus Walleij2744e8a2011-05-02 20:50:54 +0200685{
Viresh Kumard1e90e92012-03-30 11:25:40 +0530686 return ARRAY_SIZE(foo_functions);
Linus Walleij2744e8a2011-05-02 20:50:54 +0200687}
688
689const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
690{
Linus Walleij336cdba02011-11-10 09:27:41 +0100691 return foo_functions[selector].name;
Linus Walleij2744e8a2011-05-02 20:50:54 +0200692}
693
694static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
695 const char * const **groups,
696 unsigned * const num_groups)
697{
698 *groups = foo_functions[selector].groups;
699 *num_groups = foo_functions[selector].num_groups;
700 return 0;
701}
702
Linus Walleij03e9f0c2014-09-03 13:02:56 +0200703int foo_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200704 unsigned group)
705{
Linus Walleij336cdba02011-11-10 09:27:41 +0100706 u8 regbit = (1 << selector + group);
Linus Walleij2744e8a2011-05-02 20:50:54 +0200707
708 writeb((readb(MUX)|regbit), MUX)
709 return 0;
710}
711
Linus Walleij2744e8a2011-05-02 20:50:54 +0200712struct pinmux_ops foo_pmxops = {
Viresh Kumard1e90e92012-03-30 11:25:40 +0530713 .get_functions_count = foo_get_functions_count,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200714 .get_function_name = foo_get_fname,
715 .get_function_groups = foo_get_groups,
Linus Walleij03e9f0c2014-09-03 13:02:56 +0200716 .set_mux = foo_set_mux,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200717};
718
719/* Pinmux operations are handled by some pin controller */
720static struct pinctrl_desc foo_desc = {
721 ...
722 .pctlops = &foo_pctrl_ops,
723 .pmxops = &foo_pmxops,
724};
725
726In the example activating muxing 0 and 1 at the same time setting bits
7270 and 1, uses one pin in common so they would collide.
728
729The beauty of the pinmux subsystem is that since it keeps track of all
730pins and who is using them, it will already have denied an impossible
731request like that, so the driver does not need to worry about such
732things - when it gets a selector passed in, the pinmux subsystem makes
733sure no other device or GPIO assignment is already using the selected
734pins. Thus bits 0 and 1 in the control register will never be set at the
735same time.
736
737All the above functions are mandatory to implement for a pinmux driver.
738
739
Linus Walleije93bcee2012-02-09 07:23:28 +0100740Pin control interaction with the GPIO subsystem
741===============================================
Linus Walleij2744e8a2011-05-02 20:50:54 +0200742
Linus Walleijfdba2d02013-03-15 12:01:20 +0100743Note that the following implies that the use case is to use a certain pin
744from the Linux kernel using the API in <linux/gpio.h> with gpio_request()
745and similar functions. There are cases where you may be using something
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000746that your datasheet calls "GPIO mode", but actually is just an electrical
Linus Walleijfdba2d02013-03-15 12:01:20 +0100747configuration for a certain device. See the section below named
748"GPIO mode pitfalls" for more details on this scenario.
749
Linus Walleije93bcee2012-02-09 07:23:28 +0100750The public pinmux API contains two functions named pinctrl_request_gpio()
751and pinctrl_free_gpio(). These two functions shall *ONLY* be called from
Linus Walleij542e7042011-11-14 10:06:22 +0100752gpiolib-based drivers as part of their gpio_request() and
Linus Walleije93bcee2012-02-09 07:23:28 +0100753gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output]
Linus Walleij542e7042011-11-14 10:06:22 +0100754shall only be called from within respective gpio_direction_[input|output]
755gpiolib implementation.
756
757NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
Linus Walleije93bcee2012-02-09 07:23:28 +0100758controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
759that driver request proper muxing and other control for its pins.
Linus Walleij542e7042011-11-14 10:06:22 +0100760
Linus Walleij2744e8a2011-05-02 20:50:54 +0200761The function list could become long, especially if you can convert every
762individual pin into a GPIO pin independent of any other pins, and then try
763the approach to define every pin as a function.
764
765In this case, the function array would become 64 entries for each GPIO
766setting and then the device functions.
767
Linus Walleije93bcee2012-02-09 07:23:28 +0100768For this reason there are two functions a pin control driver can implement
Linus Walleij542e7042011-11-14 10:06:22 +0100769to enable only GPIO on an individual pin: .gpio_request_enable() and
770.gpio_disable_free().
Linus Walleij2744e8a2011-05-02 20:50:54 +0200771
772This function will pass in the affected GPIO range identified by the pin
773controller core, so you know which GPIO pins are being affected by the request
774operation.
775
Linus Walleij542e7042011-11-14 10:06:22 +0100776If your driver needs to have an indication from the framework of whether the
777GPIO pin shall be used for input or output you can implement the
778.gpio_set_direction() function. As described this shall be called from the
779gpiolib driver and the affected GPIO range, pin offset and desired direction
780will be passed along to this function.
781
782Alternatively to using these special functions, it is fully allowed to use
Linus Walleije93bcee2012-02-09 07:23:28 +0100783named functions for each GPIO pin, the pinctrl_request_gpio() will attempt to
Linus Walleij542e7042011-11-14 10:06:22 +0100784obtain the function "gpioN" where "N" is the global GPIO pin number if no
785special GPIO-handler is registered.
Linus Walleij2744e8a2011-05-02 20:50:54 +0200786
787
Linus Walleijfdba2d02013-03-15 12:01:20 +0100788GPIO mode pitfalls
789==================
790
Linus Walleijeb6002d2013-06-25 16:17:15 +0200791Due to the naming conventions used by hardware engineers, where "GPIO"
792is taken to mean different things than what the kernel does, the developer
793may be confused by a datasheet talking about a pin being possible to set
794into "GPIO mode". It appears that what hardware engineers mean with
795"GPIO mode" is not necessarily the use case that is implied in the kernel
796interface <linux/gpio.h>: a pin that you grab from kernel code and then
797either listen for input or drive high/low to assert/deassert some
798external line.
Linus Walleijfdba2d02013-03-15 12:01:20 +0100799
800Rather hardware engineers think that "GPIO mode" means that you can
801software-control a few electrical properties of the pin that you would
802not be able to control if the pin was in some other mode, such as muxed in
803for a device.
804
Linus Walleijeb6002d2013-06-25 16:17:15 +0200805The GPIO portions of a pin and its relation to a certain pin controller
806configuration and muxing logic can be constructed in several ways. Here
807are two examples:
808
809(A)
810 pin config
811 logic regs
812 | +- SPI
813 Physical pins --- pad --- pinmux -+- I2C
814 | +- mmc
815 | +- GPIO
816 pin
817 multiplex
818 logic regs
819
820Here some electrical properties of the pin can be configured no matter
821whether the pin is used for GPIO or not. If you multiplex a GPIO onto a
822pin, you can also drive it high/low from "GPIO" registers.
823Alternatively, the pin can be controlled by a certain peripheral, while
824still applying desired pin config properties. GPIO functionality is thus
825orthogonal to any other device using the pin.
826
827In this arrangement the registers for the GPIO portions of the pin controller,
828or the registers for the GPIO hardware module are likely to reside in a
829separate memory range only intended for GPIO driving, and the register
830range dealing with pin config and pin multiplexing get placed into a
831different memory range and a separate section of the data sheet.
832
833(B)
834
835 pin config
836 logic regs
837 | +- SPI
838 Physical pins --- pad --- pinmux -+- I2C
839 | | +- mmc
840 | |
841 GPIO pin
842 multiplex
843 logic regs
844
845In this arrangement, the GPIO functionality can always be enabled, such that
846e.g. a GPIO input can be used to "spy" on the SPI/I2C/MMC signal while it is
847pulsed out. It is likely possible to disrupt the traffic on the pin by doing
848wrong things on the GPIO block, as it is never really disconnected. It is
849possible that the GPIO, pin config and pin multiplex registers are placed into
850the same memory range and the same section of the data sheet, although that
851need not be the case.
852
853From a kernel point of view, however, these are different aspects of the
854hardware and shall be put into different subsystems:
855
856- Registers (or fields within registers) that control electrical
857 properties of the pin such as biasing and drive strength should be
858 exposed through the pinctrl subsystem, as "pin configuration" settings.
859
860- Registers (or fields within registers) that control muxing of signals
861 from various other HW blocks (e.g. I2C, MMC, or GPIO) onto pins should
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000862 be exposed through the pinctrl subsystem, as mux functions.
Linus Walleijeb6002d2013-06-25 16:17:15 +0200863
864- Registers (or fields within registers) that control GPIO functionality
865 such as setting a GPIO's output value, reading a GPIO's input value, or
866 setting GPIO pin direction should be exposed through the GPIO subsystem,
867 and if they also support interrupt capabilities, through the irqchip
868 abstraction.
869
870Depending on the exact HW register design, some functions exposed by the
871GPIO subsystem may call into the pinctrl subsystem in order to
872co-ordinate register settings across HW modules. In particular, this may
873be needed for HW with separate GPIO and pin controller HW modules, where
874e.g. GPIO direction is determined by a register in the pin controller HW
875module rather than the GPIO HW module.
876
877Electrical properties of the pin such as biasing and drive strength
878may be placed at some pin-specific register in all cases or as part
879of the GPIO register in case (B) especially. This doesn't mean that such
880properties necessarily pertain to what the Linux kernel calls "GPIO".
881
Linus Walleijfdba2d02013-03-15 12:01:20 +0100882Example: a pin is usually muxed in to be used as a UART TX line. But during
883system sleep, we need to put this pin into "GPIO mode" and ground it.
884
885If you make a 1-to-1 map to the GPIO subsystem for this pin, you may start
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000886to think that you need to come up with something really complex, that the
Linus Walleijfdba2d02013-03-15 12:01:20 +0100887pin shall be used for UART TX and GPIO at the same time, that you will grab
888a pin control handle and set it to a certain state to enable UART TX to be
889muxed in, then twist it over to GPIO mode and use gpio_direction_output()
890to drive it low during sleep, then mux it over to UART TX again when you
891wake up and maybe even gpio_request/gpio_free as part of this cycle. This
892all gets very complicated.
893
894The solution is to not think that what the datasheet calls "GPIO mode"
895has to be handled by the <linux/gpio.h> interface. Instead view this as
896a certain pin config setting. Look in e.g. <linux/pinctrl/pinconf-generic.h>
897and you find this in the documentation:
898
899 PIN_CONFIG_OUTPUT: this will configure the pin in output, use argument
900 1 to indicate high level, argument 0 to indicate low level.
901
902So it is perfectly possible to push a pin into "GPIO mode" and drive the
903line low as part of the usual pin control map. So for example your UART
904driver may look like this:
905
906#include <linux/pinctrl/consumer.h>
907
908struct pinctrl *pinctrl;
909struct pinctrl_state *pins_default;
910struct pinctrl_state *pins_sleep;
911
912pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT);
913pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP);
914
915/* Normal mode */
916retval = pinctrl_select_state(pinctrl, pins_default);
917/* Sleep mode */
918retval = pinctrl_select_state(pinctrl, pins_sleep);
919
920And your machine configuration may look like this:
921--------------------------------------------------
922
923static unsigned long uart_default_mode[] = {
924 PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0),
925};
926
927static unsigned long uart_sleep_mode[] = {
928 PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0),
929};
930
Sachin Kamat2868a072013-08-08 10:50:59 +0530931static struct pinctrl_map pinmap[] __initdata = {
Linus Walleijfdba2d02013-03-15 12:01:20 +0100932 PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
933 "u0_group", "u0"),
934 PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
935 "UART_TX_PIN", uart_default_mode),
936 PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
937 "u0_group", "gpio-mode"),
938 PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
939 "UART_TX_PIN", uart_sleep_mode),
940};
941
942foo_init(void) {
943 pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap));
944}
945
946Here the pins we want to control are in the "u0_group" and there is some
947function called "u0" that can be enabled on this group of pins, and then
948everything is UART business as usual. But there is also some function
949named "gpio-mode" that can be mapped onto the same pins to move them into
950GPIO mode.
951
952This will give the desired effect without any bogus interaction with the
953GPIO subsystem. It is just an electrical configuration used by that device
954when going to sleep, it might imply that the pin is set into something the
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000955datasheet calls "GPIO mode", but that is not the point: it is still used
Linus Walleijfdba2d02013-03-15 12:01:20 +0100956by that UART device to control the pins that pertain to that very UART
957driver, putting them into modes needed by the UART. GPIO in the Linux
958kernel sense are just some 1-bit line, and is a different use case.
959
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000960How the registers are poked to attain the push or pull, and output low
Linus Walleijfdba2d02013-03-15 12:01:20 +0100961configuration and the muxing of the "u0" or "gpio-mode" group onto these
962pins is a question for the driver.
963
964Some datasheets will be more helpful and refer to the "GPIO mode" as
965"low power mode" rather than anything to do with GPIO. This often means
966the same thing electrically speaking, but in this latter case the
967software engineers will usually quickly identify that this is some
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +0000968specific muxing or configuration rather than anything related to the GPIO
Linus Walleijfdba2d02013-03-15 12:01:20 +0100969API.
970
971
Stephen Warren1e2082b2012-03-02 13:05:48 -0700972Board/machine configuration
Linus Walleij2744e8a2011-05-02 20:50:54 +0200973==================================
974
975Boards and machines define how a certain complete running system is put
976together, including how GPIOs and devices are muxed, how regulators are
977constrained and how the clock tree looks. Of course pinmux settings are also
978part of this.
979
Stephen Warren1e2082b2012-03-02 13:05:48 -0700980A pin controller configuration for a machine looks pretty much like a simple
981regulator configuration, so for the example array above we want to enable i2c
982and spi on the second function mapping:
Linus Walleij2744e8a2011-05-02 20:50:54 +0200983
984#include <linux/pinctrl/machine.h>
985
Uwe Kleine-König122dbe72012-03-30 22:04:51 +0200986static const struct pinctrl_map mapping[] __initconst = {
Linus Walleij2744e8a2011-05-02 20:50:54 +0200987 {
Stephen Warren806d3142012-02-23 17:04:39 -0700988 .dev_name = "foo-spi.0",
Stephen Warren110e4ec2012-03-01 18:48:33 -0700989 .name = PINCTRL_STATE_DEFAULT,
Stephen Warren1e2082b2012-03-02 13:05:48 -0700990 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -0700991 .ctrl_dev_name = "pinctrl-foo",
Stephen Warren1e2082b2012-03-02 13:05:48 -0700992 .data.mux.function = "spi0",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200993 },
994 {
Stephen Warren806d3142012-02-23 17:04:39 -0700995 .dev_name = "foo-i2c.0",
Stephen Warren110e4ec2012-03-01 18:48:33 -0700996 .name = PINCTRL_STATE_DEFAULT,
Stephen Warren1e2082b2012-03-02 13:05:48 -0700997 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -0700998 .ctrl_dev_name = "pinctrl-foo",
Stephen Warren1e2082b2012-03-02 13:05:48 -0700999 .data.mux.function = "i2c0",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001000 },
1001 {
Stephen Warren806d3142012-02-23 17:04:39 -07001002 .dev_name = "foo-mmc.0",
Stephen Warren110e4ec2012-03-01 18:48:33 -07001003 .name = PINCTRL_STATE_DEFAULT,
Stephen Warren1e2082b2012-03-02 13:05:48 -07001004 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001005 .ctrl_dev_name = "pinctrl-foo",
Stephen Warren1e2082b2012-03-02 13:05:48 -07001006 .data.mux.function = "mmc0",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001007 },
1008};
1009
1010The dev_name here matches to the unique device name that can be used to look
1011up the device struct (just like with clockdev or regulators). The function name
1012must match a function provided by the pinmux driver handling this pin range.
1013
1014As you can see we may have several pin controllers on the system and thus
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +00001015we need to specify which one of them contains the functions we wish to map.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001016
1017You register this pinmux mapping to the pinmux subsystem by simply:
1018
Linus Walleije93bcee2012-02-09 07:23:28 +01001019 ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));
Linus Walleij2744e8a2011-05-02 20:50:54 +02001020
1021Since the above construct is pretty common there is a helper macro to make
Stephen Warren51cd24e2011-12-09 16:59:05 -07001022it even more compact which assumes you want to use pinctrl-foo and position
Linus Walleij2744e8a2011-05-02 20:50:54 +020010230 for mapping, for example:
1024
Sachin Kamat2868a072013-08-08 10:50:59 +05301025static struct pinctrl_map mapping[] __initdata = {
Stephen Warren1e2082b2012-03-02 13:05:48 -07001026 PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT, "pinctrl-foo", NULL, "i2c0"),
1027};
1028
1029The mapping table may also contain pin configuration entries. It's common for
1030each pin/group to have a number of configuration entries that affect it, so
1031the table entries for configuration reference an array of config parameters
1032and values. An example using the convenience macros is shown below:
1033
1034static unsigned long i2c_grp_configs[] = {
1035 FOO_PIN_DRIVEN,
1036 FOO_PIN_PULLUP,
1037};
1038
1039static unsigned long i2c_pin_configs[] = {
1040 FOO_OPEN_COLLECTOR,
1041 FOO_SLEW_RATE_SLOW,
1042};
1043
Sachin Kamat2868a072013-08-08 10:50:59 +05301044static struct pinctrl_map mapping[] __initdata = {
Stephen Warren1e2082b2012-03-02 13:05:48 -07001045 PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", "i2c0"),
Daniel Mackd1a83d32012-08-09 21:02:19 +02001046 PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs),
1047 PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs),
1048 PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs),
Stephen Warren1e2082b2012-03-02 13:05:48 -07001049};
1050
1051Finally, some devices expect the mapping table to contain certain specific
1052named states. When running on hardware that doesn't need any pin controller
1053configuration, the mapping table must still contain those named states, in
1054order to explicitly indicate that the states were provided and intended to
1055be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining
1056a named state without causing any pin controller to be programmed:
1057
Sachin Kamat2868a072013-08-08 10:50:59 +05301058static struct pinctrl_map mapping[] __initdata = {
Stephen Warren1e2082b2012-03-02 13:05:48 -07001059 PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
Linus Walleij2744e8a2011-05-02 20:50:54 +02001060};
1061
1062
1063Complex mappings
1064================
1065
1066As it is possible to map a function to different groups of pins an optional
1067.group can be specified like this:
1068
1069...
1070{
Stephen Warren806d3142012-02-23 17:04:39 -07001071 .dev_name = "foo-spi.0",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001072 .name = "spi0-pos-A",
Stephen Warren1e2082b2012-03-02 13:05:48 -07001073 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001074 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001075 .function = "spi0",
1076 .group = "spi0_0_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001077},
1078{
Stephen Warren806d3142012-02-23 17:04:39 -07001079 .dev_name = "foo-spi.0",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001080 .name = "spi0-pos-B",
Stephen Warren1e2082b2012-03-02 13:05:48 -07001081 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001082 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001083 .function = "spi0",
1084 .group = "spi0_1_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001085},
1086...
1087
1088This example mapping is used to switch between two positions for spi0 at
1089runtime, as described further below under the heading "Runtime pinmuxing".
1090
Stephen Warren6e5e9592012-03-02 13:05:47 -07001091Further it is possible for one named state to affect the muxing of several
1092groups of pins, say for example in the mmc0 example above, where you can
Linus Walleij2744e8a2011-05-02 20:50:54 +02001093additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
1094three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the
1095case), we define a mapping like this:
1096
1097...
1098{
Stephen Warren806d3142012-02-23 17:04:39 -07001099 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +01001100 .name = "2bit"
Stephen Warren1e2082b2012-03-02 13:05:48 -07001101 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001102 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001103 .function = "mmc0",
Linus Walleij336cdba02011-11-10 09:27:41 +01001104 .group = "mmc0_1_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001105},
1106{
Stephen Warren806d3142012-02-23 17:04:39 -07001107 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +01001108 .name = "4bit"
Stephen Warren1e2082b2012-03-02 13:05:48 -07001109 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001110 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001111 .function = "mmc0",
1112 .group = "mmc0_1_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001113},
1114{
Stephen Warren806d3142012-02-23 17:04:39 -07001115 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +01001116 .name = "4bit"
Stephen Warren1e2082b2012-03-02 13:05:48 -07001117 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001118 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001119 .function = "mmc0",
Linus Walleij336cdba02011-11-10 09:27:41 +01001120 .group = "mmc0_2_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001121},
1122{
Stephen Warren806d3142012-02-23 17:04:39 -07001123 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +01001124 .name = "8bit"
Stephen Warren1e2082b2012-03-02 13:05:48 -07001125 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001126 .ctrl_dev_name = "pinctrl-foo",
Stephen Warren6e5e9592012-03-02 13:05:47 -07001127 .function = "mmc0",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001128 .group = "mmc0_1_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001129},
1130{
Stephen Warren806d3142012-02-23 17:04:39 -07001131 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +01001132 .name = "8bit"
Stephen Warren1e2082b2012-03-02 13:05:48 -07001133 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001134 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001135 .function = "mmc0",
1136 .group = "mmc0_2_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001137},
Linus Walleij336cdba02011-11-10 09:27:41 +01001138{
Stephen Warren806d3142012-02-23 17:04:39 -07001139 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +01001140 .name = "8bit"
Stephen Warren1e2082b2012-03-02 13:05:48 -07001141 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001142 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij336cdba02011-11-10 09:27:41 +01001143 .function = "mmc0",
1144 .group = "mmc0_3_grp",
Linus Walleij336cdba02011-11-10 09:27:41 +01001145},
Linus Walleij2744e8a2011-05-02 20:50:54 +02001146...
1147
1148The result of grabbing this mapping from the device with something like
1149this (see next paragraph):
1150
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001151 p = devm_pinctrl_get(dev);
Stephen Warren6e5e9592012-03-02 13:05:47 -07001152 s = pinctrl_lookup_state(p, "8bit");
1153 ret = pinctrl_select_state(p, s);
1154
1155or more simply:
1156
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001157 p = devm_pinctrl_get_select(dev, "8bit");
Linus Walleij2744e8a2011-05-02 20:50:54 +02001158
1159Will be that you activate all the three bottom records in the mapping at
Stephen Warren6e5e9592012-03-02 13:05:47 -07001160once. Since they share the same name, pin controller device, function and
Linus Walleij2744e8a2011-05-02 20:50:54 +02001161device, and since we allow multiple groups to match to a single device, they
1162all get selected, and they all get enabled and disable simultaneously by the
1163pinmux core.
1164
1165
Linus Walleijc31a00c2012-09-10 17:22:00 +02001166Pin control requests from drivers
1167=================================
Linus Walleij2744e8a2011-05-02 20:50:54 +02001168
Linus Walleijab780292013-01-22 10:56:14 -07001169When a device driver is about to probe the device core will automatically
1170attempt to issue pinctrl_get_select_default() on these devices.
1171This way driver writers do not need to add any of the boilerplate code
1172of the type found below. However when doing fine-grained state selection
1173and not using the "default" state, you may have to do some device driver
1174handling of the pinctrl handles and states.
1175
1176So if you just want to put the pins for a certain device into the default
1177state and be done with it, there is nothing you need to do besides
1178providing the proper mapping table. The device core will take care of
1179the rest.
1180
Linus Walleije93bcee2012-02-09 07:23:28 +01001181Generally it is discouraged to let individual drivers get and enable pin
1182control. So if possible, handle the pin control in platform code or some other
1183place where you have access to all the affected struct device * pointers. In
1184some cases where a driver needs to e.g. switch between different mux mappings
1185at runtime this is not possible.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001186
Linus Walleijc31a00c2012-09-10 17:22:00 +02001187A typical case is if a driver needs to switch bias of pins from normal
1188operation and going to sleep, moving from the PINCTRL_STATE_DEFAULT to
1189PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save
1190current in sleep mode.
1191
Linus Walleije93bcee2012-02-09 07:23:28 +01001192A driver may request a certain control state to be activated, usually just the
1193default state like this:
Linus Walleij2744e8a2011-05-02 20:50:54 +02001194
Linus Walleij28a8d142012-02-09 01:52:22 +01001195#include <linux/pinctrl/consumer.h>
Linus Walleij2744e8a2011-05-02 20:50:54 +02001196
1197struct foo_state {
Linus Walleije93bcee2012-02-09 07:23:28 +01001198 struct pinctrl *p;
Stephen Warren6e5e9592012-03-02 13:05:47 -07001199 struct pinctrl_state *s;
Linus Walleij2744e8a2011-05-02 20:50:54 +02001200 ...
1201};
1202
1203foo_probe()
1204{
Stephen Warren6e5e9592012-03-02 13:05:47 -07001205 /* Allocate a state holder named "foo" etc */
1206 struct foo_state *foo = ...;
Linus Walleij2744e8a2011-05-02 20:50:54 +02001207
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001208 foo->p = devm_pinctrl_get(&device);
Stephen Warren6e5e9592012-03-02 13:05:47 -07001209 if (IS_ERR(foo->p)) {
1210 /* FIXME: clean up "foo" here */
1211 return PTR_ERR(foo->p);
1212 }
Linus Walleij2744e8a2011-05-02 20:50:54 +02001213
Stephen Warren6e5e9592012-03-02 13:05:47 -07001214 foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
1215 if (IS_ERR(foo->s)) {
Stephen Warren6e5e9592012-03-02 13:05:47 -07001216 /* FIXME: clean up "foo" here */
1217 return PTR_ERR(s);
1218 }
1219
1220 ret = pinctrl_select_state(foo->s);
1221 if (ret < 0) {
Stephen Warren6e5e9592012-03-02 13:05:47 -07001222 /* FIXME: clean up "foo" here */
1223 return ret;
1224 }
Linus Walleij2744e8a2011-05-02 20:50:54 +02001225}
1226
Stephen Warren6e5e9592012-03-02 13:05:47 -07001227This get/lookup/select/put sequence can just as well be handled by bus drivers
Linus Walleij2744e8a2011-05-02 20:50:54 +02001228if you don't want each and every driver to handle it and you know the
1229arrangement on your bus.
1230
Stephen Warren6e5e9592012-03-02 13:05:47 -07001231The semantics of the pinctrl APIs are:
Linus Walleij2744e8a2011-05-02 20:50:54 +02001232
Stephen Warren6e5e9592012-03-02 13:05:47 -07001233- pinctrl_get() is called in process context to obtain a handle to all pinctrl
1234 information for a given client device. It will allocate a struct from the
1235 kernel memory to hold the pinmux state. All mapping table parsing or similar
1236 slow operations take place within this API.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001237
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001238- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
1239 to be called automatically on the retrieved pointer when the associated
1240 device is removed. It is recommended to use this function over plain
1241 pinctrl_get().
1242
Stephen Warren6e5e9592012-03-02 13:05:47 -07001243- pinctrl_lookup_state() is called in process context to obtain a handle to a
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +00001244 specific state for a client device. This operation may be slow, too.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001245
Stephen Warren6e5e9592012-03-02 13:05:47 -07001246- pinctrl_select_state() programs pin controller hardware according to the
Laszlo Papp4dfb0bd2014-01-13 19:00:14 +00001247 definition of the state as given by the mapping table. In theory, this is a
Stephen Warren6e5e9592012-03-02 13:05:47 -07001248 fast-path operation, since it only involved blasting some register settings
1249 into hardware. However, note that some pin controllers may have their
1250 registers on a slow/IRQ-based bus, so client devices should not assume they
1251 can call pinctrl_select_state() from non-blocking contexts.
1252
1253- pinctrl_put() frees all information associated with a pinctrl handle.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001254
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001255- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
1256 explicitly destroy a pinctrl object returned by devm_pinctrl_get().
1257 However, use of this function will be rare, due to the automatic cleanup
1258 that will occur even without calling it.
1259
1260 pinctrl_get() must be paired with a plain pinctrl_put().
1261 pinctrl_get() may not be paired with devm_pinctrl_put().
1262 devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
1263 devm_pinctrl_get() may not be paired with plain pinctrl_put().
1264
Linus Walleije93bcee2012-02-09 07:23:28 +01001265Usually the pin control core handled the get/put pair and call out to the
1266device drivers bookkeeping operations, like checking available functions and
1267the associated pins, whereas the enable/disable pass on to the pin controller
Linus Walleij2744e8a2011-05-02 20:50:54 +02001268driver which takes care of activating and/or deactivating the mux setting by
1269quickly poking some registers.
1270
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001271The pins are allocated for your device when you issue the devm_pinctrl_get()
1272call, after this you should be able to see this in the debugfs listing of all
1273pins.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001274
Linus Walleijc05127c2012-04-10 10:00:38 +02001275NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
1276requested pinctrl handles, for example if the pinctrl driver has not yet
1277registered. Thus make sure that the error path in your driver gracefully
1278cleans up and is ready to retry the probing later in the startup process.
1279
Linus Walleij2744e8a2011-05-02 20:50:54 +02001280
Linus Walleijc31a00c2012-09-10 17:22:00 +02001281Drivers needing both pin control and GPIOs
1282==========================================
1283
1284Again, it is discouraged to let drivers lookup and select pin control states
1285themselves, but again sometimes this is unavoidable.
1286
1287So say that your driver is fetching its resources like this:
1288
1289#include <linux/pinctrl/consumer.h>
1290#include <linux/gpio.h>
1291
1292struct pinctrl *pinctrl;
1293int gpio;
1294
1295pinctrl = devm_pinctrl_get_select_default(&dev);
1296gpio = devm_gpio_request(&dev, 14, "foo");
1297
1298Here we first request a certain pin state and then request GPIO 14 to be
1299used. If you're using the subsystems orthogonally like this, you should
1300nominally always get your pinctrl handle and select the desired pinctrl
1301state BEFORE requesting the GPIO. This is a semantic convention to avoid
1302situations that can be electrically unpleasant, you will certainly want to
1303mux in and bias pins in a certain way before the GPIO subsystems starts to
1304deal with them.
1305
Linus Walleijab780292013-01-22 10:56:14 -07001306The above can be hidden: using the device core, the pinctrl core may be
1307setting up the config and muxing for the pins right before the device is
1308probing, nevertheless orthogonal to the GPIO subsystem.
Linus Walleijc31a00c2012-09-10 17:22:00 +02001309
1310But there are also situations where it makes sense for the GPIO subsystem
James Hogan7bbc87b2013-05-28 10:31:48 +01001311to communicate directly with the pinctrl subsystem, using the latter as a
1312back-end. This is when the GPIO driver may call out to the functions
Linus Walleijc31a00c2012-09-10 17:22:00 +02001313described in the section "Pin control interaction with the GPIO subsystem"
1314above. This only involves per-pin multiplexing, and will be completely
1315hidden behind the gpio_*() function namespace. In this case, the driver
1316need not interact with the pin control subsystem at all.
1317
1318If a pin control driver and a GPIO driver is dealing with the same pins
1319and the use cases involve multiplexing, you MUST implement the pin controller
1320as a back-end for the GPIO driver like this, unless your hardware design
1321is such that the GPIO controller can override the pin controller's
1322multiplexing state through hardware without the need to interact with the
1323pin control system.
1324
1325
Linus Walleije93bcee2012-02-09 07:23:28 +01001326System pin control hogging
1327==========================
Linus Walleij2744e8a2011-05-02 20:50:54 +02001328
Stephen Warren1681f5a2012-02-22 14:25:58 -07001329Pin control map entries can be hogged by the core when the pin controller
Stephen Warren6e5e9592012-03-02 13:05:47 -07001330is registered. This means that the core will attempt to call pinctrl_get(),
1331lookup_state() and select_state() on it immediately after the pin control
1332device has been registered.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001333
Stephen Warren6e5e9592012-03-02 13:05:47 -07001334This occurs for mapping table entries where the client device name is equal
1335to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001336
1337{
Stephen Warren806d3142012-02-23 17:04:39 -07001338 .dev_name = "pinctrl-foo",
Stephen Warren46919ae2012-03-01 18:48:32 -07001339 .name = PINCTRL_STATE_DEFAULT,
Stephen Warren1e2082b2012-03-02 13:05:48 -07001340 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001341 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001342 .function = "power_func",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001343},
1344
1345Since it may be common to request the core to hog a few always-applicable
1346mux settings on the primary pin controller, there is a convenience macro for
1347this:
1348
Stephen Warren1e2082b2012-03-02 13:05:48 -07001349PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, "power_func")
Linus Walleij2744e8a2011-05-02 20:50:54 +02001350
1351This gives the exact same result as the above construction.
1352
1353
1354Runtime pinmuxing
1355=================
1356
1357It is possible to mux a certain function in and out at runtime, say to move
1358an SPI port from one set of pins to another set of pins. Say for example for
1359spi0 in the example above, we expose two different groups of pins for the same
1360function, but with different named in the mapping as described under
Stephen Warren6e5e9592012-03-02 13:05:47 -07001361"Advanced mapping" above. So that for an SPI device, we have two states named
1362"pos-A" and "pos-B".
Linus Walleij2744e8a2011-05-02 20:50:54 +02001363
1364This snippet first muxes the function in the pins defined by group A, enables
1365it, disables and releases it, and muxes it in on the pins defined by group B:
1366
Linus Walleij28a8d142012-02-09 01:52:22 +01001367#include <linux/pinctrl/consumer.h>
1368
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001369struct pinctrl *p;
1370struct pinctrl_state *s1, *s2;
Stephen Warren6e5e9592012-03-02 13:05:47 -07001371
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001372foo_probe()
1373{
Stephen Warren6e5e9592012-03-02 13:05:47 -07001374 /* Setup */
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001375 p = devm_pinctrl_get(&device);
Stephen Warren6e5e9592012-03-02 13:05:47 -07001376 if (IS_ERR(p))
1377 ...
1378
1379 s1 = pinctrl_lookup_state(foo->p, "pos-A");
1380 if (IS_ERR(s1))
1381 ...
1382
1383 s2 = pinctrl_lookup_state(foo->p, "pos-B");
1384 if (IS_ERR(s2))
1385 ...
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001386}
Linus Walleij2744e8a2011-05-02 20:50:54 +02001387
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001388foo_switch()
1389{
Linus Walleij2744e8a2011-05-02 20:50:54 +02001390 /* Enable on position A */
Stephen Warren6e5e9592012-03-02 13:05:47 -07001391 ret = pinctrl_select_state(s1);
1392 if (ret < 0)
1393 ...
Linus Walleij2744e8a2011-05-02 20:50:54 +02001394
Stephen Warren6e5e9592012-03-02 13:05:47 -07001395 ...
Linus Walleij2744e8a2011-05-02 20:50:54 +02001396
1397 /* Enable on position B */
Stephen Warren6e5e9592012-03-02 13:05:47 -07001398 ret = pinctrl_select_state(s2);
1399 if (ret < 0)
1400 ...
1401
Linus Walleij2744e8a2011-05-02 20:50:54 +02001402 ...
Linus Walleij2744e8a2011-05-02 20:50:54 +02001403}
1404
Linus Walleij1a789582012-10-17 20:51:54 +02001405The above has to be done from process context. The reservation of the pins
1406will be done when the state is activated, so in effect one specific pin
1407can be used by different functions at different times on a running system.