blob: 5a98c5d61a2bb9c381a983a223e89569562a612c [file] [log] [blame]
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001/*
2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/kernel.h>
Thomas Petazzonic5aff182012-08-17 14:04:28 +030015#include <linux/netdevice.h>
16#include <linux/etherdevice.h>
17#include <linux/platform_device.h>
18#include <linux/skbuff.h>
19#include <linux/inetdevice.h>
20#include <linux/mbus.h>
21#include <linux/module.h>
22#include <linux/interrupt.h>
David S. Miller2d39d122014-08-25 20:21:55 -070023#include <linux/if_vlan.h>
Thomas Petazzonic5aff182012-08-17 14:04:28 +030024#include <net/ip.h>
25#include <net/ipv6.h>
Thomas Petazzonic3f0dd32014-03-27 11:39:29 +010026#include <linux/io.h>
Ezequiel Garcia2adb7192014-05-19 13:59:55 -030027#include <net/tso.h>
Thomas Petazzonic5aff182012-08-17 14:04:28 +030028#include <linux/of.h>
29#include <linux/of_irq.h>
30#include <linux/of_mdio.h>
31#include <linux/of_net.h>
32#include <linux/of_address.h>
33#include <linux/phy.h>
Thomas Petazzoni189dd622012-11-19 14:15:25 +010034#include <linux/clk.h>
Maxime Ripardf8642882015-09-25 18:09:38 +020035#include <linux/cpu.h>
Thomas Petazzonic5aff182012-08-17 14:04:28 +030036
37/* Registers */
38#define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
Marcin Wojtase5bdf682015-11-30 13:27:42 +010039#define MVNETA_RXQ_HW_BUF_ALLOC BIT(0)
Thomas Petazzonic5aff182012-08-17 14:04:28 +030040#define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
41#define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
42#define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
43#define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
44#define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
45#define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
46#define MVNETA_RXQ_BUF_SIZE_SHIFT 19
47#define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
48#define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
49#define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
50#define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
51#define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
52#define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
53#define MVNETA_PORT_RX_RESET 0x1cc0
54#define MVNETA_PORT_RX_DMA_RESET BIT(0)
55#define MVNETA_PHY_ADDR 0x2000
56#define MVNETA_PHY_ADDR_MASK 0x1f
57#define MVNETA_MBUS_RETRY 0x2010
58#define MVNETA_UNIT_INTR_CAUSE 0x2080
59#define MVNETA_UNIT_CONTROL 0x20B0
60#define MVNETA_PHY_POLLING_ENABLE BIT(1)
61#define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
62#define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
63#define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
64#define MVNETA_BASE_ADDR_ENABLE 0x2290
Marcin Wojtasdb6ba9a2015-11-30 13:27:41 +010065#define MVNETA_ACCESS_PROTECT_ENABLE 0x2294
Thomas Petazzonic5aff182012-08-17 14:04:28 +030066#define MVNETA_PORT_CONFIG 0x2400
67#define MVNETA_UNI_PROMISC_MODE BIT(0)
68#define MVNETA_DEF_RXQ(q) ((q) << 1)
69#define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
70#define MVNETA_TX_UNSET_ERR_SUM BIT(12)
71#define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
72#define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
73#define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
74#define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
75#define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
76 MVNETA_DEF_RXQ_ARP(q) | \
77 MVNETA_DEF_RXQ_TCP(q) | \
78 MVNETA_DEF_RXQ_UDP(q) | \
79 MVNETA_DEF_RXQ_BPDU(q) | \
80 MVNETA_TX_UNSET_ERR_SUM | \
81 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
82#define MVNETA_PORT_CONFIG_EXTEND 0x2404
83#define MVNETA_MAC_ADDR_LOW 0x2414
84#define MVNETA_MAC_ADDR_HIGH 0x2418
85#define MVNETA_SDMA_CONFIG 0x241c
86#define MVNETA_SDMA_BRST_SIZE_16 4
Thomas Petazzonic5aff182012-08-17 14:04:28 +030087#define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
88#define MVNETA_RX_NO_DATA_SWAP BIT(4)
89#define MVNETA_TX_NO_DATA_SWAP BIT(5)
Thomas Petazzoni9ad8fef2013-07-29 15:21:28 +020090#define MVNETA_DESC_SWAP BIT(6)
Thomas Petazzonic5aff182012-08-17 14:04:28 +030091#define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
92#define MVNETA_PORT_STATUS 0x2444
93#define MVNETA_TX_IN_PRGRS BIT(1)
94#define MVNETA_TX_FIFO_EMPTY BIT(8)
95#define MVNETA_RX_MIN_FRAME_SIZE 0x247c
Thomas Petazzoni3f1dd4b2014-04-15 15:50:20 +020096#define MVNETA_SERDES_CFG 0x24A0
Arnaud Patard \(Rtp\)5445eaf2013-07-29 21:56:48 +020097#define MVNETA_SGMII_SERDES_PROTO 0x0cc7
Thomas Petazzoni3f1dd4b2014-04-15 15:50:20 +020098#define MVNETA_QSGMII_SERDES_PROTO 0x0667
Thomas Petazzonic5aff182012-08-17 14:04:28 +030099#define MVNETA_TYPE_PRIO 0x24bc
100#define MVNETA_FORCE_UNI BIT(21)
101#define MVNETA_TXQ_CMD_1 0x24e4
102#define MVNETA_TXQ_CMD 0x2448
103#define MVNETA_TXQ_DISABLE_SHIFT 8
104#define MVNETA_TXQ_ENABLE_MASK 0x000000ff
Andrew Lunne4839112015-10-22 18:37:36 +0100105#define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484
106#define MVNETA_OVERRUN_FRAME_COUNT 0x2488
Stas Sergeev898b2972015-04-01 20:32:49 +0300107#define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4
108#define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31)
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300109#define MVNETA_ACC_MODE 0x2500
110#define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
111#define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
112#define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
113#define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
willy tarreau40ba35e2014-01-16 08:20:10 +0100114
115/* Exception Interrupt Port/Queue Cause register */
116
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300117#define MVNETA_INTR_NEW_CAUSE 0x25a0
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300118#define MVNETA_INTR_NEW_MASK 0x25a4
willy tarreau40ba35e2014-01-16 08:20:10 +0100119
120/* bits 0..7 = TXQ SENT, one bit per queue.
121 * bits 8..15 = RXQ OCCUP, one bit per queue.
122 * bits 16..23 = RXQ FREE, one bit per queue.
123 * bit 29 = OLD_REG_SUM, see old reg ?
124 * bit 30 = TX_ERR_SUM, one bit for 4 ports
125 * bit 31 = MISC_SUM, one bit for 4 ports
126 */
127#define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
128#define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
129#define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
130#define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
Stas Sergeev898b2972015-04-01 20:32:49 +0300131#define MVNETA_MISCINTR_INTR_MASK BIT(31)
willy tarreau40ba35e2014-01-16 08:20:10 +0100132
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300133#define MVNETA_INTR_OLD_CAUSE 0x25a8
134#define MVNETA_INTR_OLD_MASK 0x25ac
willy tarreau40ba35e2014-01-16 08:20:10 +0100135
136/* Data Path Port/Queue Cause Register */
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300137#define MVNETA_INTR_MISC_CAUSE 0x25b0
138#define MVNETA_INTR_MISC_MASK 0x25b4
willy tarreau40ba35e2014-01-16 08:20:10 +0100139
140#define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
141#define MVNETA_CAUSE_LINK_CHANGE BIT(1)
142#define MVNETA_CAUSE_PTP BIT(4)
143
144#define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
145#define MVNETA_CAUSE_RX_OVERRUN BIT(8)
146#define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
147#define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
148#define MVNETA_CAUSE_TX_UNDERUN BIT(11)
149#define MVNETA_CAUSE_PRBS_ERR BIT(12)
150#define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
151#define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
152
153#define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
154#define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
155#define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
156
157#define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
158#define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
159#define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
160
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300161#define MVNETA_INTR_ENABLE 0x25b8
162#define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
Marcin Wojtasdc1aadf2015-11-30 13:27:43 +0100163#define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff
willy tarreau40ba35e2014-01-16 08:20:10 +0100164
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300165#define MVNETA_RXQ_CMD 0x2680
166#define MVNETA_RXQ_DISABLE_SHIFT 8
167#define MVNETA_RXQ_ENABLE_MASK 0x000000ff
168#define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
169#define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
170#define MVNETA_GMAC_CTRL_0 0x2c00
171#define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
172#define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
173#define MVNETA_GMAC0_PORT_ENABLE BIT(0)
174#define MVNETA_GMAC_CTRL_2 0x2c08
Stas Sergeev898b2972015-04-01 20:32:49 +0300175#define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
Thomas Petazzonia79121d2014-03-26 00:25:41 +0100176#define MVNETA_GMAC2_PCS_ENABLE BIT(3)
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300177#define MVNETA_GMAC2_PORT_RGMII BIT(4)
178#define MVNETA_GMAC2_PORT_RESET BIT(6)
179#define MVNETA_GMAC_STATUS 0x2c10
180#define MVNETA_GMAC_LINK_UP BIT(0)
181#define MVNETA_GMAC_SPEED_1000 BIT(1)
182#define MVNETA_GMAC_SPEED_100 BIT(2)
183#define MVNETA_GMAC_FULL_DUPLEX BIT(3)
184#define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
185#define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
186#define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
187#define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
188#define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
189#define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
190#define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
Stas Sergeev898b2972015-04-01 20:32:49 +0300191#define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300192#define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
193#define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
Thomas Petazzoni71408602013-09-04 16:21:18 +0200194#define MVNETA_GMAC_AN_SPEED_EN BIT(7)
Stas Sergeev898b2972015-04-01 20:32:49 +0300195#define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300196#define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
Thomas Petazzoni71408602013-09-04 16:21:18 +0200197#define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
Andrew Lunne4839112015-10-22 18:37:36 +0100198#define MVNETA_MIB_COUNTERS_BASE 0x3000
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300199#define MVNETA_MIB_LATE_COLLISION 0x7c
200#define MVNETA_DA_FILT_SPEC_MCAST 0x3400
201#define MVNETA_DA_FILT_OTH_MCAST 0x3500
202#define MVNETA_DA_FILT_UCAST_BASE 0x3600
203#define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
204#define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
205#define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
206#define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
207#define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
208#define MVNETA_TXQ_DEC_SENT_SHIFT 16
209#define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
210#define MVNETA_TXQ_SENT_DESC_SHIFT 16
211#define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
212#define MVNETA_PORT_TX_RESET 0x3cf0
213#define MVNETA_PORT_TX_DMA_RESET BIT(0)
214#define MVNETA_TX_MTU 0x3e0c
215#define MVNETA_TX_TOKEN_SIZE 0x3e14
216#define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
217#define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
218#define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
219
220#define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
221
222/* Descriptor ring Macros */
223#define MVNETA_QUEUE_NEXT_DESC(q, index) \
224 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
225
226/* Various constants */
227
228/* Coalescing */
willy tarreauaebea2b2014-12-02 08:13:04 +0100229#define MVNETA_TXDONE_COAL_PKTS 1
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300230#define MVNETA_RX_COAL_PKTS 32
231#define MVNETA_RX_COAL_USEC 100
232
Thomas Petazzoni6a20c172012-11-19 11:41:25 +0100233/* The two bytes Marvell header. Either contains a special value used
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300234 * by Marvell switches when a specific hardware mode is enabled (not
235 * supported by this driver) or is filled automatically by zeroes on
236 * the RX side. Those two bytes being at the front of the Ethernet
237 * header, they allow to have the IP header aligned on a 4 bytes
238 * boundary automatically: the hardware skips those two bytes on its
239 * own.
240 */
241#define MVNETA_MH_SIZE 2
242
243#define MVNETA_VLAN_TAG_LEN 4
244
245#define MVNETA_CPU_D_CACHE_LINE_SIZE 32
246#define MVNETA_TX_CSUM_MAX_SIZE 9800
247#define MVNETA_ACC_MODE_EXT 1
248
249/* Timeout constants */
250#define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
251#define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
252#define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
253
254#define MVNETA_TX_MTU_MAX 0x3ffff
255
Ezequiel Garcia2adb7192014-05-19 13:59:55 -0300256/* TSO header size */
257#define TSO_HEADER_SIZE 128
258
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300259/* Max number of Rx descriptors */
260#define MVNETA_MAX_RXD 128
261
262/* Max number of Tx descriptors */
263#define MVNETA_MAX_TXD 532
264
Ezequiel Garcia8eef5f92014-05-30 13:40:05 -0300265/* Max number of allowed TCP segments for software TSO */
266#define MVNETA_MAX_TSO_SEGS 100
267
268#define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
269
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300270/* descriptor aligned size */
271#define MVNETA_DESC_ALIGNED_SIZE 32
272
273#define MVNETA_RX_PKT_SIZE(mtu) \
274 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
275 ETH_HLEN + ETH_FCS_LEN, \
276 MVNETA_CPU_D_CACHE_LINE_SIZE)
277
Ezequiel Garcia2e3173a2014-05-30 13:40:07 -0300278#define IS_TSO_HEADER(txq, addr) \
279 ((addr >= txq->tso_hdrs_phys) && \
280 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
281
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300282#define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
283
Russell King9b0cdef2015-10-22 18:37:30 +0100284struct mvneta_statistic {
285 unsigned short offset;
286 unsigned short type;
287 const char name[ETH_GSTRING_LEN];
288};
289
290#define T_REG_32 32
291#define T_REG_64 64
292
293static const struct mvneta_statistic mvneta_statistics[] = {
294 { 0x3000, T_REG_64, "good_octets_received", },
295 { 0x3010, T_REG_32, "good_frames_received", },
296 { 0x3008, T_REG_32, "bad_octets_received", },
297 { 0x3014, T_REG_32, "bad_frames_received", },
298 { 0x3018, T_REG_32, "broadcast_frames_received", },
299 { 0x301c, T_REG_32, "multicast_frames_received", },
300 { 0x3050, T_REG_32, "unrec_mac_control_received", },
301 { 0x3058, T_REG_32, "good_fc_received", },
302 { 0x305c, T_REG_32, "bad_fc_received", },
303 { 0x3060, T_REG_32, "undersize_received", },
304 { 0x3064, T_REG_32, "fragments_received", },
305 { 0x3068, T_REG_32, "oversize_received", },
306 { 0x306c, T_REG_32, "jabber_received", },
307 { 0x3070, T_REG_32, "mac_receive_error", },
308 { 0x3074, T_REG_32, "bad_crc_event", },
309 { 0x3078, T_REG_32, "collision", },
310 { 0x307c, T_REG_32, "late_collision", },
311 { 0x2484, T_REG_32, "rx_discard", },
312 { 0x2488, T_REG_32, "rx_overrun", },
313 { 0x3020, T_REG_32, "frames_64_octets", },
314 { 0x3024, T_REG_32, "frames_65_to_127_octets", },
315 { 0x3028, T_REG_32, "frames_128_to_255_octets", },
316 { 0x302c, T_REG_32, "frames_256_to_511_octets", },
317 { 0x3030, T_REG_32, "frames_512_to_1023_octets", },
318 { 0x3034, T_REG_32, "frames_1024_to_max_octets", },
319 { 0x3038, T_REG_64, "good_octets_sent", },
320 { 0x3040, T_REG_32, "good_frames_sent", },
321 { 0x3044, T_REG_32, "excessive_collision", },
322 { 0x3048, T_REG_32, "multicast_frames_sent", },
323 { 0x304c, T_REG_32, "broadcast_frames_sent", },
324 { 0x3054, T_REG_32, "fc_sent", },
325 { 0x300c, T_REG_32, "internal_mac_transmit_err", },
326};
327
willy tarreau74c41b02014-01-16 08:20:08 +0100328struct mvneta_pcpu_stats {
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300329 struct u64_stats_sync syncp;
willy tarreau74c41b02014-01-16 08:20:08 +0100330 u64 rx_packets;
331 u64 rx_bytes;
332 u64 tx_packets;
333 u64 tx_bytes;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300334};
335
Maxime Ripard12bb03b2015-09-25 18:09:36 +0200336struct mvneta_pcpu_port {
337 /* Pointer to the shared port */
338 struct mvneta_port *pp;
339
340 /* Pointer to the CPU-local NAPI struct */
341 struct napi_struct napi;
342
343 /* Cause of the previous interrupt */
344 u32 cause_rx_tx;
345};
346
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300347struct mvneta_port {
Maxime Ripard12bb03b2015-09-25 18:09:36 +0200348 struct mvneta_pcpu_port __percpu *ports;
349 struct mvneta_pcpu_stats __percpu *stats;
350
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300351 int pkt_size;
willy tarreau8ec2cd42014-01-16 08:20:16 +0100352 unsigned int frag_size;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300353 void __iomem *base;
354 struct mvneta_rx_queue *rxqs;
355 struct mvneta_tx_queue *txqs;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300356 struct net_device *dev;
Maxime Ripardf8642882015-09-25 18:09:38 +0200357 struct notifier_block cpu_notifier;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300358
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300359 /* Core clock */
Thomas Petazzoni189dd622012-11-19 14:15:25 +0100360 struct clk *clk;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300361 u8 mcast_count[256];
362 u16 tx_ring_size;
363 u16 rx_ring_size;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300364
365 struct mii_bus *mii_bus;
366 struct phy_device *phy_dev;
367 phy_interface_t phy_interface;
368 struct device_node *phy_node;
369 unsigned int link;
370 unsigned int duplex;
371 unsigned int speed;
Simon Guinotb65657f2015-06-30 16:20:22 +0200372 unsigned int tx_csum_limit;
Stas Sergeev898b2972015-04-01 20:32:49 +0300373 int use_inband_status:1;
Russell King9b0cdef2015-10-22 18:37:30 +0100374
375 u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300376};
377
Thomas Petazzoni6a20c172012-11-19 11:41:25 +0100378/* The mvneta_tx_desc and mvneta_rx_desc structures describe the
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300379 * layout of the transmit and reception DMA descriptors, and their
380 * layout is therefore defined by the hardware design
381 */
Thomas Petazzoni6083ed42013-07-29 15:21:27 +0200382
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300383#define MVNETA_TX_L3_OFF_SHIFT 0
384#define MVNETA_TX_IP_HLEN_SHIFT 8
385#define MVNETA_TX_L4_UDP BIT(16)
386#define MVNETA_TX_L3_IP6 BIT(17)
387#define MVNETA_TXD_IP_CSUM BIT(18)
388#define MVNETA_TXD_Z_PAD BIT(19)
389#define MVNETA_TXD_L_DESC BIT(20)
390#define MVNETA_TXD_F_DESC BIT(21)
391#define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
392 MVNETA_TXD_L_DESC | \
393 MVNETA_TXD_F_DESC)
394#define MVNETA_TX_L4_CSUM_FULL BIT(30)
395#define MVNETA_TX_L4_CSUM_NOT BIT(31)
396
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300397#define MVNETA_RXD_ERR_CRC 0x0
398#define MVNETA_RXD_ERR_SUMMARY BIT(16)
399#define MVNETA_RXD_ERR_OVERRUN BIT(17)
400#define MVNETA_RXD_ERR_LEN BIT(18)
401#define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
402#define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
403#define MVNETA_RXD_L3_IP4 BIT(25)
404#define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
405#define MVNETA_RXD_L4_CSUM_OK BIT(30)
406
Thomas Petazzoni9ad8fef2013-07-29 15:21:28 +0200407#if defined(__LITTLE_ENDIAN)
Thomas Petazzoni6083ed42013-07-29 15:21:27 +0200408struct mvneta_tx_desc {
409 u32 command; /* Options used by HW for packet transmitting.*/
410 u16 reserverd1; /* csum_l4 (for future use) */
411 u16 data_size; /* Data size of transmitted packet in bytes */
412 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
413 u32 reserved2; /* hw_cmd - (for future use, PMT) */
414 u32 reserved3[4]; /* Reserved - (for future use) */
415};
416
417struct mvneta_rx_desc {
418 u32 status; /* Info about received packet */
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300419 u16 reserved1; /* pnc_info - (for future use, PnC) */
420 u16 data_size; /* Size of received packet in bytes */
Thomas Petazzoni6083ed42013-07-29 15:21:27 +0200421
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300422 u32 buf_phys_addr; /* Physical address of the buffer */
423 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
Thomas Petazzoni6083ed42013-07-29 15:21:27 +0200424
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300425 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
426 u16 reserved3; /* prefetch_cmd, for future use */
427 u16 reserved4; /* csum_l4 - (for future use, PnC) */
Thomas Petazzoni6083ed42013-07-29 15:21:27 +0200428
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300429 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
430 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
431};
Thomas Petazzoni9ad8fef2013-07-29 15:21:28 +0200432#else
433struct mvneta_tx_desc {
434 u16 data_size; /* Data size of transmitted packet in bytes */
435 u16 reserverd1; /* csum_l4 (for future use) */
436 u32 command; /* Options used by HW for packet transmitting.*/
437 u32 reserved2; /* hw_cmd - (for future use, PMT) */
438 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
439 u32 reserved3[4]; /* Reserved - (for future use) */
440};
441
442struct mvneta_rx_desc {
443 u16 data_size; /* Size of received packet in bytes */
444 u16 reserved1; /* pnc_info - (for future use, PnC) */
445 u32 status; /* Info about received packet */
446
447 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
448 u32 buf_phys_addr; /* Physical address of the buffer */
449
450 u16 reserved4; /* csum_l4 - (for future use, PnC) */
451 u16 reserved3; /* prefetch_cmd, for future use */
452 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
453
454 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
455 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
456};
457#endif
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300458
459struct mvneta_tx_queue {
460 /* Number of this TX queue, in the range 0-7 */
461 u8 id;
462
463 /* Number of TX DMA descriptors in the descriptor ring */
464 int size;
465
466 /* Number of currently used TX DMA descriptor in the
Thomas Petazzoni6a20c172012-11-19 11:41:25 +0100467 * descriptor ring
468 */
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300469 int count;
Ezequiel Garcia8eef5f92014-05-30 13:40:05 -0300470 int tx_stop_threshold;
471 int tx_wake_threshold;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300472
473 /* Array of transmitted skb */
474 struct sk_buff **tx_skb;
475
476 /* Index of last TX DMA descriptor that was inserted */
477 int txq_put_index;
478
479 /* Index of the TX DMA descriptor to be cleaned up */
480 int txq_get_index;
481
482 u32 done_pkts_coal;
483
484 /* Virtual address of the TX DMA descriptors array */
485 struct mvneta_tx_desc *descs;
486
487 /* DMA address of the TX DMA descriptors array */
488 dma_addr_t descs_phys;
489
490 /* Index of the last TX DMA descriptor */
491 int last_desc;
492
493 /* Index of the next TX DMA descriptor to process */
494 int next_desc_to_proc;
Ezequiel Garcia2adb7192014-05-19 13:59:55 -0300495
496 /* DMA buffers for TSO headers */
497 char *tso_hdrs;
498
499 /* DMA address of TSO headers */
500 dma_addr_t tso_hdrs_phys;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300501};
502
503struct mvneta_rx_queue {
504 /* rx queue number, in the range 0-7 */
505 u8 id;
506
507 /* num of rx descriptors in the rx descriptor ring */
508 int size;
509
510 /* counter of times when mvneta_refill() failed */
511 int missed;
512
513 u32 pkts_coal;
514 u32 time_coal;
515
516 /* Virtual address of the RX DMA descriptors array */
517 struct mvneta_rx_desc *descs;
518
519 /* DMA address of the RX DMA descriptors array */
520 dma_addr_t descs_phys;
521
522 /* Index of the last RX DMA descriptor */
523 int last_desc;
524
525 /* Index of the next RX DMA descriptor to process */
526 int next_desc_to_proc;
527};
528
Ezequiel Garciaedadb7f2014-05-22 20:07:01 -0300529/* The hardware supports eight (8) rx queues, but we are only allowing
530 * the first one to be used. Therefore, let's just allocate one queue.
531 */
Maxime Ripardd8936652015-09-25 18:09:37 +0200532static int rxq_number = 8;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300533static int txq_number = 8;
534
535static int rxq_def;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300536
willy tarreauf19fadf2014-01-16 08:20:17 +0100537static int rx_copybreak __read_mostly = 256;
538
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300539#define MVNETA_DRIVER_NAME "mvneta"
540#define MVNETA_DRIVER_VERSION "1.0"
541
542/* Utility/helper methods */
543
544/* Write helper method */
545static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
546{
547 writel(data, pp->base + offset);
548}
549
550/* Read helper method */
551static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
552{
553 return readl(pp->base + offset);
554}
555
556/* Increment txq get counter */
557static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
558{
559 txq->txq_get_index++;
560 if (txq->txq_get_index == txq->size)
561 txq->txq_get_index = 0;
562}
563
564/* Increment txq put counter */
565static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
566{
567 txq->txq_put_index++;
568 if (txq->txq_put_index == txq->size)
569 txq->txq_put_index = 0;
570}
571
572
573/* Clear all MIB counters */
574static void mvneta_mib_counters_clear(struct mvneta_port *pp)
575{
576 int i;
577 u32 dummy;
578
579 /* Perform dummy reads from MIB counters */
580 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
581 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
Andrew Lunne4839112015-10-22 18:37:36 +0100582 dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT);
583 dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT);
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300584}
585
586/* Get System Network Statistics */
587struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev,
588 struct rtnl_link_stats64 *stats)
589{
590 struct mvneta_port *pp = netdev_priv(dev);
591 unsigned int start;
willy tarreau74c41b02014-01-16 08:20:08 +0100592 int cpu;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300593
willy tarreau74c41b02014-01-16 08:20:08 +0100594 for_each_possible_cpu(cpu) {
595 struct mvneta_pcpu_stats *cpu_stats;
596 u64 rx_packets;
597 u64 rx_bytes;
598 u64 tx_packets;
599 u64 tx_bytes;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300600
willy tarreau74c41b02014-01-16 08:20:08 +0100601 cpu_stats = per_cpu_ptr(pp->stats, cpu);
602 do {
Eric W. Biederman57a77442014-03-13 21:26:42 -0700603 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
willy tarreau74c41b02014-01-16 08:20:08 +0100604 rx_packets = cpu_stats->rx_packets;
605 rx_bytes = cpu_stats->rx_bytes;
606 tx_packets = cpu_stats->tx_packets;
607 tx_bytes = cpu_stats->tx_bytes;
Eric W. Biederman57a77442014-03-13 21:26:42 -0700608 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300609
willy tarreau74c41b02014-01-16 08:20:08 +0100610 stats->rx_packets += rx_packets;
611 stats->rx_bytes += rx_bytes;
612 stats->tx_packets += tx_packets;
613 stats->tx_bytes += tx_bytes;
614 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300615
616 stats->rx_errors = dev->stats.rx_errors;
617 stats->rx_dropped = dev->stats.rx_dropped;
618
619 stats->tx_dropped = dev->stats.tx_dropped;
620
621 return stats;
622}
623
624/* Rx descriptors helper methods */
625
willy tarreau54282132014-01-16 08:20:14 +0100626/* Checks whether the RX descriptor having this status is both the first
627 * and the last descriptor for the RX packet. Each RX packet is currently
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300628 * received through a single RX descriptor, so not having each RX
629 * descriptor with its first and last bits set is an error
630 */
willy tarreau54282132014-01-16 08:20:14 +0100631static int mvneta_rxq_desc_is_first_last(u32 status)
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300632{
willy tarreau54282132014-01-16 08:20:14 +0100633 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300634 MVNETA_RXD_FIRST_LAST_DESC;
635}
636
637/* Add number of descriptors ready to receive new packets */
638static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
639 struct mvneta_rx_queue *rxq,
640 int ndescs)
641{
642 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
Thomas Petazzoni6a20c172012-11-19 11:41:25 +0100643 * be added at once
644 */
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300645 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
646 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
647 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
648 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
649 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
650 }
651
652 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
653 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
654}
655
656/* Get number of RX descriptors occupied by received packets */
657static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
658 struct mvneta_rx_queue *rxq)
659{
660 u32 val;
661
662 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
663 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
664}
665
Thomas Petazzoni6a20c172012-11-19 11:41:25 +0100666/* Update num of rx desc called upon return from rx path or
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300667 * from mvneta_rxq_drop_pkts().
668 */
669static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
670 struct mvneta_rx_queue *rxq,
671 int rx_done, int rx_filled)
672{
673 u32 val;
674
675 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
676 val = rx_done |
677 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
678 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
679 return;
680 }
681
682 /* Only 255 descriptors can be added at once */
683 while ((rx_done > 0) || (rx_filled > 0)) {
684 if (rx_done <= 0xff) {
685 val = rx_done;
686 rx_done = 0;
687 } else {
688 val = 0xff;
689 rx_done -= 0xff;
690 }
691 if (rx_filled <= 0xff) {
692 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
693 rx_filled = 0;
694 } else {
695 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
696 rx_filled -= 0xff;
697 }
698 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
699 }
700}
701
702/* Get pointer to next RX descriptor to be processed by SW */
703static struct mvneta_rx_desc *
704mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
705{
706 int rx_desc = rxq->next_desc_to_proc;
707
708 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
willy tarreau34e41792014-01-16 08:20:15 +0100709 prefetch(rxq->descs + rxq->next_desc_to_proc);
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300710 return rxq->descs + rx_desc;
711}
712
713/* Change maximum receive size of the port. */
714static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
715{
716 u32 val;
717
718 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
719 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
720 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
721 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
722 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
723}
724
725
726/* Set rx queue offset */
727static void mvneta_rxq_offset_set(struct mvneta_port *pp,
728 struct mvneta_rx_queue *rxq,
729 int offset)
730{
731 u32 val;
732
733 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
734 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
735
736 /* Offset is in */
737 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
738 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
739}
740
741
742/* Tx descriptors helper methods */
743
744/* Update HW with number of TX descriptors to be sent */
745static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
746 struct mvneta_tx_queue *txq,
747 int pend_desc)
748{
749 u32 val;
750
751 /* Only 255 descriptors can be added at once ; Assume caller
Thomas Petazzoni6a20c172012-11-19 11:41:25 +0100752 * process TX desriptors in quanta less than 256
753 */
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300754 val = pend_desc;
755 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
756}
757
758/* Get pointer to next TX descriptor to be processed (send) by HW */
759static struct mvneta_tx_desc *
760mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
761{
762 int tx_desc = txq->next_desc_to_proc;
763
764 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
765 return txq->descs + tx_desc;
766}
767
768/* Release the last allocated TX descriptor. Useful to handle DMA
Thomas Petazzoni6a20c172012-11-19 11:41:25 +0100769 * mapping failures in the TX path.
770 */
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300771static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
772{
773 if (txq->next_desc_to_proc == 0)
774 txq->next_desc_to_proc = txq->last_desc - 1;
775 else
776 txq->next_desc_to_proc--;
777}
778
779/* Set rxq buf size */
780static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
781 struct mvneta_rx_queue *rxq,
782 int buf_size)
783{
784 u32 val;
785
786 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
787
788 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
789 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
790
791 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
792}
793
794/* Disable buffer management (BM) */
795static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
796 struct mvneta_rx_queue *rxq)
797{
798 u32 val;
799
800 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
801 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
802 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
803}
804
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300805/* Start the Ethernet port RX and TX activity */
806static void mvneta_port_up(struct mvneta_port *pp)
807{
808 int queue;
809 u32 q_map;
810
811 /* Enable all initialized TXs. */
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300812 q_map = 0;
813 for (queue = 0; queue < txq_number; queue++) {
814 struct mvneta_tx_queue *txq = &pp->txqs[queue];
815 if (txq->descs != NULL)
816 q_map |= (1 << queue);
817 }
818 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
819
820 /* Enable all initialized RXQs. */
Maxime Ripardd8936652015-09-25 18:09:37 +0200821 mvreg_write(pp, MVNETA_RXQ_CMD, BIT(rxq_def));
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300822}
823
824/* Stop the Ethernet port activity */
825static void mvneta_port_down(struct mvneta_port *pp)
826{
827 u32 val;
828 int count;
829
830 /* Stop Rx port activity. Check port Rx activity. */
831 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
832
833 /* Issue stop command for active channels only */
834 if (val != 0)
835 mvreg_write(pp, MVNETA_RXQ_CMD,
836 val << MVNETA_RXQ_DISABLE_SHIFT);
837
838 /* Wait for all Rx activity to terminate. */
839 count = 0;
840 do {
841 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
842 netdev_warn(pp->dev,
843 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
844 val);
845 break;
846 }
847 mdelay(1);
848
849 val = mvreg_read(pp, MVNETA_RXQ_CMD);
850 } while (val & 0xff);
851
852 /* Stop Tx port activity. Check port Tx activity. Issue stop
Thomas Petazzoni6a20c172012-11-19 11:41:25 +0100853 * command for active channels only
854 */
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300855 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
856
857 if (val != 0)
858 mvreg_write(pp, MVNETA_TXQ_CMD,
859 (val << MVNETA_TXQ_DISABLE_SHIFT));
860
861 /* Wait for all Tx activity to terminate. */
862 count = 0;
863 do {
864 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
865 netdev_warn(pp->dev,
866 "TIMEOUT for TX stopped status=0x%08x\n",
867 val);
868 break;
869 }
870 mdelay(1);
871
872 /* Check TX Command reg that all Txqs are stopped */
873 val = mvreg_read(pp, MVNETA_TXQ_CMD);
874
875 } while (val & 0xff);
876
877 /* Double check to verify that TX FIFO is empty */
878 count = 0;
879 do {
880 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
881 netdev_warn(pp->dev,
882 "TX FIFO empty timeout status=0x08%x\n",
883 val);
884 break;
885 }
886 mdelay(1);
887
888 val = mvreg_read(pp, MVNETA_PORT_STATUS);
889 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
890 (val & MVNETA_TX_IN_PRGRS));
891
892 udelay(200);
893}
894
895/* Enable the port by setting the port enable bit of the MAC control register */
896static void mvneta_port_enable(struct mvneta_port *pp)
897{
898 u32 val;
899
900 /* Enable port */
901 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
902 val |= MVNETA_GMAC0_PORT_ENABLE;
903 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
904}
905
906/* Disable the port and wait for about 200 usec before retuning */
907static void mvneta_port_disable(struct mvneta_port *pp)
908{
909 u32 val;
910
911 /* Reset the Enable bit in the Serial Control Register */
912 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
913 val &= ~MVNETA_GMAC0_PORT_ENABLE;
914 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
915
916 udelay(200);
917}
918
919/* Multicast tables methods */
920
921/* Set all entries in Unicast MAC Table; queue==-1 means reject all */
922static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
923{
924 int offset;
925 u32 val;
926
927 if (queue == -1) {
928 val = 0;
929 } else {
930 val = 0x1 | (queue << 1);
931 val |= (val << 24) | (val << 16) | (val << 8);
932 }
933
934 for (offset = 0; offset <= 0xc; offset += 4)
935 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
936}
937
938/* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
939static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
940{
941 int offset;
942 u32 val;
943
944 if (queue == -1) {
945 val = 0;
946 } else {
947 val = 0x1 | (queue << 1);
948 val |= (val << 24) | (val << 16) | (val << 8);
949 }
950
951 for (offset = 0; offset <= 0xfc; offset += 4)
952 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
953
954}
955
956/* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
957static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
958{
959 int offset;
960 u32 val;
961
962 if (queue == -1) {
963 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
964 val = 0;
965 } else {
966 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
967 val = 0x1 | (queue << 1);
968 val |= (val << 24) | (val << 16) | (val << 8);
969 }
970
971 for (offset = 0; offset <= 0xfc; offset += 4)
972 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
973}
974
975/* This method sets defaults to the NETA port:
976 * Clears interrupt Cause and Mask registers.
977 * Clears all MAC tables.
978 * Sets defaults to all registers.
979 * Resets RX and TX descriptor rings.
980 * Resets PHY.
981 * This method can be called after mvneta_port_down() to return the port
982 * settings to defaults.
983 */
984static void mvneta_defaults_set(struct mvneta_port *pp)
985{
986 int cpu;
987 int queue;
988 u32 val;
989
990 /* Clear all Cause registers */
991 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
992 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
993 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
994
995 /* Mask all interrupts */
996 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
997 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
998 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
999 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
1000
1001 /* Enable MBUS Retry bit16 */
1002 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
1003
1004 /* Set CPU queue access map - all CPUs have access to all RX
Thomas Petazzoni6a20c172012-11-19 11:41:25 +01001005 * queues and to all TX queues
1006 */
Maxime Ripard2502d0e2015-09-25 18:09:35 +02001007 for_each_present_cpu(cpu)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001008 mvreg_write(pp, MVNETA_CPU_MAP(cpu),
1009 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
1010 MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
1011
1012 /* Reset RX and TX DMAs */
1013 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
1014 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1015
1016 /* Disable Legacy WRR, Disable EJP, Release from reset */
1017 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
1018 for (queue = 0; queue < txq_number; queue++) {
1019 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
1020 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
1021 }
1022
1023 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1024 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
1025
1026 /* Set Port Acceleration Mode */
1027 val = MVNETA_ACC_MODE_EXT;
1028 mvreg_write(pp, MVNETA_ACC_MODE, val);
1029
1030 /* Update val of portCfg register accordingly with all RxQueue types */
1031 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
1032 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
1033
1034 val = 0;
1035 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
1036 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
1037
1038 /* Build PORT_SDMA_CONFIG_REG */
1039 val = 0;
1040
1041 /* Default burst size */
1042 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1043 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
Thomas Petazzoni9ad8fef2013-07-29 15:21:28 +02001044 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001045
Thomas Petazzoni9ad8fef2013-07-29 15:21:28 +02001046#if defined(__BIG_ENDIAN)
1047 val |= MVNETA_DESC_SWAP;
1048#endif
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001049
1050 /* Assign port SDMA configuration */
1051 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
1052
Thomas Petazzoni71408602013-09-04 16:21:18 +02001053 /* Disable PHY polling in hardware, since we're using the
1054 * kernel phylib to do this.
1055 */
1056 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
1057 val &= ~MVNETA_PHY_POLLING_ENABLE;
1058 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
1059
Stas Sergeev898b2972015-04-01 20:32:49 +03001060 if (pp->use_inband_status) {
1061 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1062 val &= ~(MVNETA_GMAC_FORCE_LINK_PASS |
1063 MVNETA_GMAC_FORCE_LINK_DOWN |
1064 MVNETA_GMAC_AN_FLOW_CTRL_EN);
1065 val |= MVNETA_GMAC_INBAND_AN_ENABLE |
1066 MVNETA_GMAC_AN_SPEED_EN |
1067 MVNETA_GMAC_AN_DUPLEX_EN;
1068 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1069 val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
1070 val |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
1071 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
Stas Sergeev538761b2015-06-18 18:36:03 +03001072 } else {
1073 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1074 val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE |
1075 MVNETA_GMAC_AN_SPEED_EN |
1076 MVNETA_GMAC_AN_DUPLEX_EN);
1077 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
Stas Sergeev898b2972015-04-01 20:32:49 +03001078 }
1079
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001080 mvneta_set_ucast_table(pp, -1);
1081 mvneta_set_special_mcast_table(pp, -1);
1082 mvneta_set_other_mcast_table(pp, -1);
1083
1084 /* Set port interrupt enable register - default enable all */
1085 mvreg_write(pp, MVNETA_INTR_ENABLE,
1086 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
1087 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
Andrew Lunne4839112015-10-22 18:37:36 +01001088
1089 mvneta_mib_counters_clear(pp);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001090}
1091
1092/* Set max sizes for tx queues */
1093static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
1094
1095{
1096 u32 val, size, mtu;
1097 int queue;
1098
1099 mtu = max_tx_size * 8;
1100 if (mtu > MVNETA_TX_MTU_MAX)
1101 mtu = MVNETA_TX_MTU_MAX;
1102
1103 /* Set MTU */
1104 val = mvreg_read(pp, MVNETA_TX_MTU);
1105 val &= ~MVNETA_TX_MTU_MAX;
1106 val |= mtu;
1107 mvreg_write(pp, MVNETA_TX_MTU, val);
1108
1109 /* TX token size and all TXQs token size must be larger that MTU */
1110 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1111
1112 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
1113 if (size < mtu) {
1114 size = mtu;
1115 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
1116 val |= size;
1117 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1118 }
1119 for (queue = 0; queue < txq_number; queue++) {
1120 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1121
1122 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
1123 if (size < mtu) {
1124 size = mtu;
1125 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
1126 val |= size;
1127 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1128 }
1129 }
1130}
1131
1132/* Set unicast address */
1133static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
1134 int queue)
1135{
1136 unsigned int unicast_reg;
1137 unsigned int tbl_offset;
1138 unsigned int reg_offset;
1139
1140 /* Locate the Unicast table entry */
1141 last_nibble = (0xf & last_nibble);
1142
1143 /* offset from unicast tbl base */
1144 tbl_offset = (last_nibble / 4) * 4;
1145
1146 /* offset within the above reg */
1147 reg_offset = last_nibble % 4;
1148
1149 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1150
1151 if (queue == -1) {
1152 /* Clear accepts frame bit at specified unicast DA tbl entry */
1153 unicast_reg &= ~(0xff << (8 * reg_offset));
1154 } else {
1155 unicast_reg &= ~(0xff << (8 * reg_offset));
1156 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1157 }
1158
1159 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1160}
1161
1162/* Set mac address */
1163static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1164 int queue)
1165{
1166 unsigned int mac_h;
1167 unsigned int mac_l;
1168
1169 if (queue != -1) {
1170 mac_l = (addr[4] << 8) | (addr[5]);
1171 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1172 (addr[2] << 8) | (addr[3] << 0);
1173
1174 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1175 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1176 }
1177
1178 /* Accept frames of this address */
1179 mvneta_set_ucast_addr(pp, addr[5], queue);
1180}
1181
Thomas Petazzoni6a20c172012-11-19 11:41:25 +01001182/* Set the number of packets that will be received before RX interrupt
1183 * will be generated by HW.
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001184 */
1185static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1186 struct mvneta_rx_queue *rxq, u32 value)
1187{
1188 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1189 value | MVNETA_RXQ_NON_OCCUPIED(0));
1190 rxq->pkts_coal = value;
1191}
1192
Thomas Petazzoni6a20c172012-11-19 11:41:25 +01001193/* Set the time delay in usec before RX interrupt will be generated by
1194 * HW.
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001195 */
1196static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1197 struct mvneta_rx_queue *rxq, u32 value)
1198{
Thomas Petazzoni189dd622012-11-19 14:15:25 +01001199 u32 val;
1200 unsigned long clk_rate;
1201
1202 clk_rate = clk_get_rate(pp->clk);
1203 val = (clk_rate / 1000000) * value;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001204
1205 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1206 rxq->time_coal = value;
1207}
1208
1209/* Set threshold for TX_DONE pkts coalescing */
1210static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1211 struct mvneta_tx_queue *txq, u32 value)
1212{
1213 u32 val;
1214
1215 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1216
1217 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1218 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1219
1220 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1221
1222 txq->done_pkts_coal = value;
1223}
1224
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001225/* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1226static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1227 u32 phys_addr, u32 cookie)
1228{
1229 rx_desc->buf_cookie = cookie;
1230 rx_desc->buf_phys_addr = phys_addr;
1231}
1232
1233/* Decrement sent descriptors counter */
1234static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1235 struct mvneta_tx_queue *txq,
1236 int sent_desc)
1237{
1238 u32 val;
1239
1240 /* Only 255 TX descriptors can be updated at once */
1241 while (sent_desc > 0xff) {
1242 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1243 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1244 sent_desc = sent_desc - 0xff;
1245 }
1246
1247 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1248 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1249}
1250
1251/* Get number of TX descriptors already sent by HW */
1252static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1253 struct mvneta_tx_queue *txq)
1254{
1255 u32 val;
1256 int sent_desc;
1257
1258 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1259 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1260 MVNETA_TXQ_SENT_DESC_SHIFT;
1261
1262 return sent_desc;
1263}
1264
Thomas Petazzoni6a20c172012-11-19 11:41:25 +01001265/* Get number of sent descriptors and decrement counter.
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001266 * The number of sent descriptors is returned.
1267 */
1268static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1269 struct mvneta_tx_queue *txq)
1270{
1271 int sent_desc;
1272
1273 /* Get number of sent descriptors */
1274 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1275
1276 /* Decrement sent descriptors counter */
1277 if (sent_desc)
1278 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1279
1280 return sent_desc;
1281}
1282
1283/* Set TXQ descriptors fields relevant for CSUM calculation */
1284static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1285 int ip_hdr_len, int l4_proto)
1286{
1287 u32 command;
1288
1289 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
Thomas Petazzoni6a20c172012-11-19 11:41:25 +01001290 * G_L4_chk, L4_type; required only for checksum
1291 * calculation
1292 */
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001293 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1294 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1295
Thomas Fitzsimmons0a198582014-07-08 19:44:07 -04001296 if (l3_proto == htons(ETH_P_IP))
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001297 command |= MVNETA_TXD_IP_CSUM;
1298 else
1299 command |= MVNETA_TX_L3_IP6;
1300
1301 if (l4_proto == IPPROTO_TCP)
1302 command |= MVNETA_TX_L4_CSUM_FULL;
1303 else if (l4_proto == IPPROTO_UDP)
1304 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1305 else
1306 command |= MVNETA_TX_L4_CSUM_NOT;
1307
1308 return command;
1309}
1310
1311
1312/* Display more error info */
1313static void mvneta_rx_error(struct mvneta_port *pp,
1314 struct mvneta_rx_desc *rx_desc)
1315{
1316 u32 status = rx_desc->status;
1317
willy tarreau54282132014-01-16 08:20:14 +01001318 if (!mvneta_rxq_desc_is_first_last(status)) {
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001319 netdev_err(pp->dev,
1320 "bad rx status %08x (buffer oversize), size=%d\n",
willy tarreau54282132014-01-16 08:20:14 +01001321 status, rx_desc->data_size);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001322 return;
1323 }
1324
1325 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1326 case MVNETA_RXD_ERR_CRC:
1327 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1328 status, rx_desc->data_size);
1329 break;
1330 case MVNETA_RXD_ERR_OVERRUN:
1331 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1332 status, rx_desc->data_size);
1333 break;
1334 case MVNETA_RXD_ERR_LEN:
1335 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1336 status, rx_desc->data_size);
1337 break;
1338 case MVNETA_RXD_ERR_RESOURCE:
1339 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1340 status, rx_desc->data_size);
1341 break;
1342 }
1343}
1344
willy tarreau54282132014-01-16 08:20:14 +01001345/* Handle RX checksum offload based on the descriptor's status */
1346static void mvneta_rx_csum(struct mvneta_port *pp, u32 status,
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001347 struct sk_buff *skb)
1348{
willy tarreau54282132014-01-16 08:20:14 +01001349 if ((status & MVNETA_RXD_L3_IP4) &&
1350 (status & MVNETA_RXD_L4_CSUM_OK)) {
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001351 skb->csum = 0;
1352 skb->ip_summed = CHECKSUM_UNNECESSARY;
1353 return;
1354 }
1355
1356 skb->ip_summed = CHECKSUM_NONE;
1357}
1358
willy tarreau6c498972014-01-16 08:20:12 +01001359/* Return tx queue pointer (find last set bit) according to <cause> returned
1360 * form tx_done reg. <cause> must not be null. The return value is always a
1361 * valid queue for matching the first one found in <cause>.
1362 */
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001363static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1364 u32 cause)
1365{
1366 int queue = fls(cause) - 1;
1367
willy tarreau6c498972014-01-16 08:20:12 +01001368 return &pp->txqs[queue];
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001369}
1370
1371/* Free tx queue skbuffs */
1372static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1373 struct mvneta_tx_queue *txq, int num)
1374{
1375 int i;
1376
1377 for (i = 0; i < num; i++) {
1378 struct mvneta_tx_desc *tx_desc = txq->descs +
1379 txq->txq_get_index;
1380 struct sk_buff *skb = txq->tx_skb[txq->txq_get_index];
1381
1382 mvneta_txq_inc_get(txq);
1383
Ezequiel Garcia2e3173a2014-05-30 13:40:07 -03001384 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
1385 dma_unmap_single(pp->dev->dev.parent,
1386 tx_desc->buf_phys_addr,
1387 tx_desc->data_size, DMA_TO_DEVICE);
Ezequiel Garciaba7e46e2014-05-30 13:40:06 -03001388 if (!skb)
1389 continue;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001390 dev_kfree_skb_any(skb);
1391 }
1392}
1393
1394/* Handle end of transmission */
Arnaud Ebalardcd713192014-01-16 08:20:19 +01001395static void mvneta_txq_done(struct mvneta_port *pp,
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001396 struct mvneta_tx_queue *txq)
1397{
1398 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1399 int tx_done;
1400
1401 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
Arnaud Ebalardcd713192014-01-16 08:20:19 +01001402 if (!tx_done)
1403 return;
1404
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001405 mvneta_txq_bufs_free(pp, txq, tx_done);
1406
1407 txq->count -= tx_done;
1408
1409 if (netif_tx_queue_stopped(nq)) {
Ezequiel Garcia8eef5f92014-05-30 13:40:05 -03001410 if (txq->count <= txq->tx_wake_threshold)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001411 netif_tx_wake_queue(nq);
1412 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001413}
1414
willy tarreau8ec2cd42014-01-16 08:20:16 +01001415static void *mvneta_frag_alloc(const struct mvneta_port *pp)
1416{
1417 if (likely(pp->frag_size <= PAGE_SIZE))
1418 return netdev_alloc_frag(pp->frag_size);
1419 else
1420 return kmalloc(pp->frag_size, GFP_ATOMIC);
1421}
1422
1423static void mvneta_frag_free(const struct mvneta_port *pp, void *data)
1424{
1425 if (likely(pp->frag_size <= PAGE_SIZE))
Alexander Duyck13dc0d22015-05-06 21:12:14 -07001426 skb_free_frag(data);
willy tarreau8ec2cd42014-01-16 08:20:16 +01001427 else
1428 kfree(data);
1429}
1430
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001431/* Refill processing */
1432static int mvneta_rx_refill(struct mvneta_port *pp,
1433 struct mvneta_rx_desc *rx_desc)
1434
1435{
1436 dma_addr_t phys_addr;
willy tarreau8ec2cd42014-01-16 08:20:16 +01001437 void *data;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001438
willy tarreau8ec2cd42014-01-16 08:20:16 +01001439 data = mvneta_frag_alloc(pp);
1440 if (!data)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001441 return -ENOMEM;
1442
willy tarreau8ec2cd42014-01-16 08:20:16 +01001443 phys_addr = dma_map_single(pp->dev->dev.parent, data,
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001444 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1445 DMA_FROM_DEVICE);
1446 if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
willy tarreau8ec2cd42014-01-16 08:20:16 +01001447 mvneta_frag_free(pp, data);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001448 return -ENOMEM;
1449 }
1450
willy tarreau8ec2cd42014-01-16 08:20:16 +01001451 mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001452 return 0;
1453}
1454
1455/* Handle tx checksum */
1456static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1457{
1458 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1459 int ip_hdr_len = 0;
Vlad Yasevich817dbfa2014-08-25 10:34:54 -04001460 __be16 l3_proto = vlan_get_protocol(skb);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001461 u8 l4_proto;
1462
Vlad Yasevich817dbfa2014-08-25 10:34:54 -04001463 if (l3_proto == htons(ETH_P_IP)) {
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001464 struct iphdr *ip4h = ip_hdr(skb);
1465
1466 /* Calculate IPv4 checksum and L4 checksum */
1467 ip_hdr_len = ip4h->ihl;
1468 l4_proto = ip4h->protocol;
Vlad Yasevich817dbfa2014-08-25 10:34:54 -04001469 } else if (l3_proto == htons(ETH_P_IPV6)) {
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001470 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1471
1472 /* Read l4_protocol from one of IPv6 extra headers */
1473 if (skb_network_header_len(skb) > 0)
1474 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1475 l4_proto = ip6h->nexthdr;
1476 } else
1477 return MVNETA_TX_L4_CSUM_NOT;
1478
1479 return mvneta_txq_desc_csum(skb_network_offset(skb),
Vlad Yasevich817dbfa2014-08-25 10:34:54 -04001480 l3_proto, ip_hdr_len, l4_proto);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001481 }
1482
1483 return MVNETA_TX_L4_CSUM_NOT;
1484}
1485
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001486/* Drop packets received by the RXQ and free buffers */
1487static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1488 struct mvneta_rx_queue *rxq)
1489{
1490 int rx_done, i;
1491
1492 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1493 for (i = 0; i < rxq->size; i++) {
1494 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
willy tarreau8ec2cd42014-01-16 08:20:16 +01001495 void *data = (void *)rx_desc->buf_cookie;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001496
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001497 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
Ezequiel Garciaa328f3a2013-12-05 13:35:37 -03001498 MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
Justin Maggard8c94ddb2015-11-09 17:21:05 -08001499 mvneta_frag_free(pp, data);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001500 }
1501
1502 if (rx_done)
1503 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1504}
1505
1506/* Main rx processing */
1507static int mvneta_rx(struct mvneta_port *pp, int rx_todo,
1508 struct mvneta_rx_queue *rxq)
1509{
Maxime Ripard12bb03b2015-09-25 18:09:36 +02001510 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001511 struct net_device *dev = pp->dev;
Simon Guinota84e3282015-07-19 13:00:53 +02001512 int rx_done;
willy tarreaudc4277d2014-01-16 08:20:07 +01001513 u32 rcvd_pkts = 0;
1514 u32 rcvd_bytes = 0;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001515
1516 /* Get number of received packets */
1517 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1518
1519 if (rx_todo > rx_done)
1520 rx_todo = rx_done;
1521
1522 rx_done = 0;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001523
1524 /* Fairness NAPI loop */
1525 while (rx_done < rx_todo) {
1526 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
1527 struct sk_buff *skb;
willy tarreau8ec2cd42014-01-16 08:20:16 +01001528 unsigned char *data;
Simon Guinotdaf158d2015-09-15 22:41:21 +02001529 dma_addr_t phys_addr;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001530 u32 rx_status;
1531 int rx_bytes, err;
1532
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001533 rx_done++;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001534 rx_status = rx_desc->status;
willy tarreauf19fadf2014-01-16 08:20:17 +01001535 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
willy tarreau8ec2cd42014-01-16 08:20:16 +01001536 data = (unsigned char *)rx_desc->buf_cookie;
Simon Guinotdaf158d2015-09-15 22:41:21 +02001537 phys_addr = rx_desc->buf_phys_addr;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001538
willy tarreau54282132014-01-16 08:20:14 +01001539 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
willy tarreauf19fadf2014-01-16 08:20:17 +01001540 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1541 err_drop_frame:
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001542 dev->stats.rx_errors++;
1543 mvneta_rx_error(pp, rx_desc);
willy tarreau8ec2cd42014-01-16 08:20:16 +01001544 /* leave the descriptor untouched */
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001545 continue;
1546 }
1547
willy tarreauf19fadf2014-01-16 08:20:17 +01001548 if (rx_bytes <= rx_copybreak) {
1549 /* better copy a small frame and not unmap the DMA region */
1550 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
1551 if (unlikely(!skb))
1552 goto err_drop_frame;
1553
1554 dma_sync_single_range_for_cpu(dev->dev.parent,
1555 rx_desc->buf_phys_addr,
1556 MVNETA_MH_SIZE + NET_SKB_PAD,
1557 rx_bytes,
1558 DMA_FROM_DEVICE);
1559 memcpy(skb_put(skb, rx_bytes),
1560 data + MVNETA_MH_SIZE + NET_SKB_PAD,
1561 rx_bytes);
1562
1563 skb->protocol = eth_type_trans(skb, dev);
1564 mvneta_rx_csum(pp, rx_status, skb);
Maxime Ripard12bb03b2015-09-25 18:09:36 +02001565 napi_gro_receive(&port->napi, skb);
willy tarreauf19fadf2014-01-16 08:20:17 +01001566
1567 rcvd_pkts++;
1568 rcvd_bytes += rx_bytes;
1569
1570 /* leave the descriptor and buffer untouched */
1571 continue;
1572 }
1573
Simon Guinota84e3282015-07-19 13:00:53 +02001574 /* Refill processing */
1575 err = mvneta_rx_refill(pp, rx_desc);
1576 if (err) {
1577 netdev_err(dev, "Linux processing - Can't refill\n");
1578 rxq->missed++;
1579 goto err_drop_frame;
1580 }
1581
willy tarreauf19fadf2014-01-16 08:20:17 +01001582 skb = build_skb(data, pp->frag_size > PAGE_SIZE ? 0 : pp->frag_size);
willy tarreauf19fadf2014-01-16 08:20:17 +01001583
Marcin Wojtas26c17a172015-11-30 13:27:44 +01001584 /* After refill old buffer has to be unmapped regardless
1585 * the skb is successfully built or not.
1586 */
Simon Guinotdaf158d2015-09-15 22:41:21 +02001587 dma_unmap_single(dev->dev.parent, phys_addr,
Ezequiel Garciaa328f3a2013-12-05 13:35:37 -03001588 MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001589
Marcin Wojtas26c17a172015-11-30 13:27:44 +01001590 if (!skb)
1591 goto err_drop_frame;
1592
willy tarreaudc4277d2014-01-16 08:20:07 +01001593 rcvd_pkts++;
1594 rcvd_bytes += rx_bytes;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001595
1596 /* Linux processing */
willy tarreau8ec2cd42014-01-16 08:20:16 +01001597 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001598 skb_put(skb, rx_bytes);
1599
1600 skb->protocol = eth_type_trans(skb, dev);
1601
willy tarreau54282132014-01-16 08:20:14 +01001602 mvneta_rx_csum(pp, rx_status, skb);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001603
Maxime Ripard12bb03b2015-09-25 18:09:36 +02001604 napi_gro_receive(&port->napi, skb);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001605 }
1606
willy tarreaudc4277d2014-01-16 08:20:07 +01001607 if (rcvd_pkts) {
willy tarreau74c41b02014-01-16 08:20:08 +01001608 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1609
1610 u64_stats_update_begin(&stats->syncp);
1611 stats->rx_packets += rcvd_pkts;
1612 stats->rx_bytes += rcvd_bytes;
1613 u64_stats_update_end(&stats->syncp);
willy tarreaudc4277d2014-01-16 08:20:07 +01001614 }
1615
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001616 /* Update rxq management counters */
Simon Guinota84e3282015-07-19 13:00:53 +02001617 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001618
1619 return rx_done;
1620}
1621
Ezequiel Garcia2adb7192014-05-19 13:59:55 -03001622static inline void
1623mvneta_tso_put_hdr(struct sk_buff *skb,
1624 struct mvneta_port *pp, struct mvneta_tx_queue *txq)
1625{
1626 struct mvneta_tx_desc *tx_desc;
1627 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1628
1629 txq->tx_skb[txq->txq_put_index] = NULL;
1630 tx_desc = mvneta_txq_next_desc_get(txq);
1631 tx_desc->data_size = hdr_len;
1632 tx_desc->command = mvneta_skb_tx_csum(pp, skb);
1633 tx_desc->command |= MVNETA_TXD_F_DESC;
1634 tx_desc->buf_phys_addr = txq->tso_hdrs_phys +
1635 txq->txq_put_index * TSO_HEADER_SIZE;
1636 mvneta_txq_inc_put(txq);
1637}
1638
1639static inline int
1640mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq,
1641 struct sk_buff *skb, char *data, int size,
1642 bool last_tcp, bool is_last)
1643{
1644 struct mvneta_tx_desc *tx_desc;
1645
1646 tx_desc = mvneta_txq_next_desc_get(txq);
1647 tx_desc->data_size = size;
1648 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data,
1649 size, DMA_TO_DEVICE);
1650 if (unlikely(dma_mapping_error(dev->dev.parent,
1651 tx_desc->buf_phys_addr))) {
1652 mvneta_txq_desc_put(txq);
1653 return -ENOMEM;
1654 }
1655
1656 tx_desc->command = 0;
1657 txq->tx_skb[txq->txq_put_index] = NULL;
1658
1659 if (last_tcp) {
1660 /* last descriptor in the TCP packet */
1661 tx_desc->command = MVNETA_TXD_L_DESC;
1662
1663 /* last descriptor in SKB */
1664 if (is_last)
1665 txq->tx_skb[txq->txq_put_index] = skb;
1666 }
1667 mvneta_txq_inc_put(txq);
1668 return 0;
1669}
1670
1671static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev,
1672 struct mvneta_tx_queue *txq)
1673{
1674 int total_len, data_left;
1675 int desc_count = 0;
1676 struct mvneta_port *pp = netdev_priv(dev);
1677 struct tso_t tso;
1678 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1679 int i;
1680
1681 /* Count needed descriptors */
1682 if ((txq->count + tso_count_descs(skb)) >= txq->size)
1683 return 0;
1684
1685 if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) {
1686 pr_info("*** Is this even possible???!?!?\n");
1687 return 0;
1688 }
1689
1690 /* Initialize the TSO handler, and prepare the first payload */
1691 tso_start(skb, &tso);
1692
1693 total_len = skb->len - hdr_len;
1694 while (total_len > 0) {
1695 char *hdr;
1696
1697 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
1698 total_len -= data_left;
1699 desc_count++;
1700
1701 /* prepare packet headers: MAC + IP + TCP */
1702 hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE;
1703 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
1704
1705 mvneta_tso_put_hdr(skb, pp, txq);
1706
1707 while (data_left > 0) {
1708 int size;
1709 desc_count++;
1710
1711 size = min_t(int, tso.size, data_left);
1712
1713 if (mvneta_tso_put_data(dev, txq, skb,
1714 tso.data, size,
1715 size == data_left,
1716 total_len == 0))
1717 goto err_release;
1718 data_left -= size;
1719
1720 tso_build_data(skb, &tso, size);
1721 }
1722 }
1723
1724 return desc_count;
1725
1726err_release:
1727 /* Release all used data descriptors; header descriptors must not
1728 * be DMA-unmapped.
1729 */
1730 for (i = desc_count - 1; i >= 0; i--) {
1731 struct mvneta_tx_desc *tx_desc = txq->descs + i;
Ezequiel Garcia2e3173a2014-05-30 13:40:07 -03001732 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
Ezequiel Garcia2adb7192014-05-19 13:59:55 -03001733 dma_unmap_single(pp->dev->dev.parent,
1734 tx_desc->buf_phys_addr,
1735 tx_desc->data_size,
1736 DMA_TO_DEVICE);
1737 mvneta_txq_desc_put(txq);
1738 }
1739 return 0;
1740}
1741
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001742/* Handle tx fragmentation processing */
1743static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
1744 struct mvneta_tx_queue *txq)
1745{
1746 struct mvneta_tx_desc *tx_desc;
Ezequiel Garcia3d4ea022014-05-22 20:06:57 -03001747 int i, nr_frags = skb_shinfo(skb)->nr_frags;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001748
Ezequiel Garcia3d4ea022014-05-22 20:06:57 -03001749 for (i = 0; i < nr_frags; i++) {
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001750 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1751 void *addr = page_address(frag->page.p) + frag->page_offset;
1752
1753 tx_desc = mvneta_txq_next_desc_get(txq);
1754 tx_desc->data_size = frag->size;
1755
1756 tx_desc->buf_phys_addr =
1757 dma_map_single(pp->dev->dev.parent, addr,
1758 tx_desc->data_size, DMA_TO_DEVICE);
1759
1760 if (dma_mapping_error(pp->dev->dev.parent,
1761 tx_desc->buf_phys_addr)) {
1762 mvneta_txq_desc_put(txq);
1763 goto error;
1764 }
1765
Ezequiel Garcia3d4ea022014-05-22 20:06:57 -03001766 if (i == nr_frags - 1) {
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001767 /* Last descriptor */
1768 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001769 txq->tx_skb[txq->txq_put_index] = skb;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001770 } else {
1771 /* Descriptor in the middle: Not First, Not Last */
1772 tx_desc->command = 0;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001773 txq->tx_skb[txq->txq_put_index] = NULL;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001774 }
Ezequiel Garcia3d4ea022014-05-22 20:06:57 -03001775 mvneta_txq_inc_put(txq);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001776 }
1777
1778 return 0;
1779
1780error:
1781 /* Release all descriptors that were used to map fragments of
Thomas Petazzoni6a20c172012-11-19 11:41:25 +01001782 * this packet, as well as the corresponding DMA mappings
1783 */
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001784 for (i = i - 1; i >= 0; i--) {
1785 tx_desc = txq->descs + i;
1786 dma_unmap_single(pp->dev->dev.parent,
1787 tx_desc->buf_phys_addr,
1788 tx_desc->data_size,
1789 DMA_TO_DEVICE);
1790 mvneta_txq_desc_put(txq);
1791 }
1792
1793 return -ENOMEM;
1794}
1795
1796/* Main tx processing */
1797static int mvneta_tx(struct sk_buff *skb, struct net_device *dev)
1798{
1799 struct mvneta_port *pp = netdev_priv(dev);
Willy Tarreauee40a112013-04-11 23:00:37 +02001800 u16 txq_id = skb_get_queue_mapping(skb);
1801 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001802 struct mvneta_tx_desc *tx_desc;
Eric Dumazet5f478b42014-12-02 04:30:59 -08001803 int len = skb->len;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001804 int frags = 0;
1805 u32 tx_cmd;
1806
1807 if (!netif_running(dev))
1808 goto out;
1809
Ezequiel Garcia2adb7192014-05-19 13:59:55 -03001810 if (skb_is_gso(skb)) {
1811 frags = mvneta_tx_tso(skb, dev, txq);
1812 goto out;
1813 }
1814
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001815 frags = skb_shinfo(skb)->nr_frags + 1;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001816
1817 /* Get a descriptor for the first part of the packet */
1818 tx_desc = mvneta_txq_next_desc_get(txq);
1819
1820 tx_cmd = mvneta_skb_tx_csum(pp, skb);
1821
1822 tx_desc->data_size = skb_headlen(skb);
1823
1824 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
1825 tx_desc->data_size,
1826 DMA_TO_DEVICE);
1827 if (unlikely(dma_mapping_error(dev->dev.parent,
1828 tx_desc->buf_phys_addr))) {
1829 mvneta_txq_desc_put(txq);
1830 frags = 0;
1831 goto out;
1832 }
1833
1834 if (frags == 1) {
1835 /* First and Last descriptor */
1836 tx_cmd |= MVNETA_TXD_FLZ_DESC;
1837 tx_desc->command = tx_cmd;
1838 txq->tx_skb[txq->txq_put_index] = skb;
1839 mvneta_txq_inc_put(txq);
1840 } else {
1841 /* First but not Last */
1842 tx_cmd |= MVNETA_TXD_F_DESC;
1843 txq->tx_skb[txq->txq_put_index] = NULL;
1844 mvneta_txq_inc_put(txq);
1845 tx_desc->command = tx_cmd;
1846 /* Continue with other skb fragments */
1847 if (mvneta_tx_frag_process(pp, skb, txq)) {
1848 dma_unmap_single(dev->dev.parent,
1849 tx_desc->buf_phys_addr,
1850 tx_desc->data_size,
1851 DMA_TO_DEVICE);
1852 mvneta_txq_desc_put(txq);
1853 frags = 0;
1854 goto out;
1855 }
1856 }
1857
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001858out:
1859 if (frags > 0) {
willy tarreau74c41b02014-01-16 08:20:08 +01001860 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
Ezequiel Garciae19d2dd2014-05-19 13:59:54 -03001861 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
1862
1863 txq->count += frags;
1864 mvneta_txq_pend_desc_add(pp, txq, frags);
1865
Ezequiel Garcia8eef5f92014-05-30 13:40:05 -03001866 if (txq->count >= txq->tx_stop_threshold)
Ezequiel Garciae19d2dd2014-05-19 13:59:54 -03001867 netif_tx_stop_queue(nq);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001868
willy tarreau74c41b02014-01-16 08:20:08 +01001869 u64_stats_update_begin(&stats->syncp);
1870 stats->tx_packets++;
Eric Dumazet5f478b42014-12-02 04:30:59 -08001871 stats->tx_bytes += len;
willy tarreau74c41b02014-01-16 08:20:08 +01001872 u64_stats_update_end(&stats->syncp);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001873 } else {
1874 dev->stats.tx_dropped++;
1875 dev_kfree_skb_any(skb);
1876 }
1877
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001878 return NETDEV_TX_OK;
1879}
1880
1881
1882/* Free tx resources, when resetting a port */
1883static void mvneta_txq_done_force(struct mvneta_port *pp,
1884 struct mvneta_tx_queue *txq)
1885
1886{
1887 int tx_done = txq->count;
1888
1889 mvneta_txq_bufs_free(pp, txq, tx_done);
1890
1891 /* reset txq */
1892 txq->count = 0;
1893 txq->txq_put_index = 0;
1894 txq->txq_get_index = 0;
1895}
1896
willy tarreau6c498972014-01-16 08:20:12 +01001897/* Handle tx done - called in softirq context. The <cause_tx_done> argument
1898 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
1899 */
Arnaud Ebalard0713a862014-01-16 08:20:18 +01001900static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001901{
1902 struct mvneta_tx_queue *txq;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001903 struct netdev_queue *nq;
1904
willy tarreau6c498972014-01-16 08:20:12 +01001905 while (cause_tx_done) {
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001906 txq = mvneta_tx_done_policy(pp, cause_tx_done);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001907
1908 nq = netdev_get_tx_queue(pp->dev, txq->id);
1909 __netif_tx_lock(nq, smp_processor_id());
1910
Arnaud Ebalard0713a862014-01-16 08:20:18 +01001911 if (txq->count)
1912 mvneta_txq_done(pp, txq);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001913
1914 __netif_tx_unlock(nq);
1915 cause_tx_done &= ~((1 << txq->id));
1916 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001917}
1918
Thomas Petazzoni6a20c172012-11-19 11:41:25 +01001919/* Compute crc8 of the specified address, using a unique algorithm ,
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001920 * according to hw spec, different than generic crc8 algorithm
1921 */
1922static int mvneta_addr_crc(unsigned char *addr)
1923{
1924 int crc = 0;
1925 int i;
1926
1927 for (i = 0; i < ETH_ALEN; i++) {
1928 int j;
1929
1930 crc = (crc ^ addr[i]) << 8;
1931 for (j = 7; j >= 0; j--) {
1932 if (crc & (0x100 << j))
1933 crc ^= 0x107 << j;
1934 }
1935 }
1936
1937 return crc;
1938}
1939
1940/* This method controls the net device special MAC multicast support.
1941 * The Special Multicast Table for MAC addresses supports MAC of the form
1942 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1943 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1944 * Table entries in the DA-Filter table. This method set the Special
1945 * Multicast Table appropriate entry.
1946 */
1947static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
1948 unsigned char last_byte,
1949 int queue)
1950{
1951 unsigned int smc_table_reg;
1952 unsigned int tbl_offset;
1953 unsigned int reg_offset;
1954
1955 /* Register offset from SMC table base */
1956 tbl_offset = (last_byte / 4);
1957 /* Entry offset within the above reg */
1958 reg_offset = last_byte % 4;
1959
1960 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
1961 + tbl_offset * 4));
1962
1963 if (queue == -1)
1964 smc_table_reg &= ~(0xff << (8 * reg_offset));
1965 else {
1966 smc_table_reg &= ~(0xff << (8 * reg_offset));
1967 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1968 }
1969
1970 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
1971 smc_table_reg);
1972}
1973
1974/* This method controls the network device Other MAC multicast support.
1975 * The Other Multicast Table is used for multicast of another type.
1976 * A CRC-8 is used as an index to the Other Multicast Table entries
1977 * in the DA-Filter table.
1978 * The method gets the CRC-8 value from the calling routine and
1979 * sets the Other Multicast Table appropriate entry according to the
1980 * specified CRC-8 .
1981 */
1982static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
1983 unsigned char crc8,
1984 int queue)
1985{
1986 unsigned int omc_table_reg;
1987 unsigned int tbl_offset;
1988 unsigned int reg_offset;
1989
1990 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
1991 reg_offset = crc8 % 4; /* Entry offset within the above reg */
1992
1993 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
1994
1995 if (queue == -1) {
1996 /* Clear accepts frame bit at specified Other DA table entry */
1997 omc_table_reg &= ~(0xff << (8 * reg_offset));
1998 } else {
1999 omc_table_reg &= ~(0xff << (8 * reg_offset));
2000 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2001 }
2002
2003 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
2004}
2005
2006/* The network device supports multicast using two tables:
2007 * 1) Special Multicast Table for MAC addresses of the form
2008 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2009 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2010 * Table entries in the DA-Filter table.
2011 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
2012 * is used as an index to the Other Multicast Table entries in the
2013 * DA-Filter table.
2014 */
2015static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
2016 int queue)
2017{
2018 unsigned char crc_result = 0;
2019
2020 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
2021 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
2022 return 0;
2023 }
2024
2025 crc_result = mvneta_addr_crc(p_addr);
2026 if (queue == -1) {
2027 if (pp->mcast_count[crc_result] == 0) {
2028 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
2029 crc_result);
2030 return -EINVAL;
2031 }
2032
2033 pp->mcast_count[crc_result]--;
2034 if (pp->mcast_count[crc_result] != 0) {
2035 netdev_info(pp->dev,
2036 "After delete there are %d valid Mcast for crc8=0x%02x\n",
2037 pp->mcast_count[crc_result], crc_result);
2038 return -EINVAL;
2039 }
2040 } else
2041 pp->mcast_count[crc_result]++;
2042
2043 mvneta_set_other_mcast_addr(pp, crc_result, queue);
2044
2045 return 0;
2046}
2047
2048/* Configure Fitering mode of Ethernet port */
2049static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
2050 int is_promisc)
2051{
2052 u32 port_cfg_reg, val;
2053
2054 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
2055
2056 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
2057
2058 /* Set / Clear UPM bit in port configuration register */
2059 if (is_promisc) {
2060 /* Accept all Unicast addresses */
2061 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
2062 val |= MVNETA_FORCE_UNI;
2063 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
2064 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
2065 } else {
2066 /* Reject all Unicast addresses */
2067 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
2068 val &= ~MVNETA_FORCE_UNI;
2069 }
2070
2071 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
2072 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
2073}
2074
2075/* register unicast and multicast addresses */
2076static void mvneta_set_rx_mode(struct net_device *dev)
2077{
2078 struct mvneta_port *pp = netdev_priv(dev);
2079 struct netdev_hw_addr *ha;
2080
2081 if (dev->flags & IFF_PROMISC) {
2082 /* Accept all: Multicast + Unicast */
2083 mvneta_rx_unicast_promisc_set(pp, 1);
2084 mvneta_set_ucast_table(pp, rxq_def);
2085 mvneta_set_special_mcast_table(pp, rxq_def);
2086 mvneta_set_other_mcast_table(pp, rxq_def);
2087 } else {
2088 /* Accept single Unicast */
2089 mvneta_rx_unicast_promisc_set(pp, 0);
2090 mvneta_set_ucast_table(pp, -1);
2091 mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def);
2092
2093 if (dev->flags & IFF_ALLMULTI) {
2094 /* Accept all multicast */
2095 mvneta_set_special_mcast_table(pp, rxq_def);
2096 mvneta_set_other_mcast_table(pp, rxq_def);
2097 } else {
2098 /* Accept only initialized multicast */
2099 mvneta_set_special_mcast_table(pp, -1);
2100 mvneta_set_other_mcast_table(pp, -1);
2101
2102 if (!netdev_mc_empty(dev)) {
2103 netdev_for_each_mc_addr(ha, dev) {
2104 mvneta_mcast_addr_set(pp, ha->addr,
2105 rxq_def);
2106 }
2107 }
2108 }
2109 }
2110}
2111
2112/* Interrupt handling - the callback for request_irq() */
2113static irqreturn_t mvneta_isr(int irq, void *dev_id)
2114{
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002115 struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002116
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002117 disable_percpu_irq(port->pp->dev->irq);
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002118 napi_schedule(&port->napi);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002119
2120 return IRQ_HANDLED;
2121}
2122
Stas Sergeev898b2972015-04-01 20:32:49 +03002123static int mvneta_fixed_link_update(struct mvneta_port *pp,
2124 struct phy_device *phy)
2125{
2126 struct fixed_phy_status status;
2127 struct fixed_phy_status changed = {};
2128 u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
2129
2130 status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
2131 if (gmac_stat & MVNETA_GMAC_SPEED_1000)
2132 status.speed = SPEED_1000;
2133 else if (gmac_stat & MVNETA_GMAC_SPEED_100)
2134 status.speed = SPEED_100;
2135 else
2136 status.speed = SPEED_10;
2137 status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
2138 changed.link = 1;
2139 changed.speed = 1;
2140 changed.duplex = 1;
2141 fixed_phy_update_state(phy, &status, &changed);
2142 return 0;
2143}
2144
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002145/* NAPI handler
2146 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
2147 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
2148 * Bits 8 -15 of the cause Rx Tx register indicate that are received
2149 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
2150 * Each CPU has its own causeRxTx register
2151 */
2152static int mvneta_poll(struct napi_struct *napi, int budget)
2153{
2154 int rx_done = 0;
2155 u32 cause_rx_tx;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002156 struct mvneta_port *pp = netdev_priv(napi->dev);
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002157 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002158
2159 if (!netif_running(pp->dev)) {
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002160 napi_complete(&port->napi);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002161 return rx_done;
2162 }
2163
2164 /* Read cause register */
Stas Sergeev898b2972015-04-01 20:32:49 +03002165 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
2166 if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) {
2167 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
2168
2169 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2170 if (pp->use_inband_status && (cause_misc &
2171 (MVNETA_CAUSE_PHY_STATUS_CHANGE |
2172 MVNETA_CAUSE_LINK_CHANGE |
2173 MVNETA_CAUSE_PSC_SYNC_CHANGE))) {
2174 mvneta_fixed_link_update(pp, pp->phy_dev);
2175 }
2176 }
willy tarreau71f6d1b2014-01-16 08:20:11 +01002177
2178 /* Release Tx descriptors */
2179 if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
Arnaud Ebalard0713a862014-01-16 08:20:18 +01002180 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL));
willy tarreau71f6d1b2014-01-16 08:20:11 +01002181 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL;
2182 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002183
Thomas Petazzoni6a20c172012-11-19 11:41:25 +01002184 /* For the case where the last mvneta_poll did not process all
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002185 * RX packets
2186 */
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002187 cause_rx_tx |= port->cause_rx_tx;
Maxime Ripardd8936652015-09-25 18:09:37 +02002188 rx_done = mvneta_rx(pp, budget, &pp->rxqs[rxq_def]);
2189 budget -= rx_done;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002190
2191 if (budget > 0) {
2192 cause_rx_tx = 0;
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002193 napi_complete(&port->napi);
2194 enable_percpu_irq(pp->dev->irq, 0);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002195 }
2196
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002197 port->cause_rx_tx = cause_rx_tx;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002198 return rx_done;
2199}
2200
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002201/* Handle rxq fill: allocates rxq skbs; called when initializing a port */
2202static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
2203 int num)
2204{
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002205 int i;
2206
2207 for (i = 0; i < num; i++) {
willy tarreaua1a65ab2014-01-16 08:20:13 +01002208 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
2209 if (mvneta_rx_refill(pp, rxq->descs + i) != 0) {
2210 netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n",
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002211 __func__, rxq->id, i, num);
2212 break;
2213 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002214 }
2215
2216 /* Add this number of RX descriptors as non occupied (ready to
Thomas Petazzoni6a20c172012-11-19 11:41:25 +01002217 * get packets)
2218 */
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002219 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
2220
2221 return i;
2222}
2223
2224/* Free all packets pending transmit from all TXQs and reset TX port */
2225static void mvneta_tx_reset(struct mvneta_port *pp)
2226{
2227 int queue;
2228
Ezequiel Garcia96728502014-05-22 20:06:59 -03002229 /* free the skb's in the tx ring */
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002230 for (queue = 0; queue < txq_number; queue++)
2231 mvneta_txq_done_force(pp, &pp->txqs[queue]);
2232
2233 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
2234 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
2235}
2236
2237static void mvneta_rx_reset(struct mvneta_port *pp)
2238{
2239 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
2240 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
2241}
2242
2243/* Rx/Tx queue initialization/cleanup methods */
2244
2245/* Create a specified RX queue */
2246static int mvneta_rxq_init(struct mvneta_port *pp,
2247 struct mvneta_rx_queue *rxq)
2248
2249{
2250 rxq->size = pp->rx_ring_size;
2251
2252 /* Allocate memory for RX descriptors */
2253 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2254 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2255 &rxq->descs_phys, GFP_KERNEL);
Joe Perchesd0320f72013-03-14 13:07:21 +00002256 if (rxq->descs == NULL)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002257 return -ENOMEM;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002258
2259 BUG_ON(rxq->descs !=
2260 PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2261
2262 rxq->last_desc = rxq->size - 1;
2263
2264 /* Set Rx descriptors queue starting address */
2265 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
2266 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
2267
2268 /* Set Offset */
2269 mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
2270
2271 /* Set coalescing pkts and time */
2272 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2273 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2274
2275 /* Fill RXQ with buffers from RX pool */
2276 mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size));
2277 mvneta_rxq_bm_disable(pp, rxq);
2278 mvneta_rxq_fill(pp, rxq, rxq->size);
2279
2280 return 0;
2281}
2282
2283/* Cleanup Rx queue */
2284static void mvneta_rxq_deinit(struct mvneta_port *pp,
2285 struct mvneta_rx_queue *rxq)
2286{
2287 mvneta_rxq_drop_pkts(pp, rxq);
2288
2289 if (rxq->descs)
2290 dma_free_coherent(pp->dev->dev.parent,
2291 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2292 rxq->descs,
2293 rxq->descs_phys);
2294
2295 rxq->descs = NULL;
2296 rxq->last_desc = 0;
2297 rxq->next_desc_to_proc = 0;
2298 rxq->descs_phys = 0;
2299}
2300
2301/* Create and initialize a tx queue */
2302static int mvneta_txq_init(struct mvneta_port *pp,
2303 struct mvneta_tx_queue *txq)
2304{
2305 txq->size = pp->tx_ring_size;
2306
Ezequiel Garcia8eef5f92014-05-30 13:40:05 -03002307 /* A queue must always have room for at least one skb.
2308 * Therefore, stop the queue when the free entries reaches
2309 * the maximum number of descriptors per skb.
2310 */
2311 txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS;
2312 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2313
2314
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002315 /* Allocate memory for TX descriptors */
2316 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2317 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2318 &txq->descs_phys, GFP_KERNEL);
Joe Perchesd0320f72013-03-14 13:07:21 +00002319 if (txq->descs == NULL)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002320 return -ENOMEM;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002321
2322 /* Make sure descriptor address is cache line size aligned */
2323 BUG_ON(txq->descs !=
2324 PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2325
2326 txq->last_desc = txq->size - 1;
2327
2328 /* Set maximum bandwidth for enabled TXQs */
2329 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
2330 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
2331
2332 /* Set Tx descriptors queue starting address */
2333 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
2334 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
2335
2336 txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL);
2337 if (txq->tx_skb == NULL) {
2338 dma_free_coherent(pp->dev->dev.parent,
2339 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2340 txq->descs, txq->descs_phys);
2341 return -ENOMEM;
2342 }
Ezequiel Garcia2adb7192014-05-19 13:59:55 -03002343
2344 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2345 txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent,
2346 txq->size * TSO_HEADER_SIZE,
2347 &txq->tso_hdrs_phys, GFP_KERNEL);
2348 if (txq->tso_hdrs == NULL) {
2349 kfree(txq->tx_skb);
2350 dma_free_coherent(pp->dev->dev.parent,
2351 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2352 txq->descs, txq->descs_phys);
2353 return -ENOMEM;
2354 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002355 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2356
2357 return 0;
2358}
2359
2360/* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2361static void mvneta_txq_deinit(struct mvneta_port *pp,
2362 struct mvneta_tx_queue *txq)
2363{
2364 kfree(txq->tx_skb);
2365
Ezequiel Garcia2adb7192014-05-19 13:59:55 -03002366 if (txq->tso_hdrs)
2367 dma_free_coherent(pp->dev->dev.parent,
2368 txq->size * TSO_HEADER_SIZE,
2369 txq->tso_hdrs, txq->tso_hdrs_phys);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002370 if (txq->descs)
2371 dma_free_coherent(pp->dev->dev.parent,
2372 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2373 txq->descs, txq->descs_phys);
2374
2375 txq->descs = NULL;
2376 txq->last_desc = 0;
2377 txq->next_desc_to_proc = 0;
2378 txq->descs_phys = 0;
2379
2380 /* Set minimum bandwidth for disabled TXQs */
2381 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
2382 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
2383
2384 /* Set Tx descriptors queue starting address and size */
2385 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
2386 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
2387}
2388
2389/* Cleanup all Tx queues */
2390static void mvneta_cleanup_txqs(struct mvneta_port *pp)
2391{
2392 int queue;
2393
2394 for (queue = 0; queue < txq_number; queue++)
2395 mvneta_txq_deinit(pp, &pp->txqs[queue]);
2396}
2397
2398/* Cleanup all Rx queues */
2399static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
2400{
Maxime Ripardd8936652015-09-25 18:09:37 +02002401 mvneta_rxq_deinit(pp, &pp->rxqs[rxq_def]);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002402}
2403
2404
2405/* Init all Rx queues */
2406static int mvneta_setup_rxqs(struct mvneta_port *pp)
2407{
Maxime Ripardd8936652015-09-25 18:09:37 +02002408 int err = mvneta_rxq_init(pp, &pp->rxqs[rxq_def]);
2409 if (err) {
2410 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
2411 __func__, rxq_def);
2412 mvneta_cleanup_rxqs(pp);
2413 return err;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002414 }
2415
2416 return 0;
2417}
2418
2419/* Init all tx queues */
2420static int mvneta_setup_txqs(struct mvneta_port *pp)
2421{
2422 int queue;
2423
2424 for (queue = 0; queue < txq_number; queue++) {
2425 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
2426 if (err) {
2427 netdev_err(pp->dev, "%s: can't create txq=%d\n",
2428 __func__, queue);
2429 mvneta_cleanup_txqs(pp);
2430 return err;
2431 }
2432 }
2433
2434 return 0;
2435}
2436
2437static void mvneta_start_dev(struct mvneta_port *pp)
2438{
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002439 unsigned int cpu;
2440
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002441 mvneta_max_rx_size_set(pp, pp->pkt_size);
2442 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
2443
2444 /* start the Rx/Tx activity */
2445 mvneta_port_enable(pp);
2446
2447 /* Enable polling on the port */
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002448 for_each_present_cpu(cpu) {
2449 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
2450
2451 napi_enable(&port->napi);
2452 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002453
2454 /* Unmask interrupts */
2455 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
Stas Sergeev898b2972015-04-01 20:32:49 +03002456 MVNETA_RX_INTR_MASK(rxq_number) |
2457 MVNETA_TX_INTR_MASK(txq_number) |
2458 MVNETA_MISCINTR_INTR_MASK);
2459 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
2460 MVNETA_CAUSE_PHY_STATUS_CHANGE |
2461 MVNETA_CAUSE_LINK_CHANGE |
2462 MVNETA_CAUSE_PSC_SYNC_CHANGE);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002463
2464 phy_start(pp->phy_dev);
2465 netif_tx_start_all_queues(pp->dev);
2466}
2467
2468static void mvneta_stop_dev(struct mvneta_port *pp)
2469{
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002470 unsigned int cpu;
2471
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002472 phy_stop(pp->phy_dev);
2473
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002474 for_each_present_cpu(cpu) {
2475 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
2476
2477 napi_disable(&port->napi);
2478 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002479
2480 netif_carrier_off(pp->dev);
2481
2482 mvneta_port_down(pp);
2483 netif_tx_stop_all_queues(pp->dev);
2484
2485 /* Stop the port activity */
2486 mvneta_port_disable(pp);
2487
2488 /* Clear all ethernet port interrupts */
2489 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2490 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
2491
2492 /* Mask all ethernet port interrupts */
2493 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2494 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2495 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2496
2497 mvneta_tx_reset(pp);
2498 mvneta_rx_reset(pp);
2499}
2500
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002501/* Return positive if MTU is valid */
2502static int mvneta_check_mtu_valid(struct net_device *dev, int mtu)
2503{
2504 if (mtu < 68) {
2505 netdev_err(dev, "cannot change mtu to less than 68\n");
2506 return -EINVAL;
2507 }
2508
Thomas Petazzoni6a20c172012-11-19 11:41:25 +01002509 /* 9676 == 9700 - 20 and rounding to 8 */
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002510 if (mtu > 9676) {
2511 netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu);
2512 mtu = 9676;
2513 }
2514
2515 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
2516 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
2517 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
2518 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
2519 }
2520
2521 return mtu;
2522}
2523
2524/* Change the device mtu */
2525static int mvneta_change_mtu(struct net_device *dev, int mtu)
2526{
2527 struct mvneta_port *pp = netdev_priv(dev);
2528 int ret;
2529
2530 mtu = mvneta_check_mtu_valid(dev, mtu);
2531 if (mtu < 0)
2532 return -EINVAL;
2533
2534 dev->mtu = mtu;
2535
Simon Guinotb65657f2015-06-30 16:20:22 +02002536 if (!netif_running(dev)) {
2537 netdev_update_features(dev);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002538 return 0;
Simon Guinotb65657f2015-06-30 16:20:22 +02002539 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002540
Thomas Petazzoni6a20c172012-11-19 11:41:25 +01002541 /* The interface is running, so we have to force a
Ezequiel Garciaa92dbd92014-05-22 20:06:58 -03002542 * reallocation of the queues
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002543 */
2544 mvneta_stop_dev(pp);
2545
2546 mvneta_cleanup_txqs(pp);
2547 mvneta_cleanup_rxqs(pp);
2548
Ezequiel Garciaa92dbd92014-05-22 20:06:58 -03002549 pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu);
willy tarreau8ec2cd42014-01-16 08:20:16 +01002550 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
2551 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002552
2553 ret = mvneta_setup_rxqs(pp);
2554 if (ret) {
Ezequiel Garciaa92dbd92014-05-22 20:06:58 -03002555 netdev_err(dev, "unable to setup rxqs after MTU change\n");
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002556 return ret;
2557 }
2558
Ezequiel Garciaa92dbd92014-05-22 20:06:58 -03002559 ret = mvneta_setup_txqs(pp);
2560 if (ret) {
2561 netdev_err(dev, "unable to setup txqs after MTU change\n");
2562 return ret;
2563 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002564
2565 mvneta_start_dev(pp);
2566 mvneta_port_up(pp);
2567
Simon Guinotb65657f2015-06-30 16:20:22 +02002568 netdev_update_features(dev);
2569
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002570 return 0;
2571}
2572
Simon Guinotb65657f2015-06-30 16:20:22 +02002573static netdev_features_t mvneta_fix_features(struct net_device *dev,
2574 netdev_features_t features)
2575{
2576 struct mvneta_port *pp = netdev_priv(dev);
2577
2578 if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) {
2579 features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO);
2580 netdev_info(dev,
2581 "Disable IP checksum for MTU greater than %dB\n",
2582 pp->tx_csum_limit);
2583 }
2584
2585 return features;
2586}
2587
Thomas Petazzoni8cc3e432013-06-04 04:52:23 +00002588/* Get mac address */
2589static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
2590{
2591 u32 mac_addr_l, mac_addr_h;
2592
2593 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
2594 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
2595 addr[0] = (mac_addr_h >> 24) & 0xFF;
2596 addr[1] = (mac_addr_h >> 16) & 0xFF;
2597 addr[2] = (mac_addr_h >> 8) & 0xFF;
2598 addr[3] = mac_addr_h & 0xFF;
2599 addr[4] = (mac_addr_l >> 8) & 0xFF;
2600 addr[5] = mac_addr_l & 0xFF;
2601}
2602
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002603/* Handle setting mac address */
2604static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
2605{
2606 struct mvneta_port *pp = netdev_priv(dev);
Ezequiel Garciae68de362014-05-22 20:07:00 -03002607 struct sockaddr *sockaddr = addr;
2608 int ret;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002609
Ezequiel Garciae68de362014-05-22 20:07:00 -03002610 ret = eth_prepare_mac_addr_change(dev, addr);
2611 if (ret < 0)
2612 return ret;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002613 /* Remove previous address table entry */
2614 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
2615
2616 /* Set new addr in hw */
Ezequiel Garciae68de362014-05-22 20:07:00 -03002617 mvneta_mac_addr_set(pp, sockaddr->sa_data, rxq_def);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002618
Ezequiel Garciae68de362014-05-22 20:07:00 -03002619 eth_commit_mac_addr_change(dev, addr);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002620 return 0;
2621}
2622
2623static void mvneta_adjust_link(struct net_device *ndev)
2624{
2625 struct mvneta_port *pp = netdev_priv(ndev);
2626 struct phy_device *phydev = pp->phy_dev;
2627 int status_change = 0;
2628
2629 if (phydev->link) {
2630 if ((pp->speed != phydev->speed) ||
2631 (pp->duplex != phydev->duplex)) {
2632 u32 val;
2633
2634 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2635 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
2636 MVNETA_GMAC_CONFIG_GMII_SPEED |
Stas Sergeev898b2972015-04-01 20:32:49 +03002637 MVNETA_GMAC_CONFIG_FULL_DUPLEX);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002638
2639 if (phydev->duplex)
2640 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
2641
2642 if (phydev->speed == SPEED_1000)
2643 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
Thomas Petazzoni4d12bc62014-07-08 10:49:43 +02002644 else if (phydev->speed == SPEED_100)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002645 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
2646
2647 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2648
2649 pp->duplex = phydev->duplex;
2650 pp->speed = phydev->speed;
2651 }
2652 }
2653
2654 if (phydev->link != pp->link) {
2655 if (!phydev->link) {
2656 pp->duplex = -1;
2657 pp->speed = 0;
2658 }
2659
2660 pp->link = phydev->link;
2661 status_change = 1;
2662 }
2663
2664 if (status_change) {
2665 if (phydev->link) {
Stas Sergeev898b2972015-04-01 20:32:49 +03002666 if (!pp->use_inband_status) {
2667 u32 val = mvreg_read(pp,
2668 MVNETA_GMAC_AUTONEG_CONFIG);
2669 val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
2670 val |= MVNETA_GMAC_FORCE_LINK_PASS;
2671 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
2672 val);
2673 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002674 mvneta_port_up(pp);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002675 } else {
Stas Sergeev898b2972015-04-01 20:32:49 +03002676 if (!pp->use_inband_status) {
2677 u32 val = mvreg_read(pp,
2678 MVNETA_GMAC_AUTONEG_CONFIG);
2679 val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
2680 val |= MVNETA_GMAC_FORCE_LINK_DOWN;
2681 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
2682 val);
2683 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002684 mvneta_port_down(pp);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002685 }
Ezequiel Garcia0089b742014-10-31 12:57:20 -03002686 phy_print_status(phydev);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002687 }
2688}
2689
2690static int mvneta_mdio_probe(struct mvneta_port *pp)
2691{
2692 struct phy_device *phy_dev;
2693
2694 phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
2695 pp->phy_interface);
2696 if (!phy_dev) {
2697 netdev_err(pp->dev, "could not find the PHY\n");
2698 return -ENODEV;
2699 }
2700
2701 phy_dev->supported &= PHY_GBIT_FEATURES;
2702 phy_dev->advertising = phy_dev->supported;
2703
2704 pp->phy_dev = phy_dev;
2705 pp->link = 0;
2706 pp->duplex = 0;
2707 pp->speed = 0;
2708
2709 return 0;
2710}
2711
2712static void mvneta_mdio_remove(struct mvneta_port *pp)
2713{
2714 phy_disconnect(pp->phy_dev);
2715 pp->phy_dev = NULL;
2716}
2717
Maxime Ripardf8642882015-09-25 18:09:38 +02002718static void mvneta_percpu_enable(void *arg)
2719{
2720 struct mvneta_port *pp = arg;
2721
2722 enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE);
2723}
2724
2725static void mvneta_percpu_disable(void *arg)
2726{
2727 struct mvneta_port *pp = arg;
2728
2729 disable_percpu_irq(pp->dev->irq);
2730}
2731
2732static void mvneta_percpu_elect(struct mvneta_port *pp)
2733{
2734 int online_cpu_idx, cpu, i = 0;
2735
2736 online_cpu_idx = rxq_def % num_online_cpus();
2737
2738 for_each_online_cpu(cpu) {
2739 if (i == online_cpu_idx)
2740 /* Enable per-CPU interrupt on the one CPU we
2741 * just elected
2742 */
2743 smp_call_function_single(cpu, mvneta_percpu_enable,
2744 pp, true);
2745 else
2746 /* Disable per-CPU interrupt on all the other CPU */
2747 smp_call_function_single(cpu, mvneta_percpu_disable,
2748 pp, true);
2749 i++;
2750 }
2751};
2752
2753static int mvneta_percpu_notifier(struct notifier_block *nfb,
2754 unsigned long action, void *hcpu)
2755{
2756 struct mvneta_port *pp = container_of(nfb, struct mvneta_port,
2757 cpu_notifier);
2758 int cpu = (unsigned long)hcpu, other_cpu;
2759 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
2760
2761 switch (action) {
2762 case CPU_ONLINE:
2763 case CPU_ONLINE_FROZEN:
2764 netif_tx_stop_all_queues(pp->dev);
2765
2766 /* We have to synchronise on tha napi of each CPU
2767 * except the one just being waked up
2768 */
2769 for_each_online_cpu(other_cpu) {
2770 if (other_cpu != cpu) {
2771 struct mvneta_pcpu_port *other_port =
2772 per_cpu_ptr(pp->ports, other_cpu);
2773
2774 napi_synchronize(&other_port->napi);
2775 }
2776 }
2777
2778 /* Mask all ethernet port interrupts */
2779 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2780 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2781 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2782 napi_enable(&port->napi);
2783
2784 /* Enable per-CPU interrupt on the one CPU we care
2785 * about.
2786 */
2787 mvneta_percpu_elect(pp);
2788
2789 /* Unmask all ethernet port interrupts */
2790 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2791 MVNETA_RX_INTR_MASK(rxq_number) |
2792 MVNETA_TX_INTR_MASK(txq_number) |
2793 MVNETA_MISCINTR_INTR_MASK);
2794 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
2795 MVNETA_CAUSE_PHY_STATUS_CHANGE |
2796 MVNETA_CAUSE_LINK_CHANGE |
2797 MVNETA_CAUSE_PSC_SYNC_CHANGE);
2798 netif_tx_start_all_queues(pp->dev);
2799 break;
2800 case CPU_DOWN_PREPARE:
2801 case CPU_DOWN_PREPARE_FROZEN:
2802 netif_tx_stop_all_queues(pp->dev);
2803 /* Mask all ethernet port interrupts */
2804 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2805 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2806 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2807
2808 napi_synchronize(&port->napi);
2809 napi_disable(&port->napi);
2810 /* Disable per-CPU interrupts on the CPU that is
2811 * brought down.
2812 */
2813 smp_call_function_single(cpu, mvneta_percpu_disable,
2814 pp, true);
2815
2816 break;
2817 case CPU_DEAD:
2818 case CPU_DEAD_FROZEN:
2819 /* Check if a new CPU must be elected now this on is down */
2820 mvneta_percpu_elect(pp);
2821 /* Unmask all ethernet port interrupts */
2822 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2823 MVNETA_RX_INTR_MASK(rxq_number) |
2824 MVNETA_TX_INTR_MASK(txq_number) |
2825 MVNETA_MISCINTR_INTR_MASK);
2826 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
2827 MVNETA_CAUSE_PHY_STATUS_CHANGE |
2828 MVNETA_CAUSE_LINK_CHANGE |
2829 MVNETA_CAUSE_PSC_SYNC_CHANGE);
2830 netif_tx_start_all_queues(pp->dev);
2831 break;
2832 }
2833
2834 return NOTIFY_OK;
2835}
2836
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002837static int mvneta_open(struct net_device *dev)
2838{
2839 struct mvneta_port *pp = netdev_priv(dev);
2840 int ret;
2841
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002842 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
willy tarreau8ec2cd42014-01-16 08:20:16 +01002843 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
2844 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002845
2846 ret = mvneta_setup_rxqs(pp);
2847 if (ret)
2848 return ret;
2849
2850 ret = mvneta_setup_txqs(pp);
2851 if (ret)
2852 goto err_cleanup_rxqs;
2853
2854 /* Connect to port interrupt line */
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002855 ret = request_percpu_irq(pp->dev->irq, mvneta_isr,
2856 MVNETA_DRIVER_NAME, pp->ports);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002857 if (ret) {
2858 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
2859 goto err_cleanup_txqs;
2860 }
2861
Maxime Ripardf8642882015-09-25 18:09:38 +02002862 /* Even though the documentation says that request_percpu_irq
2863 * doesn't enable the interrupts automatically, it actually
2864 * does so on the local CPU.
2865 *
2866 * Make sure it's disabled.
2867 */
2868 mvneta_percpu_disable(pp);
2869
2870 /* Elect a CPU to handle our RX queue interrupt */
2871 mvneta_percpu_elect(pp);
2872
2873 /* Register a CPU notifier to handle the case where our CPU
2874 * might be taken offline.
2875 */
2876 register_cpu_notifier(&pp->cpu_notifier);
2877
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002878 /* In default link is down */
2879 netif_carrier_off(pp->dev);
2880
2881 ret = mvneta_mdio_probe(pp);
2882 if (ret < 0) {
2883 netdev_err(dev, "cannot probe MDIO bus\n");
2884 goto err_free_irq;
2885 }
2886
2887 mvneta_start_dev(pp);
2888
2889 return 0;
2890
2891err_free_irq:
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002892 free_percpu_irq(pp->dev->irq, pp->ports);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002893err_cleanup_txqs:
2894 mvneta_cleanup_txqs(pp);
2895err_cleanup_rxqs:
2896 mvneta_cleanup_rxqs(pp);
2897 return ret;
2898}
2899
2900/* Stop the port, free port interrupt line */
2901static int mvneta_stop(struct net_device *dev)
2902{
2903 struct mvneta_port *pp = netdev_priv(dev);
Maxime Ripardf8642882015-09-25 18:09:38 +02002904 int cpu;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002905
2906 mvneta_stop_dev(pp);
2907 mvneta_mdio_remove(pp);
Maxime Ripardf8642882015-09-25 18:09:38 +02002908 unregister_cpu_notifier(&pp->cpu_notifier);
2909 for_each_present_cpu(cpu)
2910 smp_call_function_single(cpu, mvneta_percpu_disable, pp, true);
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002911 free_percpu_irq(dev->irq, pp->ports);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002912 mvneta_cleanup_rxqs(pp);
2913 mvneta_cleanup_txqs(pp);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002914
2915 return 0;
2916}
2917
Thomas Petazzoni15f59452013-09-04 16:26:52 +02002918static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2919{
2920 struct mvneta_port *pp = netdev_priv(dev);
Thomas Petazzoni15f59452013-09-04 16:26:52 +02002921
2922 if (!pp->phy_dev)
2923 return -ENOTSUPP;
2924
Stas Sergeevecf7b362015-04-01 19:23:29 +03002925 return phy_mii_ioctl(pp->phy_dev, ifr, cmd);
Thomas Petazzoni15f59452013-09-04 16:26:52 +02002926}
2927
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002928/* Ethtool methods */
2929
2930/* Get settings (phy address, speed) for ethtools */
2931int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2932{
2933 struct mvneta_port *pp = netdev_priv(dev);
2934
2935 if (!pp->phy_dev)
2936 return -ENODEV;
2937
2938 return phy_ethtool_gset(pp->phy_dev, cmd);
2939}
2940
2941/* Set settings (phy address, speed) for ethtools */
2942int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2943{
2944 struct mvneta_port *pp = netdev_priv(dev);
2945
2946 if (!pp->phy_dev)
2947 return -ENODEV;
2948
2949 return phy_ethtool_sset(pp->phy_dev, cmd);
2950}
2951
2952/* Set interrupt coalescing for ethtools */
2953static int mvneta_ethtool_set_coalesce(struct net_device *dev,
2954 struct ethtool_coalesce *c)
2955{
2956 struct mvneta_port *pp = netdev_priv(dev);
2957 int queue;
2958
2959 for (queue = 0; queue < rxq_number; queue++) {
2960 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
2961 rxq->time_coal = c->rx_coalesce_usecs;
2962 rxq->pkts_coal = c->rx_max_coalesced_frames;
2963 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2964 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2965 }
2966
2967 for (queue = 0; queue < txq_number; queue++) {
2968 struct mvneta_tx_queue *txq = &pp->txqs[queue];
2969 txq->done_pkts_coal = c->tx_max_coalesced_frames;
2970 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2971 }
2972
2973 return 0;
2974}
2975
2976/* get coalescing for ethtools */
2977static int mvneta_ethtool_get_coalesce(struct net_device *dev,
2978 struct ethtool_coalesce *c)
2979{
2980 struct mvneta_port *pp = netdev_priv(dev);
2981
2982 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
2983 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
2984
2985 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
2986 return 0;
2987}
2988
2989
2990static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
2991 struct ethtool_drvinfo *drvinfo)
2992{
2993 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
2994 sizeof(drvinfo->driver));
2995 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
2996 sizeof(drvinfo->version));
2997 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
2998 sizeof(drvinfo->bus_info));
2999}
3000
3001
3002static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
3003 struct ethtool_ringparam *ring)
3004{
3005 struct mvneta_port *pp = netdev_priv(netdev);
3006
3007 ring->rx_max_pending = MVNETA_MAX_RXD;
3008 ring->tx_max_pending = MVNETA_MAX_TXD;
3009 ring->rx_pending = pp->rx_ring_size;
3010 ring->tx_pending = pp->tx_ring_size;
3011}
3012
3013static int mvneta_ethtool_set_ringparam(struct net_device *dev,
3014 struct ethtool_ringparam *ring)
3015{
3016 struct mvneta_port *pp = netdev_priv(dev);
3017
3018 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
3019 return -EINVAL;
3020 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
3021 ring->rx_pending : MVNETA_MAX_RXD;
Ezequiel Garcia8eef5f92014-05-30 13:40:05 -03003022
3023 pp->tx_ring_size = clamp_t(u16, ring->tx_pending,
3024 MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD);
3025 if (pp->tx_ring_size != ring->tx_pending)
3026 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
3027 pp->tx_ring_size, ring->tx_pending);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003028
3029 if (netif_running(dev)) {
3030 mvneta_stop(dev);
3031 if (mvneta_open(dev)) {
3032 netdev_err(dev,
3033 "error on opening device after ring param change\n");
3034 return -ENOMEM;
3035 }
3036 }
3037
3038 return 0;
3039}
3040
Russell King9b0cdef2015-10-22 18:37:30 +01003041static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset,
3042 u8 *data)
3043{
3044 if (sset == ETH_SS_STATS) {
3045 int i;
3046
3047 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
3048 memcpy(data + i * ETH_GSTRING_LEN,
3049 mvneta_statistics[i].name, ETH_GSTRING_LEN);
3050 }
3051}
3052
3053static void mvneta_ethtool_update_stats(struct mvneta_port *pp)
3054{
3055 const struct mvneta_statistic *s;
3056 void __iomem *base = pp->base;
3057 u32 high, low, val;
3058 int i;
3059
3060 for (i = 0, s = mvneta_statistics;
3061 s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics);
3062 s++, i++) {
3063 val = 0;
3064
3065 switch (s->type) {
3066 case T_REG_32:
3067 val = readl_relaxed(base + s->offset);
3068 break;
3069 case T_REG_64:
3070 /* Docs say to read low 32-bit then high */
3071 low = readl_relaxed(base + s->offset);
3072 high = readl_relaxed(base + s->offset + 4);
3073 val = (u64)high << 32 | low;
3074 break;
3075 }
3076
3077 pp->ethtool_stats[i] += val;
3078 }
3079}
3080
3081static void mvneta_ethtool_get_stats(struct net_device *dev,
3082 struct ethtool_stats *stats, u64 *data)
3083{
3084 struct mvneta_port *pp = netdev_priv(dev);
3085 int i;
3086
3087 mvneta_ethtool_update_stats(pp);
3088
3089 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
3090 *data++ = pp->ethtool_stats[i];
3091}
3092
3093static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset)
3094{
3095 if (sset == ETH_SS_STATS)
3096 return ARRAY_SIZE(mvneta_statistics);
3097 return -EOPNOTSUPP;
3098}
3099
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003100static const struct net_device_ops mvneta_netdev_ops = {
3101 .ndo_open = mvneta_open,
3102 .ndo_stop = mvneta_stop,
3103 .ndo_start_xmit = mvneta_tx,
3104 .ndo_set_rx_mode = mvneta_set_rx_mode,
3105 .ndo_set_mac_address = mvneta_set_mac_addr,
3106 .ndo_change_mtu = mvneta_change_mtu,
Simon Guinotb65657f2015-06-30 16:20:22 +02003107 .ndo_fix_features = mvneta_fix_features,
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003108 .ndo_get_stats64 = mvneta_get_stats64,
Thomas Petazzoni15f59452013-09-04 16:26:52 +02003109 .ndo_do_ioctl = mvneta_ioctl,
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003110};
3111
3112const struct ethtool_ops mvneta_eth_tool_ops = {
3113 .get_link = ethtool_op_get_link,
3114 .get_settings = mvneta_ethtool_get_settings,
3115 .set_settings = mvneta_ethtool_set_settings,
3116 .set_coalesce = mvneta_ethtool_set_coalesce,
3117 .get_coalesce = mvneta_ethtool_get_coalesce,
3118 .get_drvinfo = mvneta_ethtool_get_drvinfo,
3119 .get_ringparam = mvneta_ethtool_get_ringparam,
3120 .set_ringparam = mvneta_ethtool_set_ringparam,
Russell King9b0cdef2015-10-22 18:37:30 +01003121 .get_strings = mvneta_ethtool_get_strings,
3122 .get_ethtool_stats = mvneta_ethtool_get_stats,
3123 .get_sset_count = mvneta_ethtool_get_sset_count,
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003124};
3125
3126/* Initialize hw */
Ezequiel Garcia96728502014-05-22 20:06:59 -03003127static int mvneta_init(struct device *dev, struct mvneta_port *pp)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003128{
3129 int queue;
3130
3131 /* Disable port */
3132 mvneta_port_disable(pp);
3133
3134 /* Set port default values */
3135 mvneta_defaults_set(pp);
3136
Ezequiel Garcia96728502014-05-22 20:06:59 -03003137 pp->txqs = devm_kcalloc(dev, txq_number, sizeof(struct mvneta_tx_queue),
3138 GFP_KERNEL);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003139 if (!pp->txqs)
3140 return -ENOMEM;
3141
3142 /* Initialize TX descriptor rings */
3143 for (queue = 0; queue < txq_number; queue++) {
3144 struct mvneta_tx_queue *txq = &pp->txqs[queue];
3145 txq->id = queue;
3146 txq->size = pp->tx_ring_size;
3147 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
3148 }
3149
Ezequiel Garcia96728502014-05-22 20:06:59 -03003150 pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(struct mvneta_rx_queue),
3151 GFP_KERNEL);
3152 if (!pp->rxqs)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003153 return -ENOMEM;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003154
3155 /* Create Rx descriptor rings */
3156 for (queue = 0; queue < rxq_number; queue++) {
3157 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
3158 rxq->id = queue;
3159 rxq->size = pp->rx_ring_size;
3160 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
3161 rxq->time_coal = MVNETA_RX_COAL_USEC;
3162 }
3163
3164 return 0;
3165}
3166
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003167/* platform glue : initialize decoding windows */
Greg KH03ce7582012-12-21 13:42:15 +00003168static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
3169 const struct mbus_dram_target_info *dram)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003170{
3171 u32 win_enable;
3172 u32 win_protect;
3173 int i;
3174
3175 for (i = 0; i < 6; i++) {
3176 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
3177 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
3178
3179 if (i < 4)
3180 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
3181 }
3182
3183 win_enable = 0x3f;
3184 win_protect = 0;
3185
3186 for (i = 0; i < dram->num_cs; i++) {
3187 const struct mbus_dram_window *cs = dram->cs + i;
3188 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
3189 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
3190
3191 mvreg_write(pp, MVNETA_WIN_SIZE(i),
3192 (cs->size - 1) & 0xffff0000);
3193
3194 win_enable &= ~(1 << i);
3195 win_protect |= 3 << (2 * i);
3196 }
3197
3198 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
Marcin Wojtasdb6ba9a2015-11-30 13:27:41 +01003199 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003200}
3201
3202/* Power up the port */
Thomas Petazzoni3f1dd4b2014-04-15 15:50:20 +02003203static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003204{
Thomas Petazzoni3f1dd4b2014-04-15 15:50:20 +02003205 u32 ctrl;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003206
3207 /* MAC Cause register should be cleared */
3208 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
3209
Thomas Petazzoni3f1dd4b2014-04-15 15:50:20 +02003210 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003211
Thomas Petazzoni3f1dd4b2014-04-15 15:50:20 +02003212 /* Even though it might look weird, when we're configured in
3213 * SGMII or QSGMII mode, the RGMII bit needs to be set.
3214 */
3215 switch(phy_mode) {
3216 case PHY_INTERFACE_MODE_QSGMII:
3217 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
3218 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
3219 break;
3220 case PHY_INTERFACE_MODE_SGMII:
3221 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
3222 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
3223 break;
3224 case PHY_INTERFACE_MODE_RGMII:
3225 case PHY_INTERFACE_MODE_RGMII_ID:
3226 ctrl |= MVNETA_GMAC2_PORT_RGMII;
3227 break;
3228 default:
3229 return -EINVAL;
3230 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003231
Stas Sergeev898b2972015-04-01 20:32:49 +03003232 if (pp->use_inband_status)
3233 ctrl |= MVNETA_GMAC2_INBAND_AN_ENABLE;
3234
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003235 /* Cancel Port Reset */
Thomas Petazzoni3f1dd4b2014-04-15 15:50:20 +02003236 ctrl &= ~MVNETA_GMAC2_PORT_RESET;
3237 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003238
3239 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
3240 MVNETA_GMAC2_PORT_RESET) != 0)
3241 continue;
Thomas Petazzoni3f1dd4b2014-04-15 15:50:20 +02003242
3243 return 0;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003244}
3245
3246/* Device initialization routine */
Greg KH03ce7582012-12-21 13:42:15 +00003247static int mvneta_probe(struct platform_device *pdev)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003248{
3249 const struct mbus_dram_target_info *dram_target_info;
Thomas Petazzonic3f0dd32014-03-27 11:39:29 +01003250 struct resource *res;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003251 struct device_node *dn = pdev->dev.of_node;
3252 struct device_node *phy_node;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003253 struct mvneta_port *pp;
3254 struct net_device *dev;
Thomas Petazzoni8cc3e432013-06-04 04:52:23 +00003255 const char *dt_mac_addr;
3256 char hw_mac_addr[ETH_ALEN];
3257 const char *mac_from;
Stas Sergeevf8af8e62015-07-20 17:49:58 -07003258 const char *managed;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003259 int phy_mode;
3260 int err;
Maxime Ripard12bb03b2015-09-25 18:09:36 +02003261 int cpu;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003262
Willy Tarreauee40a112013-04-11 23:00:37 +02003263 dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003264 if (!dev)
3265 return -ENOMEM;
3266
3267 dev->irq = irq_of_parse_and_map(dn, 0);
3268 if (dev->irq == 0) {
3269 err = -EINVAL;
3270 goto err_free_netdev;
3271 }
3272
3273 phy_node = of_parse_phandle(dn, "phy", 0);
3274 if (!phy_node) {
Thomas Petazzoni83895be2014-05-16 16:14:06 +02003275 if (!of_phy_is_fixed_link(dn)) {
3276 dev_err(&pdev->dev, "no PHY specified\n");
3277 err = -ENODEV;
3278 goto err_free_irq;
3279 }
3280
3281 err = of_phy_register_fixed_link(dn);
3282 if (err < 0) {
3283 dev_err(&pdev->dev, "cannot register fixed PHY\n");
3284 goto err_free_irq;
3285 }
3286
3287 /* In the case of a fixed PHY, the DT node associated
3288 * to the PHY is the Ethernet MAC DT node.
3289 */
Uwe Kleine-Königc891c242014-08-07 21:58:46 +02003290 phy_node = of_node_get(dn);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003291 }
3292
3293 phy_mode = of_get_phy_mode(dn);
3294 if (phy_mode < 0) {
3295 dev_err(&pdev->dev, "incorrect phy-mode\n");
3296 err = -EINVAL;
Uwe Kleine-Königc891c242014-08-07 21:58:46 +02003297 goto err_put_phy_node;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003298 }
3299
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003300 dev->tx_queue_len = MVNETA_MAX_TXD;
3301 dev->watchdog_timeo = 5 * HZ;
3302 dev->netdev_ops = &mvneta_netdev_ops;
3303
Wilfried Klaebe7ad24ea2014-05-11 00:12:32 +00003304 dev->ethtool_ops = &mvneta_eth_tool_ops;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003305
3306 pp = netdev_priv(dev);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003307 pp->phy_node = phy_node;
3308 pp->phy_interface = phy_mode;
Stas Sergeevf8af8e62015-07-20 17:49:58 -07003309
3310 err = of_property_read_string(dn, "managed", &managed);
3311 pp->use_inband_status = (err == 0 &&
3312 strcmp(managed, "in-band-status") == 0);
Maxime Ripardf8642882015-09-25 18:09:38 +02003313 pp->cpu_notifier.notifier_call = mvneta_percpu_notifier;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003314
Thomas Petazzoni189dd622012-11-19 14:15:25 +01003315 pp->clk = devm_clk_get(&pdev->dev, NULL);
3316 if (IS_ERR(pp->clk)) {
3317 err = PTR_ERR(pp->clk);
Uwe Kleine-Königc891c242014-08-07 21:58:46 +02003318 goto err_put_phy_node;
Thomas Petazzoni189dd622012-11-19 14:15:25 +01003319 }
3320
3321 clk_prepare_enable(pp->clk);
3322
Thomas Petazzonic3f0dd32014-03-27 11:39:29 +01003323 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3324 pp->base = devm_ioremap_resource(&pdev->dev, res);
3325 if (IS_ERR(pp->base)) {
3326 err = PTR_ERR(pp->base);
Arnaud Patard \(Rtp\)5445eaf2013-07-29 21:56:48 +02003327 goto err_clk;
3328 }
3329
Maxime Ripard12bb03b2015-09-25 18:09:36 +02003330 /* Alloc per-cpu port structure */
3331 pp->ports = alloc_percpu(struct mvneta_pcpu_port);
3332 if (!pp->ports) {
3333 err = -ENOMEM;
3334 goto err_clk;
3335 }
3336
willy tarreau74c41b02014-01-16 08:20:08 +01003337 /* Alloc per-cpu stats */
WANG Cong1c213bd2014-02-13 11:46:28 -08003338 pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats);
willy tarreau74c41b02014-01-16 08:20:08 +01003339 if (!pp->stats) {
3340 err = -ENOMEM;
Maxime Ripard12bb03b2015-09-25 18:09:36 +02003341 goto err_free_ports;
willy tarreau74c41b02014-01-16 08:20:08 +01003342 }
3343
Thomas Petazzoni8cc3e432013-06-04 04:52:23 +00003344 dt_mac_addr = of_get_mac_address(dn);
Luka Perkov6c7a9a32013-10-30 00:10:01 +01003345 if (dt_mac_addr) {
Thomas Petazzoni8cc3e432013-06-04 04:52:23 +00003346 mac_from = "device tree";
3347 memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN);
3348 } else {
3349 mvneta_get_mac_addr(pp, hw_mac_addr);
3350 if (is_valid_ether_addr(hw_mac_addr)) {
3351 mac_from = "hardware";
3352 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
3353 } else {
3354 mac_from = "random";
3355 eth_hw_addr_random(dev);
3356 }
3357 }
3358
Simon Guinotb65657f2015-06-30 16:20:22 +02003359 if (of_device_is_compatible(dn, "marvell,armada-370-neta"))
3360 pp->tx_csum_limit = 1600;
3361
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003362 pp->tx_ring_size = MVNETA_MAX_TXD;
3363 pp->rx_ring_size = MVNETA_MAX_RXD;
3364
3365 pp->dev = dev;
3366 SET_NETDEV_DEV(dev, &pdev->dev);
3367
Ezequiel Garcia96728502014-05-22 20:06:59 -03003368 err = mvneta_init(&pdev->dev, pp);
3369 if (err < 0)
willy tarreau74c41b02014-01-16 08:20:08 +01003370 goto err_free_stats;
Thomas Petazzoni3f1dd4b2014-04-15 15:50:20 +02003371
3372 err = mvneta_port_power_up(pp, phy_mode);
3373 if (err < 0) {
3374 dev_err(&pdev->dev, "can't power up port\n");
Ezequiel Garcia96728502014-05-22 20:06:59 -03003375 goto err_free_stats;
Thomas Petazzoni3f1dd4b2014-04-15 15:50:20 +02003376 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003377
3378 dram_target_info = mv_mbus_dram_info();
3379 if (dram_target_info)
3380 mvneta_conf_mbus_windows(pp, dram_target_info);
3381
Maxime Ripard12bb03b2015-09-25 18:09:36 +02003382 for_each_present_cpu(cpu) {
3383 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
3384
3385 netif_napi_add(dev, &port->napi, mvneta_poll, NAPI_POLL_WEIGHT);
3386 port->pp = pp;
3387 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003388
Ezequiel Garcia2adb7192014-05-19 13:59:55 -03003389 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
Ezequiel Garcia01ef26c2014-05-19 13:59:53 -03003390 dev->hw_features |= dev->features;
3391 dev->vlan_features |= dev->features;
willy tarreaub50b72d2013-04-06 08:47:01 +00003392 dev->priv_flags |= IFF_UNICAST_FLT;
Ezequiel Garcia8eef5f92014-05-30 13:40:05 -03003393 dev->gso_max_segs = MVNETA_MAX_TSO_SEGS;
willy tarreaub50b72d2013-04-06 08:47:01 +00003394
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003395 err = register_netdev(dev);
3396 if (err < 0) {
3397 dev_err(&pdev->dev, "failed to register\n");
Ezequiel Garcia96728502014-05-22 20:06:59 -03003398 goto err_free_stats;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003399 }
3400
Thomas Petazzoni8cc3e432013-06-04 04:52:23 +00003401 netdev_info(dev, "Using %s mac address %pM\n", mac_from,
3402 dev->dev_addr);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003403
3404 platform_set_drvdata(pdev, pp->dev);
3405
Stas Sergeev898b2972015-04-01 20:32:49 +03003406 if (pp->use_inband_status) {
3407 struct phy_device *phy = of_phy_find_device(dn);
3408
3409 mvneta_fixed_link_update(pp, phy);
Russell King04d53b22015-09-24 20:36:18 +01003410
3411 put_device(&phy->dev);
Stas Sergeev898b2972015-04-01 20:32:49 +03003412 }
3413
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003414 return 0;
3415
willy tarreau74c41b02014-01-16 08:20:08 +01003416err_free_stats:
3417 free_percpu(pp->stats);
Maxime Ripard12bb03b2015-09-25 18:09:36 +02003418err_free_ports:
3419 free_percpu(pp->ports);
Arnaud Patard \(Rtp\)5445eaf2013-07-29 21:56:48 +02003420err_clk:
3421 clk_disable_unprepare(pp->clk);
Uwe Kleine-Königc891c242014-08-07 21:58:46 +02003422err_put_phy_node:
3423 of_node_put(phy_node);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003424err_free_irq:
3425 irq_dispose_mapping(dev->irq);
3426err_free_netdev:
3427 free_netdev(dev);
3428 return err;
3429}
3430
3431/* Device removal routine */
Greg KH03ce7582012-12-21 13:42:15 +00003432static int mvneta_remove(struct platform_device *pdev)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003433{
3434 struct net_device *dev = platform_get_drvdata(pdev);
3435 struct mvneta_port *pp = netdev_priv(dev);
3436
3437 unregister_netdev(dev);
Thomas Petazzoni189dd622012-11-19 14:15:25 +01003438 clk_disable_unprepare(pp->clk);
Maxime Ripard12bb03b2015-09-25 18:09:36 +02003439 free_percpu(pp->ports);
willy tarreau74c41b02014-01-16 08:20:08 +01003440 free_percpu(pp->stats);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003441 irq_dispose_mapping(dev->irq);
Uwe Kleine-Königc891c242014-08-07 21:58:46 +02003442 of_node_put(pp->phy_node);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003443 free_netdev(dev);
3444
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003445 return 0;
3446}
3447
3448static const struct of_device_id mvneta_match[] = {
3449 { .compatible = "marvell,armada-370-neta" },
Simon Guinotf522a972015-06-30 16:20:20 +02003450 { .compatible = "marvell,armada-xp-neta" },
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003451 { }
3452};
3453MODULE_DEVICE_TABLE(of, mvneta_match);
3454
3455static struct platform_driver mvneta_driver = {
3456 .probe = mvneta_probe,
Greg KH03ce7582012-12-21 13:42:15 +00003457 .remove = mvneta_remove,
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003458 .driver = {
3459 .name = MVNETA_DRIVER_NAME,
3460 .of_match_table = mvneta_match,
3461 },
3462};
3463
3464module_platform_driver(mvneta_driver);
3465
3466MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
3467MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
3468MODULE_LICENSE("GPL");
3469
3470module_param(rxq_number, int, S_IRUGO);
3471module_param(txq_number, int, S_IRUGO);
3472
3473module_param(rxq_def, int, S_IRUGO);
willy tarreauf19fadf2014-01-16 08:20:17 +01003474module_param(rx_copybreak, int, S_IRUGO | S_IWUSR);