blob: b3f37e7b33c0471dcbce61afb345ac6c0c740fb0 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio.
4 *
5 * Copyright(c) 2004 Intel Corporation. All rights reserved.
6 *
7 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
8 * PeiSen Hou <pshou@realtek.com.tw>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along with
21 * this program; if not, write to the Free Software Foundation, Inc., 59
22 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 *
24 * CONTACTS:
25 *
26 * Matt Jared matt.jared@intel.com
27 * Andy Kopp andy.kopp@intel.com
28 * Dan Kogan dan.d.kogan@intel.com
29 *
30 * CHANGES:
31 *
32 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
33 *
34 */
35
36#include <sound/driver.h>
37#include <asm/io.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
Randy Dunlap362775e2005-11-07 14:43:23 +010040#include <linux/kernel.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070041#include <linux/module.h>
42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
46#include <sound/core.h>
47#include <sound/initval.h>
48#include "hda_codec.h"
49
50
Clemens Ladischb7fe4622005-10-04 08:46:51 +020051static int index = SNDRV_DEFAULT_IDX1;
52static char *id = SNDRV_DEFAULT_STR1;
53static char *model;
54static int position_fix;
Matt Porter954fa192005-11-29 14:46:01 +010055static int probe_mask = -1;
Takashi Iwai27346162006-01-12 18:28:44 +010056static int single_cmd;
Linus Torvalds1da177e2005-04-16 15:20:36 -070057
Clemens Ladischb7fe4622005-10-04 08:46:51 +020058module_param(index, int, 0444);
Linus Torvalds1da177e2005-04-16 15:20:36 -070059MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
Clemens Ladischb7fe4622005-10-04 08:46:51 +020060module_param(id, charp, 0444);
Linus Torvalds1da177e2005-04-16 15:20:36 -070061MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
Clemens Ladischb7fe4622005-10-04 08:46:51 +020062module_param(model, charp, 0444);
Linus Torvalds1da177e2005-04-16 15:20:36 -070063MODULE_PARM_DESC(model, "Use the given board model.");
Clemens Ladischb7fe4622005-10-04 08:46:51 +020064module_param(position_fix, int, 0444);
Takashi Iwai0be3b5d2005-09-05 17:11:40 +020065MODULE_PARM_DESC(position_fix, "Fix DMA pointer (0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
Takashi Iwai606ad752005-11-24 16:03:40 +010066module_param(probe_mask, int, 0444);
67MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
Takashi Iwai27346162006-01-12 18:28:44 +010068module_param(single_cmd, bool, 0444);
69MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs (for debugging only).");
Takashi Iwai606ad752005-11-24 16:03:40 +010070
Linus Torvalds1da177e2005-04-16 15:20:36 -070071
Takashi Iwai2b3e5842005-10-06 13:47:23 +020072/* just for backward compatibility */
73static int enable;
Takashi Iwai698444f2005-10-20 16:53:49 +020074module_param(enable, bool, 0444);
Takashi Iwai2b3e5842005-10-06 13:47:23 +020075
Linus Torvalds1da177e2005-04-16 15:20:36 -070076MODULE_LICENSE("GPL");
77MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
78 "{Intel, ICH6M},"
Jason Gaston2f1b3812005-05-01 08:58:50 -070079 "{Intel, ICH7},"
Frederick Lif5d40b32005-05-12 14:55:20 +020080 "{Intel, ESB2},"
Jason Gastond2981392006-01-10 11:07:37 +010081 "{Intel, ICH8},"
Takashi Iwaifc20a562005-05-12 15:00:41 +020082 "{ATI, SB450},"
83 "{VIA, VT8251},"
Takashi Iwai47672312005-08-12 16:44:04 +020084 "{VIA, VT8237A},"
Takashi Iwai07e4ca52005-08-24 14:14:57 +020085 "{SiS, SIS966},"
86 "{ULI, M5461}}");
Linus Torvalds1da177e2005-04-16 15:20:36 -070087MODULE_DESCRIPTION("Intel HDA driver");
88
89#define SFX "hda-intel: "
90
91/*
92 * registers
93 */
94#define ICH6_REG_GCAP 0x00
95#define ICH6_REG_VMIN 0x02
96#define ICH6_REG_VMAJ 0x03
97#define ICH6_REG_OUTPAY 0x04
98#define ICH6_REG_INPAY 0x06
99#define ICH6_REG_GCTL 0x08
100#define ICH6_REG_WAKEEN 0x0c
101#define ICH6_REG_STATESTS 0x0e
102#define ICH6_REG_GSTS 0x10
103#define ICH6_REG_INTCTL 0x20
104#define ICH6_REG_INTSTS 0x24
105#define ICH6_REG_WALCLK 0x30
106#define ICH6_REG_SYNC 0x34
107#define ICH6_REG_CORBLBASE 0x40
108#define ICH6_REG_CORBUBASE 0x44
109#define ICH6_REG_CORBWP 0x48
110#define ICH6_REG_CORBRP 0x4A
111#define ICH6_REG_CORBCTL 0x4c
112#define ICH6_REG_CORBSTS 0x4d
113#define ICH6_REG_CORBSIZE 0x4e
114
115#define ICH6_REG_RIRBLBASE 0x50
116#define ICH6_REG_RIRBUBASE 0x54
117#define ICH6_REG_RIRBWP 0x58
118#define ICH6_REG_RINTCNT 0x5a
119#define ICH6_REG_RIRBCTL 0x5c
120#define ICH6_REG_RIRBSTS 0x5d
121#define ICH6_REG_RIRBSIZE 0x5e
122
123#define ICH6_REG_IC 0x60
124#define ICH6_REG_IR 0x64
125#define ICH6_REG_IRS 0x68
126#define ICH6_IRS_VALID (1<<1)
127#define ICH6_IRS_BUSY (1<<0)
128
129#define ICH6_REG_DPLBASE 0x70
130#define ICH6_REG_DPUBASE 0x74
131#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
132
133/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
134enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
135
136/* stream register offsets from stream base */
137#define ICH6_REG_SD_CTL 0x00
138#define ICH6_REG_SD_STS 0x03
139#define ICH6_REG_SD_LPIB 0x04
140#define ICH6_REG_SD_CBL 0x08
141#define ICH6_REG_SD_LVI 0x0c
142#define ICH6_REG_SD_FIFOW 0x0e
143#define ICH6_REG_SD_FIFOSIZE 0x10
144#define ICH6_REG_SD_FORMAT 0x12
145#define ICH6_REG_SD_BDLPL 0x18
146#define ICH6_REG_SD_BDLPU 0x1c
147
148/* PCI space */
149#define ICH6_PCIREG_TCSEL 0x44
150
151/*
152 * other constants
153 */
154
155/* max number of SDs */
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200156/* ICH, ATI and VIA have 4 playback and 4 capture */
157#define ICH6_CAPTURE_INDEX 0
158#define ICH6_NUM_CAPTURE 4
159#define ICH6_PLAYBACK_INDEX 4
160#define ICH6_NUM_PLAYBACK 4
161
162/* ULI has 6 playback and 5 capture */
163#define ULI_CAPTURE_INDEX 0
164#define ULI_NUM_CAPTURE 5
165#define ULI_PLAYBACK_INDEX 5
166#define ULI_NUM_PLAYBACK 6
167
168/* this number is statically defined for simplicity */
169#define MAX_AZX_DEV 16
170
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171/* max number of fragments - we may use more if allocating more pages for BDL */
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200172#define BDL_SIZE PAGE_ALIGN(8192)
173#define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174/* max buffer size - no h/w limit, you can increase as you like */
175#define AZX_MAX_BUF_SIZE (1024*1024*1024)
176/* max number of PCM devics per card */
Takashi Iwaiec9e1c52005-09-07 13:29:22 +0200177#define AZX_MAX_AUDIO_PCMS 6
178#define AZX_MAX_MODEM_PCMS 2
179#define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180
181/* RIRB int mask: overrun[2], response[0] */
182#define RIRB_INT_RESPONSE 0x01
183#define RIRB_INT_OVERRUN 0x04
184#define RIRB_INT_MASK 0x05
185
186/* STATESTS int mask: SD2,SD1,SD0 */
187#define STATESTS_INT_MASK 0x07
Frederick Lif5d40b32005-05-12 14:55:20 +0200188#define AZX_MAX_CODECS 4
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189
190/* SD_CTL bits */
191#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
192#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
193#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
194#define SD_CTL_STREAM_TAG_SHIFT 20
195
196/* SD_CTL and SD_STS */
197#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
198#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
199#define SD_INT_COMPLETE 0x04 /* completion interrupt */
200#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE)
201
202/* SD_STS */
203#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
204
205/* INTCTL and INTSTS */
206#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
207#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
208#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
209
Matt41e2fce2005-07-04 17:49:55 +0200210/* GCTL unsolicited response enable bit */
211#define ICH6_GCTL_UREN (1<<8)
212
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213/* GCTL reset bit */
214#define ICH6_GCTL_RESET (1<<0)
215
216/* CORB/RIRB control, read/write pointer */
217#define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
218#define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
219#define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
220/* below are so far hardcoded - should read registers in future */
221#define ICH6_MAX_CORB_ENTRIES 256
222#define ICH6_MAX_RIRB_ENTRIES 256
223
Takashi Iwaic74db862005-05-12 14:26:27 +0200224/* position fix mode */
225enum {
Takashi Iwai0be3b5d2005-09-05 17:11:40 +0200226 POS_FIX_AUTO,
Takashi Iwaic74db862005-05-12 14:26:27 +0200227 POS_FIX_NONE,
Takashi Iwai0be3b5d2005-09-05 17:11:40 +0200228 POS_FIX_POSBUF,
229 POS_FIX_FIFO,
Takashi Iwaic74db862005-05-12 14:26:27 +0200230};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231
Frederick Lif5d40b32005-05-12 14:55:20 +0200232/* Defines for ATI HD Audio support in SB450 south bridge */
Frederick Lif5d40b32005-05-12 14:55:20 +0200233#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
234#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
235
Vinod Gda3fca22005-09-13 18:49:12 +0200236/* Defines for Nvidia HDA support */
237#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
238#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
Frederick Lif5d40b32005-05-12 14:55:20 +0200239
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241 */
242
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100243struct azx_dev {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244 u32 *bdl; /* virtual address of the BDL */
245 dma_addr_t bdl_addr; /* physical address of the BDL */
246 volatile u32 *posbuf; /* position buffer pointer */
247
248 unsigned int bufsize; /* size of the play buffer in bytes */
249 unsigned int fragsize; /* size of each period in bytes */
250 unsigned int frags; /* number for period in the play buffer */
251 unsigned int fifo_size; /* FIFO size */
Takashi Iwai0be3b5d2005-09-05 17:11:40 +0200252 unsigned int last_pos; /* last updated period position */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253
254 void __iomem *sd_addr; /* stream descriptor pointer */
255
256 u32 sd_int_sta_mask; /* stream int status mask */
257
258 /* pcm support */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100259 struct snd_pcm_substream *substream; /* assigned substream, set in PCM open */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700260 unsigned int format_val; /* format value to be set in the controller and the codec */
261 unsigned char stream_tag; /* assigned stream */
262 unsigned char index; /* stream index */
263
264 unsigned int opened: 1;
265 unsigned int running: 1;
Takashi Iwai0be3b5d2005-09-05 17:11:40 +0200266 unsigned int period_updating: 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267};
268
269/* CORB/RIRB */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100270struct azx_rb {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271 u32 *buf; /* CORB/RIRB buffer
272 * Each CORB entry is 4byte, RIRB is 8byte
273 */
274 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
275 /* for RIRB */
276 unsigned short rp, wp; /* read/write pointers */
277 int cmds; /* number of pending requests */
278 u32 res; /* last read value */
279};
280
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100281struct azx {
282 struct snd_card *card;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700283 struct pci_dev *pci;
284
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200285 /* chip type specific */
286 int driver_type;
287 int playback_streams;
288 int playback_index_offset;
289 int capture_streams;
290 int capture_index_offset;
291 int num_streams;
292
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293 /* pci resources */
294 unsigned long addr;
295 void __iomem *remap_addr;
296 int irq;
297
298 /* locks */
299 spinlock_t reg_lock;
300 struct semaphore open_mutex;
301
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200302 /* streams (x num_streams) */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100303 struct azx_dev *azx_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304
305 /* PCM */
306 unsigned int pcm_devs;
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100307 struct snd_pcm *pcm[AZX_MAX_PCMS];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308
309 /* HD codec */
310 unsigned short codec_mask;
311 struct hda_bus *bus;
312
313 /* CORB/RIRB */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100314 struct azx_rb corb;
315 struct azx_rb rirb;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700316
317 /* BDL, CORB/RIRB and position buffers */
318 struct snd_dma_buffer bdl;
319 struct snd_dma_buffer rb;
320 struct snd_dma_buffer posbuf;
Takashi Iwaic74db862005-05-12 14:26:27 +0200321
322 /* flags */
323 int position_fix;
Takashi Iwaice43fba2005-05-30 20:33:44 +0200324 unsigned int initialized: 1;
Takashi Iwai27346162006-01-12 18:28:44 +0100325 unsigned int single_cmd: 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326};
327
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200328/* driver types */
329enum {
330 AZX_DRIVER_ICH,
331 AZX_DRIVER_ATI,
332 AZX_DRIVER_VIA,
333 AZX_DRIVER_SIS,
334 AZX_DRIVER_ULI,
Vinod Gda3fca22005-09-13 18:49:12 +0200335 AZX_DRIVER_NVIDIA,
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200336};
337
338static char *driver_short_names[] __devinitdata = {
339 [AZX_DRIVER_ICH] = "HDA Intel",
340 [AZX_DRIVER_ATI] = "HDA ATI SB",
341 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
342 [AZX_DRIVER_SIS] = "HDA SIS966",
Vinod Gda3fca22005-09-13 18:49:12 +0200343 [AZX_DRIVER_ULI] = "HDA ULI M5461",
344 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200345};
346
Linus Torvalds1da177e2005-04-16 15:20:36 -0700347/*
348 * macros for easy use
349 */
350#define azx_writel(chip,reg,value) \
351 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
352#define azx_readl(chip,reg) \
353 readl((chip)->remap_addr + ICH6_REG_##reg)
354#define azx_writew(chip,reg,value) \
355 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
356#define azx_readw(chip,reg) \
357 readw((chip)->remap_addr + ICH6_REG_##reg)
358#define azx_writeb(chip,reg,value) \
359 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
360#define azx_readb(chip,reg) \
361 readb((chip)->remap_addr + ICH6_REG_##reg)
362
363#define azx_sd_writel(dev,reg,value) \
364 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
365#define azx_sd_readl(dev,reg) \
366 readl((dev)->sd_addr + ICH6_REG_##reg)
367#define azx_sd_writew(dev,reg,value) \
368 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
369#define azx_sd_readw(dev,reg) \
370 readw((dev)->sd_addr + ICH6_REG_##reg)
371#define azx_sd_writeb(dev,reg,value) \
372 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
373#define azx_sd_readb(dev,reg) \
374 readb((dev)->sd_addr + ICH6_REG_##reg)
375
376/* for pcm support */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100377#define get_azx_dev(substream) (substream->runtime->private_data)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378
379/* Get the upper 32bit of the given dma_addr_t
380 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
381 */
382#define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
383
384
385/*
386 * Interface for HD codec
387 */
388
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389/*
390 * CORB / RIRB interface
391 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100392static int azx_alloc_cmd_io(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700393{
394 int err;
395
396 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
397 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
398 PAGE_SIZE, &chip->rb);
399 if (err < 0) {
400 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
401 return err;
402 }
403 return 0;
404}
405
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100406static void azx_init_cmd_io(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700407{
408 /* CORB set up */
409 chip->corb.addr = chip->rb.addr;
410 chip->corb.buf = (u32 *)chip->rb.area;
411 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
412 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
413
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200414 /* set the corb size to 256 entries (ULI requires explicitly) */
415 azx_writeb(chip, CORBSIZE, 0x02);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700416 /* set the corb write pointer to 0 */
417 azx_writew(chip, CORBWP, 0);
418 /* reset the corb hw read pointer */
419 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
420 /* enable corb dma */
421 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
422
423 /* RIRB set up */
424 chip->rirb.addr = chip->rb.addr + 2048;
425 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
426 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
427 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
428
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200429 /* set the rirb size to 256 entries (ULI requires explicitly) */
430 azx_writeb(chip, RIRBSIZE, 0x02);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431 /* reset the rirb hw write pointer */
432 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
433 /* set N=1, get RIRB response interrupt for new entry */
434 azx_writew(chip, RINTCNT, 1);
435 /* enable rirb dma and response irq */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700437 chip->rirb.rp = chip->rirb.cmds = 0;
438}
439
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100440static void azx_free_cmd_io(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441{
442 /* disable ringbuffer DMAs */
443 azx_writeb(chip, RIRBCTL, 0);
444 azx_writeb(chip, CORBCTL, 0);
445}
446
447/* send a command */
448static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
449 unsigned int verb, unsigned int para)
450{
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100451 struct azx *chip = codec->bus->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700452 unsigned int wp;
453 u32 val;
454
455 val = (u32)(codec->addr & 0x0f) << 28;
456 val |= (u32)direct << 27;
457 val |= (u32)nid << 20;
458 val |= verb << 8;
459 val |= para;
460
461 /* add command to corb */
462 wp = azx_readb(chip, CORBWP);
463 wp++;
464 wp %= ICH6_MAX_CORB_ENTRIES;
465
466 spin_lock_irq(&chip->reg_lock);
467 chip->rirb.cmds++;
468 chip->corb.buf[wp] = cpu_to_le32(val);
469 azx_writel(chip, CORBWP, wp);
470 spin_unlock_irq(&chip->reg_lock);
471
472 return 0;
473}
474
475#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
476
477/* retrieve RIRB entry - called from interrupt handler */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100478static void azx_update_rirb(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700479{
480 unsigned int rp, wp;
481 u32 res, res_ex;
482
483 wp = azx_readb(chip, RIRBWP);
484 if (wp == chip->rirb.wp)
485 return;
486 chip->rirb.wp = wp;
487
488 while (chip->rirb.rp != wp) {
489 chip->rirb.rp++;
490 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
491
492 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
493 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
494 res = le32_to_cpu(chip->rirb.buf[rp]);
495 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
496 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
497 else if (chip->rirb.cmds) {
498 chip->rirb.cmds--;
499 chip->rirb.res = res;
500 }
501 }
502}
503
504/* receive a response */
505static unsigned int azx_get_response(struct hda_codec *codec)
506{
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100507 struct azx *chip = codec->bus->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508 int timeout = 50;
509
510 while (chip->rirb.cmds) {
511 if (! --timeout) {
Randy Dunlap362775e2005-11-07 14:43:23 +0100512 if (printk_ratelimit())
513 snd_printk(KERN_ERR
514 "azx_get_response timeout\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700515 chip->rirb.rp = azx_readb(chip, RIRBWP);
516 chip->rirb.cmds = 0;
517 return -1;
518 }
519 msleep(1);
520 }
521 return chip->rirb.res; /* the last value */
522}
523
Linus Torvalds1da177e2005-04-16 15:20:36 -0700524/*
525 * Use the single immediate command instead of CORB/RIRB for simplicity
526 *
527 * Note: according to Intel, this is not preferred use. The command was
528 * intended for the BIOS only, and may get confused with unsolicited
529 * responses. So, we shouldn't use it for normal operation from the
530 * driver.
531 * I left the codes, however, for debugging/testing purposes.
532 */
533
Linus Torvalds1da177e2005-04-16 15:20:36 -0700534/* send a command */
Takashi Iwai27346162006-01-12 18:28:44 +0100535static int azx_single_send_cmd(struct hda_codec *codec, hda_nid_t nid,
536 int direct, unsigned int verb,
537 unsigned int para)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538{
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100539 struct azx *chip = codec->bus->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700540 u32 val;
541 int timeout = 50;
542
543 val = (u32)(codec->addr & 0x0f) << 28;
544 val |= (u32)direct << 27;
545 val |= (u32)nid << 20;
546 val |= verb << 8;
547 val |= para;
548
549 while (timeout--) {
550 /* check ICB busy bit */
551 if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) {
552 /* Clear IRV valid bit */
553 azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID);
554 azx_writel(chip, IC, val);
555 azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY);
556 return 0;
557 }
558 udelay(1);
559 }
560 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val);
561 return -EIO;
562}
563
564/* receive a response */
Takashi Iwai27346162006-01-12 18:28:44 +0100565static unsigned int azx_single_get_response(struct hda_codec *codec)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700566{
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100567 struct azx *chip = codec->bus->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700568 int timeout = 50;
569
570 while (timeout--) {
571 /* check IRV busy bit */
572 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
573 return azx_readl(chip, IR);
574 udelay(1);
575 }
576 snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS));
577 return (unsigned int)-1;
578}
579
Linus Torvalds1da177e2005-04-16 15:20:36 -0700580/* reset codec link */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100581static int azx_reset(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700582{
583 int count;
584
585 /* reset controller */
586 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
587
588 count = 50;
589 while (azx_readb(chip, GCTL) && --count)
590 msleep(1);
591
592 /* delay for >= 100us for codec PLL to settle per spec
593 * Rev 0.9 section 5.5.1
594 */
595 msleep(1);
596
597 /* Bring controller out of reset */
598 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
599
600 count = 50;
601 while (! azx_readb(chip, GCTL) && --count)
602 msleep(1);
603
604 /* Brent Chartrand said to wait >= 540us for codecs to intialize */
605 msleep(1);
606
607 /* check to see if controller is ready */
608 if (! azx_readb(chip, GCTL)) {
609 snd_printd("azx_reset: controller not ready!\n");
610 return -EBUSY;
611 }
612
Matt41e2fce2005-07-04 17:49:55 +0200613 /* Accept unsolicited responses */
614 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
615
Linus Torvalds1da177e2005-04-16 15:20:36 -0700616 /* detect codecs */
617 if (! chip->codec_mask) {
618 chip->codec_mask = azx_readw(chip, STATESTS);
619 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
620 }
621
622 return 0;
623}
624
625
626/*
627 * Lowlevel interface
628 */
629
630/* enable interrupts */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100631static void azx_int_enable(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700632{
633 /* enable controller CIE and GIE */
634 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
635 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
636}
637
638/* disable interrupts */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100639static void azx_int_disable(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700640{
641 int i;
642
643 /* disable interrupts in stream descriptor */
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200644 for (i = 0; i < chip->num_streams; i++) {
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100645 struct azx_dev *azx_dev = &chip->azx_dev[i];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700646 azx_sd_writeb(azx_dev, SD_CTL,
647 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
648 }
649
650 /* disable SIE for all streams */
651 azx_writeb(chip, INTCTL, 0);
652
653 /* disable controller CIE and GIE */
654 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
655 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
656}
657
658/* clear interrupts */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100659static void azx_int_clear(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660{
661 int i;
662
663 /* clear stream status */
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200664 for (i = 0; i < chip->num_streams; i++) {
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100665 struct azx_dev *azx_dev = &chip->azx_dev[i];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700666 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
667 }
668
669 /* clear STATESTS */
670 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
671
672 /* clear rirb status */
673 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
674
675 /* clear int status */
676 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
677}
678
679/* start a stream */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100680static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700681{
682 /* enable SIE */
683 azx_writeb(chip, INTCTL,
684 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
685 /* set DMA start and interrupt mask */
686 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
687 SD_CTL_DMA_START | SD_INT_MASK);
688}
689
690/* stop a stream */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100691static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692{
693 /* stop DMA */
694 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
695 ~(SD_CTL_DMA_START | SD_INT_MASK));
696 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
697 /* disable SIE */
698 azx_writeb(chip, INTCTL,
699 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
700}
701
702
703/*
704 * initialize the chip
705 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100706static void azx_init_chip(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700707{
Vinod Gda3fca22005-09-13 18:49:12 +0200708 unsigned char reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700709
710 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
711 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
712 * Ensuring these bits are 0 clears playback static on some HD Audio codecs
713 */
Vinod Gda3fca22005-09-13 18:49:12 +0200714 pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, &reg);
715 pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, reg & 0xf8);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700716
717 /* reset controller */
718 azx_reset(chip);
719
720 /* initialize interrupts */
721 azx_int_clear(chip);
722 azx_int_enable(chip);
723
724 /* initialize the codec command I/O */
Takashi Iwai27346162006-01-12 18:28:44 +0100725 if (! chip->single_cmd)
726 azx_init_cmd_io(chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700727
Takashi Iwai0be3b5d2005-09-05 17:11:40 +0200728 /* program the position buffer */
729 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
730 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
Frederick Lif5d40b32005-05-12 14:55:20 +0200731
Vinod Gda3fca22005-09-13 18:49:12 +0200732 switch (chip->driver_type) {
733 case AZX_DRIVER_ATI:
734 /* For ATI SB450 azalia HD audio, we need to enable snoop */
Frederick Lif5d40b32005-05-12 14:55:20 +0200735 pci_read_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
Vinod Gda3fca22005-09-13 18:49:12 +0200736 &reg);
Frederick Lif5d40b32005-05-12 14:55:20 +0200737 pci_write_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
Vinod Gda3fca22005-09-13 18:49:12 +0200738 (reg & 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP);
739 break;
740 case AZX_DRIVER_NVIDIA:
741 /* For NVIDIA HDA, enable snoop */
742 pci_read_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR, &reg);
743 pci_write_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR,
744 (reg & 0xf0) | NVIDIA_HDA_ENABLE_COHBITS);
745 break;
746 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747}
748
749
750/*
751 * interrupt handler
752 */
753static irqreturn_t azx_interrupt(int irq, void* dev_id, struct pt_regs *regs)
754{
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100755 struct azx *chip = dev_id;
756 struct azx_dev *azx_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700757 u32 status;
758 int i;
759
760 spin_lock(&chip->reg_lock);
761
762 status = azx_readl(chip, INTSTS);
763 if (status == 0) {
764 spin_unlock(&chip->reg_lock);
765 return IRQ_NONE;
766 }
767
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200768 for (i = 0; i < chip->num_streams; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700769 azx_dev = &chip->azx_dev[i];
770 if (status & azx_dev->sd_int_sta_mask) {
771 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
772 if (azx_dev->substream && azx_dev->running) {
Takashi Iwai0be3b5d2005-09-05 17:11:40 +0200773 azx_dev->period_updating = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774 spin_unlock(&chip->reg_lock);
775 snd_pcm_period_elapsed(azx_dev->substream);
776 spin_lock(&chip->reg_lock);
Takashi Iwai0be3b5d2005-09-05 17:11:40 +0200777 azx_dev->period_updating = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700778 }
779 }
780 }
781
782 /* clear rirb int */
783 status = azx_readb(chip, RIRBSTS);
784 if (status & RIRB_INT_MASK) {
Takashi Iwai27346162006-01-12 18:28:44 +0100785 if (! chip->single_cmd && (status & RIRB_INT_RESPONSE))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700786 azx_update_rirb(chip);
787 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
788 }
789
790#if 0
791 /* clear state status int */
792 if (azx_readb(chip, STATESTS) & 0x04)
793 azx_writeb(chip, STATESTS, 0x04);
794#endif
795 spin_unlock(&chip->reg_lock);
796
797 return IRQ_HANDLED;
798}
799
800
801/*
802 * set up BDL entries
803 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100804static void azx_setup_periods(struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700805{
806 u32 *bdl = azx_dev->bdl;
807 dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
808 int idx;
809
810 /* reset BDL address */
811 azx_sd_writel(azx_dev, SD_BDLPL, 0);
812 azx_sd_writel(azx_dev, SD_BDLPU, 0);
813
814 /* program the initial BDL entries */
815 for (idx = 0; idx < azx_dev->frags; idx++) {
816 unsigned int off = idx << 2; /* 4 dword step */
817 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
818 /* program the address field of the BDL entry */
819 bdl[off] = cpu_to_le32((u32)addr);
820 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
821
822 /* program the size field of the BDL entry */
823 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
824
825 /* program the IOC to enable interrupt when buffer completes */
826 bdl[off+3] = cpu_to_le32(0x01);
827 }
828}
829
830/*
831 * set up the SD for streaming
832 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100833static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700834{
835 unsigned char val;
836 int timeout;
837
838 /* make sure the run bit is zero for SD */
839 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START);
840 /* reset stream */
841 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET);
842 udelay(3);
843 timeout = 300;
844 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
845 --timeout)
846 ;
847 val &= ~SD_CTL_STREAM_RESET;
848 azx_sd_writeb(azx_dev, SD_CTL, val);
849 udelay(3);
850
851 timeout = 300;
852 /* waiting for hardware to report that the stream is out of reset */
853 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
854 --timeout)
855 ;
856
857 /* program the stream_tag */
858 azx_sd_writel(azx_dev, SD_CTL,
859 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) |
860 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
861
862 /* program the length of samples in cyclic buffer */
863 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
864
865 /* program the stream format */
866 /* this value needs to be the same as the one programmed */
867 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
868
869 /* program the stream LVI (last valid index) of the BDL */
870 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
871
872 /* program the BDL address */
873 /* lower BDL address */
874 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
875 /* upper BDL address */
876 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
877
Takashi Iwai0be3b5d2005-09-05 17:11:40 +0200878 /* enable the position buffer */
879 if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
880 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
Takashi Iwaic74db862005-05-12 14:26:27 +0200881
Linus Torvalds1da177e2005-04-16 15:20:36 -0700882 /* set the interrupt enable bits in the descriptor control register */
883 azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
884
885 return 0;
886}
887
888
889/*
890 * Codec initialization
891 */
892
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100893static int __devinit azx_codec_create(struct azx *chip, const char *model)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700894{
895 struct hda_bus_template bus_temp;
896 int c, codecs, err;
897
898 memset(&bus_temp, 0, sizeof(bus_temp));
899 bus_temp.private_data = chip;
900 bus_temp.modelname = model;
901 bus_temp.pci = chip->pci;
Takashi Iwai27346162006-01-12 18:28:44 +0100902 if (chip->single_cmd) {
903 bus_temp.ops.command = azx_single_send_cmd;
904 bus_temp.ops.get_response = azx_single_get_response;
905 } else {
906 bus_temp.ops.command = azx_send_cmd;
907 bus_temp.ops.get_response = azx_get_response;
908 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700909
910 if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0)
911 return err;
912
913 codecs = 0;
914 for (c = 0; c < AZX_MAX_CODECS; c++) {
Takashi Iwai606ad752005-11-24 16:03:40 +0100915 if ((chip->codec_mask & (1 << c)) & probe_mask) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700916 err = snd_hda_codec_new(chip->bus, c, NULL);
917 if (err < 0)
918 continue;
919 codecs++;
920 }
921 }
922 if (! codecs) {
923 snd_printk(KERN_ERR SFX "no codecs initialized\n");
924 return -ENXIO;
925 }
926
927 return 0;
928}
929
930
931/*
932 * PCM support
933 */
934
935/* assign a stream for the PCM */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100936static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700937{
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200938 int dev, i, nums;
939 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
940 dev = chip->playback_index_offset;
941 nums = chip->playback_streams;
942 } else {
943 dev = chip->capture_index_offset;
944 nums = chip->capture_streams;
945 }
946 for (i = 0; i < nums; i++, dev++)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700947 if (! chip->azx_dev[dev].opened) {
948 chip->azx_dev[dev].opened = 1;
949 return &chip->azx_dev[dev];
950 }
951 return NULL;
952}
953
954/* release the assigned stream */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100955static inline void azx_release_device(struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700956{
957 azx_dev->opened = 0;
958}
959
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100960static struct snd_pcm_hardware azx_pcm_hw = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700961 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
962 SNDRV_PCM_INFO_BLOCK_TRANSFER |
963 SNDRV_PCM_INFO_MMAP_VALID |
Jaroslav Kysela47123192005-08-15 20:53:07 +0200964 SNDRV_PCM_INFO_PAUSE /*|*/
965 /*SNDRV_PCM_INFO_RESUME*/),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700966 .formats = SNDRV_PCM_FMTBIT_S16_LE,
967 .rates = SNDRV_PCM_RATE_48000,
968 .rate_min = 48000,
969 .rate_max = 48000,
970 .channels_min = 2,
971 .channels_max = 2,
972 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
973 .period_bytes_min = 128,
974 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
975 .periods_min = 2,
976 .periods_max = AZX_MAX_FRAG,
977 .fifo_size = 0,
978};
979
980struct azx_pcm {
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100981 struct azx *chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700982 struct hda_codec *codec;
983 struct hda_pcm_stream *hinfo[2];
984};
985
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100986static int azx_pcm_open(struct snd_pcm_substream *substream)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700987{
988 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
989 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100990 struct azx *chip = apcm->chip;
991 struct azx_dev *azx_dev;
992 struct snd_pcm_runtime *runtime = substream->runtime;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700993 unsigned long flags;
994 int err;
995
996 down(&chip->open_mutex);
997 azx_dev = azx_assign_device(chip, substream->stream);
998 if (azx_dev == NULL) {
999 up(&chip->open_mutex);
1000 return -EBUSY;
1001 }
1002 runtime->hw = azx_pcm_hw;
1003 runtime->hw.channels_min = hinfo->channels_min;
1004 runtime->hw.channels_max = hinfo->channels_max;
1005 runtime->hw.formats = hinfo->formats;
1006 runtime->hw.rates = hinfo->rates;
1007 snd_pcm_limit_hw_rates(runtime);
1008 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1009 if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
1010 azx_release_device(azx_dev);
1011 up(&chip->open_mutex);
1012 return err;
1013 }
1014 spin_lock_irqsave(&chip->reg_lock, flags);
1015 azx_dev->substream = substream;
1016 azx_dev->running = 0;
1017 spin_unlock_irqrestore(&chip->reg_lock, flags);
1018
1019 runtime->private_data = azx_dev;
1020 up(&chip->open_mutex);
1021 return 0;
1022}
1023
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001024static int azx_pcm_close(struct snd_pcm_substream *substream)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001025{
1026 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1027 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001028 struct azx *chip = apcm->chip;
1029 struct azx_dev *azx_dev = get_azx_dev(substream);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001030 unsigned long flags;
1031
1032 down(&chip->open_mutex);
1033 spin_lock_irqsave(&chip->reg_lock, flags);
1034 azx_dev->substream = NULL;
1035 azx_dev->running = 0;
1036 spin_unlock_irqrestore(&chip->reg_lock, flags);
1037 azx_release_device(azx_dev);
1038 hinfo->ops.close(hinfo, apcm->codec, substream);
1039 up(&chip->open_mutex);
1040 return 0;
1041}
1042
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001043static int azx_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001044{
1045 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1046}
1047
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001048static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001049{
1050 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001051 struct azx_dev *azx_dev = get_azx_dev(substream);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001052 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1053
1054 /* reset BDL address */
1055 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1056 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1057 azx_sd_writel(azx_dev, SD_CTL, 0);
1058
1059 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1060
1061 return snd_pcm_lib_free_pages(substream);
1062}
1063
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001064static int azx_pcm_prepare(struct snd_pcm_substream *substream)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001065{
1066 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001067 struct azx *chip = apcm->chip;
1068 struct azx_dev *azx_dev = get_azx_dev(substream);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001069 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001070 struct snd_pcm_runtime *runtime = substream->runtime;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001071
1072 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1073 azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1074 azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1075 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1076 runtime->channels,
1077 runtime->format,
1078 hinfo->maxbps);
1079 if (! azx_dev->format_val) {
1080 snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n",
1081 runtime->rate, runtime->channels, runtime->format);
1082 return -EINVAL;
1083 }
1084
1085 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n",
1086 azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1087 azx_setup_periods(azx_dev);
1088 azx_setup_controller(chip, azx_dev);
1089 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1090 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1091 else
1092 azx_dev->fifo_size = 0;
Takashi Iwai0be3b5d2005-09-05 17:11:40 +02001093 azx_dev->last_pos = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001094
1095 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1096 azx_dev->format_val, substream);
1097}
1098
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001099static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001100{
1101 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001102 struct azx_dev *azx_dev = get_azx_dev(substream);
1103 struct azx *chip = apcm->chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001104 int err = 0;
1105
1106 spin_lock(&chip->reg_lock);
1107 switch (cmd) {
1108 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1109 case SNDRV_PCM_TRIGGER_RESUME:
1110 case SNDRV_PCM_TRIGGER_START:
1111 azx_stream_start(chip, azx_dev);
1112 azx_dev->running = 1;
1113 break;
1114 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
Jaroslav Kysela47123192005-08-15 20:53:07 +02001115 case SNDRV_PCM_TRIGGER_SUSPEND:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001116 case SNDRV_PCM_TRIGGER_STOP:
1117 azx_stream_stop(chip, azx_dev);
1118 azx_dev->running = 0;
1119 break;
1120 default:
1121 err = -EINVAL;
1122 }
1123 spin_unlock(&chip->reg_lock);
1124 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
Jaroslav Kysela47123192005-08-15 20:53:07 +02001125 cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
Linus Torvalds1da177e2005-04-16 15:20:36 -07001126 cmd == SNDRV_PCM_TRIGGER_STOP) {
1127 int timeout = 5000;
1128 while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout)
1129 ;
1130 }
1131 return err;
1132}
1133
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001134static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001135{
Takashi Iwaic74db862005-05-12 14:26:27 +02001136 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001137 struct azx *chip = apcm->chip;
1138 struct azx_dev *azx_dev = get_azx_dev(substream);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001139 unsigned int pos;
1140
Takashi Iwaic74db862005-05-12 14:26:27 +02001141 if (chip->position_fix == POS_FIX_POSBUF) {
1142 /* use the position buffer */
1143 pos = *azx_dev->posbuf;
1144 } else {
1145 /* read LPIB */
1146 pos = azx_sd_readl(azx_dev, SD_LPIB);
1147 if (chip->position_fix == POS_FIX_FIFO)
1148 pos += azx_dev->fifo_size;
1149 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001150 if (pos >= azx_dev->bufsize)
1151 pos = 0;
1152 return bytes_to_frames(substream->runtime, pos);
1153}
1154
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001155static struct snd_pcm_ops azx_pcm_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001156 .open = azx_pcm_open,
1157 .close = azx_pcm_close,
1158 .ioctl = snd_pcm_lib_ioctl,
1159 .hw_params = azx_pcm_hw_params,
1160 .hw_free = azx_pcm_hw_free,
1161 .prepare = azx_pcm_prepare,
1162 .trigger = azx_pcm_trigger,
1163 .pointer = azx_pcm_pointer,
1164};
1165
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001166static void azx_pcm_free(struct snd_pcm *pcm)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001167{
1168 kfree(pcm->private_data);
1169}
1170
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001171static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001172 struct hda_pcm *cpcm, int pcm_dev)
1173{
1174 int err;
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001175 struct snd_pcm *pcm;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001176 struct azx_pcm *apcm;
1177
1178 snd_assert(cpcm->stream[0].substreams || cpcm->stream[1].substreams, return -EINVAL);
1179 snd_assert(cpcm->name, return -EINVAL);
1180
1181 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1182 cpcm->stream[0].substreams, cpcm->stream[1].substreams,
1183 &pcm);
1184 if (err < 0)
1185 return err;
1186 strcpy(pcm->name, cpcm->name);
1187 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1188 if (apcm == NULL)
1189 return -ENOMEM;
1190 apcm->chip = chip;
1191 apcm->codec = codec;
1192 apcm->hinfo[0] = &cpcm->stream[0];
1193 apcm->hinfo[1] = &cpcm->stream[1];
1194 pcm->private_data = apcm;
1195 pcm->private_free = azx_pcm_free;
1196 if (cpcm->stream[0].substreams)
1197 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1198 if (cpcm->stream[1].substreams)
1199 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1200 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1201 snd_dma_pci_data(chip->pci),
1202 1024 * 64, 1024 * 128);
1203 chip->pcm[pcm_dev] = pcm;
Jaroslav Kysela47123192005-08-15 20:53:07 +02001204 chip->pcm_devs = pcm_dev + 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001205
1206 return 0;
1207}
1208
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001209static int __devinit azx_pcm_create(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001210{
1211 struct list_head *p;
1212 struct hda_codec *codec;
1213 int c, err;
1214 int pcm_dev;
1215
1216 if ((err = snd_hda_build_pcms(chip->bus)) < 0)
1217 return err;
1218
Takashi Iwaiec9e1c52005-09-07 13:29:22 +02001219 /* create audio PCMs */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001220 pcm_dev = 0;
1221 list_for_each(p, &chip->bus->codec_list) {
1222 codec = list_entry(p, struct hda_codec, list);
1223 for (c = 0; c < codec->num_pcms; c++) {
Takashi Iwaiec9e1c52005-09-07 13:29:22 +02001224 if (codec->pcm_info[c].is_modem)
1225 continue; /* create later */
1226 if (pcm_dev >= AZX_MAX_AUDIO_PCMS) {
1227 snd_printk(KERN_ERR SFX "Too many audio PCMs\n");
1228 return -EINVAL;
1229 }
1230 err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1231 if (err < 0)
1232 return err;
1233 pcm_dev++;
1234 }
1235 }
1236
1237 /* create modem PCMs */
1238 pcm_dev = AZX_MAX_AUDIO_PCMS;
1239 list_for_each(p, &chip->bus->codec_list) {
1240 codec = list_entry(p, struct hda_codec, list);
1241 for (c = 0; c < codec->num_pcms; c++) {
1242 if (! codec->pcm_info[c].is_modem)
1243 continue; /* already created */
Takashi Iwaia28f1cd2005-09-07 15:26:56 +02001244 if (pcm_dev >= AZX_MAX_PCMS) {
Takashi Iwaiec9e1c52005-09-07 13:29:22 +02001245 snd_printk(KERN_ERR SFX "Too many modem PCMs\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001246 return -EINVAL;
1247 }
1248 err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1249 if (err < 0)
1250 return err;
Sasha Khapyorsky6632d192005-09-29 11:48:17 +02001251 chip->pcm[pcm_dev]->dev_class = SNDRV_PCM_CLASS_MODEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001252 pcm_dev++;
1253 }
1254 }
1255 return 0;
1256}
1257
1258/*
1259 * mixer creation - all stuff is implemented in hda module
1260 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001261static int __devinit azx_mixer_create(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001262{
1263 return snd_hda_build_controls(chip->bus);
1264}
1265
1266
1267/*
1268 * initialize SD streams
1269 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001270static int __devinit azx_init_stream(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001271{
1272 int i;
1273
1274 /* initialize each stream (aka device)
1275 * assign the starting bdl address to each stream (device) and initialize
1276 */
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001277 for (i = 0; i < chip->num_streams; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001278 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001279 struct azx_dev *azx_dev = &chip->azx_dev[i];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001280 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1281 azx_dev->bdl_addr = chip->bdl.addr + off;
Takashi Iwai0be3b5d2005-09-05 17:11:40 +02001282 azx_dev->posbuf = (volatile u32 *)(chip->posbuf.area + i * 8);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001283 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1284 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1285 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1286 azx_dev->sd_int_sta_mask = 1 << i;
1287 /* stream tag: must be non-zero and unique */
1288 azx_dev->index = i;
1289 azx_dev->stream_tag = i + 1;
1290 }
1291
1292 return 0;
1293}
1294
1295
1296#ifdef CONFIG_PM
1297/*
1298 * power management
1299 */
Takashi Iwai421a1252005-11-17 16:11:09 +01001300static int azx_suspend(struct pci_dev *pci, pm_message_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001301{
Takashi Iwai421a1252005-11-17 16:11:09 +01001302 struct snd_card *card = pci_get_drvdata(pci);
1303 struct azx *chip = card->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001304 int i;
1305
Takashi Iwai421a1252005-11-17 16:11:09 +01001306 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001307 for (i = 0; i < chip->pcm_devs; i++)
Takashi Iwai421a1252005-11-17 16:11:09 +01001308 snd_pcm_suspend_all(chip->pcm[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001309 snd_hda_suspend(chip->bus, state);
Takashi Iwai27346162006-01-12 18:28:44 +01001310 if (! chip->single_cmd)
1311 azx_free_cmd_io(chip);
Takashi Iwai421a1252005-11-17 16:11:09 +01001312 pci_disable_device(pci);
1313 pci_save_state(pci);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001314 return 0;
1315}
1316
Takashi Iwai421a1252005-11-17 16:11:09 +01001317static int azx_resume(struct pci_dev *pci)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001318{
Takashi Iwai421a1252005-11-17 16:11:09 +01001319 struct snd_card *card = pci_get_drvdata(pci);
1320 struct azx *chip = card->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001321
Takashi Iwai421a1252005-11-17 16:11:09 +01001322 pci_restore_state(pci);
1323 pci_enable_device(pci);
1324 pci_set_master(pci);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001325 azx_init_chip(chip);
1326 snd_hda_resume(chip->bus);
Takashi Iwai421a1252005-11-17 16:11:09 +01001327 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001328 return 0;
1329}
1330#endif /* CONFIG_PM */
1331
1332
1333/*
1334 * destructor
1335 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001336static int azx_free(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001337{
Takashi Iwaice43fba2005-05-30 20:33:44 +02001338 if (chip->initialized) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001339 int i;
1340
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001341 for (i = 0; i < chip->num_streams; i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001342 azx_stream_stop(chip, &chip->azx_dev[i]);
1343
1344 /* disable interrupts */
1345 azx_int_disable(chip);
1346 azx_int_clear(chip);
1347
1348 /* disable CORB/RIRB */
Takashi Iwai27346162006-01-12 18:28:44 +01001349 if (! chip->single_cmd)
1350 azx_free_cmd_io(chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001351
1352 /* disable position buffer */
1353 azx_writel(chip, DPLBASE, 0);
1354 azx_writel(chip, DPUBASE, 0);
1355
1356 /* wait a little for interrupts to finish */
1357 msleep(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001358 }
1359
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001360 if (chip->remap_addr)
1361 iounmap(chip->remap_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001362 if (chip->irq >= 0)
1363 free_irq(chip->irq, (void*)chip);
1364
1365 if (chip->bdl.area)
1366 snd_dma_free_pages(&chip->bdl);
1367 if (chip->rb.area)
1368 snd_dma_free_pages(&chip->rb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001369 if (chip->posbuf.area)
1370 snd_dma_free_pages(&chip->posbuf);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001371 pci_release_regions(chip->pci);
1372 pci_disable_device(chip->pci);
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001373 kfree(chip->azx_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001374 kfree(chip);
1375
1376 return 0;
1377}
1378
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001379static int azx_dev_free(struct snd_device *device)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001380{
1381 return azx_free(device->device_data);
1382}
1383
1384/*
1385 * constructor
1386 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001387static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
Takashi Iwai606ad752005-11-24 16:03:40 +01001388 int driver_type,
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001389 struct azx **rchip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001390{
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001391 struct azx *chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001392 int err = 0;
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001393 static struct snd_device_ops ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001394 .dev_free = azx_dev_free,
1395 };
1396
1397 *rchip = NULL;
1398
1399 if ((err = pci_enable_device(pci)) < 0)
1400 return err;
1401
Takashi Iwaie560d8d2005-09-09 14:21:46 +02001402 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001403
1404 if (NULL == chip) {
1405 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1406 pci_disable_device(pci);
1407 return -ENOMEM;
1408 }
1409
1410 spin_lock_init(&chip->reg_lock);
1411 init_MUTEX(&chip->open_mutex);
1412 chip->card = card;
1413 chip->pci = pci;
1414 chip->irq = -1;
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001415 chip->driver_type = driver_type;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001416
Takashi Iwai606ad752005-11-24 16:03:40 +01001417 chip->position_fix = position_fix ? position_fix : POS_FIX_POSBUF;
Takashi Iwai27346162006-01-12 18:28:44 +01001418 chip->single_cmd = single_cmd;
Takashi Iwaic74db862005-05-12 14:26:27 +02001419
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001420#if BITS_PER_LONG != 64
1421 /* Fix up base address on ULI M5461 */
1422 if (chip->driver_type == AZX_DRIVER_ULI) {
1423 u16 tmp3;
1424 pci_read_config_word(pci, 0x40, &tmp3);
1425 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1426 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1427 }
1428#endif
1429
Linus Torvalds1da177e2005-04-16 15:20:36 -07001430 if ((err = pci_request_regions(pci, "ICH HD audio")) < 0) {
1431 kfree(chip);
1432 pci_disable_device(pci);
1433 return err;
1434 }
1435
1436 chip->addr = pci_resource_start(pci,0);
1437 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1438 if (chip->remap_addr == NULL) {
1439 snd_printk(KERN_ERR SFX "ioremap error\n");
1440 err = -ENXIO;
1441 goto errout;
1442 }
1443
1444 if (request_irq(pci->irq, azx_interrupt, SA_INTERRUPT|SA_SHIRQ,
1445 "HDA Intel", (void*)chip)) {
1446 snd_printk(KERN_ERR SFX "unable to grab IRQ %d\n", pci->irq);
1447 err = -EBUSY;
1448 goto errout;
1449 }
1450 chip->irq = pci->irq;
1451
1452 pci_set_master(pci);
1453 synchronize_irq(chip->irq);
1454
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001455 switch (chip->driver_type) {
1456 case AZX_DRIVER_ULI:
1457 chip->playback_streams = ULI_NUM_PLAYBACK;
1458 chip->capture_streams = ULI_NUM_CAPTURE;
1459 chip->playback_index_offset = ULI_PLAYBACK_INDEX;
1460 chip->capture_index_offset = ULI_CAPTURE_INDEX;
1461 break;
1462 default:
1463 chip->playback_streams = ICH6_NUM_PLAYBACK;
1464 chip->capture_streams = ICH6_NUM_CAPTURE;
1465 chip->playback_index_offset = ICH6_PLAYBACK_INDEX;
1466 chip->capture_index_offset = ICH6_CAPTURE_INDEX;
1467 break;
1468 }
1469 chip->num_streams = chip->playback_streams + chip->capture_streams;
1470 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), GFP_KERNEL);
1471 if (! chip->azx_dev) {
1472 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1473 goto errout;
1474 }
1475
Linus Torvalds1da177e2005-04-16 15:20:36 -07001476 /* allocate memory for the BDL for each stream */
1477 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001478 BDL_SIZE, &chip->bdl)) < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001479 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1480 goto errout;
1481 }
Takashi Iwai0be3b5d2005-09-05 17:11:40 +02001482 /* allocate memory for the position buffer */
1483 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1484 chip->num_streams * 8, &chip->posbuf)) < 0) {
1485 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1486 goto errout;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001487 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001488 /* allocate CORB/RIRB */
Takashi Iwai27346162006-01-12 18:28:44 +01001489 if (! chip->single_cmd)
1490 if ((err = azx_alloc_cmd_io(chip)) < 0)
1491 goto errout;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001492
1493 /* initialize streams */
1494 azx_init_stream(chip);
1495
1496 /* initialize chip */
1497 azx_init_chip(chip);
1498
Takashi Iwaice43fba2005-05-30 20:33:44 +02001499 chip->initialized = 1;
1500
Linus Torvalds1da177e2005-04-16 15:20:36 -07001501 /* codec detection */
1502 if (! chip->codec_mask) {
1503 snd_printk(KERN_ERR SFX "no codecs found!\n");
1504 err = -ENODEV;
1505 goto errout;
1506 }
1507
1508 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) {
1509 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1510 goto errout;
1511 }
1512
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001513 strcpy(card->driver, "HDA-Intel");
1514 strcpy(card->shortname, driver_short_names[chip->driver_type]);
1515 sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq);
1516
Linus Torvalds1da177e2005-04-16 15:20:36 -07001517 *rchip = chip;
1518 return 0;
1519
1520 errout:
1521 azx_free(chip);
1522 return err;
1523}
1524
1525static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1526{
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001527 struct snd_card *card;
1528 struct azx *chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001529 int err = 0;
1530
Clemens Ladischb7fe4622005-10-04 08:46:51 +02001531 card = snd_card_new(index, id, THIS_MODULE, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001532 if (NULL == card) {
1533 snd_printk(KERN_ERR SFX "Error creating card!\n");
1534 return -ENOMEM;
1535 }
1536
Takashi Iwai606ad752005-11-24 16:03:40 +01001537 if ((err = azx_create(card, pci, pci_id->driver_data,
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001538 &chip)) < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001539 snd_card_free(card);
1540 return err;
1541 }
Takashi Iwai421a1252005-11-17 16:11:09 +01001542 card->private_data = chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001543
Linus Torvalds1da177e2005-04-16 15:20:36 -07001544 /* create codec instances */
Clemens Ladischb7fe4622005-10-04 08:46:51 +02001545 if ((err = azx_codec_create(chip, model)) < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001546 snd_card_free(card);
1547 return err;
1548 }
1549
1550 /* create PCM streams */
1551 if ((err = azx_pcm_create(chip)) < 0) {
1552 snd_card_free(card);
1553 return err;
1554 }
1555
1556 /* create mixer controls */
1557 if ((err = azx_mixer_create(chip)) < 0) {
1558 snd_card_free(card);
1559 return err;
1560 }
1561
Linus Torvalds1da177e2005-04-16 15:20:36 -07001562 snd_card_set_dev(card, &pci->dev);
1563
1564 if ((err = snd_card_register(card)) < 0) {
1565 snd_card_free(card);
1566 return err;
1567 }
1568
1569 pci_set_drvdata(pci, card);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001570
1571 return err;
1572}
1573
1574static void __devexit azx_remove(struct pci_dev *pci)
1575{
1576 snd_card_free(pci_get_drvdata(pci));
1577 pci_set_drvdata(pci, NULL);
1578}
1579
1580/* PCI IDs */
1581static struct pci_device_id azx_ids[] = {
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001582 { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
1583 { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
1584 { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
Jason Gastond2981392006-01-10 11:07:37 +01001585 { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001586 { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
1587 { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
1588 { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
1589 { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
Vinod Gda3fca22005-09-13 18:49:12 +02001590 { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA 026c */
1591 { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA 0371 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001592 { 0, }
1593};
1594MODULE_DEVICE_TABLE(pci, azx_ids);
1595
1596/* pci_driver definition */
1597static struct pci_driver driver = {
1598 .name = "HDA Intel",
1599 .id_table = azx_ids,
1600 .probe = azx_probe,
1601 .remove = __devexit_p(azx_remove),
Takashi Iwai421a1252005-11-17 16:11:09 +01001602#ifdef CONFIG_PM
1603 .suspend = azx_suspend,
1604 .resume = azx_resume,
1605#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001606};
1607
1608static int __init alsa_card_azx_init(void)
1609{
Takashi Iwai01d25d42005-04-11 16:58:24 +02001610 return pci_register_driver(&driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001611}
1612
1613static void __exit alsa_card_azx_exit(void)
1614{
1615 pci_unregister_driver(&driver);
1616}
1617
1618module_init(alsa_card_azx_init)
1619module_exit(alsa_card_azx_exit)