Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. |
| 3 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
Julien Grall | 68628bb | 2016-04-11 16:32:55 +0100 | [diff] [blame] | 18 | #define pr_fmt(fmt) "GICv3: " fmt |
| 19 | |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 20 | #include <linux/acpi.h> |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 21 | #include <linux/cpu.h> |
Sudeep Holla | 3708d52 | 2014-08-26 16:03:35 +0100 | [diff] [blame] | 22 | #include <linux/cpu_pm.h> |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 23 | #include <linux/delay.h> |
| 24 | #include <linux/interrupt.h> |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 25 | #include <linux/irqdomain.h> |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 26 | #include <linux/of.h> |
| 27 | #include <linux/of_address.h> |
| 28 | #include <linux/of_irq.h> |
| 29 | #include <linux/percpu.h> |
| 30 | #include <linux/slab.h> |
Channagoud Kadabi | df16454 | 2016-09-19 20:24:21 -0700 | [diff] [blame] | 31 | #include <linux/msm_rtb.h> |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 32 | |
Joel Porquet | 41a83e0 | 2015-07-07 17:11:46 -0400 | [diff] [blame] | 33 | #include <linux/irqchip.h> |
Julien Grall | 1839e57 | 2016-04-11 16:32:57 +0100 | [diff] [blame] | 34 | #include <linux/irqchip/arm-gic-common.h> |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 35 | #include <linux/irqchip/arm-gic-v3.h> |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 36 | #include <linux/irqchip/irq-partition-percpu.h> |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 37 | |
| 38 | #include <asm/cputype.h> |
| 39 | #include <asm/exception.h> |
| 40 | #include <asm/smp_plat.h> |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 41 | #include <asm/virt.h> |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 42 | |
| 43 | #include "irq-gic-common.h" |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 44 | |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 45 | struct redist_region { |
| 46 | void __iomem *redist_base; |
| 47 | phys_addr_t phys_base; |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 48 | bool single_redist; |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 49 | }; |
| 50 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 51 | struct gic_chip_data { |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 52 | struct fwnode_handle *fwnode; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 53 | void __iomem *dist_base; |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 54 | struct redist_region *redist_regions; |
| 55 | struct rdists rdists; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 56 | struct irq_domain *domain; |
| 57 | u64 redist_stride; |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 58 | u32 nr_redist_regions; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 59 | unsigned int irq_nr; |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 60 | struct partition_desc *ppi_descs[16]; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 61 | }; |
| 62 | |
| 63 | static struct gic_chip_data gic_data __read_mostly; |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 64 | static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 65 | |
Julien Grall | 1839e57 | 2016-04-11 16:32:57 +0100 | [diff] [blame] | 66 | static struct gic_kvm_info gic_v3_kvm_info; |
| 67 | |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 68 | #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) |
| 69 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 70 | #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) |
| 71 | |
| 72 | /* Our default, arbitrary priority value. Linux only uses one anyway. */ |
| 73 | #define DEFAULT_PMR_VALUE 0xf0 |
| 74 | |
| 75 | static inline unsigned int gic_irq(struct irq_data *d) |
| 76 | { |
| 77 | return d->hwirq; |
| 78 | } |
| 79 | |
| 80 | static inline int gic_irq_in_rdist(struct irq_data *d) |
| 81 | { |
| 82 | return gic_irq(d) < 32; |
| 83 | } |
| 84 | |
| 85 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
| 86 | { |
| 87 | if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ |
| 88 | return gic_data_rdist_sgi_base(); |
| 89 | |
| 90 | if (d->hwirq <= 1023) /* SPI -> dist_base */ |
| 91 | return gic_data.dist_base; |
| 92 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 93 | return NULL; |
| 94 | } |
| 95 | |
| 96 | static void gic_do_wait_for_rwp(void __iomem *base) |
| 97 | { |
| 98 | u32 count = 1000000; /* 1s! */ |
| 99 | |
Runmin Wang | 62c17dc | 2016-09-09 17:33:20 -0700 | [diff] [blame] | 100 | while (readl_relaxed_no_log(base + GICD_CTLR) & GICD_CTLR_RWP) { |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 101 | count--; |
| 102 | if (!count) { |
| 103 | pr_err_ratelimited("RWP timeout, gone fishing\n"); |
| 104 | return; |
| 105 | } |
| 106 | cpu_relax(); |
| 107 | udelay(1); |
| 108 | }; |
| 109 | } |
| 110 | |
| 111 | /* Wait for completion of a distributor change */ |
| 112 | static void gic_dist_wait_for_rwp(void) |
| 113 | { |
| 114 | gic_do_wait_for_rwp(gic_data.dist_base); |
| 115 | } |
| 116 | |
| 117 | /* Wait for completion of a redistributor change */ |
| 118 | static void gic_redist_wait_for_rwp(void) |
| 119 | { |
| 120 | gic_do_wait_for_rwp(gic_data_rdist_rd_base()); |
| 121 | } |
| 122 | |
Jean-Philippe Brucker | 7936e91 | 2015-10-01 13:47:14 +0100 | [diff] [blame] | 123 | #ifdef CONFIG_ARM64 |
Robert Richter | 8ac2a17 | 2015-09-21 22:58:39 +0200 | [diff] [blame] | 124 | static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx); |
Robert Richter | 6d4e11c | 2015-09-21 22:58:35 +0200 | [diff] [blame] | 125 | |
| 126 | static u64 __maybe_unused gic_read_iar(void) |
| 127 | { |
Robert Richter | 8ac2a17 | 2015-09-21 22:58:39 +0200 | [diff] [blame] | 128 | if (static_branch_unlikely(&is_cavium_thunderx)) |
Robert Richter | 6d4e11c | 2015-09-21 22:58:35 +0200 | [diff] [blame] | 129 | return gic_read_iar_cavium_thunderx(); |
| 130 | else |
| 131 | return gic_read_iar_common(); |
| 132 | } |
Jean-Philippe Brucker | 7936e91 | 2015-10-01 13:47:14 +0100 | [diff] [blame] | 133 | #endif |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 134 | |
Sudeep Holla | a2c2251 | 2014-08-26 16:03:34 +0100 | [diff] [blame] | 135 | static void gic_enable_redist(bool enable) |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 136 | { |
| 137 | void __iomem *rbase; |
| 138 | u32 count = 1000000; /* 1s! */ |
| 139 | u32 val; |
| 140 | |
| 141 | rbase = gic_data_rdist_rd_base(); |
| 142 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 143 | val = readl_relaxed(rbase + GICR_WAKER); |
Sudeep Holla | a2c2251 | 2014-08-26 16:03:34 +0100 | [diff] [blame] | 144 | if (enable) |
| 145 | /* Wake up this CPU redistributor */ |
| 146 | val &= ~GICR_WAKER_ProcessorSleep; |
| 147 | else |
| 148 | val |= GICR_WAKER_ProcessorSleep; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 149 | writel_relaxed(val, rbase + GICR_WAKER); |
| 150 | |
Sudeep Holla | a2c2251 | 2014-08-26 16:03:34 +0100 | [diff] [blame] | 151 | if (!enable) { /* Check that GICR_WAKER is writeable */ |
| 152 | val = readl_relaxed(rbase + GICR_WAKER); |
| 153 | if (!(val & GICR_WAKER_ProcessorSleep)) |
| 154 | return; /* No PM support in this redistributor */ |
| 155 | } |
| 156 | |
Dan Carpenter | d102eb5 | 2016-10-14 10:26:21 +0300 | [diff] [blame] | 157 | while (--count) { |
Sudeep Holla | a2c2251 | 2014-08-26 16:03:34 +0100 | [diff] [blame] | 158 | val = readl_relaxed(rbase + GICR_WAKER); |
Andrew Jones | cf1d9d1 | 2016-05-11 21:23:17 +0200 | [diff] [blame] | 159 | if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) |
Sudeep Holla | a2c2251 | 2014-08-26 16:03:34 +0100 | [diff] [blame] | 160 | break; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 161 | cpu_relax(); |
| 162 | udelay(1); |
| 163 | }; |
Sudeep Holla | a2c2251 | 2014-08-26 16:03:34 +0100 | [diff] [blame] | 164 | if (!count) |
| 165 | pr_err_ratelimited("redistributor failed to %s...\n", |
| 166 | enable ? "wakeup" : "sleep"); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 167 | } |
| 168 | |
| 169 | /* |
| 170 | * Routines to disable, enable, EOI and route interrupts |
| 171 | */ |
Marc Zyngier | b594c6e | 2015-03-18 11:01:24 +0000 | [diff] [blame] | 172 | static int gic_peek_irq(struct irq_data *d, u32 offset) |
| 173 | { |
| 174 | u32 mask = 1 << (gic_irq(d) % 32); |
| 175 | void __iomem *base; |
| 176 | |
| 177 | if (gic_irq_in_rdist(d)) |
| 178 | base = gic_data_rdist_sgi_base(); |
| 179 | else |
| 180 | base = gic_data.dist_base; |
| 181 | |
Runmin Wang | 62c17dc | 2016-09-09 17:33:20 -0700 | [diff] [blame] | 182 | return !!(readl_relaxed_no_log(base + offset + (gic_irq(d) / 32) * 4) & mask); |
Marc Zyngier | b594c6e | 2015-03-18 11:01:24 +0000 | [diff] [blame] | 183 | } |
| 184 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 185 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
| 186 | { |
| 187 | u32 mask = 1 << (gic_irq(d) % 32); |
| 188 | void (*rwp_wait)(void); |
| 189 | void __iomem *base; |
| 190 | |
| 191 | if (gic_irq_in_rdist(d)) { |
| 192 | base = gic_data_rdist_sgi_base(); |
| 193 | rwp_wait = gic_redist_wait_for_rwp; |
| 194 | } else { |
| 195 | base = gic_data.dist_base; |
| 196 | rwp_wait = gic_dist_wait_for_rwp; |
| 197 | } |
| 198 | |
| 199 | writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); |
| 200 | rwp_wait(); |
| 201 | } |
| 202 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 203 | static void gic_mask_irq(struct irq_data *d) |
| 204 | { |
| 205 | gic_poke_irq(d, GICD_ICENABLER); |
| 206 | } |
| 207 | |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 208 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
| 209 | { |
| 210 | gic_mask_irq(d); |
Marc Zyngier | 530bf35 | 2015-08-26 17:00:43 +0100 | [diff] [blame] | 211 | /* |
| 212 | * When masking a forwarded interrupt, make sure it is |
| 213 | * deactivated as well. |
| 214 | * |
| 215 | * This ensures that an interrupt that is getting |
| 216 | * disabled/masked will not get "stuck", because there is |
| 217 | * noone to deactivate it (guest is being terminated). |
| 218 | */ |
Thomas Gleixner | 4df7f54 | 2015-09-15 13:19:16 +0200 | [diff] [blame] | 219 | if (irqd_is_forwarded_to_vcpu(d)) |
Marc Zyngier | 530bf35 | 2015-08-26 17:00:43 +0100 | [diff] [blame] | 220 | gic_poke_irq(d, GICD_ICACTIVER); |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 221 | } |
| 222 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 223 | static void gic_unmask_irq(struct irq_data *d) |
| 224 | { |
| 225 | gic_poke_irq(d, GICD_ISENABLER); |
| 226 | } |
| 227 | |
Marc Zyngier | b594c6e | 2015-03-18 11:01:24 +0000 | [diff] [blame] | 228 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
| 229 | enum irqchip_irq_state which, bool val) |
| 230 | { |
| 231 | u32 reg; |
| 232 | |
| 233 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ |
| 234 | return -EINVAL; |
| 235 | |
| 236 | switch (which) { |
| 237 | case IRQCHIP_STATE_PENDING: |
| 238 | reg = val ? GICD_ISPENDR : GICD_ICPENDR; |
| 239 | break; |
| 240 | |
| 241 | case IRQCHIP_STATE_ACTIVE: |
| 242 | reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; |
| 243 | break; |
| 244 | |
| 245 | case IRQCHIP_STATE_MASKED: |
| 246 | reg = val ? GICD_ICENABLER : GICD_ISENABLER; |
| 247 | break; |
| 248 | |
| 249 | default: |
| 250 | return -EINVAL; |
| 251 | } |
| 252 | |
| 253 | gic_poke_irq(d, reg); |
| 254 | return 0; |
| 255 | } |
| 256 | |
| 257 | static int gic_irq_get_irqchip_state(struct irq_data *d, |
| 258 | enum irqchip_irq_state which, bool *val) |
| 259 | { |
| 260 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ |
| 261 | return -EINVAL; |
| 262 | |
| 263 | switch (which) { |
| 264 | case IRQCHIP_STATE_PENDING: |
| 265 | *val = gic_peek_irq(d, GICD_ISPENDR); |
| 266 | break; |
| 267 | |
| 268 | case IRQCHIP_STATE_ACTIVE: |
| 269 | *val = gic_peek_irq(d, GICD_ISACTIVER); |
| 270 | break; |
| 271 | |
| 272 | case IRQCHIP_STATE_MASKED: |
| 273 | *val = !gic_peek_irq(d, GICD_ISENABLER); |
| 274 | break; |
| 275 | |
| 276 | default: |
| 277 | return -EINVAL; |
| 278 | } |
| 279 | |
| 280 | return 0; |
| 281 | } |
| 282 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 283 | static void gic_eoi_irq(struct irq_data *d) |
| 284 | { |
| 285 | gic_write_eoir(gic_irq(d)); |
| 286 | } |
| 287 | |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 288 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
| 289 | { |
| 290 | /* |
Marc Zyngier | 530bf35 | 2015-08-26 17:00:43 +0100 | [diff] [blame] | 291 | * No need to deactivate an LPI, or an interrupt that |
| 292 | * is is getting forwarded to a vcpu. |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 293 | */ |
Thomas Gleixner | 4df7f54 | 2015-09-15 13:19:16 +0200 | [diff] [blame] | 294 | if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 295 | return; |
| 296 | gic_write_dir(gic_irq(d)); |
| 297 | } |
| 298 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 299 | static int gic_set_type(struct irq_data *d, unsigned int type) |
| 300 | { |
| 301 | unsigned int irq = gic_irq(d); |
| 302 | void (*rwp_wait)(void); |
| 303 | void __iomem *base; |
| 304 | |
| 305 | /* Interrupt configuration for SGIs can't be changed */ |
| 306 | if (irq < 16) |
| 307 | return -EINVAL; |
| 308 | |
Liviu Dudau | fb7e7de | 2015-01-20 16:52:59 +0000 | [diff] [blame] | 309 | /* SPIs have restrictions on the supported types */ |
| 310 | if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && |
| 311 | type != IRQ_TYPE_EDGE_RISING) |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 312 | return -EINVAL; |
| 313 | |
| 314 | if (gic_irq_in_rdist(d)) { |
| 315 | base = gic_data_rdist_sgi_base(); |
| 316 | rwp_wait = gic_redist_wait_for_rwp; |
| 317 | } else { |
| 318 | base = gic_data.dist_base; |
| 319 | rwp_wait = gic_dist_wait_for_rwp; |
| 320 | } |
| 321 | |
Liviu Dudau | fb7e7de | 2015-01-20 16:52:59 +0000 | [diff] [blame] | 322 | return gic_configure_irq(irq, type, base, rwp_wait); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 323 | } |
| 324 | |
Marc Zyngier | 530bf35 | 2015-08-26 17:00:43 +0100 | [diff] [blame] | 325 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
| 326 | { |
Thomas Gleixner | 4df7f54 | 2015-09-15 13:19:16 +0200 | [diff] [blame] | 327 | if (vcpu) |
| 328 | irqd_set_forwarded_to_vcpu(d); |
| 329 | else |
| 330 | irqd_clr_forwarded_to_vcpu(d); |
Marc Zyngier | 530bf35 | 2015-08-26 17:00:43 +0100 | [diff] [blame] | 331 | return 0; |
| 332 | } |
| 333 | |
Jean-Philippe Brucker | f6c86a4 | 2015-10-01 13:47:15 +0100 | [diff] [blame] | 334 | static u64 gic_mpidr_to_affinity(unsigned long mpidr) |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 335 | { |
| 336 | u64 aff; |
| 337 | |
Jean-Philippe Brucker | f6c86a4 | 2015-10-01 13:47:15 +0100 | [diff] [blame] | 338 | aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 339 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | |
| 340 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | |
| 341 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); |
| 342 | |
| 343 | return aff; |
| 344 | } |
| 345 | |
| 346 | static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) |
| 347 | { |
Jean-Philippe Brucker | f6c86a4 | 2015-10-01 13:47:15 +0100 | [diff] [blame] | 348 | u32 irqnr; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 349 | |
| 350 | do { |
| 351 | irqnr = gic_read_iar(); |
| 352 | |
Marc Zyngier | da33f31 | 2014-11-24 14:35:18 +0000 | [diff] [blame] | 353 | if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { |
Marc Zyngier | ebc6de0 | 2014-08-26 11:03:33 +0100 | [diff] [blame] | 354 | int err; |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 355 | |
Channagoud Kadabi | df16454 | 2016-09-19 20:24:21 -0700 | [diff] [blame] | 356 | uncached_logk(LOGK_IRQ, (void *)(uintptr_t)irqnr); |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 357 | if (static_key_true(&supports_deactivate)) |
| 358 | gic_write_eoir(irqnr); |
| 359 | |
Marc Zyngier | ebc6de0 | 2014-08-26 11:03:33 +0100 | [diff] [blame] | 360 | err = handle_domain_irq(gic_data.domain, irqnr, regs); |
| 361 | if (err) { |
Marc Zyngier | da33f31 | 2014-11-24 14:35:18 +0000 | [diff] [blame] | 362 | WARN_ONCE(true, "Unexpected interrupt received!\n"); |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 363 | if (static_key_true(&supports_deactivate)) { |
| 364 | if (irqnr < 8192) |
| 365 | gic_write_dir(irqnr); |
| 366 | } else { |
| 367 | gic_write_eoir(irqnr); |
| 368 | } |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 369 | } |
Marc Zyngier | ebc6de0 | 2014-08-26 11:03:33 +0100 | [diff] [blame] | 370 | continue; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 371 | } |
| 372 | if (irqnr < 16) { |
Channagoud Kadabi | df16454 | 2016-09-19 20:24:21 -0700 | [diff] [blame] | 373 | uncached_logk(LOGK_IRQ, (void *)(uintptr_t)irqnr); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 374 | gic_write_eoir(irqnr); |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 375 | if (static_key_true(&supports_deactivate)) |
| 376 | gic_write_dir(irqnr); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 377 | #ifdef CONFIG_SMP |
Will Deacon | f86c4fb | 2016-04-26 12:00:00 +0100 | [diff] [blame] | 378 | /* |
| 379 | * Unlike GICv2, we don't need an smp_rmb() here. |
| 380 | * The control dependency from gic_read_iar to |
| 381 | * the ISB in gic_write_eoir is enough to ensure |
| 382 | * that any shared data read by handle_IPI will |
| 383 | * be read after the ACK. |
| 384 | */ |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 385 | handle_IPI(irqnr, regs); |
| 386 | #else |
| 387 | WARN_ONCE(true, "Unexpected SGI received!\n"); |
| 388 | #endif |
| 389 | continue; |
| 390 | } |
| 391 | } while (irqnr != ICC_IAR1_EL1_SPURIOUS); |
| 392 | } |
| 393 | |
| 394 | static void __init gic_dist_init(void) |
| 395 | { |
| 396 | unsigned int i; |
| 397 | u64 affinity; |
| 398 | void __iomem *base = gic_data.dist_base; |
| 399 | |
| 400 | /* Disable the distributor */ |
| 401 | writel_relaxed(0, base + GICD_CTLR); |
| 402 | gic_dist_wait_for_rwp(); |
| 403 | |
Marc Zyngier | 7c9b973 | 2016-05-06 19:41:56 +0100 | [diff] [blame] | 404 | /* |
| 405 | * Configure SPIs as non-secure Group-1. This will only matter |
| 406 | * if the GIC only has a single security state. This will not |
| 407 | * do the right thing if the kernel is running in secure mode, |
| 408 | * but that's not the intended use case anyway. |
| 409 | */ |
| 410 | for (i = 32; i < gic_data.irq_nr; i += 32) |
| 411 | writel_relaxed(~0, base + GICD_IGROUPR + i / 8); |
| 412 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 413 | gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); |
| 414 | |
| 415 | /* Enable distributor with ARE, Group1 */ |
| 416 | writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, |
| 417 | base + GICD_CTLR); |
| 418 | |
| 419 | /* |
| 420 | * Set all global interrupts to the boot CPU only. ARE must be |
| 421 | * enabled. |
| 422 | */ |
| 423 | affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); |
| 424 | for (i = 32; i < gic_data.irq_nr; i++) |
Jean-Philippe Brucker | 72c9712 | 2015-10-01 13:47:16 +0100 | [diff] [blame] | 425 | gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 426 | } |
| 427 | |
| 428 | static int gic_populate_rdist(void) |
| 429 | { |
Jean-Philippe Brucker | f6c86a4 | 2015-10-01 13:47:15 +0100 | [diff] [blame] | 430 | unsigned long mpidr = cpu_logical_map(smp_processor_id()); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 431 | u64 typer; |
| 432 | u32 aff; |
| 433 | int i; |
| 434 | |
| 435 | /* |
| 436 | * Convert affinity to a 32bit value that can be matched to |
| 437 | * GICR_TYPER bits [63:32]. |
| 438 | */ |
| 439 | aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | |
| 440 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | |
| 441 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | |
| 442 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); |
| 443 | |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 444 | for (i = 0; i < gic_data.nr_redist_regions; i++) { |
| 445 | void __iomem *ptr = gic_data.redist_regions[i].redist_base; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 446 | u32 reg; |
| 447 | |
| 448 | reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; |
| 449 | if (reg != GIC_PIDR2_ARCH_GICv3 && |
| 450 | reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ |
| 451 | pr_warn("No redistributor present @%p\n", ptr); |
| 452 | break; |
| 453 | } |
| 454 | |
| 455 | do { |
Jean-Philippe Brucker | 72c9712 | 2015-10-01 13:47:16 +0100 | [diff] [blame] | 456 | typer = gic_read_typer(ptr + GICR_TYPER); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 457 | if ((typer >> 32) == aff) { |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 458 | u64 offset = ptr - gic_data.redist_regions[i].redist_base; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 459 | gic_data_rdist_rd_base() = ptr; |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 460 | gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; |
Jean-Philippe Brucker | f6c86a4 | 2015-10-01 13:47:15 +0100 | [diff] [blame] | 461 | pr_info("CPU%d: found redistributor %lx region %d:%pa\n", |
| 462 | smp_processor_id(), mpidr, i, |
| 463 | &gic_data_rdist()->phys_base); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 464 | return 0; |
| 465 | } |
| 466 | |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 467 | if (gic_data.redist_regions[i].single_redist) |
| 468 | break; |
| 469 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 470 | if (gic_data.redist_stride) { |
| 471 | ptr += gic_data.redist_stride; |
| 472 | } else { |
| 473 | ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ |
| 474 | if (typer & GICR_TYPER_VLPIS) |
| 475 | ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ |
| 476 | } |
| 477 | } while (!(typer & GICR_TYPER_LAST)); |
| 478 | } |
| 479 | |
| 480 | /* We couldn't even deal with ourselves... */ |
Jean-Philippe Brucker | f6c86a4 | 2015-10-01 13:47:15 +0100 | [diff] [blame] | 481 | WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", |
| 482 | smp_processor_id(), mpidr); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 483 | return -ENODEV; |
| 484 | } |
| 485 | |
Sudeep Holla | 3708d52 | 2014-08-26 16:03:35 +0100 | [diff] [blame] | 486 | static void gic_cpu_sys_reg_init(void) |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 487 | { |
Marc Zyngier | 7cabd00 | 2015-09-30 11:48:01 +0100 | [diff] [blame] | 488 | /* |
| 489 | * Need to check that the SRE bit has actually been set. If |
| 490 | * not, it means that SRE is disabled at EL2. We're going to |
| 491 | * die painfully, and there is nothing we can do about it. |
| 492 | * |
| 493 | * Kindly inform the luser. |
| 494 | */ |
| 495 | if (!gic_enable_sre()) |
| 496 | pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 497 | |
| 498 | /* Set priority mask register */ |
| 499 | gic_write_pmr(DEFAULT_PMR_VALUE); |
| 500 | |
Daniel Thompson | 91ef844 | 2016-08-19 17:13:09 +0100 | [diff] [blame] | 501 | /* |
| 502 | * Some firmwares hand over to the kernel with the BPR changed from |
| 503 | * its reset value (and with a value large enough to prevent |
| 504 | * any pre-emptive interrupts from working at all). Writing a zero |
| 505 | * to BPR restores is reset value. |
| 506 | */ |
| 507 | gic_write_bpr1(0); |
| 508 | |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 509 | if (static_key_true(&supports_deactivate)) { |
| 510 | /* EOI drops priority only (mode 1) */ |
| 511 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); |
| 512 | } else { |
| 513 | /* EOI deactivates interrupt too (mode 0) */ |
| 514 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); |
| 515 | } |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 516 | |
| 517 | /* ... and let's hit the road... */ |
| 518 | gic_write_grpen1(1); |
| 519 | } |
| 520 | |
Marc Zyngier | da33f31 | 2014-11-24 14:35:18 +0000 | [diff] [blame] | 521 | static int gic_dist_supports_lpis(void) |
| 522 | { |
| 523 | return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); |
| 524 | } |
| 525 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 526 | static void gic_cpu_init(void) |
| 527 | { |
| 528 | void __iomem *rbase; |
| 529 | |
| 530 | /* Register ourselves with the rest of the world */ |
| 531 | if (gic_populate_rdist()) |
| 532 | return; |
| 533 | |
Sudeep Holla | a2c2251 | 2014-08-26 16:03:34 +0100 | [diff] [blame] | 534 | gic_enable_redist(true); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 535 | |
| 536 | rbase = gic_data_rdist_sgi_base(); |
| 537 | |
Marc Zyngier | 7c9b973 | 2016-05-06 19:41:56 +0100 | [diff] [blame] | 538 | /* Configure SGIs/PPIs as non-secure Group-1 */ |
| 539 | writel_relaxed(~0, rbase + GICR_IGROUPR0); |
| 540 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 541 | gic_cpu_config(rbase, gic_redist_wait_for_rwp); |
| 542 | |
Marc Zyngier | da33f31 | 2014-11-24 14:35:18 +0000 | [diff] [blame] | 543 | /* Give LPIs a spin */ |
Channagoud Kadabi | fdb0664 | 2016-09-19 20:55:36 -0700 | [diff] [blame] | 544 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() && |
| 545 | !IS_ENABLED(CONFIG_ARM_GIC_V3_ACL)) |
Marc Zyngier | da33f31 | 2014-11-24 14:35:18 +0000 | [diff] [blame] | 546 | its_cpu_init(); |
| 547 | |
Sudeep Holla | 3708d52 | 2014-08-26 16:03:35 +0100 | [diff] [blame] | 548 | /* initialise system registers */ |
| 549 | gic_cpu_sys_reg_init(); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 550 | } |
| 551 | |
| 552 | #ifdef CONFIG_SMP |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 553 | |
Richard Cochran | 6670a6d | 2016-07-13 17:16:05 +0000 | [diff] [blame] | 554 | static int gic_starting_cpu(unsigned int cpu) |
| 555 | { |
| 556 | gic_cpu_init(); |
| 557 | return 0; |
| 558 | } |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 559 | |
| 560 | static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, |
Jean-Philippe Brucker | f6c86a4 | 2015-10-01 13:47:15 +0100 | [diff] [blame] | 561 | unsigned long cluster_id) |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 562 | { |
James Morse | 727653d | 2016-09-19 18:29:15 +0100 | [diff] [blame] | 563 | int next_cpu, cpu = *base_cpu; |
Jean-Philippe Brucker | f6c86a4 | 2015-10-01 13:47:15 +0100 | [diff] [blame] | 564 | unsigned long mpidr = cpu_logical_map(cpu); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 565 | u16 tlist = 0; |
| 566 | |
| 567 | while (cpu < nr_cpu_ids) { |
| 568 | /* |
| 569 | * If we ever get a cluster of more than 16 CPUs, just |
| 570 | * scream and skip that CPU. |
| 571 | */ |
| 572 | if (WARN_ON((mpidr & 0xff) >= 16)) |
| 573 | goto out; |
| 574 | |
| 575 | tlist |= 1 << (mpidr & 0xf); |
| 576 | |
James Morse | 727653d | 2016-09-19 18:29:15 +0100 | [diff] [blame] | 577 | next_cpu = cpumask_next(cpu, mask); |
| 578 | if (next_cpu >= nr_cpu_ids) |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 579 | goto out; |
James Morse | 727653d | 2016-09-19 18:29:15 +0100 | [diff] [blame] | 580 | cpu = next_cpu; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 581 | |
| 582 | mpidr = cpu_logical_map(cpu); |
| 583 | |
| 584 | if (cluster_id != (mpidr & ~0xffUL)) { |
| 585 | cpu--; |
| 586 | goto out; |
| 587 | } |
| 588 | } |
| 589 | out: |
| 590 | *base_cpu = cpu; |
| 591 | return tlist; |
| 592 | } |
| 593 | |
Andre Przywara | 7e58027 | 2014-11-12 13:46:06 +0000 | [diff] [blame] | 594 | #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ |
| 595 | (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ |
| 596 | << ICC_SGI1R_AFFINITY_## level ##_SHIFT) |
| 597 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 598 | static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) |
| 599 | { |
| 600 | u64 val; |
| 601 | |
Andre Przywara | 7e58027 | 2014-11-12 13:46:06 +0000 | [diff] [blame] | 602 | val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | |
| 603 | MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | |
| 604 | irq << ICC_SGI1R_SGI_ID_SHIFT | |
| 605 | MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | |
| 606 | tlist << ICC_SGI1R_TARGET_LIST_SHIFT); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 607 | |
| 608 | pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); |
| 609 | gic_write_sgi1r(val); |
| 610 | } |
| 611 | |
| 612 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
| 613 | { |
| 614 | int cpu; |
| 615 | |
| 616 | if (WARN_ON(irq >= 16)) |
| 617 | return; |
| 618 | |
| 619 | /* |
| 620 | * Ensure that stores to Normal memory are visible to the |
| 621 | * other CPUs before issuing the IPI. |
| 622 | */ |
| 623 | smp_wmb(); |
| 624 | |
Rusty Russell | f9b531f | 2015-03-05 10:49:16 +1030 | [diff] [blame] | 625 | for_each_cpu(cpu, mask) { |
Jean-Philippe Brucker | f6c86a4 | 2015-10-01 13:47:15 +0100 | [diff] [blame] | 626 | unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 627 | u16 tlist; |
| 628 | |
| 629 | tlist = gic_compute_target_list(&cpu, mask, cluster_id); |
| 630 | gic_send_sgi(cluster_id, tlist, irq); |
| 631 | } |
| 632 | |
| 633 | /* Force the above writes to ICC_SGI1R_EL1 to be executed */ |
| 634 | isb(); |
| 635 | } |
| 636 | |
| 637 | static void gic_smp_init(void) |
| 638 | { |
| 639 | set_smp_cross_call(gic_raise_softirq); |
Richard Cochran | 6670a6d | 2016-07-13 17:16:05 +0000 | [diff] [blame] | 640 | cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GICV3_STARTING, |
| 641 | "AP_IRQ_GICV3_STARTING", gic_starting_cpu, |
| 642 | NULL); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 643 | } |
| 644 | |
| 645 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
| 646 | bool force) |
| 647 | { |
| 648 | unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); |
| 649 | void __iomem *reg; |
| 650 | int enabled; |
| 651 | u64 val; |
| 652 | |
| 653 | if (gic_irq_in_rdist(d)) |
| 654 | return -EINVAL; |
| 655 | |
| 656 | /* If interrupt was enabled, disable it first */ |
| 657 | enabled = gic_peek_irq(d, GICD_ISENABLER); |
| 658 | if (enabled) |
| 659 | gic_mask_irq(d); |
| 660 | |
| 661 | reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); |
| 662 | val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); |
| 663 | |
Jean-Philippe Brucker | 72c9712 | 2015-10-01 13:47:16 +0100 | [diff] [blame] | 664 | gic_write_irouter(val, reg); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 665 | |
| 666 | /* |
| 667 | * If the interrupt was enabled, enabled it again. Otherwise, |
| 668 | * just wait for the distributor to have digested our changes. |
| 669 | */ |
| 670 | if (enabled) |
| 671 | gic_unmask_irq(d); |
| 672 | else |
| 673 | gic_dist_wait_for_rwp(); |
| 674 | |
Antoine Tenart | 0fc6fa2 | 2016-02-19 16:22:43 +0100 | [diff] [blame] | 675 | return IRQ_SET_MASK_OK_DONE; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 676 | } |
| 677 | #else |
| 678 | #define gic_set_affinity NULL |
| 679 | #define gic_smp_init() do { } while(0) |
| 680 | #endif |
| 681 | |
Sudeep Holla | 3708d52 | 2014-08-26 16:03:35 +0100 | [diff] [blame] | 682 | #ifdef CONFIG_CPU_PM |
Sudeep Holla | ccd9432 | 2016-08-17 13:49:19 +0100 | [diff] [blame] | 683 | /* Check whether it's single security state view */ |
| 684 | static bool gic_dist_security_disabled(void) |
| 685 | { |
| 686 | return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; |
| 687 | } |
| 688 | |
Sudeep Holla | 3708d52 | 2014-08-26 16:03:35 +0100 | [diff] [blame] | 689 | static int gic_cpu_pm_notifier(struct notifier_block *self, |
| 690 | unsigned long cmd, void *v) |
| 691 | { |
Murali Nalajala | 00aaa93 | 2015-05-19 10:26:11 -0700 | [diff] [blame] | 692 | if (from_suspend) |
| 693 | return NOTIFY_OK; |
| 694 | |
Sudeep Holla | 3708d52 | 2014-08-26 16:03:35 +0100 | [diff] [blame] | 695 | if (cmd == CPU_PM_EXIT) { |
Sudeep Holla | ccd9432 | 2016-08-17 13:49:19 +0100 | [diff] [blame] | 696 | if (gic_dist_security_disabled()) |
| 697 | gic_enable_redist(true); |
Sudeep Holla | 3708d52 | 2014-08-26 16:03:35 +0100 | [diff] [blame] | 698 | gic_cpu_sys_reg_init(); |
Sudeep Holla | ccd9432 | 2016-08-17 13:49:19 +0100 | [diff] [blame] | 699 | } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { |
Sudeep Holla | 3708d52 | 2014-08-26 16:03:35 +0100 | [diff] [blame] | 700 | gic_write_grpen1(0); |
| 701 | gic_enable_redist(false); |
| 702 | } |
| 703 | return NOTIFY_OK; |
| 704 | } |
| 705 | |
| 706 | static struct notifier_block gic_cpu_pm_notifier_block = { |
| 707 | .notifier_call = gic_cpu_pm_notifier, |
| 708 | }; |
| 709 | |
| 710 | static void gic_cpu_pm_init(void) |
| 711 | { |
| 712 | cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); |
| 713 | } |
| 714 | |
| 715 | #else |
| 716 | static inline void gic_cpu_pm_init(void) { } |
| 717 | #endif /* CONFIG_CPU_PM */ |
| 718 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 719 | static struct irq_chip gic_chip = { |
| 720 | .name = "GICv3", |
| 721 | .irq_mask = gic_mask_irq, |
| 722 | .irq_unmask = gic_unmask_irq, |
| 723 | .irq_eoi = gic_eoi_irq, |
| 724 | .irq_set_type = gic_set_type, |
| 725 | .irq_set_affinity = gic_set_affinity, |
Marc Zyngier | b594c6e | 2015-03-18 11:01:24 +0000 | [diff] [blame] | 726 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
| 727 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, |
Sudeep Holla | 55963c9 | 2015-06-05 11:59:57 +0100 | [diff] [blame] | 728 | .flags = IRQCHIP_SET_TYPE_MASKED, |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 729 | }; |
| 730 | |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 731 | static struct irq_chip gic_eoimode1_chip = { |
| 732 | .name = "GICv3", |
| 733 | .irq_mask = gic_eoimode1_mask_irq, |
| 734 | .irq_unmask = gic_unmask_irq, |
| 735 | .irq_eoi = gic_eoimode1_eoi_irq, |
| 736 | .irq_set_type = gic_set_type, |
| 737 | .irq_set_affinity = gic_set_affinity, |
| 738 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
| 739 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, |
Marc Zyngier | 530bf35 | 2015-08-26 17:00:43 +0100 | [diff] [blame] | 740 | .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 741 | .flags = IRQCHIP_SET_TYPE_MASKED, |
| 742 | }; |
| 743 | |
Marc Zyngier | da33f31 | 2014-11-24 14:35:18 +0000 | [diff] [blame] | 744 | #define GIC_ID_NR (1U << gic_data.rdists.id_bits) |
| 745 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 746 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
| 747 | irq_hw_number_t hw) |
| 748 | { |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 749 | struct irq_chip *chip = &gic_chip; |
| 750 | |
| 751 | if (static_key_true(&supports_deactivate)) |
| 752 | chip = &gic_eoimode1_chip; |
| 753 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 754 | /* SGIs are private to the core kernel */ |
| 755 | if (hw < 16) |
| 756 | return -EPERM; |
Marc Zyngier | da33f31 | 2014-11-24 14:35:18 +0000 | [diff] [blame] | 757 | /* Nothing here */ |
| 758 | if (hw >= gic_data.irq_nr && hw < 8192) |
| 759 | return -EPERM; |
| 760 | /* Off limits */ |
| 761 | if (hw >= GIC_ID_NR) |
| 762 | return -EPERM; |
| 763 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 764 | /* PPIs */ |
| 765 | if (hw < 32) { |
| 766 | irq_set_percpu_devid(irq); |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 767 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
Marc Zyngier | 443acc4 | 2014-11-24 14:35:09 +0000 | [diff] [blame] | 768 | handle_percpu_devid_irq, NULL, NULL); |
Rob Herring | d17cab4 | 2015-08-29 18:01:22 -0500 | [diff] [blame] | 769 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 770 | } |
| 771 | /* SPIs */ |
| 772 | if (hw >= 32 && hw < gic_data.irq_nr) { |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 773 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
Marc Zyngier | 443acc4 | 2014-11-24 14:35:09 +0000 | [diff] [blame] | 774 | handle_fasteoi_irq, NULL, NULL); |
Rob Herring | d17cab4 | 2015-08-29 18:01:22 -0500 | [diff] [blame] | 775 | irq_set_probe(irq); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 776 | } |
Marc Zyngier | da33f31 | 2014-11-24 14:35:18 +0000 | [diff] [blame] | 777 | /* LPIs */ |
| 778 | if (hw >= 8192 && hw < GIC_ID_NR) { |
| 779 | if (!gic_dist_supports_lpis()) |
| 780 | return -EPERM; |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 781 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
Marc Zyngier | da33f31 | 2014-11-24 14:35:18 +0000 | [diff] [blame] | 782 | handle_fasteoi_irq, NULL, NULL); |
Marc Zyngier | da33f31 | 2014-11-24 14:35:18 +0000 | [diff] [blame] | 783 | } |
| 784 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 785 | return 0; |
| 786 | } |
| 787 | |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 788 | static int gic_irq_domain_translate(struct irq_domain *d, |
| 789 | struct irq_fwspec *fwspec, |
| 790 | unsigned long *hwirq, |
| 791 | unsigned int *type) |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 792 | { |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 793 | if (is_of_node(fwspec->fwnode)) { |
| 794 | if (fwspec->param_count < 3) |
| 795 | return -EINVAL; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 796 | |
Marc Zyngier | db8c70e | 2015-10-14 12:27:16 +0100 | [diff] [blame] | 797 | switch (fwspec->param[0]) { |
| 798 | case 0: /* SPI */ |
| 799 | *hwirq = fwspec->param[1] + 32; |
| 800 | break; |
| 801 | case 1: /* PPI */ |
| 802 | *hwirq = fwspec->param[1] + 16; |
| 803 | break; |
| 804 | case GIC_IRQ_TYPE_LPI: /* LPI */ |
| 805 | *hwirq = fwspec->param[1]; |
| 806 | break; |
| 807 | default: |
| 808 | return -EINVAL; |
| 809 | } |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 810 | |
| 811 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; |
| 812 | return 0; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 813 | } |
| 814 | |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 815 | if (is_fwnode_irqchip(fwspec->fwnode)) { |
| 816 | if(fwspec->param_count != 2) |
| 817 | return -EINVAL; |
| 818 | |
| 819 | *hwirq = fwspec->param[0]; |
| 820 | *type = fwspec->param[1]; |
| 821 | return 0; |
| 822 | } |
| 823 | |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 824 | return -EINVAL; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 825 | } |
| 826 | |
Marc Zyngier | 443acc4 | 2014-11-24 14:35:09 +0000 | [diff] [blame] | 827 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
| 828 | unsigned int nr_irqs, void *arg) |
| 829 | { |
| 830 | int i, ret; |
| 831 | irq_hw_number_t hwirq; |
| 832 | unsigned int type = IRQ_TYPE_NONE; |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 833 | struct irq_fwspec *fwspec = arg; |
Marc Zyngier | 443acc4 | 2014-11-24 14:35:09 +0000 | [diff] [blame] | 834 | |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 835 | ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); |
Marc Zyngier | 443acc4 | 2014-11-24 14:35:09 +0000 | [diff] [blame] | 836 | if (ret) |
| 837 | return ret; |
| 838 | |
| 839 | for (i = 0; i < nr_irqs; i++) |
| 840 | gic_irq_domain_map(domain, virq + i, hwirq + i); |
| 841 | |
| 842 | return 0; |
| 843 | } |
| 844 | |
| 845 | static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, |
| 846 | unsigned int nr_irqs) |
| 847 | { |
| 848 | int i; |
| 849 | |
| 850 | for (i = 0; i < nr_irqs; i++) { |
| 851 | struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); |
| 852 | irq_set_handler(virq + i, NULL); |
| 853 | irq_domain_reset_irq_data(d); |
| 854 | } |
| 855 | } |
| 856 | |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 857 | static int gic_irq_domain_select(struct irq_domain *d, |
| 858 | struct irq_fwspec *fwspec, |
| 859 | enum irq_domain_bus_token bus_token) |
| 860 | { |
| 861 | /* Not for us */ |
| 862 | if (fwspec->fwnode != d->fwnode) |
| 863 | return 0; |
| 864 | |
| 865 | /* If this is not DT, then we have a single domain */ |
| 866 | if (!is_of_node(fwspec->fwnode)) |
| 867 | return 1; |
| 868 | |
| 869 | /* |
| 870 | * If this is a PPI and we have a 4th (non-null) parameter, |
| 871 | * then we need to match the partition domain. |
| 872 | */ |
| 873 | if (fwspec->param_count >= 4 && |
| 874 | fwspec->param[0] == 1 && fwspec->param[3] != 0) |
| 875 | return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); |
| 876 | |
| 877 | return d == gic_data.domain; |
| 878 | } |
| 879 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 880 | static const struct irq_domain_ops gic_irq_domain_ops = { |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 881 | .translate = gic_irq_domain_translate, |
Marc Zyngier | 443acc4 | 2014-11-24 14:35:09 +0000 | [diff] [blame] | 882 | .alloc = gic_irq_domain_alloc, |
| 883 | .free = gic_irq_domain_free, |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 884 | .select = gic_irq_domain_select, |
| 885 | }; |
| 886 | |
| 887 | static int partition_domain_translate(struct irq_domain *d, |
| 888 | struct irq_fwspec *fwspec, |
| 889 | unsigned long *hwirq, |
| 890 | unsigned int *type) |
| 891 | { |
| 892 | struct device_node *np; |
| 893 | int ret; |
| 894 | |
| 895 | np = of_find_node_by_phandle(fwspec->param[3]); |
| 896 | if (WARN_ON(!np)) |
| 897 | return -EINVAL; |
| 898 | |
| 899 | ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], |
| 900 | of_node_to_fwnode(np)); |
| 901 | if (ret < 0) |
| 902 | return ret; |
| 903 | |
| 904 | *hwirq = ret; |
| 905 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; |
| 906 | |
| 907 | return 0; |
| 908 | } |
| 909 | |
| 910 | static const struct irq_domain_ops partition_domain_ops = { |
| 911 | .translate = partition_domain_translate, |
| 912 | .select = gic_irq_domain_select, |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 913 | }; |
| 914 | |
Robert Richter | 6d4e11c | 2015-09-21 22:58:35 +0200 | [diff] [blame] | 915 | static void gicv3_enable_quirks(void) |
| 916 | { |
Jean-Philippe Brucker | 7936e91 | 2015-10-01 13:47:14 +0100 | [diff] [blame] | 917 | #ifdef CONFIG_ARM64 |
Robert Richter | 6d4e11c | 2015-09-21 22:58:35 +0200 | [diff] [blame] | 918 | if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154)) |
Robert Richter | 8ac2a17 | 2015-09-21 22:58:39 +0200 | [diff] [blame] | 919 | static_branch_enable(&is_cavium_thunderx); |
Jean-Philippe Brucker | 7936e91 | 2015-10-01 13:47:14 +0100 | [diff] [blame] | 920 | #endif |
Robert Richter | 6d4e11c | 2015-09-21 22:58:35 +0200 | [diff] [blame] | 921 | } |
| 922 | |
Tomasz Nowicki | db57d74 | 2016-01-19 14:11:14 +0100 | [diff] [blame] | 923 | static int __init gic_init_bases(void __iomem *dist_base, |
| 924 | struct redist_region *rdist_regs, |
| 925 | u32 nr_redist_regions, |
| 926 | u64 redist_stride, |
| 927 | struct fwnode_handle *handle) |
| 928 | { |
Tomasz Nowicki | db57d74 | 2016-01-19 14:11:14 +0100 | [diff] [blame] | 929 | u32 typer; |
| 930 | int gic_irqs; |
| 931 | int err; |
| 932 | |
| 933 | if (!is_hyp_mode_available()) |
| 934 | static_key_slow_dec(&supports_deactivate); |
| 935 | |
| 936 | if (static_key_true(&supports_deactivate)) |
| 937 | pr_info("GIC: Using split EOI/Deactivate mode\n"); |
| 938 | |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 939 | gic_data.fwnode = handle; |
Tomasz Nowicki | db57d74 | 2016-01-19 14:11:14 +0100 | [diff] [blame] | 940 | gic_data.dist_base = dist_base; |
| 941 | gic_data.redist_regions = rdist_regs; |
| 942 | gic_data.nr_redist_regions = nr_redist_regions; |
| 943 | gic_data.redist_stride = redist_stride; |
| 944 | |
| 945 | gicv3_enable_quirks(); |
| 946 | |
| 947 | /* |
| 948 | * Find out how many interrupts are supported. |
| 949 | * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) |
| 950 | */ |
| 951 | typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); |
| 952 | gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); |
| 953 | gic_irqs = GICD_TYPER_IRQS(typer); |
| 954 | if (gic_irqs > 1020) |
| 955 | gic_irqs = 1020; |
| 956 | gic_data.irq_nr = gic_irqs; |
| 957 | |
| 958 | gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, |
| 959 | &gic_data); |
| 960 | gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); |
| 961 | |
| 962 | if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { |
| 963 | err = -ENOMEM; |
| 964 | goto out_free; |
| 965 | } |
| 966 | |
| 967 | set_handle_irq(gic_handle_irq); |
| 968 | |
Tomasz Nowicki | db57d74 | 2016-01-19 14:11:14 +0100 | [diff] [blame] | 969 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() && |
Kyle Yan | 65be4a5 | 2016-10-31 15:05:00 -0700 | [diff] [blame] | 970 | !IS_ENABLED(CONFIG_ARM_GIC_V3_ACL)) |
Tomasz Nowicki | db40f0a | 2016-09-12 20:32:24 +0200 | [diff] [blame] | 971 | its_init(handle, &gic_data.rdists, gic_data.domain); |
Tomasz Nowicki | db57d74 | 2016-01-19 14:11:14 +0100 | [diff] [blame] | 972 | |
| 973 | gic_smp_init(); |
| 974 | gic_dist_init(); |
| 975 | gic_cpu_init(); |
| 976 | gic_cpu_pm_init(); |
| 977 | |
| 978 | return 0; |
| 979 | |
| 980 | out_free: |
| 981 | if (gic_data.domain) |
| 982 | irq_domain_remove(gic_data.domain); |
| 983 | free_percpu(gic_data.rdists.rdist); |
| 984 | return err; |
| 985 | } |
| 986 | |
| 987 | static int __init gic_validate_dist_version(void __iomem *dist_base) |
| 988 | { |
| 989 | u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; |
| 990 | |
| 991 | if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) |
| 992 | return -ENODEV; |
| 993 | |
| 994 | return 0; |
| 995 | } |
| 996 | |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 997 | static int get_cpu_number(struct device_node *dn) |
| 998 | { |
| 999 | const __be32 *cell; |
| 1000 | u64 hwid; |
| 1001 | int i; |
| 1002 | |
| 1003 | cell = of_get_property(dn, "reg", NULL); |
| 1004 | if (!cell) |
| 1005 | return -1; |
| 1006 | |
| 1007 | hwid = of_read_number(cell, of_n_addr_cells(dn)); |
| 1008 | |
| 1009 | /* |
| 1010 | * Non affinity bits must be set to 0 in the DT |
| 1011 | */ |
| 1012 | if (hwid & ~MPIDR_HWID_BITMASK) |
| 1013 | return -1; |
| 1014 | |
| 1015 | for (i = 0; i < num_possible_cpus(); i++) |
| 1016 | if (cpu_logical_map(i) == hwid) |
| 1017 | return i; |
| 1018 | |
| 1019 | return -1; |
| 1020 | } |
| 1021 | |
| 1022 | /* Create all possible partitions at boot time */ |
Linus Torvalds | 7beaa24 | 2016-05-19 11:27:09 -0700 | [diff] [blame] | 1023 | static void __init gic_populate_ppi_partitions(struct device_node *gic_node) |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 1024 | { |
| 1025 | struct device_node *parts_node, *child_part; |
| 1026 | int part_idx = 0, i; |
| 1027 | int nr_parts; |
| 1028 | struct partition_affinity *parts; |
| 1029 | |
| 1030 | parts_node = of_find_node_by_name(gic_node, "ppi-partitions"); |
| 1031 | if (!parts_node) |
| 1032 | return; |
| 1033 | |
| 1034 | nr_parts = of_get_child_count(parts_node); |
| 1035 | |
| 1036 | if (!nr_parts) |
| 1037 | return; |
| 1038 | |
| 1039 | parts = kzalloc(sizeof(*parts) * nr_parts, GFP_KERNEL); |
| 1040 | if (WARN_ON(!parts)) |
| 1041 | return; |
| 1042 | |
| 1043 | for_each_child_of_node(parts_node, child_part) { |
| 1044 | struct partition_affinity *part; |
| 1045 | int n; |
| 1046 | |
| 1047 | part = &parts[part_idx]; |
| 1048 | |
| 1049 | part->partition_id = of_node_to_fwnode(child_part); |
| 1050 | |
| 1051 | pr_info("GIC: PPI partition %s[%d] { ", |
| 1052 | child_part->name, part_idx); |
| 1053 | |
| 1054 | n = of_property_count_elems_of_size(child_part, "affinity", |
| 1055 | sizeof(u32)); |
| 1056 | WARN_ON(n <= 0); |
| 1057 | |
| 1058 | for (i = 0; i < n; i++) { |
| 1059 | int err, cpu; |
| 1060 | u32 cpu_phandle; |
| 1061 | struct device_node *cpu_node; |
| 1062 | |
| 1063 | err = of_property_read_u32_index(child_part, "affinity", |
| 1064 | i, &cpu_phandle); |
| 1065 | if (WARN_ON(err)) |
| 1066 | continue; |
| 1067 | |
| 1068 | cpu_node = of_find_node_by_phandle(cpu_phandle); |
| 1069 | if (WARN_ON(!cpu_node)) |
| 1070 | continue; |
| 1071 | |
| 1072 | cpu = get_cpu_number(cpu_node); |
| 1073 | if (WARN_ON(cpu == -1)) |
| 1074 | continue; |
| 1075 | |
| 1076 | pr_cont("%s[%d] ", cpu_node->full_name, cpu); |
| 1077 | |
| 1078 | cpumask_set_cpu(cpu, &part->mask); |
| 1079 | } |
| 1080 | |
| 1081 | pr_cont("}\n"); |
| 1082 | part_idx++; |
| 1083 | } |
| 1084 | |
| 1085 | for (i = 0; i < 16; i++) { |
| 1086 | unsigned int irq; |
| 1087 | struct partition_desc *desc; |
| 1088 | struct irq_fwspec ppi_fwspec = { |
| 1089 | .fwnode = gic_data.fwnode, |
| 1090 | .param_count = 3, |
| 1091 | .param = { |
| 1092 | [0] = 1, |
| 1093 | [1] = i, |
| 1094 | [2] = IRQ_TYPE_NONE, |
| 1095 | }, |
| 1096 | }; |
| 1097 | |
| 1098 | irq = irq_create_fwspec_mapping(&ppi_fwspec); |
| 1099 | if (WARN_ON(!irq)) |
| 1100 | continue; |
| 1101 | desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, |
| 1102 | irq, &partition_domain_ops); |
| 1103 | if (WARN_ON(!desc)) |
| 1104 | continue; |
| 1105 | |
| 1106 | gic_data.ppi_descs[i] = desc; |
| 1107 | } |
| 1108 | } |
| 1109 | |
Julien Grall | 1839e57 | 2016-04-11 16:32:57 +0100 | [diff] [blame] | 1110 | static void __init gic_of_setup_kvm_info(struct device_node *node) |
| 1111 | { |
| 1112 | int ret; |
| 1113 | struct resource r; |
| 1114 | u32 gicv_idx; |
| 1115 | |
| 1116 | gic_v3_kvm_info.type = GIC_V3; |
| 1117 | |
| 1118 | gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); |
| 1119 | if (!gic_v3_kvm_info.maint_irq) |
| 1120 | return; |
| 1121 | |
| 1122 | if (of_property_read_u32(node, "#redistributor-regions", |
| 1123 | &gicv_idx)) |
| 1124 | gicv_idx = 1; |
| 1125 | |
| 1126 | gicv_idx += 3; /* Also skip GICD, GICC, GICH */ |
| 1127 | ret = of_address_to_resource(node, gicv_idx, &r); |
| 1128 | if (!ret) |
| 1129 | gic_v3_kvm_info.vcpu = r; |
| 1130 | |
| 1131 | gic_set_kvm_info(&gic_v3_kvm_info); |
| 1132 | } |
| 1133 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1134 | static int __init gic_of_init(struct device_node *node, struct device_node *parent) |
| 1135 | { |
| 1136 | void __iomem *dist_base; |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 1137 | struct redist_region *rdist_regs; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1138 | u64 redist_stride; |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 1139 | u32 nr_redist_regions; |
Tomasz Nowicki | db57d74 | 2016-01-19 14:11:14 +0100 | [diff] [blame] | 1140 | int err, i; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1141 | |
| 1142 | dist_base = of_iomap(node, 0); |
| 1143 | if (!dist_base) { |
| 1144 | pr_err("%s: unable to map gic dist registers\n", |
| 1145 | node->full_name); |
| 1146 | return -ENXIO; |
| 1147 | } |
| 1148 | |
Tomasz Nowicki | db57d74 | 2016-01-19 14:11:14 +0100 | [diff] [blame] | 1149 | err = gic_validate_dist_version(dist_base); |
| 1150 | if (err) { |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1151 | pr_err("%s: no distributor detected, giving up\n", |
| 1152 | node->full_name); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1153 | goto out_unmap_dist; |
| 1154 | } |
| 1155 | |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 1156 | if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) |
| 1157 | nr_redist_regions = 1; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1158 | |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 1159 | rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); |
| 1160 | if (!rdist_regs) { |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1161 | err = -ENOMEM; |
| 1162 | goto out_unmap_dist; |
| 1163 | } |
| 1164 | |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 1165 | for (i = 0; i < nr_redist_regions; i++) { |
| 1166 | struct resource res; |
| 1167 | int ret; |
| 1168 | |
| 1169 | ret = of_address_to_resource(node, 1 + i, &res); |
| 1170 | rdist_regs[i].redist_base = of_iomap(node, 1 + i); |
| 1171 | if (ret || !rdist_regs[i].redist_base) { |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1172 | pr_err("%s: couldn't map region %d\n", |
| 1173 | node->full_name, i); |
| 1174 | err = -ENODEV; |
| 1175 | goto out_unmap_rdist; |
| 1176 | } |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 1177 | rdist_regs[i].phys_base = res.start; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1178 | } |
| 1179 | |
| 1180 | if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) |
| 1181 | redist_stride = 0; |
| 1182 | |
Tomasz Nowicki | db57d74 | 2016-01-19 14:11:14 +0100 | [diff] [blame] | 1183 | err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, |
| 1184 | redist_stride, &node->fwnode); |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 1185 | if (err) |
| 1186 | goto out_unmap_rdist; |
| 1187 | |
| 1188 | gic_populate_ppi_partitions(node); |
Linus Torvalds | 7beaa24 | 2016-05-19 11:27:09 -0700 | [diff] [blame] | 1189 | gic_of_setup_kvm_info(node); |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 1190 | return 0; |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 1191 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1192 | out_unmap_rdist: |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 1193 | for (i = 0; i < nr_redist_regions; i++) |
| 1194 | if (rdist_regs[i].redist_base) |
| 1195 | iounmap(rdist_regs[i].redist_base); |
| 1196 | kfree(rdist_regs); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1197 | out_unmap_dist: |
| 1198 | iounmap(dist_base); |
| 1199 | return err; |
| 1200 | } |
| 1201 | |
| 1202 | IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1203 | |
| 1204 | #ifdef CONFIG_ACPI |
Julien Grall | 611f039 | 2016-04-11 16:32:56 +0100 | [diff] [blame] | 1205 | static struct |
| 1206 | { |
| 1207 | void __iomem *dist_base; |
| 1208 | struct redist_region *redist_regs; |
| 1209 | u32 nr_redist_regions; |
| 1210 | bool single_redist; |
Julien Grall | 1839e57 | 2016-04-11 16:32:57 +0100 | [diff] [blame] | 1211 | u32 maint_irq; |
| 1212 | int maint_irq_mode; |
| 1213 | phys_addr_t vcpu_base; |
Julien Grall | 611f039 | 2016-04-11 16:32:56 +0100 | [diff] [blame] | 1214 | } acpi_data __initdata; |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 1215 | |
| 1216 | static void __init |
| 1217 | gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) |
| 1218 | { |
| 1219 | static int count = 0; |
| 1220 | |
Julien Grall | 611f039 | 2016-04-11 16:32:56 +0100 | [diff] [blame] | 1221 | acpi_data.redist_regs[count].phys_base = phys_base; |
| 1222 | acpi_data.redist_regs[count].redist_base = redist_base; |
| 1223 | acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 1224 | count++; |
| 1225 | } |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1226 | |
| 1227 | static int __init |
| 1228 | gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, |
| 1229 | const unsigned long end) |
| 1230 | { |
| 1231 | struct acpi_madt_generic_redistributor *redist = |
| 1232 | (struct acpi_madt_generic_redistributor *)header; |
| 1233 | void __iomem *redist_base; |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1234 | |
| 1235 | redist_base = ioremap(redist->base_address, redist->length); |
| 1236 | if (!redist_base) { |
| 1237 | pr_err("Couldn't map GICR region @%llx\n", redist->base_address); |
| 1238 | return -ENOMEM; |
| 1239 | } |
| 1240 | |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 1241 | gic_acpi_register_redist(redist->base_address, redist_base); |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1242 | return 0; |
| 1243 | } |
| 1244 | |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 1245 | static int __init |
| 1246 | gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, |
| 1247 | const unsigned long end) |
| 1248 | { |
| 1249 | struct acpi_madt_generic_interrupt *gicc = |
| 1250 | (struct acpi_madt_generic_interrupt *)header; |
Julien Grall | 611f039 | 2016-04-11 16:32:56 +0100 | [diff] [blame] | 1251 | u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 1252 | u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; |
| 1253 | void __iomem *redist_base; |
| 1254 | |
| 1255 | redist_base = ioremap(gicc->gicr_base_address, size); |
| 1256 | if (!redist_base) |
| 1257 | return -ENOMEM; |
| 1258 | |
| 1259 | gic_acpi_register_redist(gicc->gicr_base_address, redist_base); |
| 1260 | return 0; |
| 1261 | } |
| 1262 | |
| 1263 | static int __init gic_acpi_collect_gicr_base(void) |
| 1264 | { |
| 1265 | acpi_tbl_entry_handler redist_parser; |
| 1266 | enum acpi_madt_type type; |
| 1267 | |
Julien Grall | 611f039 | 2016-04-11 16:32:56 +0100 | [diff] [blame] | 1268 | if (acpi_data.single_redist) { |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 1269 | type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; |
| 1270 | redist_parser = gic_acpi_parse_madt_gicc; |
| 1271 | } else { |
| 1272 | type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; |
| 1273 | redist_parser = gic_acpi_parse_madt_redist; |
| 1274 | } |
| 1275 | |
| 1276 | /* Collect redistributor base addresses in GICR entries */ |
| 1277 | if (acpi_table_parse_madt(type, redist_parser, 0) > 0) |
| 1278 | return 0; |
| 1279 | |
| 1280 | pr_info("No valid GICR entries exist\n"); |
| 1281 | return -ENODEV; |
| 1282 | } |
| 1283 | |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1284 | static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, |
| 1285 | const unsigned long end) |
| 1286 | { |
| 1287 | /* Subtable presence means that redist exists, that's it */ |
| 1288 | return 0; |
| 1289 | } |
| 1290 | |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 1291 | static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, |
| 1292 | const unsigned long end) |
| 1293 | { |
| 1294 | struct acpi_madt_generic_interrupt *gicc = |
| 1295 | (struct acpi_madt_generic_interrupt *)header; |
| 1296 | |
| 1297 | /* |
| 1298 | * If GICC is enabled and has valid gicr base address, then it means |
| 1299 | * GICR base is presented via GICC |
| 1300 | */ |
| 1301 | if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) |
| 1302 | return 0; |
| 1303 | |
| 1304 | return -ENODEV; |
| 1305 | } |
| 1306 | |
| 1307 | static int __init gic_acpi_count_gicr_regions(void) |
| 1308 | { |
| 1309 | int count; |
| 1310 | |
| 1311 | /* |
| 1312 | * Count how many redistributor regions we have. It is not allowed |
| 1313 | * to mix redistributor description, GICR and GICC subtables have to be |
| 1314 | * mutually exclusive. |
| 1315 | */ |
| 1316 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, |
| 1317 | gic_acpi_match_gicr, 0); |
| 1318 | if (count > 0) { |
Julien Grall | 611f039 | 2016-04-11 16:32:56 +0100 | [diff] [blame] | 1319 | acpi_data.single_redist = false; |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 1320 | return count; |
| 1321 | } |
| 1322 | |
| 1323 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, |
| 1324 | gic_acpi_match_gicc, 0); |
| 1325 | if (count > 0) |
Julien Grall | 611f039 | 2016-04-11 16:32:56 +0100 | [diff] [blame] | 1326 | acpi_data.single_redist = true; |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 1327 | |
| 1328 | return count; |
| 1329 | } |
| 1330 | |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1331 | static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, |
| 1332 | struct acpi_probe_entry *ape) |
| 1333 | { |
| 1334 | struct acpi_madt_generic_distributor *dist; |
| 1335 | int count; |
| 1336 | |
| 1337 | dist = (struct acpi_madt_generic_distributor *)header; |
| 1338 | if (dist->version != ape->driver_data) |
| 1339 | return false; |
| 1340 | |
| 1341 | /* We need to do that exercise anyway, the sooner the better */ |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 1342 | count = gic_acpi_count_gicr_regions(); |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1343 | if (count <= 0) |
| 1344 | return false; |
| 1345 | |
Julien Grall | 611f039 | 2016-04-11 16:32:56 +0100 | [diff] [blame] | 1346 | acpi_data.nr_redist_regions = count; |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1347 | return true; |
| 1348 | } |
| 1349 | |
Julien Grall | 1839e57 | 2016-04-11 16:32:57 +0100 | [diff] [blame] | 1350 | static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header, |
| 1351 | const unsigned long end) |
| 1352 | { |
| 1353 | struct acpi_madt_generic_interrupt *gicc = |
| 1354 | (struct acpi_madt_generic_interrupt *)header; |
| 1355 | int maint_irq_mode; |
| 1356 | static int first_madt = true; |
| 1357 | |
| 1358 | /* Skip unusable CPUs */ |
| 1359 | if (!(gicc->flags & ACPI_MADT_ENABLED)) |
| 1360 | return 0; |
| 1361 | |
| 1362 | maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? |
| 1363 | ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; |
| 1364 | |
| 1365 | if (first_madt) { |
| 1366 | first_madt = false; |
| 1367 | |
| 1368 | acpi_data.maint_irq = gicc->vgic_interrupt; |
| 1369 | acpi_data.maint_irq_mode = maint_irq_mode; |
| 1370 | acpi_data.vcpu_base = gicc->gicv_base_address; |
| 1371 | |
| 1372 | return 0; |
| 1373 | } |
| 1374 | |
| 1375 | /* |
| 1376 | * The maintenance interrupt and GICV should be the same for every CPU |
| 1377 | */ |
| 1378 | if ((acpi_data.maint_irq != gicc->vgic_interrupt) || |
| 1379 | (acpi_data.maint_irq_mode != maint_irq_mode) || |
| 1380 | (acpi_data.vcpu_base != gicc->gicv_base_address)) |
| 1381 | return -EINVAL; |
| 1382 | |
| 1383 | return 0; |
| 1384 | } |
| 1385 | |
| 1386 | static bool __init gic_acpi_collect_virt_info(void) |
| 1387 | { |
| 1388 | int count; |
| 1389 | |
| 1390 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, |
| 1391 | gic_acpi_parse_virt_madt_gicc, 0); |
| 1392 | |
| 1393 | return (count > 0); |
| 1394 | } |
| 1395 | |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1396 | #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) |
Julien Grall | 1839e57 | 2016-04-11 16:32:57 +0100 | [diff] [blame] | 1397 | #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) |
| 1398 | #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) |
| 1399 | |
| 1400 | static void __init gic_acpi_setup_kvm_info(void) |
| 1401 | { |
| 1402 | int irq; |
| 1403 | |
| 1404 | if (!gic_acpi_collect_virt_info()) { |
| 1405 | pr_warn("Unable to get hardware information used for virtualization\n"); |
| 1406 | return; |
| 1407 | } |
| 1408 | |
| 1409 | gic_v3_kvm_info.type = GIC_V3; |
| 1410 | |
| 1411 | irq = acpi_register_gsi(NULL, acpi_data.maint_irq, |
| 1412 | acpi_data.maint_irq_mode, |
| 1413 | ACPI_ACTIVE_HIGH); |
| 1414 | if (irq <= 0) |
| 1415 | return; |
| 1416 | |
| 1417 | gic_v3_kvm_info.maint_irq = irq; |
| 1418 | |
| 1419 | if (acpi_data.vcpu_base) { |
| 1420 | struct resource *vcpu = &gic_v3_kvm_info.vcpu; |
| 1421 | |
| 1422 | vcpu->flags = IORESOURCE_MEM; |
| 1423 | vcpu->start = acpi_data.vcpu_base; |
| 1424 | vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; |
| 1425 | } |
| 1426 | |
| 1427 | gic_set_kvm_info(&gic_v3_kvm_info); |
| 1428 | } |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1429 | |
| 1430 | static int __init |
| 1431 | gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) |
| 1432 | { |
| 1433 | struct acpi_madt_generic_distributor *dist; |
| 1434 | struct fwnode_handle *domain_handle; |
Julien Grall | 611f039 | 2016-04-11 16:32:56 +0100 | [diff] [blame] | 1435 | size_t size; |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 1436 | int i, err; |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1437 | |
| 1438 | /* Get distributor base address */ |
| 1439 | dist = (struct acpi_madt_generic_distributor *)header; |
Julien Grall | 611f039 | 2016-04-11 16:32:56 +0100 | [diff] [blame] | 1440 | acpi_data.dist_base = ioremap(dist->base_address, |
| 1441 | ACPI_GICV3_DIST_MEM_SIZE); |
| 1442 | if (!acpi_data.dist_base) { |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1443 | pr_err("Unable to map GICD registers\n"); |
| 1444 | return -ENOMEM; |
| 1445 | } |
| 1446 | |
Julien Grall | 611f039 | 2016-04-11 16:32:56 +0100 | [diff] [blame] | 1447 | err = gic_validate_dist_version(acpi_data.dist_base); |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1448 | if (err) { |
Julien Grall | 611f039 | 2016-04-11 16:32:56 +0100 | [diff] [blame] | 1449 | pr_err("No distributor detected at @%p, giving up", |
| 1450 | acpi_data.dist_base); |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1451 | goto out_dist_unmap; |
| 1452 | } |
| 1453 | |
Julien Grall | 611f039 | 2016-04-11 16:32:56 +0100 | [diff] [blame] | 1454 | size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; |
| 1455 | acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); |
| 1456 | if (!acpi_data.redist_regs) { |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1457 | err = -ENOMEM; |
| 1458 | goto out_dist_unmap; |
| 1459 | } |
| 1460 | |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 1461 | err = gic_acpi_collect_gicr_base(); |
| 1462 | if (err) |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1463 | goto out_redist_unmap; |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1464 | |
Julien Grall | 611f039 | 2016-04-11 16:32:56 +0100 | [diff] [blame] | 1465 | domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base); |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1466 | if (!domain_handle) { |
| 1467 | err = -ENOMEM; |
| 1468 | goto out_redist_unmap; |
| 1469 | } |
| 1470 | |
Julien Grall | 611f039 | 2016-04-11 16:32:56 +0100 | [diff] [blame] | 1471 | err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, |
| 1472 | acpi_data.nr_redist_regions, 0, domain_handle); |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1473 | if (err) |
| 1474 | goto out_fwhandle_free; |
| 1475 | |
| 1476 | acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); |
Julien Grall | 1839e57 | 2016-04-11 16:32:57 +0100 | [diff] [blame] | 1477 | gic_acpi_setup_kvm_info(); |
| 1478 | |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1479 | return 0; |
| 1480 | |
| 1481 | out_fwhandle_free: |
| 1482 | irq_domain_free_fwnode(domain_handle); |
| 1483 | out_redist_unmap: |
Julien Grall | 611f039 | 2016-04-11 16:32:56 +0100 | [diff] [blame] | 1484 | for (i = 0; i < acpi_data.nr_redist_regions; i++) |
| 1485 | if (acpi_data.redist_regs[i].redist_base) |
| 1486 | iounmap(acpi_data.redist_regs[i].redist_base); |
| 1487 | kfree(acpi_data.redist_regs); |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1488 | out_dist_unmap: |
Julien Grall | 611f039 | 2016-04-11 16:32:56 +0100 | [diff] [blame] | 1489 | iounmap(acpi_data.dist_base); |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1490 | return err; |
| 1491 | } |
| 1492 | IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, |
| 1493 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, |
| 1494 | gic_acpi_init); |
| 1495 | IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, |
| 1496 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, |
| 1497 | gic_acpi_init); |
| 1498 | IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, |
| 1499 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, |
| 1500 | gic_acpi_init); |
| 1501 | #endif |