Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1 | /**************************************************************************** |
| 2 | * Driver for Solarflare Solarstorm network controllers and boards |
| 3 | * Copyright 2005-2006 Fen Systems Ltd. |
| 4 | * Copyright 2006-2008 Solarflare Communications Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published |
| 8 | * by the Free Software Foundation, incorporated herein by reference. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/bitops.h> |
| 12 | #include <linux/delay.h> |
| 13 | #include <linux/pci.h> |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/seq_file.h> |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 16 | #include <linux/i2c.h> |
| 17 | #include <linux/i2c-algo-bit.h> |
Ben Hutchings | f31a45d | 2008-12-12 21:43:33 -0800 | [diff] [blame] | 18 | #include <linux/mii.h> |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 19 | #include "net_driver.h" |
| 20 | #include "bitfield.h" |
| 21 | #include "efx.h" |
| 22 | #include "mac.h" |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 23 | #include "spi.h" |
| 24 | #include "falcon.h" |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 25 | #include "regs.h" |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 26 | #include "io.h" |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 27 | #include "mdio_10g.h" |
| 28 | #include "phy.h" |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 29 | #include "workarounds.h" |
| 30 | |
| 31 | /* Falcon hardware control. |
| 32 | * Falcon is the internal codename for the SFC4000 controller that is |
| 33 | * present in SFE400X evaluation boards |
| 34 | */ |
| 35 | |
| 36 | /** |
| 37 | * struct falcon_nic_data - Falcon NIC state |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 38 | * @pci_dev2: The secondary PCI device if present |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 39 | * @i2c_data: Operations and state for I2C bit-bashing algorithm |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 40 | */ |
| 41 | struct falcon_nic_data { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 42 | struct pci_dev *pci_dev2; |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 43 | struct i2c_algo_bit_data i2c_data; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 44 | }; |
| 45 | |
| 46 | /************************************************************************** |
| 47 | * |
| 48 | * Configurable values |
| 49 | * |
| 50 | ************************************************************************** |
| 51 | */ |
| 52 | |
| 53 | static int disable_dma_stats; |
| 54 | |
| 55 | /* This is set to 16 for a good reason. In summary, if larger than |
| 56 | * 16, the descriptor cache holds more than a default socket |
| 57 | * buffer's worth of packets (for UDP we can only have at most one |
| 58 | * socket buffer's worth outstanding). This combined with the fact |
| 59 | * that we only get 1 TX event per descriptor cache means the NIC |
| 60 | * goes idle. |
| 61 | */ |
| 62 | #define TX_DC_ENTRIES 16 |
| 63 | #define TX_DC_ENTRIES_ORDER 0 |
| 64 | #define TX_DC_BASE 0x130000 |
| 65 | |
| 66 | #define RX_DC_ENTRIES 64 |
| 67 | #define RX_DC_ENTRIES_ORDER 2 |
| 68 | #define RX_DC_BASE 0x100000 |
| 69 | |
Ben Hutchings | 2f7f573 | 2008-12-12 21:34:25 -0800 | [diff] [blame] | 70 | static const unsigned int |
| 71 | /* "Large" EEPROM device: Atmel AT25640 or similar |
| 72 | * 8 KB, 16-bit address, 32 B write block */ |
| 73 | large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN) |
| 74 | | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN) |
| 75 | | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)), |
| 76 | /* Default flash device: Atmel AT25F1024 |
| 77 | * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */ |
| 78 | default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN) |
| 79 | | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN) |
| 80 | | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN) |
| 81 | | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN) |
| 82 | | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)); |
| 83 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 84 | /* RX FIFO XOFF watermark |
| 85 | * |
| 86 | * When the amount of the RX FIFO increases used increases past this |
| 87 | * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A) |
| 88 | * This also has an effect on RX/TX arbitration |
| 89 | */ |
| 90 | static int rx_xoff_thresh_bytes = -1; |
| 91 | module_param(rx_xoff_thresh_bytes, int, 0644); |
| 92 | MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold"); |
| 93 | |
| 94 | /* RX FIFO XON watermark |
| 95 | * |
| 96 | * When the amount of the RX FIFO used decreases below this |
| 97 | * watermark send XON. Only used if TX flow control is enabled (ethtool -A) |
| 98 | * This also has an effect on RX/TX arbitration |
| 99 | */ |
| 100 | static int rx_xon_thresh_bytes = -1; |
| 101 | module_param(rx_xon_thresh_bytes, int, 0644); |
| 102 | MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold"); |
| 103 | |
Ben Hutchings | 2c3c3d0 | 2009-03-04 10:01:57 +0000 | [diff] [blame] | 104 | /* If FALCON_MAX_INT_ERRORS internal errors occur within |
| 105 | * FALCON_INT_ERROR_EXPIRE seconds, we consider the NIC broken and |
| 106 | * disable it. |
| 107 | */ |
| 108 | #define FALCON_INT_ERROR_EXPIRE 3600 |
| 109 | #define FALCON_MAX_INT_ERRORS 5 |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 110 | |
Ben Hutchings | 6bc5d3a | 2008-09-01 12:49:37 +0100 | [diff] [blame] | 111 | /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times |
| 112 | */ |
| 113 | #define FALCON_FLUSH_INTERVAL 10 |
| 114 | #define FALCON_FLUSH_POLL_COUNT 100 |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 115 | |
| 116 | /************************************************************************** |
| 117 | * |
| 118 | * Falcon constants |
| 119 | * |
| 120 | ************************************************************************** |
| 121 | */ |
| 122 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 123 | /* Size and alignment of special buffers (4KB) */ |
| 124 | #define FALCON_BUF_SIZE 4096 |
| 125 | |
| 126 | /* Dummy SRAM size code */ |
| 127 | #define SRM_NB_BSZ_ONCHIP_ONLY (-1) |
| 128 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 129 | #define FALCON_IS_DUAL_FUNC(efx) \ |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 130 | (falcon_rev(efx) < FALCON_REV_B0) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 131 | |
| 132 | /************************************************************************** |
| 133 | * |
| 134 | * Falcon hardware access |
| 135 | * |
| 136 | **************************************************************************/ |
| 137 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 138 | static inline void falcon_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value, |
| 139 | unsigned int index) |
| 140 | { |
| 141 | efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base, |
| 142 | value, index); |
| 143 | } |
| 144 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 145 | /* Read the current event from the event queue */ |
| 146 | static inline efx_qword_t *falcon_event(struct efx_channel *channel, |
| 147 | unsigned int index) |
| 148 | { |
| 149 | return (((efx_qword_t *) (channel->eventq.addr)) + index); |
| 150 | } |
| 151 | |
| 152 | /* See if an event is present |
| 153 | * |
| 154 | * We check both the high and low dword of the event for all ones. We |
| 155 | * wrote all ones when we cleared the event, and no valid event can |
| 156 | * have all ones in either its high or low dwords. This approach is |
| 157 | * robust against reordering. |
| 158 | * |
| 159 | * Note that using a single 64-bit comparison is incorrect; even |
| 160 | * though the CPU read will be atomic, the DMA write may not be. |
| 161 | */ |
| 162 | static inline int falcon_event_present(efx_qword_t *event) |
| 163 | { |
| 164 | return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) | |
| 165 | EFX_DWORD_IS_ALL_ONES(event->dword[1]))); |
| 166 | } |
| 167 | |
| 168 | /************************************************************************** |
| 169 | * |
| 170 | * I2C bus - this is a bit-bashing interface using GPIO pins |
| 171 | * Note that it uses the output enables to tristate the outputs |
| 172 | * SDA is the data pin and SCL is the clock |
| 173 | * |
| 174 | ************************************************************************** |
| 175 | */ |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 176 | static void falcon_setsda(void *data, int state) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 177 | { |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 178 | struct efx_nic *efx = (struct efx_nic *)data; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 179 | efx_oword_t reg; |
| 180 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 181 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 182 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 183 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 184 | } |
| 185 | |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 186 | static void falcon_setscl(void *data, int state) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 187 | { |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 188 | struct efx_nic *efx = (struct efx_nic *)data; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 189 | efx_oword_t reg; |
| 190 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 191 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 192 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 193 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 194 | } |
| 195 | |
| 196 | static int falcon_getsda(void *data) |
| 197 | { |
| 198 | struct efx_nic *efx = (struct efx_nic *)data; |
| 199 | efx_oword_t reg; |
| 200 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 201 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 202 | return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 203 | } |
| 204 | |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 205 | static int falcon_getscl(void *data) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 206 | { |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 207 | struct efx_nic *efx = (struct efx_nic *)data; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 208 | efx_oword_t reg; |
| 209 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 210 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 211 | return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 212 | } |
| 213 | |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 214 | static struct i2c_algo_bit_data falcon_i2c_bit_operations = { |
| 215 | .setsda = falcon_setsda, |
| 216 | .setscl = falcon_setscl, |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 217 | .getsda = falcon_getsda, |
| 218 | .getscl = falcon_getscl, |
Ben Hutchings | 62c7832 | 2008-05-30 22:27:46 +0100 | [diff] [blame] | 219 | .udelay = 5, |
Ben Hutchings | 9dadae6 | 2008-07-18 18:59:12 +0100 | [diff] [blame] | 220 | /* Wait up to 50 ms for slave to let us pull SCL high */ |
| 221 | .timeout = DIV_ROUND_UP(HZ, 20), |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 222 | }; |
| 223 | |
| 224 | /************************************************************************** |
| 225 | * |
| 226 | * Falcon special buffer handling |
| 227 | * Special buffers are used for event queues and the TX and RX |
| 228 | * descriptor rings. |
| 229 | * |
| 230 | *************************************************************************/ |
| 231 | |
| 232 | /* |
| 233 | * Initialise a Falcon special buffer |
| 234 | * |
| 235 | * This will define a buffer (previously allocated via |
| 236 | * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing |
| 237 | * it to be used for event queues, descriptor rings etc. |
| 238 | */ |
Ben Hutchings | bc3c90a | 2008-09-01 12:48:46 +0100 | [diff] [blame] | 239 | static void |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 240 | falcon_init_special_buffer(struct efx_nic *efx, |
| 241 | struct efx_special_buffer *buffer) |
| 242 | { |
| 243 | efx_qword_t buf_desc; |
| 244 | int index; |
| 245 | dma_addr_t dma_addr; |
| 246 | int i; |
| 247 | |
| 248 | EFX_BUG_ON_PARANOID(!buffer->addr); |
| 249 | |
| 250 | /* Write buffer descriptors to NIC */ |
| 251 | for (i = 0; i < buffer->entries; i++) { |
| 252 | index = buffer->index + i; |
| 253 | dma_addr = buffer->dma_addr + (i * 4096); |
| 254 | EFX_LOG(efx, "mapping special buffer %d at %llx\n", |
| 255 | index, (unsigned long long)dma_addr); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 256 | EFX_POPULATE_QWORD_3(buf_desc, |
| 257 | FRF_AZ_BUF_ADR_REGION, 0, |
| 258 | FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12, |
| 259 | FRF_AZ_BUF_OWNER_ID_FBUF, 0); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 260 | falcon_write_buf_tbl(efx, &buf_desc, index); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 261 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 262 | } |
| 263 | |
| 264 | /* Unmaps a buffer from Falcon and clears the buffer table entries */ |
| 265 | static void |
| 266 | falcon_fini_special_buffer(struct efx_nic *efx, |
| 267 | struct efx_special_buffer *buffer) |
| 268 | { |
| 269 | efx_oword_t buf_tbl_upd; |
| 270 | unsigned int start = buffer->index; |
| 271 | unsigned int end = (buffer->index + buffer->entries - 1); |
| 272 | |
| 273 | if (!buffer->entries) |
| 274 | return; |
| 275 | |
| 276 | EFX_LOG(efx, "unmapping special buffers %d-%d\n", |
| 277 | buffer->index, buffer->index + buffer->entries - 1); |
| 278 | |
| 279 | EFX_POPULATE_OWORD_4(buf_tbl_upd, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 280 | FRF_AZ_BUF_UPD_CMD, 0, |
| 281 | FRF_AZ_BUF_CLR_CMD, 1, |
| 282 | FRF_AZ_BUF_CLR_END_ID, end, |
| 283 | FRF_AZ_BUF_CLR_START_ID, start); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 284 | efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 285 | } |
| 286 | |
| 287 | /* |
| 288 | * Allocate a new Falcon special buffer |
| 289 | * |
| 290 | * This allocates memory for a new buffer, clears it and allocates a |
| 291 | * new buffer ID range. It does not write into Falcon's buffer table. |
| 292 | * |
| 293 | * This call will allocate 4KB buffers, since Falcon can't use 8KB |
| 294 | * buffers for event queues and descriptor rings. |
| 295 | */ |
| 296 | static int falcon_alloc_special_buffer(struct efx_nic *efx, |
| 297 | struct efx_special_buffer *buffer, |
| 298 | unsigned int len) |
| 299 | { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 300 | len = ALIGN(len, FALCON_BUF_SIZE); |
| 301 | |
| 302 | buffer->addr = pci_alloc_consistent(efx->pci_dev, len, |
| 303 | &buffer->dma_addr); |
| 304 | if (!buffer->addr) |
| 305 | return -ENOMEM; |
| 306 | buffer->len = len; |
| 307 | buffer->entries = len / FALCON_BUF_SIZE; |
| 308 | BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1)); |
| 309 | |
| 310 | /* All zeros is a potentially valid event so memset to 0xff */ |
| 311 | memset(buffer->addr, 0xff, len); |
| 312 | |
| 313 | /* Select new buffer ID */ |
Ben Hutchings | 0484e0d | 2009-10-23 08:32:04 +0000 | [diff] [blame] | 314 | buffer->index = efx->next_buffer_table; |
| 315 | efx->next_buffer_table += buffer->entries; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 316 | |
| 317 | EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x " |
Jaswinder Singh Rajput | 9c8976a | 2009-02-11 23:49:52 +0530 | [diff] [blame] | 318 | "(virt %p phys %llx)\n", buffer->index, |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 319 | buffer->index + buffer->entries - 1, |
Jaswinder Singh Rajput | 9c8976a | 2009-02-11 23:49:52 +0530 | [diff] [blame] | 320 | (u64)buffer->dma_addr, len, |
| 321 | buffer->addr, (u64)virt_to_phys(buffer->addr)); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 322 | |
| 323 | return 0; |
| 324 | } |
| 325 | |
| 326 | static void falcon_free_special_buffer(struct efx_nic *efx, |
| 327 | struct efx_special_buffer *buffer) |
| 328 | { |
| 329 | if (!buffer->addr) |
| 330 | return; |
| 331 | |
| 332 | EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x " |
Jaswinder Singh Rajput | 9c8976a | 2009-02-11 23:49:52 +0530 | [diff] [blame] | 333 | "(virt %p phys %llx)\n", buffer->index, |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 334 | buffer->index + buffer->entries - 1, |
Jaswinder Singh Rajput | 9c8976a | 2009-02-11 23:49:52 +0530 | [diff] [blame] | 335 | (u64)buffer->dma_addr, buffer->len, |
| 336 | buffer->addr, (u64)virt_to_phys(buffer->addr)); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 337 | |
| 338 | pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr, |
| 339 | buffer->dma_addr); |
| 340 | buffer->addr = NULL; |
| 341 | buffer->entries = 0; |
| 342 | } |
| 343 | |
| 344 | /************************************************************************** |
| 345 | * |
| 346 | * Falcon generic buffer handling |
| 347 | * These buffers are used for interrupt status and MAC stats |
| 348 | * |
| 349 | **************************************************************************/ |
| 350 | |
| 351 | static int falcon_alloc_buffer(struct efx_nic *efx, |
| 352 | struct efx_buffer *buffer, unsigned int len) |
| 353 | { |
| 354 | buffer->addr = pci_alloc_consistent(efx->pci_dev, len, |
| 355 | &buffer->dma_addr); |
| 356 | if (!buffer->addr) |
| 357 | return -ENOMEM; |
| 358 | buffer->len = len; |
| 359 | memset(buffer->addr, 0, len); |
| 360 | return 0; |
| 361 | } |
| 362 | |
| 363 | static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer) |
| 364 | { |
| 365 | if (buffer->addr) { |
| 366 | pci_free_consistent(efx->pci_dev, buffer->len, |
| 367 | buffer->addr, buffer->dma_addr); |
| 368 | buffer->addr = NULL; |
| 369 | } |
| 370 | } |
| 371 | |
| 372 | /************************************************************************** |
| 373 | * |
| 374 | * Falcon TX path |
| 375 | * |
| 376 | **************************************************************************/ |
| 377 | |
| 378 | /* Returns a pointer to the specified transmit descriptor in the TX |
| 379 | * descriptor queue belonging to the specified channel. |
| 380 | */ |
| 381 | static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue, |
| 382 | unsigned int index) |
| 383 | { |
| 384 | return (((efx_qword_t *) (tx_queue->txd.addr)) + index); |
| 385 | } |
| 386 | |
| 387 | /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ |
| 388 | static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue) |
| 389 | { |
| 390 | unsigned write_ptr; |
| 391 | efx_dword_t reg; |
| 392 | |
Ben Hutchings | 3ffeabd | 2009-10-23 08:30:58 +0000 | [diff] [blame] | 393 | write_ptr = tx_queue->write_count & EFX_TXQ_MASK; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 394 | EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 395 | efx_writed_page(tx_queue->efx, ®, |
| 396 | FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 397 | } |
| 398 | |
| 399 | |
| 400 | /* For each entry inserted into the software descriptor ring, create a |
| 401 | * descriptor in the hardware TX descriptor ring (in host memory), and |
| 402 | * write a doorbell. |
| 403 | */ |
| 404 | void falcon_push_buffers(struct efx_tx_queue *tx_queue) |
| 405 | { |
| 406 | |
| 407 | struct efx_tx_buffer *buffer; |
| 408 | efx_qword_t *txd; |
| 409 | unsigned write_ptr; |
| 410 | |
| 411 | BUG_ON(tx_queue->write_count == tx_queue->insert_count); |
| 412 | |
| 413 | do { |
Ben Hutchings | 3ffeabd | 2009-10-23 08:30:58 +0000 | [diff] [blame] | 414 | write_ptr = tx_queue->write_count & EFX_TXQ_MASK; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 415 | buffer = &tx_queue->buffer[write_ptr]; |
| 416 | txd = falcon_tx_desc(tx_queue, write_ptr); |
| 417 | ++tx_queue->write_count; |
| 418 | |
| 419 | /* Create TX descriptor ring entry */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 420 | EFX_POPULATE_QWORD_4(*txd, |
| 421 | FSF_AZ_TX_KER_CONT, buffer->continuation, |
| 422 | FSF_AZ_TX_KER_BYTE_COUNT, buffer->len, |
| 423 | FSF_AZ_TX_KER_BUF_REGION, 0, |
| 424 | FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 425 | } while (tx_queue->write_count != tx_queue->insert_count); |
| 426 | |
| 427 | wmb(); /* Ensure descriptors are written before they are fetched */ |
| 428 | falcon_notify_tx_desc(tx_queue); |
| 429 | } |
| 430 | |
| 431 | /* Allocate hardware resources for a TX queue */ |
| 432 | int falcon_probe_tx(struct efx_tx_queue *tx_queue) |
| 433 | { |
| 434 | struct efx_nic *efx = tx_queue->efx; |
Ben Hutchings | 3ffeabd | 2009-10-23 08:30:58 +0000 | [diff] [blame] | 435 | BUILD_BUG_ON(EFX_TXQ_SIZE < 512 || EFX_TXQ_SIZE > 4096 || |
| 436 | EFX_TXQ_SIZE & EFX_TXQ_MASK); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 437 | return falcon_alloc_special_buffer(efx, &tx_queue->txd, |
Ben Hutchings | 3ffeabd | 2009-10-23 08:30:58 +0000 | [diff] [blame] | 438 | EFX_TXQ_SIZE * sizeof(efx_qword_t)); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 439 | } |
| 440 | |
Ben Hutchings | bc3c90a | 2008-09-01 12:48:46 +0100 | [diff] [blame] | 441 | void falcon_init_tx(struct efx_tx_queue *tx_queue) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 442 | { |
| 443 | efx_oword_t tx_desc_ptr; |
| 444 | struct efx_nic *efx = tx_queue->efx; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 445 | |
Ben Hutchings | 6bc5d3a | 2008-09-01 12:49:37 +0100 | [diff] [blame] | 446 | tx_queue->flushed = false; |
| 447 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 448 | /* Pin TX descriptor ring */ |
Ben Hutchings | bc3c90a | 2008-09-01 12:48:46 +0100 | [diff] [blame] | 449 | falcon_init_special_buffer(efx, &tx_queue->txd); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 450 | |
| 451 | /* Push TX descriptor ring to card */ |
| 452 | EFX_POPULATE_OWORD_10(tx_desc_ptr, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 453 | FRF_AZ_TX_DESCQ_EN, 1, |
| 454 | FRF_AZ_TX_ISCSI_DDIG_EN, 0, |
| 455 | FRF_AZ_TX_ISCSI_HDIG_EN, 0, |
| 456 | FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index, |
| 457 | FRF_AZ_TX_DESCQ_EVQ_ID, |
| 458 | tx_queue->channel->channel, |
| 459 | FRF_AZ_TX_DESCQ_OWNER_ID, 0, |
| 460 | FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue, |
Ben Hutchings | 3ffeabd | 2009-10-23 08:30:58 +0000 | [diff] [blame] | 461 | FRF_AZ_TX_DESCQ_SIZE, |
| 462 | __ffs(tx_queue->txd.entries), |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 463 | FRF_AZ_TX_DESCQ_TYPE, 0, |
| 464 | FRF_BZ_TX_NON_IP_DROP_DIS, 1); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 465 | |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 466 | if (falcon_rev(efx) >= FALCON_REV_B0) { |
Ben Hutchings | 60ac106 | 2008-09-01 12:44:59 +0100 | [diff] [blame] | 467 | int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 468 | EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum); |
| 469 | EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS, |
| 470 | !csum); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 471 | } |
| 472 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 473 | efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base, |
| 474 | tx_queue->queue); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 475 | |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 476 | if (falcon_rev(efx) < FALCON_REV_B0) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 477 | efx_oword_t reg; |
| 478 | |
Ben Hutchings | 60ac106 | 2008-09-01 12:44:59 +0100 | [diff] [blame] | 479 | /* Only 128 bits in this register */ |
| 480 | BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 481 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 482 | efx_reado(efx, ®, FR_AA_TX_CHKSM_CFG); |
Ben Hutchings | 60ac106 | 2008-09-01 12:44:59 +0100 | [diff] [blame] | 483 | if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 484 | clear_bit_le(tx_queue->queue, (void *)®); |
| 485 | else |
| 486 | set_bit_le(tx_queue->queue, (void *)®); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 487 | efx_writeo(efx, ®, FR_AA_TX_CHKSM_CFG); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 488 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 489 | } |
| 490 | |
Ben Hutchings | 6bc5d3a | 2008-09-01 12:49:37 +0100 | [diff] [blame] | 491 | static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 492 | { |
| 493 | struct efx_nic *efx = tx_queue->efx; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 494 | efx_oword_t tx_flush_descq; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 495 | |
| 496 | /* Post a flush command */ |
| 497 | EFX_POPULATE_OWORD_2(tx_flush_descq, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 498 | FRF_AZ_TX_FLUSH_DESCQ_CMD, 1, |
| 499 | FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 500 | efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 501 | } |
| 502 | |
| 503 | void falcon_fini_tx(struct efx_tx_queue *tx_queue) |
| 504 | { |
| 505 | struct efx_nic *efx = tx_queue->efx; |
| 506 | efx_oword_t tx_desc_ptr; |
| 507 | |
Ben Hutchings | 6bc5d3a | 2008-09-01 12:49:37 +0100 | [diff] [blame] | 508 | /* The queue should have been flushed */ |
| 509 | WARN_ON(!tx_queue->flushed); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 510 | |
| 511 | /* Remove TX descriptor ring from card */ |
| 512 | EFX_ZERO_OWORD(tx_desc_ptr); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 513 | efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base, |
| 514 | tx_queue->queue); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 515 | |
| 516 | /* Unpin TX descriptor ring */ |
| 517 | falcon_fini_special_buffer(efx, &tx_queue->txd); |
| 518 | } |
| 519 | |
| 520 | /* Free buffers backing TX queue */ |
| 521 | void falcon_remove_tx(struct efx_tx_queue *tx_queue) |
| 522 | { |
| 523 | falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd); |
| 524 | } |
| 525 | |
| 526 | /************************************************************************** |
| 527 | * |
| 528 | * Falcon RX path |
| 529 | * |
| 530 | **************************************************************************/ |
| 531 | |
| 532 | /* Returns a pointer to the specified descriptor in the RX descriptor queue */ |
| 533 | static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue, |
| 534 | unsigned int index) |
| 535 | { |
| 536 | return (((efx_qword_t *) (rx_queue->rxd.addr)) + index); |
| 537 | } |
| 538 | |
| 539 | /* This creates an entry in the RX descriptor queue */ |
| 540 | static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue, |
| 541 | unsigned index) |
| 542 | { |
| 543 | struct efx_rx_buffer *rx_buf; |
| 544 | efx_qword_t *rxd; |
| 545 | |
| 546 | rxd = falcon_rx_desc(rx_queue, index); |
| 547 | rx_buf = efx_rx_buffer(rx_queue, index); |
| 548 | EFX_POPULATE_QWORD_3(*rxd, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 549 | FSF_AZ_RX_KER_BUF_SIZE, |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 550 | rx_buf->len - |
| 551 | rx_queue->efx->type->rx_buffer_padding, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 552 | FSF_AZ_RX_KER_BUF_REGION, 0, |
| 553 | FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 554 | } |
| 555 | |
| 556 | /* This writes to the RX_DESC_WPTR register for the specified receive |
| 557 | * descriptor ring. |
| 558 | */ |
| 559 | void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue) |
| 560 | { |
| 561 | efx_dword_t reg; |
| 562 | unsigned write_ptr; |
| 563 | |
| 564 | while (rx_queue->notified_count != rx_queue->added_count) { |
| 565 | falcon_build_rx_desc(rx_queue, |
| 566 | rx_queue->notified_count & |
Ben Hutchings | 3ffeabd | 2009-10-23 08:30:58 +0000 | [diff] [blame] | 567 | EFX_RXQ_MASK); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 568 | ++rx_queue->notified_count; |
| 569 | } |
| 570 | |
| 571 | wmb(); |
Ben Hutchings | 3ffeabd | 2009-10-23 08:30:58 +0000 | [diff] [blame] | 572 | write_ptr = rx_queue->added_count & EFX_RXQ_MASK; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 573 | EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 574 | efx_writed_page(rx_queue->efx, ®, |
| 575 | FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 576 | } |
| 577 | |
| 578 | int falcon_probe_rx(struct efx_rx_queue *rx_queue) |
| 579 | { |
| 580 | struct efx_nic *efx = rx_queue->efx; |
Ben Hutchings | 3ffeabd | 2009-10-23 08:30:58 +0000 | [diff] [blame] | 581 | BUILD_BUG_ON(EFX_RXQ_SIZE < 512 || EFX_RXQ_SIZE > 4096 || |
| 582 | EFX_RXQ_SIZE & EFX_RXQ_MASK); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 583 | return falcon_alloc_special_buffer(efx, &rx_queue->rxd, |
Ben Hutchings | 3ffeabd | 2009-10-23 08:30:58 +0000 | [diff] [blame] | 584 | EFX_RXQ_SIZE * sizeof(efx_qword_t)); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 585 | } |
| 586 | |
Ben Hutchings | bc3c90a | 2008-09-01 12:48:46 +0100 | [diff] [blame] | 587 | void falcon_init_rx(struct efx_rx_queue *rx_queue) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 588 | { |
| 589 | efx_oword_t rx_desc_ptr; |
| 590 | struct efx_nic *efx = rx_queue->efx; |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 591 | bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0; |
| 592 | bool iscsi_digest_en = is_b0; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 593 | |
| 594 | EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n", |
| 595 | rx_queue->queue, rx_queue->rxd.index, |
| 596 | rx_queue->rxd.index + rx_queue->rxd.entries - 1); |
| 597 | |
Ben Hutchings | 6bc5d3a | 2008-09-01 12:49:37 +0100 | [diff] [blame] | 598 | rx_queue->flushed = false; |
| 599 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 600 | /* Pin RX descriptor ring */ |
Ben Hutchings | bc3c90a | 2008-09-01 12:48:46 +0100 | [diff] [blame] | 601 | falcon_init_special_buffer(efx, &rx_queue->rxd); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 602 | |
| 603 | /* Push RX descriptor ring to card */ |
| 604 | EFX_POPULATE_OWORD_10(rx_desc_ptr, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 605 | FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en, |
| 606 | FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en, |
| 607 | FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index, |
| 608 | FRF_AZ_RX_DESCQ_EVQ_ID, |
| 609 | rx_queue->channel->channel, |
| 610 | FRF_AZ_RX_DESCQ_OWNER_ID, 0, |
| 611 | FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue, |
Ben Hutchings | 3ffeabd | 2009-10-23 08:30:58 +0000 | [diff] [blame] | 612 | FRF_AZ_RX_DESCQ_SIZE, |
| 613 | __ffs(rx_queue->rxd.entries), |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 614 | FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ , |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 615 | /* For >=B0 this is scatter so disable */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 616 | FRF_AZ_RX_DESCQ_JUMBO, !is_b0, |
| 617 | FRF_AZ_RX_DESCQ_EN, 1); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 618 | efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, |
| 619 | rx_queue->queue); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 620 | } |
| 621 | |
Ben Hutchings | 6bc5d3a | 2008-09-01 12:49:37 +0100 | [diff] [blame] | 622 | static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 623 | { |
| 624 | struct efx_nic *efx = rx_queue->efx; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 625 | efx_oword_t rx_flush_descq; |
| 626 | |
| 627 | /* Post a flush command */ |
| 628 | EFX_POPULATE_OWORD_2(rx_flush_descq, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 629 | FRF_AZ_RX_FLUSH_DESCQ_CMD, 1, |
| 630 | FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 631 | efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 632 | } |
| 633 | |
| 634 | void falcon_fini_rx(struct efx_rx_queue *rx_queue) |
| 635 | { |
| 636 | efx_oword_t rx_desc_ptr; |
| 637 | struct efx_nic *efx = rx_queue->efx; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 638 | |
Ben Hutchings | 6bc5d3a | 2008-09-01 12:49:37 +0100 | [diff] [blame] | 639 | /* The queue should already have been flushed */ |
| 640 | WARN_ON(!rx_queue->flushed); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 641 | |
| 642 | /* Remove RX descriptor ring from card */ |
| 643 | EFX_ZERO_OWORD(rx_desc_ptr); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 644 | efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, |
| 645 | rx_queue->queue); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 646 | |
| 647 | /* Unpin RX descriptor ring */ |
| 648 | falcon_fini_special_buffer(efx, &rx_queue->rxd); |
| 649 | } |
| 650 | |
| 651 | /* Free buffers backing RX queue */ |
| 652 | void falcon_remove_rx(struct efx_rx_queue *rx_queue) |
| 653 | { |
| 654 | falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd); |
| 655 | } |
| 656 | |
| 657 | /************************************************************************** |
| 658 | * |
| 659 | * Falcon event queue processing |
| 660 | * Event queues are processed by per-channel tasklets. |
| 661 | * |
| 662 | **************************************************************************/ |
| 663 | |
| 664 | /* Update a channel's event queue's read pointer (RPTR) register |
| 665 | * |
| 666 | * This writes the EVQ_RPTR_REG register for the specified channel's |
| 667 | * event queue. |
| 668 | * |
| 669 | * Note that EVQ_RPTR_REG contains the index of the "last read" event, |
| 670 | * whereas channel->eventq_read_ptr contains the index of the "next to |
| 671 | * read" event. |
| 672 | */ |
| 673 | void falcon_eventq_read_ack(struct efx_channel *channel) |
| 674 | { |
| 675 | efx_dword_t reg; |
| 676 | struct efx_nic *efx = channel->efx; |
| 677 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 678 | EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 679 | efx_writed_table(efx, ®, efx->type->evq_rptr_tbl_base, |
Ben Hutchings | d307402 | 2008-09-01 12:48:03 +0100 | [diff] [blame] | 680 | channel->channel); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 681 | } |
| 682 | |
| 683 | /* Use HW to insert a SW defined event */ |
| 684 | void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event) |
| 685 | { |
| 686 | efx_oword_t drv_ev_reg; |
| 687 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 688 | BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 || |
| 689 | FRF_AZ_DRV_EV_DATA_WIDTH != 64); |
| 690 | drv_ev_reg.u32[0] = event->u32[0]; |
| 691 | drv_ev_reg.u32[1] = event->u32[1]; |
| 692 | drv_ev_reg.u32[2] = 0; |
| 693 | drv_ev_reg.u32[3] = 0; |
| 694 | EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 695 | efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 696 | } |
| 697 | |
| 698 | /* Handle a transmit completion event |
| 699 | * |
| 700 | * Falcon batches TX completion events; the message we receive is of |
| 701 | * the form "complete all TX events up to this index". |
| 702 | */ |
Ben Hutchings | 4d56606 | 2008-09-01 12:47:12 +0100 | [diff] [blame] | 703 | static void falcon_handle_tx_event(struct efx_channel *channel, |
| 704 | efx_qword_t *event) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 705 | { |
| 706 | unsigned int tx_ev_desc_ptr; |
| 707 | unsigned int tx_ev_q_label; |
| 708 | struct efx_tx_queue *tx_queue; |
| 709 | struct efx_nic *efx = channel->efx; |
| 710 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 711 | if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 712 | /* Transmit completion */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 713 | tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR); |
| 714 | tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 715 | tx_queue = &efx->tx_queue[tx_ev_q_label]; |
Ben Hutchings | 6fb70fd | 2009-03-20 13:30:37 +0000 | [diff] [blame] | 716 | channel->irq_mod_score += |
| 717 | (tx_ev_desc_ptr - tx_queue->read_count) & |
Ben Hutchings | 3ffeabd | 2009-10-23 08:30:58 +0000 | [diff] [blame] | 718 | EFX_TXQ_MASK; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 719 | efx_xmit_done(tx_queue, tx_ev_desc_ptr); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 720 | } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 721 | /* Rewrite the FIFO write pointer */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 722 | tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 723 | tx_queue = &efx->tx_queue[tx_ev_q_label]; |
| 724 | |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 725 | if (efx_dev_registered(efx)) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 726 | netif_tx_lock(efx->net_dev); |
| 727 | falcon_notify_tx_desc(tx_queue); |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 728 | if (efx_dev_registered(efx)) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 729 | netif_tx_unlock(efx->net_dev); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 730 | } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) && |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 731 | EFX_WORKAROUND_10727(efx)) { |
| 732 | efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH); |
| 733 | } else { |
| 734 | EFX_ERR(efx, "channel %d unexpected TX event " |
| 735 | EFX_QWORD_FMT"\n", channel->channel, |
| 736 | EFX_QWORD_VAL(*event)); |
| 737 | } |
| 738 | } |
| 739 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 740 | /* Detect errors included in the rx_evt_pkt_ok bit. */ |
| 741 | static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue, |
| 742 | const efx_qword_t *event, |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 743 | bool *rx_ev_pkt_ok, |
| 744 | bool *discard) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 745 | { |
| 746 | struct efx_nic *efx = rx_queue->efx; |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 747 | bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err; |
| 748 | bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err; |
| 749 | bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc; |
| 750 | bool rx_ev_other_err, rx_ev_pause_frm; |
| 751 | bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt; |
| 752 | unsigned rx_ev_pkt_type; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 753 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 754 | rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE); |
| 755 | rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT); |
| 756 | rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC); |
| 757 | rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 758 | rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 759 | FSF_AZ_RX_EV_BUF_OWNER_ID_ERR); |
| 760 | rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_IP_FRAG_ERR); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 761 | rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 762 | FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 763 | rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 764 | FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR); |
| 765 | rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR); |
| 766 | rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC); |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 767 | rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ? |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 768 | 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB)); |
| 769 | rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 770 | |
| 771 | /* Every error apart from tobe_disc and pause_frm */ |
| 772 | rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err | |
| 773 | rx_ev_buf_owner_id_err | rx_ev_eth_crc_err | |
| 774 | rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err); |
| 775 | |
Ben Hutchings | 5005087 | 2008-12-12 21:42:42 -0800 | [diff] [blame] | 776 | /* Count errors that are not in MAC stats. Ignore expected |
| 777 | * checksum errors during self-test. */ |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 778 | if (rx_ev_frm_trunc) |
| 779 | ++rx_queue->channel->n_rx_frm_trunc; |
| 780 | else if (rx_ev_tobe_disc) |
| 781 | ++rx_queue->channel->n_rx_tobe_disc; |
Ben Hutchings | 5005087 | 2008-12-12 21:42:42 -0800 | [diff] [blame] | 782 | else if (!efx->loopback_selftest) { |
| 783 | if (rx_ev_ip_hdr_chksum_err) |
| 784 | ++rx_queue->channel->n_rx_ip_hdr_chksum_err; |
| 785 | else if (rx_ev_tcp_udp_chksum_err) |
| 786 | ++rx_queue->channel->n_rx_tcp_udp_chksum_err; |
| 787 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 788 | if (rx_ev_ip_frag_err) |
| 789 | ++rx_queue->channel->n_rx_ip_frag_err; |
| 790 | |
| 791 | /* The frame must be discarded if any of these are true. */ |
| 792 | *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib | |
| 793 | rx_ev_tobe_disc | rx_ev_pause_frm); |
| 794 | |
| 795 | /* TOBE_DISC is expected on unicast mismatches; don't print out an |
| 796 | * error message. FRM_TRUNC indicates RXDP dropped the packet due |
| 797 | * to a FIFO overflow. |
| 798 | */ |
| 799 | #ifdef EFX_ENABLE_DEBUG |
| 800 | if (rx_ev_other_err) { |
| 801 | EFX_INFO_RL(efx, " RX queue %d unexpected RX event " |
Ben Hutchings | 5b39fe3 | 2008-09-01 12:46:03 +0100 | [diff] [blame] | 802 | EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n", |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 803 | rx_queue->queue, EFX_QWORD_VAL(*event), |
| 804 | rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "", |
| 805 | rx_ev_ip_hdr_chksum_err ? |
| 806 | " [IP_HDR_CHKSUM_ERR]" : "", |
| 807 | rx_ev_tcp_udp_chksum_err ? |
| 808 | " [TCP_UDP_CHKSUM_ERR]" : "", |
| 809 | rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "", |
| 810 | rx_ev_frm_trunc ? " [FRM_TRUNC]" : "", |
| 811 | rx_ev_drib_nib ? " [DRIB_NIB]" : "", |
| 812 | rx_ev_tobe_disc ? " [TOBE_DISC]" : "", |
Ben Hutchings | 5b39fe3 | 2008-09-01 12:46:03 +0100 | [diff] [blame] | 813 | rx_ev_pause_frm ? " [PAUSE]" : ""); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 814 | } |
| 815 | #endif |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 816 | } |
| 817 | |
| 818 | /* Handle receive events that are not in-order. */ |
| 819 | static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue, |
| 820 | unsigned index) |
| 821 | { |
| 822 | struct efx_nic *efx = rx_queue->efx; |
| 823 | unsigned expected, dropped; |
| 824 | |
Ben Hutchings | 3ffeabd | 2009-10-23 08:30:58 +0000 | [diff] [blame] | 825 | expected = rx_queue->removed_count & EFX_RXQ_MASK; |
| 826 | dropped = (index - expected) & EFX_RXQ_MASK; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 827 | EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n", |
| 828 | dropped, index, expected); |
| 829 | |
| 830 | efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ? |
| 831 | RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE); |
| 832 | } |
| 833 | |
| 834 | /* Handle a packet received event |
| 835 | * |
| 836 | * Falcon silicon gives a "discard" flag if it's a unicast packet with the |
| 837 | * wrong destination address |
| 838 | * Also "is multicast" and "matches multicast filter" flags can be used to |
| 839 | * discard non-matching multicast packets. |
| 840 | */ |
Ben Hutchings | 42cbe2d | 2008-09-01 12:48:08 +0100 | [diff] [blame] | 841 | static void falcon_handle_rx_event(struct efx_channel *channel, |
| 842 | const efx_qword_t *event) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 843 | { |
Ben Hutchings | 42cbe2d | 2008-09-01 12:48:08 +0100 | [diff] [blame] | 844 | unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt; |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 845 | unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 846 | unsigned expected_ptr; |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 847 | bool rx_ev_pkt_ok, discard = false, checksummed; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 848 | struct efx_rx_queue *rx_queue; |
| 849 | struct efx_nic *efx = channel->efx; |
| 850 | |
| 851 | /* Basic packet information */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 852 | rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT); |
| 853 | rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK); |
| 854 | rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE); |
| 855 | WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT)); |
| 856 | WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1); |
| 857 | WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) != |
| 858 | channel->channel); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 859 | |
Ben Hutchings | 42cbe2d | 2008-09-01 12:48:08 +0100 | [diff] [blame] | 860 | rx_queue = &efx->rx_queue[channel->channel]; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 861 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 862 | rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR); |
Ben Hutchings | 3ffeabd | 2009-10-23 08:30:58 +0000 | [diff] [blame] | 863 | expected_ptr = rx_queue->removed_count & EFX_RXQ_MASK; |
Ben Hutchings | 42cbe2d | 2008-09-01 12:48:08 +0100 | [diff] [blame] | 864 | if (unlikely(rx_ev_desc_ptr != expected_ptr)) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 865 | falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 866 | |
| 867 | if (likely(rx_ev_pkt_ok)) { |
| 868 | /* If packet is marked as OK and packet type is TCP/IPv4 or |
| 869 | * UDP/IPv4, then we can rely on the hardware checksum. |
| 870 | */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 871 | checksummed = |
Ben Hutchings | 9c1bbba | 2009-10-28 02:50:44 -0700 | [diff] [blame] | 872 | efx->rx_checksum_enabled && |
| 873 | (rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP || |
| 874 | rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 875 | } else { |
| 876 | falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok, |
Ben Hutchings | 5b39fe3 | 2008-09-01 12:46:03 +0100 | [diff] [blame] | 877 | &discard); |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 878 | checksummed = false; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 879 | } |
| 880 | |
| 881 | /* Detect multicast packets that didn't match the filter */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 882 | rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 883 | if (rx_ev_mcast_pkt) { |
| 884 | unsigned int rx_ev_mcast_hash_match = |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 885 | EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 886 | |
| 887 | if (unlikely(!rx_ev_mcast_hash_match)) |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 888 | discard = true; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 889 | } |
| 890 | |
Ben Hutchings | 6fb70fd | 2009-03-20 13:30:37 +0000 | [diff] [blame] | 891 | channel->irq_mod_score += 2; |
| 892 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 893 | /* Handle received packet */ |
| 894 | efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt, |
| 895 | checksummed, discard); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 896 | } |
| 897 | |
| 898 | /* Global events are basically PHY events */ |
| 899 | static void falcon_handle_global_event(struct efx_channel *channel, |
| 900 | efx_qword_t *event) |
| 901 | { |
| 902 | struct efx_nic *efx = channel->efx; |
Ben Hutchings | 766ca0f | 2008-12-12 21:59:24 -0800 | [diff] [blame] | 903 | bool handled = false; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 904 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 905 | if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) || |
| 906 | EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) || |
| 907 | EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) { |
Ben Hutchings | 766ca0f | 2008-12-12 21:59:24 -0800 | [diff] [blame] | 908 | efx->phy_op->clear_interrupt(efx); |
| 909 | queue_work(efx->workqueue, &efx->phy_work); |
| 910 | handled = true; |
| 911 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 912 | |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 913 | if ((falcon_rev(efx) >= FALCON_REV_B0) && |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 914 | EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) { |
Ben Hutchings | 766ca0f | 2008-12-12 21:59:24 -0800 | [diff] [blame] | 915 | queue_work(efx->workqueue, &efx->mac_work); |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 916 | handled = true; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 917 | } |
| 918 | |
Ben Hutchings | 56241ce | 2009-10-23 08:30:06 +0000 | [diff] [blame] | 919 | if (falcon_rev(efx) <= FALCON_REV_A1 ? |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 920 | EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) : |
| 921 | EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 922 | EFX_ERR(efx, "channel %d seen global RX_RESET " |
| 923 | "event. Resetting.\n", channel->channel); |
| 924 | |
| 925 | atomic_inc(&efx->rx_reset); |
| 926 | efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ? |
| 927 | RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE); |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 928 | handled = true; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 929 | } |
| 930 | |
| 931 | if (!handled) |
| 932 | EFX_ERR(efx, "channel %d unknown global event " |
| 933 | EFX_QWORD_FMT "\n", channel->channel, |
| 934 | EFX_QWORD_VAL(*event)); |
| 935 | } |
| 936 | |
| 937 | static void falcon_handle_driver_event(struct efx_channel *channel, |
| 938 | efx_qword_t *event) |
| 939 | { |
| 940 | struct efx_nic *efx = channel->efx; |
| 941 | unsigned int ev_sub_code; |
| 942 | unsigned int ev_sub_data; |
| 943 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 944 | ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE); |
| 945 | ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 946 | |
| 947 | switch (ev_sub_code) { |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 948 | case FSE_AZ_TX_DESCQ_FLS_DONE_EV: |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 949 | EFX_TRACE(efx, "channel %d TXQ %d flushed\n", |
| 950 | channel->channel, ev_sub_data); |
| 951 | break; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 952 | case FSE_AZ_RX_DESCQ_FLS_DONE_EV: |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 953 | EFX_TRACE(efx, "channel %d RXQ %d flushed\n", |
| 954 | channel->channel, ev_sub_data); |
| 955 | break; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 956 | case FSE_AZ_EVQ_INIT_DONE_EV: |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 957 | EFX_LOG(efx, "channel %d EVQ %d initialised\n", |
| 958 | channel->channel, ev_sub_data); |
| 959 | break; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 960 | case FSE_AZ_SRM_UPD_DONE_EV: |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 961 | EFX_TRACE(efx, "channel %d SRAM update done\n", |
| 962 | channel->channel); |
| 963 | break; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 964 | case FSE_AZ_WAKE_UP_EV: |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 965 | EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n", |
| 966 | channel->channel, ev_sub_data); |
| 967 | break; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 968 | case FSE_AZ_TIMER_EV: |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 969 | EFX_TRACE(efx, "channel %d RX queue %d timer expired\n", |
| 970 | channel->channel, ev_sub_data); |
| 971 | break; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 972 | case FSE_AA_RX_RECOVER_EV: |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 973 | EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. " |
| 974 | "Resetting.\n", channel->channel); |
Ben Hutchings | 05e3ec0 | 2008-05-07 13:00:39 +0100 | [diff] [blame] | 975 | atomic_inc(&efx->rx_reset); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 976 | efx_schedule_reset(efx, |
| 977 | EFX_WORKAROUND_6555(efx) ? |
| 978 | RESET_TYPE_RX_RECOVERY : |
| 979 | RESET_TYPE_DISABLE); |
| 980 | break; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 981 | case FSE_BZ_RX_DSC_ERROR_EV: |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 982 | EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error." |
| 983 | " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data); |
| 984 | efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH); |
| 985 | break; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 986 | case FSE_BZ_TX_DSC_ERROR_EV: |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 987 | EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error." |
| 988 | " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data); |
| 989 | efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH); |
| 990 | break; |
| 991 | default: |
| 992 | EFX_TRACE(efx, "channel %d unknown driver event code %d " |
| 993 | "data %04x\n", channel->channel, ev_sub_code, |
| 994 | ev_sub_data); |
| 995 | break; |
| 996 | } |
| 997 | } |
| 998 | |
Ben Hutchings | 42cbe2d | 2008-09-01 12:48:08 +0100 | [diff] [blame] | 999 | int falcon_process_eventq(struct efx_channel *channel, int rx_quota) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1000 | { |
| 1001 | unsigned int read_ptr; |
| 1002 | efx_qword_t event, *p_event; |
| 1003 | int ev_code; |
Ben Hutchings | 42cbe2d | 2008-09-01 12:48:08 +0100 | [diff] [blame] | 1004 | int rx_packets = 0; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1005 | |
| 1006 | read_ptr = channel->eventq_read_ptr; |
| 1007 | |
| 1008 | do { |
| 1009 | p_event = falcon_event(channel, read_ptr); |
| 1010 | event = *p_event; |
| 1011 | |
| 1012 | if (!falcon_event_present(&event)) |
| 1013 | /* End of events */ |
| 1014 | break; |
| 1015 | |
| 1016 | EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n", |
| 1017 | channel->channel, EFX_QWORD_VAL(event)); |
| 1018 | |
| 1019 | /* Clear this event by marking it all ones */ |
| 1020 | EFX_SET_QWORD(*p_event); |
| 1021 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1022 | ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1023 | |
| 1024 | switch (ev_code) { |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1025 | case FSE_AZ_EV_CODE_RX_EV: |
Ben Hutchings | 42cbe2d | 2008-09-01 12:48:08 +0100 | [diff] [blame] | 1026 | falcon_handle_rx_event(channel, &event); |
| 1027 | ++rx_packets; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1028 | break; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1029 | case FSE_AZ_EV_CODE_TX_EV: |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1030 | falcon_handle_tx_event(channel, &event); |
| 1031 | break; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1032 | case FSE_AZ_EV_CODE_DRV_GEN_EV: |
| 1033 | channel->eventq_magic = EFX_QWORD_FIELD( |
| 1034 | event, FSF_AZ_DRV_GEN_EV_MAGIC); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1035 | EFX_LOG(channel->efx, "channel %d received generated " |
| 1036 | "event "EFX_QWORD_FMT"\n", channel->channel, |
| 1037 | EFX_QWORD_VAL(event)); |
| 1038 | break; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1039 | case FSE_AZ_EV_CODE_GLOBAL_EV: |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1040 | falcon_handle_global_event(channel, &event); |
| 1041 | break; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1042 | case FSE_AZ_EV_CODE_DRIVER_EV: |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1043 | falcon_handle_driver_event(channel, &event); |
| 1044 | break; |
| 1045 | default: |
| 1046 | EFX_ERR(channel->efx, "channel %d unknown event type %d" |
| 1047 | " (data " EFX_QWORD_FMT ")\n", channel->channel, |
| 1048 | ev_code, EFX_QWORD_VAL(event)); |
| 1049 | } |
| 1050 | |
| 1051 | /* Increment read pointer */ |
Ben Hutchings | 3ffeabd | 2009-10-23 08:30:58 +0000 | [diff] [blame] | 1052 | read_ptr = (read_ptr + 1) & EFX_EVQ_MASK; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1053 | |
Ben Hutchings | 42cbe2d | 2008-09-01 12:48:08 +0100 | [diff] [blame] | 1054 | } while (rx_packets < rx_quota); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1055 | |
| 1056 | channel->eventq_read_ptr = read_ptr; |
Ben Hutchings | 42cbe2d | 2008-09-01 12:48:08 +0100 | [diff] [blame] | 1057 | return rx_packets; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1058 | } |
| 1059 | |
| 1060 | void falcon_set_int_moderation(struct efx_channel *channel) |
| 1061 | { |
| 1062 | efx_dword_t timer_cmd; |
| 1063 | struct efx_nic *efx = channel->efx; |
| 1064 | |
| 1065 | /* Set timer register */ |
| 1066 | if (channel->irq_moderation) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1067 | EFX_POPULATE_DWORD_2(timer_cmd, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1068 | FRF_AB_TC_TIMER_MODE, |
| 1069 | FFE_BB_TIMER_MODE_INT_HLDOFF, |
| 1070 | FRF_AB_TC_TIMER_VAL, |
Ben Hutchings | 0d86ebd | 2009-10-23 08:32:13 +0000 | [diff] [blame] | 1071 | channel->irq_moderation - 1); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1072 | } else { |
| 1073 | EFX_POPULATE_DWORD_2(timer_cmd, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1074 | FRF_AB_TC_TIMER_MODE, |
| 1075 | FFE_BB_TIMER_MODE_DIS, |
| 1076 | FRF_AB_TC_TIMER_VAL, 0); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1077 | } |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1078 | BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1079 | efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0, |
| 1080 | channel->channel); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1081 | |
| 1082 | } |
| 1083 | |
| 1084 | /* Allocate buffer table entries for event queue */ |
| 1085 | int falcon_probe_eventq(struct efx_channel *channel) |
| 1086 | { |
| 1087 | struct efx_nic *efx = channel->efx; |
Ben Hutchings | 3ffeabd | 2009-10-23 08:30:58 +0000 | [diff] [blame] | 1088 | BUILD_BUG_ON(EFX_EVQ_SIZE < 512 || EFX_EVQ_SIZE > 32768 || |
| 1089 | EFX_EVQ_SIZE & EFX_EVQ_MASK); |
| 1090 | return falcon_alloc_special_buffer(efx, &channel->eventq, |
| 1091 | EFX_EVQ_SIZE * sizeof(efx_qword_t)); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1092 | } |
| 1093 | |
Ben Hutchings | bc3c90a | 2008-09-01 12:48:46 +0100 | [diff] [blame] | 1094 | void falcon_init_eventq(struct efx_channel *channel) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1095 | { |
| 1096 | efx_oword_t evq_ptr; |
| 1097 | struct efx_nic *efx = channel->efx; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1098 | |
| 1099 | EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n", |
| 1100 | channel->channel, channel->eventq.index, |
| 1101 | channel->eventq.index + channel->eventq.entries - 1); |
| 1102 | |
| 1103 | /* Pin event queue buffer */ |
Ben Hutchings | bc3c90a | 2008-09-01 12:48:46 +0100 | [diff] [blame] | 1104 | falcon_init_special_buffer(efx, &channel->eventq); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1105 | |
| 1106 | /* Fill event queue with all ones (i.e. empty events) */ |
| 1107 | memset(channel->eventq.addr, 0xff, channel->eventq.len); |
| 1108 | |
| 1109 | /* Push event queue to card */ |
| 1110 | EFX_POPULATE_OWORD_3(evq_ptr, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1111 | FRF_AZ_EVQ_EN, 1, |
Ben Hutchings | 3ffeabd | 2009-10-23 08:30:58 +0000 | [diff] [blame] | 1112 | FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries), |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1113 | FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1114 | efx_writeo_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base, |
| 1115 | channel->channel); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1116 | |
| 1117 | falcon_set_int_moderation(channel); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1118 | } |
| 1119 | |
| 1120 | void falcon_fini_eventq(struct efx_channel *channel) |
| 1121 | { |
| 1122 | efx_oword_t eventq_ptr; |
| 1123 | struct efx_nic *efx = channel->efx; |
| 1124 | |
| 1125 | /* Remove event queue from card */ |
| 1126 | EFX_ZERO_OWORD(eventq_ptr); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1127 | efx_writeo_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base, |
| 1128 | channel->channel); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1129 | |
| 1130 | /* Unpin event queue */ |
| 1131 | falcon_fini_special_buffer(efx, &channel->eventq); |
| 1132 | } |
| 1133 | |
| 1134 | /* Free buffers backing event queue */ |
| 1135 | void falcon_remove_eventq(struct efx_channel *channel) |
| 1136 | { |
| 1137 | falcon_free_special_buffer(channel->efx, &channel->eventq); |
| 1138 | } |
| 1139 | |
| 1140 | |
| 1141 | /* Generates a test event on the event queue. A subsequent call to |
| 1142 | * process_eventq() should pick up the event and place the value of |
| 1143 | * "magic" into channel->eventq_magic; |
| 1144 | */ |
| 1145 | void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic) |
| 1146 | { |
| 1147 | efx_qword_t test_event; |
| 1148 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1149 | EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE, |
| 1150 | FSE_AZ_EV_CODE_DRV_GEN_EV, |
| 1151 | FSF_AZ_DRV_GEN_EV_MAGIC, magic); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1152 | falcon_generate_event(channel, &test_event); |
| 1153 | } |
| 1154 | |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 1155 | void falcon_sim_phy_event(struct efx_nic *efx) |
| 1156 | { |
| 1157 | efx_qword_t phy_event; |
| 1158 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1159 | EFX_POPULATE_QWORD_1(phy_event, FSF_AZ_EV_CODE, |
| 1160 | FSE_AZ_EV_CODE_GLOBAL_EV); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 1161 | if (EFX_IS10G(efx)) |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1162 | EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_XG_PHY0_INTR, 1); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 1163 | else |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1164 | EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_G_PHY0_INTR, 1); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 1165 | |
| 1166 | falcon_generate_event(&efx->channel[0], &phy_event); |
| 1167 | } |
| 1168 | |
Ben Hutchings | 6bc5d3a | 2008-09-01 12:49:37 +0100 | [diff] [blame] | 1169 | /************************************************************************** |
| 1170 | * |
| 1171 | * Flush handling |
| 1172 | * |
| 1173 | **************************************************************************/ |
| 1174 | |
| 1175 | |
| 1176 | static void falcon_poll_flush_events(struct efx_nic *efx) |
| 1177 | { |
| 1178 | struct efx_channel *channel = &efx->channel[0]; |
| 1179 | struct efx_tx_queue *tx_queue; |
| 1180 | struct efx_rx_queue *rx_queue; |
Ben Hutchings | 4720bc6 | 2009-03-04 10:01:15 +0000 | [diff] [blame] | 1181 | unsigned int read_ptr = channel->eventq_read_ptr; |
Ben Hutchings | 3ffeabd | 2009-10-23 08:30:58 +0000 | [diff] [blame] | 1182 | unsigned int end_ptr = (read_ptr - 1) & EFX_EVQ_MASK; |
Ben Hutchings | 6bc5d3a | 2008-09-01 12:49:37 +0100 | [diff] [blame] | 1183 | |
Ben Hutchings | 4720bc6 | 2009-03-04 10:01:15 +0000 | [diff] [blame] | 1184 | do { |
Ben Hutchings | 6bc5d3a | 2008-09-01 12:49:37 +0100 | [diff] [blame] | 1185 | efx_qword_t *event = falcon_event(channel, read_ptr); |
| 1186 | int ev_code, ev_sub_code, ev_queue; |
| 1187 | bool ev_failed; |
Ben Hutchings | 4720bc6 | 2009-03-04 10:01:15 +0000 | [diff] [blame] | 1188 | |
Ben Hutchings | 6bc5d3a | 2008-09-01 12:49:37 +0100 | [diff] [blame] | 1189 | if (!falcon_event_present(event)) |
| 1190 | break; |
| 1191 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1192 | ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE); |
| 1193 | ev_sub_code = EFX_QWORD_FIELD(*event, |
| 1194 | FSF_AZ_DRIVER_EV_SUBCODE); |
| 1195 | if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV && |
| 1196 | ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) { |
Ben Hutchings | 6bc5d3a | 2008-09-01 12:49:37 +0100 | [diff] [blame] | 1197 | ev_queue = EFX_QWORD_FIELD(*event, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1198 | FSF_AZ_DRIVER_EV_SUBDATA); |
Ben Hutchings | 6bc5d3a | 2008-09-01 12:49:37 +0100 | [diff] [blame] | 1199 | if (ev_queue < EFX_TX_QUEUE_COUNT) { |
| 1200 | tx_queue = efx->tx_queue + ev_queue; |
| 1201 | tx_queue->flushed = true; |
| 1202 | } |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1203 | } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV && |
| 1204 | ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) { |
| 1205 | ev_queue = EFX_QWORD_FIELD( |
| 1206 | *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); |
| 1207 | ev_failed = EFX_QWORD_FIELD( |
| 1208 | *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); |
Ben Hutchings | 6bc5d3a | 2008-09-01 12:49:37 +0100 | [diff] [blame] | 1209 | if (ev_queue < efx->n_rx_queues) { |
| 1210 | rx_queue = efx->rx_queue + ev_queue; |
| 1211 | |
| 1212 | /* retry the rx flush */ |
| 1213 | if (ev_failed) |
| 1214 | falcon_flush_rx_queue(rx_queue); |
| 1215 | else |
| 1216 | rx_queue->flushed = true; |
| 1217 | } |
Ben Hutchings | 6bc5d3a | 2008-09-01 12:49:37 +0100 | [diff] [blame] | 1218 | } |
| 1219 | |
Ben Hutchings | 3ffeabd | 2009-10-23 08:30:58 +0000 | [diff] [blame] | 1220 | read_ptr = (read_ptr + 1) & EFX_EVQ_MASK; |
Ben Hutchings | 4720bc6 | 2009-03-04 10:01:15 +0000 | [diff] [blame] | 1221 | } while (read_ptr != end_ptr); |
Ben Hutchings | 6bc5d3a | 2008-09-01 12:49:37 +0100 | [diff] [blame] | 1222 | } |
| 1223 | |
| 1224 | /* Handle tx and rx flushes at the same time, since they run in |
| 1225 | * parallel in the hardware and there's no reason for us to |
| 1226 | * serialise them */ |
| 1227 | int falcon_flush_queues(struct efx_nic *efx) |
| 1228 | { |
| 1229 | struct efx_rx_queue *rx_queue; |
| 1230 | struct efx_tx_queue *tx_queue; |
| 1231 | int i; |
| 1232 | bool outstanding; |
| 1233 | |
| 1234 | /* Issue flush requests */ |
| 1235 | efx_for_each_tx_queue(tx_queue, efx) { |
| 1236 | tx_queue->flushed = false; |
| 1237 | falcon_flush_tx_queue(tx_queue); |
| 1238 | } |
| 1239 | efx_for_each_rx_queue(rx_queue, efx) { |
| 1240 | rx_queue->flushed = false; |
| 1241 | falcon_flush_rx_queue(rx_queue); |
| 1242 | } |
| 1243 | |
| 1244 | /* Poll the evq looking for flush completions. Since we're not pushing |
| 1245 | * any more rx or tx descriptors at this point, we're in no danger of |
| 1246 | * overflowing the evq whilst we wait */ |
| 1247 | for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) { |
| 1248 | msleep(FALCON_FLUSH_INTERVAL); |
| 1249 | falcon_poll_flush_events(efx); |
| 1250 | |
| 1251 | /* Check if every queue has been succesfully flushed */ |
| 1252 | outstanding = false; |
| 1253 | efx_for_each_tx_queue(tx_queue, efx) |
| 1254 | outstanding |= !tx_queue->flushed; |
| 1255 | efx_for_each_rx_queue(rx_queue, efx) |
| 1256 | outstanding |= !rx_queue->flushed; |
| 1257 | if (!outstanding) |
| 1258 | return 0; |
| 1259 | } |
| 1260 | |
| 1261 | /* Mark the queues as all flushed. We're going to return failure |
| 1262 | * leading to a reset, or fake up success anyway. "flushed" now |
| 1263 | * indicates that we tried to flush. */ |
| 1264 | efx_for_each_tx_queue(tx_queue, efx) { |
| 1265 | if (!tx_queue->flushed) |
| 1266 | EFX_ERR(efx, "tx queue %d flush command timed out\n", |
| 1267 | tx_queue->queue); |
| 1268 | tx_queue->flushed = true; |
| 1269 | } |
| 1270 | efx_for_each_rx_queue(rx_queue, efx) { |
| 1271 | if (!rx_queue->flushed) |
| 1272 | EFX_ERR(efx, "rx queue %d flush command timed out\n", |
| 1273 | rx_queue->queue); |
| 1274 | rx_queue->flushed = true; |
| 1275 | } |
| 1276 | |
| 1277 | if (EFX_WORKAROUND_7803(efx)) |
| 1278 | return 0; |
| 1279 | |
| 1280 | return -ETIMEDOUT; |
| 1281 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1282 | |
| 1283 | /************************************************************************** |
| 1284 | * |
| 1285 | * Falcon hardware interrupts |
| 1286 | * The hardware interrupt handler does very little work; all the event |
| 1287 | * queue processing is carried out by per-channel tasklets. |
| 1288 | * |
| 1289 | **************************************************************************/ |
| 1290 | |
| 1291 | /* Enable/disable/generate Falcon interrupts */ |
| 1292 | static inline void falcon_interrupts(struct efx_nic *efx, int enabled, |
| 1293 | int force) |
| 1294 | { |
| 1295 | efx_oword_t int_en_reg_ker; |
| 1296 | |
| 1297 | EFX_POPULATE_OWORD_2(int_en_reg_ker, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1298 | FRF_AZ_KER_INT_KER, force, |
| 1299 | FRF_AZ_DRV_INT_EN_KER, enabled); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1300 | efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1301 | } |
| 1302 | |
| 1303 | void falcon_enable_interrupts(struct efx_nic *efx) |
| 1304 | { |
| 1305 | efx_oword_t int_adr_reg_ker; |
| 1306 | struct efx_channel *channel; |
| 1307 | |
| 1308 | EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr)); |
| 1309 | wmb(); /* Ensure interrupt vector is clear before interrupts enabled */ |
| 1310 | |
| 1311 | /* Program address */ |
| 1312 | EFX_POPULATE_OWORD_2(int_adr_reg_ker, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1313 | FRF_AZ_NORM_INT_VEC_DIS_KER, |
| 1314 | EFX_INT_MODE_USE_MSI(efx), |
| 1315 | FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1316 | efx_writeo(efx, &int_adr_reg_ker, FR_AZ_INT_ADR_KER); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1317 | |
| 1318 | /* Enable interrupts */ |
| 1319 | falcon_interrupts(efx, 1, 0); |
| 1320 | |
| 1321 | /* Force processing of all the channels to get the EVQ RPTRs up to |
| 1322 | date */ |
Ben Hutchings | 64ee312 | 2008-09-01 12:47:38 +0100 | [diff] [blame] | 1323 | efx_for_each_channel(channel, efx) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1324 | efx_schedule_channel(channel); |
| 1325 | } |
| 1326 | |
| 1327 | void falcon_disable_interrupts(struct efx_nic *efx) |
| 1328 | { |
| 1329 | /* Disable interrupts */ |
| 1330 | falcon_interrupts(efx, 0, 0); |
| 1331 | } |
| 1332 | |
| 1333 | /* Generate a Falcon test interrupt |
| 1334 | * Interrupt must already have been enabled, otherwise nasty things |
| 1335 | * may happen. |
| 1336 | */ |
| 1337 | void falcon_generate_interrupt(struct efx_nic *efx) |
| 1338 | { |
| 1339 | falcon_interrupts(efx, 1, 1); |
| 1340 | } |
| 1341 | |
| 1342 | /* Acknowledge a legacy interrupt from Falcon |
| 1343 | * |
| 1344 | * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG. |
| 1345 | * |
| 1346 | * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the |
| 1347 | * BIU. Interrupt acknowledge is read sensitive so must write instead |
| 1348 | * (then read to ensure the BIU collector is flushed) |
| 1349 | * |
| 1350 | * NB most hardware supports MSI interrupts |
| 1351 | */ |
| 1352 | static inline void falcon_irq_ack_a1(struct efx_nic *efx) |
| 1353 | { |
| 1354 | efx_dword_t reg; |
| 1355 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1356 | EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1357 | efx_writed(efx, ®, FR_AA_INT_ACK_KER); |
| 1358 | efx_readd(efx, ®, FR_AA_WORK_AROUND_BROKEN_PCI_READS); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1359 | } |
| 1360 | |
| 1361 | /* Process a fatal interrupt |
| 1362 | * Disable bus mastering ASAP and schedule a reset |
| 1363 | */ |
| 1364 | static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx) |
| 1365 | { |
| 1366 | struct falcon_nic_data *nic_data = efx->nic_data; |
Ben Hutchings | d3208b5 | 2008-05-16 21:20:00 +0100 | [diff] [blame] | 1367 | efx_oword_t *int_ker = efx->irq_status.addr; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1368 | efx_oword_t fatal_intr; |
| 1369 | int error, mem_perr; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1370 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1371 | efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1372 | error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1373 | |
| 1374 | EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status " |
| 1375 | EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker), |
| 1376 | EFX_OWORD_VAL(fatal_intr), |
| 1377 | error ? "disabling bus mastering" : "no recognised error"); |
| 1378 | if (error == 0) |
| 1379 | goto out; |
| 1380 | |
| 1381 | /* If this is a memory parity error dump which blocks are offending */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1382 | mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1383 | if (mem_perr) { |
| 1384 | efx_oword_t reg; |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1385 | efx_reado(efx, ®, FR_AZ_MEM_STAT); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1386 | EFX_ERR(efx, "SYSTEM ERROR: memory parity error " |
| 1387 | EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg)); |
| 1388 | } |
| 1389 | |
Ben Hutchings | 0a62f1a | 2008-09-01 12:50:14 +0100 | [diff] [blame] | 1390 | /* Disable both devices */ |
Ben Hutchings | ef1bba2 | 2008-12-23 03:09:53 +0000 | [diff] [blame] | 1391 | pci_clear_master(efx->pci_dev); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1392 | if (FALCON_IS_DUAL_FUNC(efx)) |
Ben Hutchings | ef1bba2 | 2008-12-23 03:09:53 +0000 | [diff] [blame] | 1393 | pci_clear_master(nic_data->pci_dev2); |
Ben Hutchings | 0a62f1a | 2008-09-01 12:50:14 +0100 | [diff] [blame] | 1394 | falcon_disable_interrupts(efx); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1395 | |
Ben Hutchings | 2c3c3d0 | 2009-03-04 10:01:57 +0000 | [diff] [blame] | 1396 | /* Count errors and reset or disable the NIC accordingly */ |
Ben Hutchings | 0484e0d | 2009-10-23 08:32:04 +0000 | [diff] [blame] | 1397 | if (efx->int_error_count == 0 || |
| 1398 | time_after(jiffies, efx->int_error_expire)) { |
| 1399 | efx->int_error_count = 0; |
| 1400 | efx->int_error_expire = |
Ben Hutchings | 2c3c3d0 | 2009-03-04 10:01:57 +0000 | [diff] [blame] | 1401 | jiffies + FALCON_INT_ERROR_EXPIRE * HZ; |
| 1402 | } |
Ben Hutchings | 0484e0d | 2009-10-23 08:32:04 +0000 | [diff] [blame] | 1403 | if (++efx->int_error_count < FALCON_MAX_INT_ERRORS) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1404 | EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n"); |
| 1405 | efx_schedule_reset(efx, RESET_TYPE_INT_ERROR); |
| 1406 | } else { |
| 1407 | EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen." |
| 1408 | "NIC will be disabled\n"); |
| 1409 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); |
| 1410 | } |
| 1411 | out: |
| 1412 | return IRQ_HANDLED; |
| 1413 | } |
| 1414 | |
| 1415 | /* Handle a legacy interrupt from Falcon |
| 1416 | * Acknowledges the interrupt and schedule event queue processing. |
| 1417 | */ |
| 1418 | static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id) |
| 1419 | { |
Ben Hutchings | d3208b5 | 2008-05-16 21:20:00 +0100 | [diff] [blame] | 1420 | struct efx_nic *efx = dev_id; |
| 1421 | efx_oword_t *int_ker = efx->irq_status.addr; |
Ben Hutchings | a9de9a7 | 2009-03-20 13:26:41 +0000 | [diff] [blame] | 1422 | irqreturn_t result = IRQ_NONE; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1423 | struct efx_channel *channel; |
| 1424 | efx_dword_t reg; |
| 1425 | u32 queues; |
| 1426 | int syserr; |
| 1427 | |
| 1428 | /* Read the ISR which also ACKs the interrupts */ |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1429 | efx_readd(efx, ®, FR_BZ_INT_ISR0); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1430 | queues = EFX_EXTRACT_DWORD(reg, 0, 31); |
| 1431 | |
| 1432 | /* Check to see if we have a serious error condition */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1433 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1434 | if (unlikely(syserr)) |
| 1435 | return falcon_fatal_interrupt(efx); |
| 1436 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1437 | /* Schedule processing of any interrupting queues */ |
Ben Hutchings | a9de9a7 | 2009-03-20 13:26:41 +0000 | [diff] [blame] | 1438 | efx_for_each_channel(channel, efx) { |
| 1439 | if ((queues & 1) || |
| 1440 | falcon_event_present( |
| 1441 | falcon_event(channel, channel->eventq_read_ptr))) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1442 | efx_schedule_channel(channel); |
Ben Hutchings | a9de9a7 | 2009-03-20 13:26:41 +0000 | [diff] [blame] | 1443 | result = IRQ_HANDLED; |
| 1444 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1445 | queues >>= 1; |
| 1446 | } |
| 1447 | |
Ben Hutchings | a9de9a7 | 2009-03-20 13:26:41 +0000 | [diff] [blame] | 1448 | if (result == IRQ_HANDLED) { |
| 1449 | efx->last_irq_cpu = raw_smp_processor_id(); |
| 1450 | EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", |
| 1451 | irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); |
| 1452 | } |
| 1453 | |
| 1454 | return result; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1455 | } |
| 1456 | |
| 1457 | |
| 1458 | static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id) |
| 1459 | { |
Ben Hutchings | d3208b5 | 2008-05-16 21:20:00 +0100 | [diff] [blame] | 1460 | struct efx_nic *efx = dev_id; |
| 1461 | efx_oword_t *int_ker = efx->irq_status.addr; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1462 | struct efx_channel *channel; |
| 1463 | int syserr; |
| 1464 | int queues; |
| 1465 | |
| 1466 | /* Check to see if this is our interrupt. If it isn't, we |
| 1467 | * exit without having touched the hardware. |
| 1468 | */ |
| 1469 | if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) { |
| 1470 | EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq, |
| 1471 | raw_smp_processor_id()); |
| 1472 | return IRQ_NONE; |
| 1473 | } |
| 1474 | efx->last_irq_cpu = raw_smp_processor_id(); |
| 1475 | EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", |
| 1476 | irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); |
| 1477 | |
| 1478 | /* Check to see if we have a serious error condition */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1479 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1480 | if (unlikely(syserr)) |
| 1481 | return falcon_fatal_interrupt(efx); |
| 1482 | |
| 1483 | /* Determine interrupting queues, clear interrupt status |
| 1484 | * register and acknowledge the device interrupt. |
| 1485 | */ |
| 1486 | BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS); |
| 1487 | queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS); |
| 1488 | EFX_ZERO_OWORD(*int_ker); |
| 1489 | wmb(); /* Ensure the vector is cleared before interrupt ack */ |
| 1490 | falcon_irq_ack_a1(efx); |
| 1491 | |
| 1492 | /* Schedule processing of any interrupting queues */ |
| 1493 | channel = &efx->channel[0]; |
| 1494 | while (queues) { |
| 1495 | if (queues & 0x01) |
| 1496 | efx_schedule_channel(channel); |
| 1497 | channel++; |
| 1498 | queues >>= 1; |
| 1499 | } |
| 1500 | |
| 1501 | return IRQ_HANDLED; |
| 1502 | } |
| 1503 | |
| 1504 | /* Handle an MSI interrupt from Falcon |
| 1505 | * |
| 1506 | * Handle an MSI hardware interrupt. This routine schedules event |
| 1507 | * queue processing. No interrupt acknowledgement cycle is necessary. |
| 1508 | * Also, we never need to check that the interrupt is for us, since |
| 1509 | * MSI interrupts cannot be shared. |
| 1510 | */ |
| 1511 | static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id) |
| 1512 | { |
Ben Hutchings | d3208b5 | 2008-05-16 21:20:00 +0100 | [diff] [blame] | 1513 | struct efx_channel *channel = dev_id; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1514 | struct efx_nic *efx = channel->efx; |
Ben Hutchings | d3208b5 | 2008-05-16 21:20:00 +0100 | [diff] [blame] | 1515 | efx_oword_t *int_ker = efx->irq_status.addr; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1516 | int syserr; |
| 1517 | |
| 1518 | efx->last_irq_cpu = raw_smp_processor_id(); |
| 1519 | EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", |
| 1520 | irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); |
| 1521 | |
| 1522 | /* Check to see if we have a serious error condition */ |
| 1523 | syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT); |
| 1524 | if (unlikely(syserr)) |
| 1525 | return falcon_fatal_interrupt(efx); |
| 1526 | |
| 1527 | /* Schedule processing of the channel */ |
| 1528 | efx_schedule_channel(channel); |
| 1529 | |
| 1530 | return IRQ_HANDLED; |
| 1531 | } |
| 1532 | |
| 1533 | |
| 1534 | /* Setup RSS indirection table. |
| 1535 | * This maps from the hash value of the packet to RXQ |
| 1536 | */ |
| 1537 | static void falcon_setup_rss_indir_table(struct efx_nic *efx) |
| 1538 | { |
| 1539 | int i = 0; |
| 1540 | unsigned long offset; |
| 1541 | efx_dword_t dword; |
| 1542 | |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 1543 | if (falcon_rev(efx) < FALCON_REV_B0) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1544 | return; |
| 1545 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1546 | for (offset = FR_BZ_RX_INDIRECTION_TBL; |
| 1547 | offset < FR_BZ_RX_INDIRECTION_TBL + 0x800; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1548 | offset += 0x10) { |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1549 | EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE, |
Ben Hutchings | 8831da7 | 2008-09-01 12:47:48 +0100 | [diff] [blame] | 1550 | i % efx->n_rx_queues); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1551 | efx_writed(efx, &dword, offset); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1552 | i++; |
| 1553 | } |
| 1554 | } |
| 1555 | |
| 1556 | /* Hook interrupt handler(s) |
| 1557 | * Try MSI and then legacy interrupts. |
| 1558 | */ |
| 1559 | int falcon_init_interrupt(struct efx_nic *efx) |
| 1560 | { |
| 1561 | struct efx_channel *channel; |
| 1562 | int rc; |
| 1563 | |
| 1564 | if (!EFX_INT_MODE_USE_MSI(efx)) { |
| 1565 | irq_handler_t handler; |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 1566 | if (falcon_rev(efx) >= FALCON_REV_B0) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1567 | handler = falcon_legacy_interrupt_b0; |
| 1568 | else |
| 1569 | handler = falcon_legacy_interrupt_a1; |
| 1570 | |
| 1571 | rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED, |
| 1572 | efx->name, efx); |
| 1573 | if (rc) { |
| 1574 | EFX_ERR(efx, "failed to hook legacy IRQ %d\n", |
| 1575 | efx->pci_dev->irq); |
| 1576 | goto fail1; |
| 1577 | } |
| 1578 | return 0; |
| 1579 | } |
| 1580 | |
| 1581 | /* Hook MSI or MSI-X interrupt */ |
Ben Hutchings | 64ee312 | 2008-09-01 12:47:38 +0100 | [diff] [blame] | 1582 | efx_for_each_channel(channel, efx) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1583 | rc = request_irq(channel->irq, falcon_msi_interrupt, |
| 1584 | IRQF_PROBE_SHARED, /* Not shared */ |
Ben Hutchings | 56536e9 | 2008-12-12 21:37:02 -0800 | [diff] [blame] | 1585 | channel->name, channel); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1586 | if (rc) { |
| 1587 | EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq); |
| 1588 | goto fail2; |
| 1589 | } |
| 1590 | } |
| 1591 | |
| 1592 | return 0; |
| 1593 | |
| 1594 | fail2: |
Ben Hutchings | 64ee312 | 2008-09-01 12:47:38 +0100 | [diff] [blame] | 1595 | efx_for_each_channel(channel, efx) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1596 | free_irq(channel->irq, channel); |
| 1597 | fail1: |
| 1598 | return rc; |
| 1599 | } |
| 1600 | |
| 1601 | void falcon_fini_interrupt(struct efx_nic *efx) |
| 1602 | { |
| 1603 | struct efx_channel *channel; |
| 1604 | efx_oword_t reg; |
| 1605 | |
| 1606 | /* Disable MSI/MSI-X interrupts */ |
Ben Hutchings | 64ee312 | 2008-09-01 12:47:38 +0100 | [diff] [blame] | 1607 | efx_for_each_channel(channel, efx) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1608 | if (channel->irq) |
| 1609 | free_irq(channel->irq, channel); |
Ben Hutchings | b347564 | 2008-05-16 21:15:49 +0100 | [diff] [blame] | 1610 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1611 | |
| 1612 | /* ACK legacy interrupt */ |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 1613 | if (falcon_rev(efx) >= FALCON_REV_B0) |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1614 | efx_reado(efx, ®, FR_BZ_INT_ISR0); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1615 | else |
| 1616 | falcon_irq_ack_a1(efx); |
| 1617 | |
| 1618 | /* Disable legacy interrupt */ |
| 1619 | if (efx->legacy_irq) |
| 1620 | free_irq(efx->legacy_irq, efx); |
| 1621 | } |
| 1622 | |
| 1623 | /************************************************************************** |
| 1624 | * |
| 1625 | * EEPROM/flash |
| 1626 | * |
| 1627 | ************************************************************************** |
| 1628 | */ |
| 1629 | |
Ben Hutchings | 23d30f0 | 2008-12-12 21:56:11 -0800 | [diff] [blame] | 1630 | #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1631 | |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 1632 | static int falcon_spi_poll(struct efx_nic *efx) |
| 1633 | { |
| 1634 | efx_oword_t reg; |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1635 | efx_reado(efx, ®, FR_AB_EE_SPI_HCMD); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1636 | return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0; |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 1637 | } |
| 1638 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1639 | /* Wait for SPI command completion */ |
| 1640 | static int falcon_spi_wait(struct efx_nic *efx) |
| 1641 | { |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 1642 | /* Most commands will finish quickly, so we start polling at |
| 1643 | * very short intervals. Sometimes the command may have to |
| 1644 | * wait for VPD or expansion ROM access outside of our |
| 1645 | * control, so we allow up to 100 ms. */ |
| 1646 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10); |
| 1647 | int i; |
| 1648 | |
| 1649 | for (i = 0; i < 10; i++) { |
| 1650 | if (!falcon_spi_poll(efx)) |
| 1651 | return 0; |
| 1652 | udelay(10); |
| 1653 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1654 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1655 | for (;;) { |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 1656 | if (!falcon_spi_poll(efx)) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1657 | return 0; |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1658 | if (time_after_eq(jiffies, timeout)) { |
| 1659 | EFX_ERR(efx, "timed out waiting for SPI\n"); |
| 1660 | return -ETIMEDOUT; |
| 1661 | } |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 1662 | schedule_timeout_uninterruptible(1); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1663 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1664 | } |
| 1665 | |
Ben Hutchings | f415072 | 2008-11-04 20:34:28 +0000 | [diff] [blame] | 1666 | int falcon_spi_cmd(const struct efx_spi_device *spi, |
| 1667 | unsigned int command, int address, |
Ben Hutchings | 23d30f0 | 2008-12-12 21:56:11 -0800 | [diff] [blame] | 1668 | const void *in, void *out, size_t len) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1669 | { |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1670 | struct efx_nic *efx = spi->efx; |
| 1671 | bool addressed = (address >= 0); |
| 1672 | bool reading = (out != NULL); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1673 | efx_oword_t reg; |
| 1674 | int rc; |
| 1675 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1676 | /* Input validation */ |
| 1677 | if (len > FALCON_SPI_MAX_LEN) |
| 1678 | return -EINVAL; |
Ben Hutchings | f415072 | 2008-11-04 20:34:28 +0000 | [diff] [blame] | 1679 | BUG_ON(!mutex_is_locked(&efx->spi_lock)); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1680 | |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 1681 | /* Check that previous command is not still running */ |
| 1682 | rc = falcon_spi_poll(efx); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1683 | if (rc) |
| 1684 | return rc; |
| 1685 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1686 | /* Program address register, if we have an address */ |
| 1687 | if (addressed) { |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1688 | EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1689 | efx_writeo(efx, ®, FR_AB_EE_SPI_HADR); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1690 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1691 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1692 | /* Program data register, if we have data */ |
| 1693 | if (in != NULL) { |
| 1694 | memcpy(®, in, len); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1695 | efx_writeo(efx, ®, FR_AB_EE_SPI_HDATA); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1696 | } |
| 1697 | |
| 1698 | /* Issue read/write command */ |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1699 | EFX_POPULATE_OWORD_7(reg, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1700 | FRF_AB_EE_SPI_HCMD_CMD_EN, 1, |
| 1701 | FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id, |
| 1702 | FRF_AB_EE_SPI_HCMD_DABCNT, len, |
| 1703 | FRF_AB_EE_SPI_HCMD_READ, reading, |
| 1704 | FRF_AB_EE_SPI_HCMD_DUBCNT, 0, |
| 1705 | FRF_AB_EE_SPI_HCMD_ADBCNT, |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1706 | (addressed ? spi->addr_len : 0), |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1707 | FRF_AB_EE_SPI_HCMD_ENC, command); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1708 | efx_writeo(efx, ®, FR_AB_EE_SPI_HCMD); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1709 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1710 | /* Wait for read/write to complete */ |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1711 | rc = falcon_spi_wait(efx); |
| 1712 | if (rc) |
| 1713 | return rc; |
| 1714 | |
| 1715 | /* Read data */ |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1716 | if (out != NULL) { |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1717 | efx_reado(efx, ®, FR_AB_EE_SPI_HDATA); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1718 | memcpy(out, ®, len); |
| 1719 | } |
| 1720 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1721 | return 0; |
| 1722 | } |
| 1723 | |
Ben Hutchings | 23d30f0 | 2008-12-12 21:56:11 -0800 | [diff] [blame] | 1724 | static size_t |
| 1725 | falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start) |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1726 | { |
| 1727 | return min(FALCON_SPI_MAX_LEN, |
| 1728 | (spi->block_size - (start & (spi->block_size - 1)))); |
| 1729 | } |
| 1730 | |
| 1731 | static inline u8 |
| 1732 | efx_spi_munge_command(const struct efx_spi_device *spi, |
| 1733 | const u8 command, const unsigned int address) |
| 1734 | { |
| 1735 | return command | (((address >> 8) & spi->munge_address) << 3); |
| 1736 | } |
| 1737 | |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 1738 | /* Wait up to 10 ms for buffered write completion */ |
| 1739 | int falcon_spi_wait_write(const struct efx_spi_device *spi) |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1740 | { |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 1741 | struct efx_nic *efx = spi->efx; |
| 1742 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1743 | u8 status; |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 1744 | int rc; |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1745 | |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 1746 | for (;;) { |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1747 | rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL, |
| 1748 | &status, sizeof(status)); |
| 1749 | if (rc) |
| 1750 | return rc; |
| 1751 | if (!(status & SPI_STATUS_NRDY)) |
| 1752 | return 0; |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 1753 | if (time_after_eq(jiffies, timeout)) { |
| 1754 | EFX_ERR(efx, "SPI write timeout on device %d" |
| 1755 | " last status=0x%02x\n", |
| 1756 | spi->device_id, status); |
| 1757 | return -ETIMEDOUT; |
| 1758 | } |
| 1759 | schedule_timeout_uninterruptible(1); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1760 | } |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1761 | } |
| 1762 | |
| 1763 | int falcon_spi_read(const struct efx_spi_device *spi, loff_t start, |
| 1764 | size_t len, size_t *retlen, u8 *buffer) |
| 1765 | { |
Ben Hutchings | 23d30f0 | 2008-12-12 21:56:11 -0800 | [diff] [blame] | 1766 | size_t block_len, pos = 0; |
| 1767 | unsigned int command; |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1768 | int rc = 0; |
| 1769 | |
| 1770 | while (pos < len) { |
Ben Hutchings | 23d30f0 | 2008-12-12 21:56:11 -0800 | [diff] [blame] | 1771 | block_len = min(len - pos, FALCON_SPI_MAX_LEN); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1772 | |
| 1773 | command = efx_spi_munge_command(spi, SPI_READ, start + pos); |
| 1774 | rc = falcon_spi_cmd(spi, command, start + pos, NULL, |
| 1775 | buffer + pos, block_len); |
| 1776 | if (rc) |
| 1777 | break; |
| 1778 | pos += block_len; |
| 1779 | |
| 1780 | /* Avoid locking up the system */ |
| 1781 | cond_resched(); |
| 1782 | if (signal_pending(current)) { |
| 1783 | rc = -EINTR; |
| 1784 | break; |
| 1785 | } |
| 1786 | } |
| 1787 | |
| 1788 | if (retlen) |
| 1789 | *retlen = pos; |
| 1790 | return rc; |
| 1791 | } |
| 1792 | |
| 1793 | int falcon_spi_write(const struct efx_spi_device *spi, loff_t start, |
| 1794 | size_t len, size_t *retlen, const u8 *buffer) |
| 1795 | { |
| 1796 | u8 verify_buffer[FALCON_SPI_MAX_LEN]; |
Ben Hutchings | 23d30f0 | 2008-12-12 21:56:11 -0800 | [diff] [blame] | 1797 | size_t block_len, pos = 0; |
| 1798 | unsigned int command; |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1799 | int rc = 0; |
| 1800 | |
| 1801 | while (pos < len) { |
| 1802 | rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0); |
| 1803 | if (rc) |
| 1804 | break; |
| 1805 | |
Ben Hutchings | 23d30f0 | 2008-12-12 21:56:11 -0800 | [diff] [blame] | 1806 | block_len = min(len - pos, |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1807 | falcon_spi_write_limit(spi, start + pos)); |
| 1808 | command = efx_spi_munge_command(spi, SPI_WRITE, start + pos); |
| 1809 | rc = falcon_spi_cmd(spi, command, start + pos, |
| 1810 | buffer + pos, NULL, block_len); |
| 1811 | if (rc) |
| 1812 | break; |
| 1813 | |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 1814 | rc = falcon_spi_wait_write(spi); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1815 | if (rc) |
| 1816 | break; |
| 1817 | |
| 1818 | command = efx_spi_munge_command(spi, SPI_READ, start + pos); |
| 1819 | rc = falcon_spi_cmd(spi, command, start + pos, |
| 1820 | NULL, verify_buffer, block_len); |
| 1821 | if (memcmp(verify_buffer, buffer + pos, block_len)) { |
| 1822 | rc = -EIO; |
| 1823 | break; |
| 1824 | } |
| 1825 | |
| 1826 | pos += block_len; |
| 1827 | |
| 1828 | /* Avoid locking up the system */ |
| 1829 | cond_resched(); |
| 1830 | if (signal_pending(current)) { |
| 1831 | rc = -EINTR; |
| 1832 | break; |
| 1833 | } |
| 1834 | } |
| 1835 | |
| 1836 | if (retlen) |
| 1837 | *retlen = pos; |
| 1838 | return rc; |
| 1839 | } |
| 1840 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1841 | /************************************************************************** |
| 1842 | * |
| 1843 | * MAC wrapper |
| 1844 | * |
| 1845 | ************************************************************************** |
| 1846 | */ |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 1847 | |
| 1848 | static int falcon_reset_macs(struct efx_nic *efx) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1849 | { |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 1850 | efx_oword_t reg; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1851 | int count; |
| 1852 | |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 1853 | if (falcon_rev(efx) < FALCON_REV_B0) { |
| 1854 | /* It's not safe to use GLB_CTL_REG to reset the |
| 1855 | * macs, so instead use the internal MAC resets |
| 1856 | */ |
| 1857 | if (!EFX_IS10G(efx)) { |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1858 | EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1859 | efx_writeo(efx, ®, FR_AB_GM_CFG1); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 1860 | udelay(1000); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1861 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1862 | EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1863 | efx_writeo(efx, ®, FR_AB_GM_CFG1); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 1864 | udelay(1000); |
| 1865 | return 0; |
| 1866 | } else { |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1867 | EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1868 | efx_writeo(efx, ®, FR_AB_XM_GLB_CFG); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 1869 | |
| 1870 | for (count = 0; count < 10000; count++) { |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1871 | efx_reado(efx, ®, FR_AB_XM_GLB_CFG); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1872 | if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) == |
| 1873 | 0) |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 1874 | return 0; |
| 1875 | udelay(10); |
| 1876 | } |
| 1877 | |
| 1878 | EFX_ERR(efx, "timed out waiting for XMAC core reset\n"); |
| 1879 | return -ETIMEDOUT; |
| 1880 | } |
| 1881 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1882 | |
| 1883 | /* MAC stats will fail whilst the TX fifo is draining. Serialise |
| 1884 | * the drain sequence with the statistics fetch */ |
Ben Hutchings | 1974cc2 | 2009-01-29 18:00:07 +0000 | [diff] [blame] | 1885 | efx_stats_disable(efx); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1886 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1887 | efx_reado(efx, ®, FR_AB_MAC_CTRL); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1888 | EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, 1); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1889 | efx_writeo(efx, ®, FR_AB_MAC_CTRL); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1890 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1891 | efx_reado(efx, ®, FR_AB_GLB_CTL); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1892 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1); |
| 1893 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1); |
| 1894 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1895 | efx_writeo(efx, ®, FR_AB_GLB_CTL); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1896 | |
| 1897 | count = 0; |
| 1898 | while (1) { |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1899 | efx_reado(efx, ®, FR_AB_GLB_CTL); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1900 | if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) && |
| 1901 | !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) && |
| 1902 | !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1903 | EFX_LOG(efx, "Completed MAC reset after %d loops\n", |
| 1904 | count); |
| 1905 | break; |
| 1906 | } |
| 1907 | if (count > 20) { |
| 1908 | EFX_ERR(efx, "MAC reset failed\n"); |
| 1909 | break; |
| 1910 | } |
| 1911 | count++; |
| 1912 | udelay(10); |
| 1913 | } |
| 1914 | |
Ben Hutchings | 1974cc2 | 2009-01-29 18:00:07 +0000 | [diff] [blame] | 1915 | efx_stats_enable(efx); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1916 | |
| 1917 | /* If we've reset the EM block and the link is up, then |
| 1918 | * we'll have to kick the XAUI link so the PHY can recover */ |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 1919 | if (efx->link_up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx)) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1920 | falcon_reset_xaui(efx); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 1921 | |
| 1922 | return 0; |
| 1923 | } |
| 1924 | |
| 1925 | void falcon_drain_tx_fifo(struct efx_nic *efx) |
| 1926 | { |
| 1927 | efx_oword_t reg; |
| 1928 | |
| 1929 | if ((falcon_rev(efx) < FALCON_REV_B0) || |
| 1930 | (efx->loopback_mode != LOOPBACK_NONE)) |
| 1931 | return; |
| 1932 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1933 | efx_reado(efx, ®, FR_AB_MAC_CTRL); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 1934 | /* There is no point in draining more than once */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1935 | if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN)) |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 1936 | return; |
| 1937 | |
| 1938 | falcon_reset_macs(efx); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1939 | } |
| 1940 | |
| 1941 | void falcon_deconfigure_mac_wrapper(struct efx_nic *efx) |
| 1942 | { |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 1943 | efx_oword_t reg; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1944 | |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 1945 | if (falcon_rev(efx) < FALCON_REV_B0) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1946 | return; |
| 1947 | |
| 1948 | /* Isolate the MAC -> RX */ |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1949 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1950 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1951 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1952 | |
| 1953 | if (!efx->link_up) |
| 1954 | falcon_drain_tx_fifo(efx); |
| 1955 | } |
| 1956 | |
| 1957 | void falcon_reconfigure_mac_wrapper(struct efx_nic *efx) |
| 1958 | { |
| 1959 | efx_oword_t reg; |
| 1960 | int link_speed; |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 1961 | bool tx_fc; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1962 | |
Ben Hutchings | f31a45d | 2008-12-12 21:43:33 -0800 | [diff] [blame] | 1963 | switch (efx->link_speed) { |
| 1964 | case 10000: link_speed = 3; break; |
| 1965 | case 1000: link_speed = 2; break; |
| 1966 | case 100: link_speed = 1; break; |
| 1967 | default: link_speed = 0; break; |
| 1968 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1969 | /* MAC_LINK_STATUS controls MAC backpressure but doesn't work |
| 1970 | * as advertised. Disable to ensure packets are not |
| 1971 | * indefinitely held and TX queue can be flushed at any point |
| 1972 | * while the link is down. */ |
| 1973 | EFX_POPULATE_OWORD_5(reg, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1974 | FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */, |
| 1975 | FRF_AB_MAC_BCAD_ACPT, 1, |
| 1976 | FRF_AB_MAC_UC_PROM, efx->promiscuous, |
| 1977 | FRF_AB_MAC_LINK_STATUS, 1, /* always set */ |
| 1978 | FRF_AB_MAC_SPEED, link_speed); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1979 | /* On B0, MAC backpressure can be disabled and packets get |
| 1980 | * discarded. */ |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 1981 | if (falcon_rev(efx) >= FALCON_REV_B0) { |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1982 | EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1983 | !efx->link_up); |
| 1984 | } |
| 1985 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1986 | efx_writeo(efx, ®, FR_AB_MAC_CTRL); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1987 | |
| 1988 | /* Restore the multicast hash registers. */ |
| 1989 | falcon_set_multicast_hash(efx); |
| 1990 | |
| 1991 | /* Transmission of pause frames when RX crosses the threshold is |
| 1992 | * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL. |
| 1993 | * Action on receipt of pause frames is controller by XM_DIS_FCNTL */ |
Ben Hutchings | 04cc8ca | 2008-12-12 21:50:46 -0800 | [diff] [blame] | 1994 | tx_fc = !!(efx->link_fc & EFX_FC_TX); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1995 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1996 | EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, tx_fc); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1997 | |
| 1998 | /* Unisolate the MAC -> RX */ |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 1999 | if (falcon_rev(efx) >= FALCON_REV_B0) |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2000 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2001 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2002 | } |
| 2003 | |
| 2004 | int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset) |
| 2005 | { |
| 2006 | efx_oword_t reg; |
| 2007 | u32 *dma_done; |
| 2008 | int i; |
| 2009 | |
| 2010 | if (disable_dma_stats) |
| 2011 | return 0; |
| 2012 | |
| 2013 | /* Statistics fetch will fail if the MAC is in TX drain */ |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 2014 | if (falcon_rev(efx) >= FALCON_REV_B0) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2015 | efx_oword_t temp; |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2016 | efx_reado(efx, &temp, FR_AB_MAC_CTRL); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2017 | if (EFX_OWORD_FIELD(temp, FRF_BB_TXFIFO_DRAIN_EN)) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2018 | return 0; |
| 2019 | } |
| 2020 | |
| 2021 | dma_done = (efx->stats_buffer.addr + done_offset); |
| 2022 | *dma_done = FALCON_STATS_NOT_DONE; |
| 2023 | wmb(); /* ensure done flag is clear */ |
| 2024 | |
| 2025 | /* Initiate DMA transfer of stats */ |
| 2026 | EFX_POPULATE_OWORD_2(reg, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2027 | FRF_AB_MAC_STAT_DMA_CMD, 1, |
| 2028 | FRF_AB_MAC_STAT_DMA_ADR, |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2029 | efx->stats_buffer.dma_addr); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2030 | efx_writeo(efx, ®, FR_AB_MAC_STAT_DMA); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2031 | |
| 2032 | /* Wait for transfer to complete */ |
| 2033 | for (i = 0; i < 400; i++) { |
Ben Hutchings | 1d0680f | 2008-09-01 12:50:08 +0100 | [diff] [blame] | 2034 | if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) { |
| 2035 | rmb(); /* Ensure the stats are valid. */ |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2036 | return 0; |
Ben Hutchings | 1d0680f | 2008-09-01 12:50:08 +0100 | [diff] [blame] | 2037 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2038 | udelay(10); |
| 2039 | } |
| 2040 | |
| 2041 | EFX_ERR(efx, "timed out waiting for statistics\n"); |
| 2042 | return -ETIMEDOUT; |
| 2043 | } |
| 2044 | |
| 2045 | /************************************************************************** |
| 2046 | * |
| 2047 | * PHY access via GMII |
| 2048 | * |
| 2049 | ************************************************************************** |
| 2050 | */ |
| 2051 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2052 | /* Wait for GMII access to complete */ |
| 2053 | static int falcon_gmii_wait(struct efx_nic *efx) |
| 2054 | { |
| 2055 | efx_dword_t md_stat; |
| 2056 | int count; |
| 2057 | |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 2058 | /* wait upto 50ms - taken max from datasheet */ |
| 2059 | for (count = 0; count < 5000; count++) { |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2060 | efx_readd(efx, &md_stat, FR_AB_MD_STAT); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2061 | if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) { |
| 2062 | if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 || |
| 2063 | EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2064 | EFX_ERR(efx, "error from GMII access " |
| 2065 | EFX_DWORD_FMT"\n", |
| 2066 | EFX_DWORD_VAL(md_stat)); |
| 2067 | return -EIO; |
| 2068 | } |
| 2069 | return 0; |
| 2070 | } |
| 2071 | udelay(10); |
| 2072 | } |
| 2073 | EFX_ERR(efx, "timed out waiting for GMII\n"); |
| 2074 | return -ETIMEDOUT; |
| 2075 | } |
| 2076 | |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 2077 | /* Write an MDIO register of a PHY connected to Falcon. */ |
| 2078 | static int falcon_mdio_write(struct net_device *net_dev, |
| 2079 | int prtad, int devad, u16 addr, u16 value) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2080 | { |
Ben Hutchings | 767e468 | 2008-09-01 12:43:14 +0100 | [diff] [blame] | 2081 | struct efx_nic *efx = netdev_priv(net_dev); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2082 | efx_oword_t reg; |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 2083 | int rc; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2084 | |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 2085 | EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n", |
| 2086 | prtad, devad, addr, value); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2087 | |
| 2088 | spin_lock_bh(&efx->phy_lock); |
| 2089 | |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 2090 | /* Check MDIO not currently being accessed */ |
| 2091 | rc = falcon_gmii_wait(efx); |
| 2092 | if (rc) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2093 | goto out; |
| 2094 | |
| 2095 | /* Write the address/ID register */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2096 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2097 | efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2098 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2099 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, |
| 2100 | FRF_AB_MD_DEV_ADR, devad); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2101 | efx_writeo(efx, ®, FR_AB_MD_ID); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2102 | |
| 2103 | /* Write data */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2104 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2105 | efx_writeo(efx, ®, FR_AB_MD_TXD); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2106 | |
| 2107 | EFX_POPULATE_OWORD_2(reg, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2108 | FRF_AB_MD_WRC, 1, |
| 2109 | FRF_AB_MD_GC, 0); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2110 | efx_writeo(efx, ®, FR_AB_MD_CS); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2111 | |
| 2112 | /* Wait for data to be written */ |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 2113 | rc = falcon_gmii_wait(efx); |
| 2114 | if (rc) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2115 | /* Abort the write operation */ |
| 2116 | EFX_POPULATE_OWORD_2(reg, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2117 | FRF_AB_MD_WRC, 0, |
| 2118 | FRF_AB_MD_GC, 1); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2119 | efx_writeo(efx, ®, FR_AB_MD_CS); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2120 | udelay(10); |
| 2121 | } |
| 2122 | |
| 2123 | out: |
| 2124 | spin_unlock_bh(&efx->phy_lock); |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 2125 | return rc; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2126 | } |
| 2127 | |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 2128 | /* Read an MDIO register of a PHY connected to Falcon. */ |
| 2129 | static int falcon_mdio_read(struct net_device *net_dev, |
| 2130 | int prtad, int devad, u16 addr) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2131 | { |
Ben Hutchings | 767e468 | 2008-09-01 12:43:14 +0100 | [diff] [blame] | 2132 | struct efx_nic *efx = netdev_priv(net_dev); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2133 | efx_oword_t reg; |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 2134 | int rc; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2135 | |
| 2136 | spin_lock_bh(&efx->phy_lock); |
| 2137 | |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 2138 | /* Check MDIO not currently being accessed */ |
| 2139 | rc = falcon_gmii_wait(efx); |
| 2140 | if (rc) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2141 | goto out; |
| 2142 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2143 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2144 | efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2145 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2146 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, |
| 2147 | FRF_AB_MD_DEV_ADR, devad); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2148 | efx_writeo(efx, ®, FR_AB_MD_ID); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2149 | |
| 2150 | /* Request data to be read */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2151 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2152 | efx_writeo(efx, ®, FR_AB_MD_CS); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2153 | |
| 2154 | /* Wait for data to become available */ |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 2155 | rc = falcon_gmii_wait(efx); |
| 2156 | if (rc == 0) { |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2157 | efx_reado(efx, ®, FR_AB_MD_RXD); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2158 | rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD); |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 2159 | EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n", |
| 2160 | prtad, devad, addr, rc); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2161 | } else { |
| 2162 | /* Abort the read operation */ |
| 2163 | EFX_POPULATE_OWORD_2(reg, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2164 | FRF_AB_MD_RIC, 0, |
| 2165 | FRF_AB_MD_GC, 1); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2166 | efx_writeo(efx, ®, FR_AB_MD_CS); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2167 | |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 2168 | EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n", |
| 2169 | prtad, devad, addr, rc); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2170 | } |
| 2171 | |
| 2172 | out: |
| 2173 | spin_unlock_bh(&efx->phy_lock); |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 2174 | return rc; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2175 | } |
| 2176 | |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 2177 | int falcon_switch_mac(struct efx_nic *efx) |
| 2178 | { |
| 2179 | struct efx_mac_operations *old_mac_op = efx->mac_op; |
| 2180 | efx_oword_t nic_stat; |
| 2181 | unsigned strap_val; |
Ben Hutchings | 1974cc2 | 2009-01-29 18:00:07 +0000 | [diff] [blame] | 2182 | int rc = 0; |
| 2183 | |
| 2184 | /* Don't try to fetch MAC stats while we're switching MACs */ |
| 2185 | efx_stats_disable(efx); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 2186 | |
| 2187 | /* Internal loopbacks override the phy speed setting */ |
| 2188 | if (efx->loopback_mode == LOOPBACK_GMAC) { |
| 2189 | efx->link_speed = 1000; |
| 2190 | efx->link_fd = true; |
| 2191 | } else if (LOOPBACK_INTERNAL(efx)) { |
| 2192 | efx->link_speed = 10000; |
| 2193 | efx->link_fd = true; |
| 2194 | } |
| 2195 | |
Steve Hodgson | 0cc128387 | 2009-01-29 17:49:59 +0000 | [diff] [blame] | 2196 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 2197 | efx->mac_op = (EFX_IS10G(efx) ? |
| 2198 | &falcon_xmac_operations : &falcon_gmac_operations); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 2199 | |
Steve Hodgson | 0cc128387 | 2009-01-29 17:49:59 +0000 | [diff] [blame] | 2200 | /* Always push the NIC_STAT_REG setting even if the mac hasn't |
| 2201 | * changed, because this function is run post online reset */ |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2202 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 2203 | strap_val = EFX_IS10G(efx) ? 5 : 3; |
| 2204 | if (falcon_rev(efx) >= FALCON_REV_B0) { |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2205 | EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1); |
| 2206 | EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2207 | efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 2208 | } else { |
| 2209 | /* Falcon A1 does not support 1G/10G speed switching |
| 2210 | * and must not be used with a PHY that does. */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2211 | BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) != |
| 2212 | strap_val); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 2213 | } |
| 2214 | |
Steve Hodgson | 0cc128387 | 2009-01-29 17:49:59 +0000 | [diff] [blame] | 2215 | if (old_mac_op == efx->mac_op) |
Ben Hutchings | 1974cc2 | 2009-01-29 18:00:07 +0000 | [diff] [blame] | 2216 | goto out; |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 2217 | |
| 2218 | EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G'); |
Steve Hodgson | 0cc128387 | 2009-01-29 17:49:59 +0000 | [diff] [blame] | 2219 | /* Not all macs support a mac-level link state */ |
| 2220 | efx->mac_up = true; |
| 2221 | |
Ben Hutchings | 1974cc2 | 2009-01-29 18:00:07 +0000 | [diff] [blame] | 2222 | rc = falcon_reset_macs(efx); |
| 2223 | out: |
| 2224 | efx_stats_enable(efx); |
| 2225 | return rc; |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 2226 | } |
| 2227 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2228 | /* This call is responsible for hooking in the MAC and PHY operations */ |
| 2229 | int falcon_probe_port(struct efx_nic *efx) |
| 2230 | { |
| 2231 | int rc; |
| 2232 | |
Ben Hutchings | 96c45726 | 2009-10-23 08:32:42 +0000 | [diff] [blame] | 2233 | switch (efx->phy_type) { |
| 2234 | case PHY_TYPE_SFX7101: |
| 2235 | efx->phy_op = &falcon_sfx7101_phy_ops; |
| 2236 | break; |
| 2237 | case PHY_TYPE_SFT9001A: |
| 2238 | case PHY_TYPE_SFT9001B: |
| 2239 | efx->phy_op = &falcon_sft9001_phy_ops; |
| 2240 | break; |
| 2241 | case PHY_TYPE_QT2022C2: |
| 2242 | case PHY_TYPE_QT2025C: |
Ben Hutchings | b37b62f | 2009-10-23 08:33:42 +0000 | [diff] [blame] | 2243 | efx->phy_op = &falcon_qt202x_phy_ops; |
Ben Hutchings | 96c45726 | 2009-10-23 08:32:42 +0000 | [diff] [blame] | 2244 | break; |
| 2245 | default: |
| 2246 | EFX_ERR(efx, "Unknown PHY type %d\n", |
| 2247 | efx->phy_type); |
| 2248 | return -ENODEV; |
| 2249 | } |
| 2250 | |
| 2251 | if (efx->phy_op->macs & EFX_XMAC) |
| 2252 | efx->loopback_modes |= ((1 << LOOPBACK_XGMII) | |
| 2253 | (1 << LOOPBACK_XGXS) | |
| 2254 | (1 << LOOPBACK_XAUI)); |
| 2255 | if (efx->phy_op->macs & EFX_GMAC) |
| 2256 | efx->loopback_modes |= (1 << LOOPBACK_GMAC); |
| 2257 | efx->loopback_modes |= efx->phy_op->loopbacks; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2258 | |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 2259 | /* Set up MDIO structure for PHY */ |
| 2260 | efx->mdio.mmds = efx->phy_op->mmds; |
| 2261 | efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; |
| 2262 | efx->mdio.mdio_read = falcon_mdio_read; |
| 2263 | efx->mdio.mdio_write = falcon_mdio_write; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2264 | |
| 2265 | /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */ |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 2266 | if (falcon_rev(efx) >= FALCON_REV_B0) |
Ben Hutchings | 04cc8ca | 2008-12-12 21:50:46 -0800 | [diff] [blame] | 2267 | efx->wanted_fc = EFX_FC_RX | EFX_FC_TX; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2268 | else |
Ben Hutchings | 04cc8ca | 2008-12-12 21:50:46 -0800 | [diff] [blame] | 2269 | efx->wanted_fc = EFX_FC_RX; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2270 | |
| 2271 | /* Allocate buffer for stats */ |
| 2272 | rc = falcon_alloc_buffer(efx, &efx->stats_buffer, |
| 2273 | FALCON_MAC_STATS_SIZE); |
| 2274 | if (rc) |
| 2275 | return rc; |
Jaswinder Singh Rajput | 9c8976a | 2009-02-11 23:49:52 +0530 | [diff] [blame] | 2276 | EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n", |
| 2277 | (u64)efx->stats_buffer.dma_addr, |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2278 | efx->stats_buffer.addr, |
Jaswinder Singh Rajput | 9c8976a | 2009-02-11 23:49:52 +0530 | [diff] [blame] | 2279 | (u64)virt_to_phys(efx->stats_buffer.addr)); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2280 | |
| 2281 | return 0; |
| 2282 | } |
| 2283 | |
| 2284 | void falcon_remove_port(struct efx_nic *efx) |
| 2285 | { |
| 2286 | falcon_free_buffer(efx, &efx->stats_buffer); |
| 2287 | } |
| 2288 | |
| 2289 | /************************************************************************** |
| 2290 | * |
| 2291 | * Multicast filtering |
| 2292 | * |
| 2293 | ************************************************************************** |
| 2294 | */ |
| 2295 | |
| 2296 | void falcon_set_multicast_hash(struct efx_nic *efx) |
| 2297 | { |
| 2298 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; |
| 2299 | |
| 2300 | /* Broadcast packets go through the multicast hash filter. |
| 2301 | * ether_crc_le() of the broadcast address is 0xbe2612ff |
| 2302 | * so we always add bit 0xff to the mask. |
| 2303 | */ |
| 2304 | set_bit_le(0xff, mc_hash->byte); |
| 2305 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2306 | efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0); |
| 2307 | efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2308 | } |
| 2309 | |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2310 | |
| 2311 | /************************************************************************** |
| 2312 | * |
| 2313 | * Falcon test code |
| 2314 | * |
| 2315 | **************************************************************************/ |
| 2316 | |
| 2317 | int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out) |
| 2318 | { |
| 2319 | struct falcon_nvconfig *nvconfig; |
| 2320 | struct efx_spi_device *spi; |
| 2321 | void *region; |
| 2322 | int rc, magic_num, struct_ver; |
| 2323 | __le16 *word, *limit; |
| 2324 | u32 csum; |
| 2325 | |
Ben Hutchings | 2f7f573 | 2008-12-12 21:34:25 -0800 | [diff] [blame] | 2326 | spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom; |
| 2327 | if (!spi) |
| 2328 | return -EINVAL; |
| 2329 | |
Ben Hutchings | 0a95f56 | 2008-11-04 20:33:11 +0000 | [diff] [blame] | 2330 | region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL); |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2331 | if (!region) |
| 2332 | return -ENOMEM; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2333 | nvconfig = region + FALCON_NVCONFIG_OFFSET; |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2334 | |
Ben Hutchings | f415072 | 2008-11-04 20:34:28 +0000 | [diff] [blame] | 2335 | mutex_lock(&efx->spi_lock); |
Ben Hutchings | 0a95f56 | 2008-11-04 20:33:11 +0000 | [diff] [blame] | 2336 | rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region); |
Ben Hutchings | f415072 | 2008-11-04 20:34:28 +0000 | [diff] [blame] | 2337 | mutex_unlock(&efx->spi_lock); |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2338 | if (rc) { |
| 2339 | EFX_ERR(efx, "Failed to read %s\n", |
| 2340 | efx->spi_flash ? "flash" : "EEPROM"); |
| 2341 | rc = -EIO; |
| 2342 | goto out; |
| 2343 | } |
| 2344 | |
| 2345 | magic_num = le16_to_cpu(nvconfig->board_magic_num); |
| 2346 | struct_ver = le16_to_cpu(nvconfig->board_struct_ver); |
| 2347 | |
| 2348 | rc = -EINVAL; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2349 | if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) { |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2350 | EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num); |
| 2351 | goto out; |
| 2352 | } |
| 2353 | if (struct_ver < 2) { |
| 2354 | EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver); |
| 2355 | goto out; |
| 2356 | } else if (struct_ver < 4) { |
| 2357 | word = &nvconfig->board_magic_num; |
| 2358 | limit = (__le16 *) (nvconfig + 1); |
| 2359 | } else { |
| 2360 | word = region; |
Ben Hutchings | 0a95f56 | 2008-11-04 20:33:11 +0000 | [diff] [blame] | 2361 | limit = region + FALCON_NVCONFIG_END; |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2362 | } |
| 2363 | for (csum = 0; word < limit; ++word) |
| 2364 | csum += le16_to_cpu(*word); |
| 2365 | |
| 2366 | if (~csum & 0xffff) { |
| 2367 | EFX_ERR(efx, "NVRAM has incorrect checksum\n"); |
| 2368 | goto out; |
| 2369 | } |
| 2370 | |
| 2371 | rc = 0; |
| 2372 | if (nvconfig_out) |
| 2373 | memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig)); |
| 2374 | |
| 2375 | out: |
| 2376 | kfree(region); |
| 2377 | return rc; |
| 2378 | } |
| 2379 | |
| 2380 | /* Registers tested in the falcon register test */ |
| 2381 | static struct { |
| 2382 | unsigned address; |
| 2383 | efx_oword_t mask; |
| 2384 | } efx_test_registers[] = { |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2385 | { FR_AZ_ADR_REGION, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2386 | EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2387 | { FR_AZ_RX_CFG, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2388 | EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2389 | { FR_AZ_TX_CFG, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2390 | EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2391 | { FR_AZ_TX_RESERVED, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2392 | EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2393 | { FR_AB_MAC_CTRL, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2394 | EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2395 | { FR_AZ_SRM_TX_DC_CFG, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2396 | EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2397 | { FR_AZ_RX_DC_CFG, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2398 | EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2399 | { FR_AZ_RX_DC_PF_WM, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2400 | EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2401 | { FR_BZ_DP_CTRL, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2402 | EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2403 | { FR_AB_GM_CFG2, |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 2404 | EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2405 | { FR_AB_GMF_CFG0, |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 2406 | EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2407 | { FR_AB_XM_GLB_CFG, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2408 | EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2409 | { FR_AB_XM_TX_CFG, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2410 | EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2411 | { FR_AB_XM_RX_CFG, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2412 | EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2413 | { FR_AB_XM_RX_PARAM, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2414 | EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2415 | { FR_AB_XM_FC, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2416 | EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2417 | { FR_AB_XM_ADR_LO, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2418 | EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2419 | { FR_AB_XX_SD_CTL, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2420 | EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) }, |
| 2421 | }; |
| 2422 | |
| 2423 | static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b, |
| 2424 | const efx_oword_t *mask) |
| 2425 | { |
| 2426 | return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) || |
| 2427 | ((a->u64[1] ^ b->u64[1]) & mask->u64[1]); |
| 2428 | } |
| 2429 | |
| 2430 | int falcon_test_registers(struct efx_nic *efx) |
| 2431 | { |
| 2432 | unsigned address = 0, i, j; |
| 2433 | efx_oword_t mask, imask, original, reg, buf; |
| 2434 | |
| 2435 | /* Falcon should be in loopback to isolate the XMAC from the PHY */ |
| 2436 | WARN_ON(!LOOPBACK_INTERNAL(efx)); |
| 2437 | |
| 2438 | for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) { |
| 2439 | address = efx_test_registers[i].address; |
| 2440 | mask = imask = efx_test_registers[i].mask; |
| 2441 | EFX_INVERT_OWORD(imask); |
| 2442 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2443 | efx_reado(efx, &original, address); |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2444 | |
| 2445 | /* bit sweep on and off */ |
| 2446 | for (j = 0; j < 128; j++) { |
| 2447 | if (!EFX_EXTRACT_OWORD32(mask, j, j)) |
| 2448 | continue; |
| 2449 | |
| 2450 | /* Test this testable bit can be set in isolation */ |
| 2451 | EFX_AND_OWORD(reg, original, mask); |
| 2452 | EFX_SET_OWORD32(reg, j, j, 1); |
| 2453 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2454 | efx_writeo(efx, ®, address); |
| 2455 | efx_reado(efx, &buf, address); |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2456 | |
| 2457 | if (efx_masked_compare_oword(®, &buf, &mask)) |
| 2458 | goto fail; |
| 2459 | |
| 2460 | /* Test this testable bit can be cleared in isolation */ |
| 2461 | EFX_OR_OWORD(reg, original, mask); |
| 2462 | EFX_SET_OWORD32(reg, j, j, 0); |
| 2463 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2464 | efx_writeo(efx, ®, address); |
| 2465 | efx_reado(efx, &buf, address); |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2466 | |
| 2467 | if (efx_masked_compare_oword(®, &buf, &mask)) |
| 2468 | goto fail; |
| 2469 | } |
| 2470 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2471 | efx_writeo(efx, &original, address); |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2472 | } |
| 2473 | |
| 2474 | return 0; |
| 2475 | |
| 2476 | fail: |
| 2477 | EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT |
| 2478 | " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg), |
| 2479 | EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask)); |
| 2480 | return -EIO; |
| 2481 | } |
| 2482 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2483 | /************************************************************************** |
| 2484 | * |
| 2485 | * Device reset |
| 2486 | * |
| 2487 | ************************************************************************** |
| 2488 | */ |
| 2489 | |
| 2490 | /* Resets NIC to known state. This routine must be called in process |
| 2491 | * context and is allowed to sleep. */ |
| 2492 | int falcon_reset_hw(struct efx_nic *efx, enum reset_type method) |
| 2493 | { |
| 2494 | struct falcon_nic_data *nic_data = efx->nic_data; |
| 2495 | efx_oword_t glb_ctl_reg_ker; |
| 2496 | int rc; |
| 2497 | |
| 2498 | EFX_LOG(efx, "performing hardware reset (%d)\n", method); |
| 2499 | |
| 2500 | /* Initiate device reset */ |
| 2501 | if (method == RESET_TYPE_WORLD) { |
| 2502 | rc = pci_save_state(efx->pci_dev); |
| 2503 | if (rc) { |
| 2504 | EFX_ERR(efx, "failed to backup PCI state of primary " |
| 2505 | "function prior to hardware reset\n"); |
| 2506 | goto fail1; |
| 2507 | } |
| 2508 | if (FALCON_IS_DUAL_FUNC(efx)) { |
| 2509 | rc = pci_save_state(nic_data->pci_dev2); |
| 2510 | if (rc) { |
| 2511 | EFX_ERR(efx, "failed to backup PCI state of " |
| 2512 | "secondary function prior to " |
| 2513 | "hardware reset\n"); |
| 2514 | goto fail2; |
| 2515 | } |
| 2516 | } |
| 2517 | |
| 2518 | EFX_POPULATE_OWORD_2(glb_ctl_reg_ker, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2519 | FRF_AB_EXT_PHY_RST_DUR, |
| 2520 | FFE_AB_EXT_PHY_RST_DUR_10240US, |
| 2521 | FRF_AB_SWRST, 1); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2522 | } else { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2523 | EFX_POPULATE_OWORD_7(glb_ctl_reg_ker, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2524 | /* exclude PHY from "invisible" reset */ |
| 2525 | FRF_AB_EXT_PHY_RST_CTL, |
| 2526 | method == RESET_TYPE_INVISIBLE, |
| 2527 | /* exclude EEPROM/flash and PCIe */ |
| 2528 | FRF_AB_PCIE_CORE_RST_CTL, 1, |
| 2529 | FRF_AB_PCIE_NSTKY_RST_CTL, 1, |
| 2530 | FRF_AB_PCIE_SD_RST_CTL, 1, |
| 2531 | FRF_AB_EE_RST_CTL, 1, |
| 2532 | FRF_AB_EXT_PHY_RST_DUR, |
| 2533 | FFE_AB_EXT_PHY_RST_DUR_10240US, |
| 2534 | FRF_AB_SWRST, 1); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2535 | } |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2536 | efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2537 | |
| 2538 | EFX_LOG(efx, "waiting for hardware reset\n"); |
| 2539 | schedule_timeout_uninterruptible(HZ / 20); |
| 2540 | |
| 2541 | /* Restore PCI configuration if needed */ |
| 2542 | if (method == RESET_TYPE_WORLD) { |
| 2543 | if (FALCON_IS_DUAL_FUNC(efx)) { |
| 2544 | rc = pci_restore_state(nic_data->pci_dev2); |
| 2545 | if (rc) { |
| 2546 | EFX_ERR(efx, "failed to restore PCI config for " |
| 2547 | "the secondary function\n"); |
| 2548 | goto fail3; |
| 2549 | } |
| 2550 | } |
| 2551 | rc = pci_restore_state(efx->pci_dev); |
| 2552 | if (rc) { |
| 2553 | EFX_ERR(efx, "failed to restore PCI config for the " |
| 2554 | "primary function\n"); |
| 2555 | goto fail4; |
| 2556 | } |
| 2557 | EFX_LOG(efx, "successfully restored PCI config\n"); |
| 2558 | } |
| 2559 | |
| 2560 | /* Assert that reset complete */ |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2561 | efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2562 | if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2563 | rc = -ETIMEDOUT; |
| 2564 | EFX_ERR(efx, "timed out waiting for hardware reset\n"); |
| 2565 | goto fail5; |
| 2566 | } |
| 2567 | EFX_LOG(efx, "hardware reset complete\n"); |
| 2568 | |
| 2569 | return 0; |
| 2570 | |
| 2571 | /* pci_save_state() and pci_restore_state() MUST be called in pairs */ |
| 2572 | fail2: |
| 2573 | fail3: |
| 2574 | pci_restore_state(efx->pci_dev); |
| 2575 | fail1: |
| 2576 | fail4: |
| 2577 | fail5: |
| 2578 | return rc; |
| 2579 | } |
| 2580 | |
| 2581 | /* Zeroes out the SRAM contents. This routine must be called in |
| 2582 | * process context and is allowed to sleep. |
| 2583 | */ |
| 2584 | static int falcon_reset_sram(struct efx_nic *efx) |
| 2585 | { |
| 2586 | efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker; |
| 2587 | int count; |
| 2588 | |
| 2589 | /* Set the SRAM wake/sleep GPIO appropriately. */ |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2590 | efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2591 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1); |
| 2592 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2593 | efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2594 | |
| 2595 | /* Initiate SRAM reset */ |
| 2596 | EFX_POPULATE_OWORD_2(srm_cfg_reg_ker, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2597 | FRF_AZ_SRM_INIT_EN, 1, |
| 2598 | FRF_AZ_SRM_NB_SZ, 0); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2599 | efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2600 | |
| 2601 | /* Wait for SRAM reset to complete */ |
| 2602 | count = 0; |
| 2603 | do { |
| 2604 | EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count); |
| 2605 | |
| 2606 | /* SRAM reset is slow; expect around 16ms */ |
| 2607 | schedule_timeout_uninterruptible(HZ / 50); |
| 2608 | |
| 2609 | /* Check for reset complete */ |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2610 | efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2611 | if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2612 | EFX_LOG(efx, "SRAM reset complete\n"); |
| 2613 | |
| 2614 | return 0; |
| 2615 | } |
| 2616 | } while (++count < 20); /* wait upto 0.4 sec */ |
| 2617 | |
| 2618 | EFX_ERR(efx, "timed out waiting for SRAM reset\n"); |
| 2619 | return -ETIMEDOUT; |
| 2620 | } |
| 2621 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 2622 | static int falcon_spi_device_init(struct efx_nic *efx, |
| 2623 | struct efx_spi_device **spi_device_ret, |
| 2624 | unsigned int device_id, u32 device_type) |
| 2625 | { |
| 2626 | struct efx_spi_device *spi_device; |
| 2627 | |
| 2628 | if (device_type != 0) { |
Ben Hutchings | 0c53d8c | 2008-12-12 22:08:50 -0800 | [diff] [blame] | 2629 | spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 2630 | if (!spi_device) |
| 2631 | return -ENOMEM; |
| 2632 | spi_device->device_id = device_id; |
| 2633 | spi_device->size = |
| 2634 | 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE); |
| 2635 | spi_device->addr_len = |
| 2636 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN); |
| 2637 | spi_device->munge_address = (spi_device->size == 1 << 9 && |
| 2638 | spi_device->addr_len == 1); |
Ben Hutchings | f415072 | 2008-11-04 20:34:28 +0000 | [diff] [blame] | 2639 | spi_device->erase_command = |
| 2640 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD); |
| 2641 | spi_device->erase_size = |
| 2642 | 1 << SPI_DEV_TYPE_FIELD(device_type, |
| 2643 | SPI_DEV_TYPE_ERASE_SIZE); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 2644 | spi_device->block_size = |
| 2645 | 1 << SPI_DEV_TYPE_FIELD(device_type, |
| 2646 | SPI_DEV_TYPE_BLOCK_SIZE); |
| 2647 | |
| 2648 | spi_device->efx = efx; |
| 2649 | } else { |
| 2650 | spi_device = NULL; |
| 2651 | } |
| 2652 | |
| 2653 | kfree(*spi_device_ret); |
| 2654 | *spi_device_ret = spi_device; |
| 2655 | return 0; |
| 2656 | } |
| 2657 | |
| 2658 | |
| 2659 | static void falcon_remove_spi_devices(struct efx_nic *efx) |
| 2660 | { |
| 2661 | kfree(efx->spi_eeprom); |
| 2662 | efx->spi_eeprom = NULL; |
| 2663 | kfree(efx->spi_flash); |
| 2664 | efx->spi_flash = NULL; |
| 2665 | } |
| 2666 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2667 | /* Extract non-volatile configuration */ |
| 2668 | static int falcon_probe_nvconfig(struct efx_nic *efx) |
| 2669 | { |
| 2670 | struct falcon_nvconfig *nvconfig; |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2671 | int board_rev; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2672 | int rc; |
| 2673 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2674 | nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 2675 | if (!nvconfig) |
| 2676 | return -ENOMEM; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2677 | |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2678 | rc = falcon_read_nvram(efx, nvconfig); |
| 2679 | if (rc == -EINVAL) { |
| 2680 | EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n"); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2681 | efx->phy_type = PHY_TYPE_NONE; |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 2682 | efx->mdio.prtad = MDIO_PRTAD_NONE; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2683 | board_rev = 0; |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2684 | rc = 0; |
| 2685 | } else if (rc) { |
| 2686 | goto fail1; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2687 | } else { |
| 2688 | struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2; |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 2689 | struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2690 | |
| 2691 | efx->phy_type = v2->port0_phy_type; |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 2692 | efx->mdio.prtad = v2->port0_phy_addr; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2693 | board_rev = le16_to_cpu(v2->board_revision); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 2694 | |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2695 | if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) { |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2696 | rc = falcon_spi_device_init( |
| 2697 | efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH, |
| 2698 | le32_to_cpu(v3->spi_device_type |
| 2699 | [FFE_AB_SPI_DEVICE_FLASH])); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 2700 | if (rc) |
| 2701 | goto fail2; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2702 | rc = falcon_spi_device_init( |
| 2703 | efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM, |
| 2704 | le32_to_cpu(v3->spi_device_type |
| 2705 | [FFE_AB_SPI_DEVICE_EEPROM])); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 2706 | if (rc) |
| 2707 | goto fail2; |
| 2708 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2709 | } |
| 2710 | |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 2711 | /* Read the MAC addresses */ |
| 2712 | memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN); |
| 2713 | |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 2714 | EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2715 | |
Ben Hutchings | 3473a5b | 2009-10-23 08:29:16 +0000 | [diff] [blame] | 2716 | falcon_probe_board(efx, board_rev); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2717 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 2718 | kfree(nvconfig); |
| 2719 | return 0; |
| 2720 | |
| 2721 | fail2: |
| 2722 | falcon_remove_spi_devices(efx); |
| 2723 | fail1: |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2724 | kfree(nvconfig); |
| 2725 | return rc; |
| 2726 | } |
| 2727 | |
| 2728 | /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port |
| 2729 | * count, port speed). Set workaround and feature flags accordingly. |
| 2730 | */ |
| 2731 | static int falcon_probe_nic_variant(struct efx_nic *efx) |
| 2732 | { |
| 2733 | efx_oword_t altera_build; |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 2734 | efx_oword_t nic_stat; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2735 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2736 | efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2737 | if (EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER)) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2738 | EFX_ERR(efx, "Falcon FPGA not supported\n"); |
| 2739 | return -ENODEV; |
| 2740 | } |
| 2741 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2742 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 2743 | |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 2744 | switch (falcon_rev(efx)) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2745 | case FALCON_REV_A0: |
| 2746 | case 0xff: |
| 2747 | EFX_ERR(efx, "Falcon rev A0 not supported\n"); |
| 2748 | return -ENODEV; |
| 2749 | |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 2750 | case FALCON_REV_A1: |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2751 | if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2752 | EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n"); |
| 2753 | return -ENODEV; |
| 2754 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2755 | break; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2756 | |
| 2757 | case FALCON_REV_B0: |
| 2758 | break; |
| 2759 | |
| 2760 | default: |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 2761 | EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx)); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2762 | return -ENODEV; |
| 2763 | } |
| 2764 | |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 2765 | /* Initial assumed speed */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2766 | efx->link_speed = EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) ? 10000 : 1000; |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 2767 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2768 | return 0; |
| 2769 | } |
| 2770 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 2771 | /* Probe all SPI devices on the NIC */ |
| 2772 | static void falcon_probe_spi_devices(struct efx_nic *efx) |
| 2773 | { |
| 2774 | efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg; |
Ben Hutchings | 2f7f573 | 2008-12-12 21:34:25 -0800 | [diff] [blame] | 2775 | int boot_dev; |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 2776 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2777 | efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL); |
| 2778 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); |
| 2779 | efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 2780 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2781 | if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) { |
| 2782 | boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ? |
| 2783 | FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM); |
Ben Hutchings | 2f7f573 | 2008-12-12 21:34:25 -0800 | [diff] [blame] | 2784 | EFX_LOG(efx, "Booted from %s\n", |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2785 | boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM"); |
Ben Hutchings | 2f7f573 | 2008-12-12 21:34:25 -0800 | [diff] [blame] | 2786 | } else { |
| 2787 | /* Disable VPD and set clock dividers to safe |
| 2788 | * values for initial programming. */ |
| 2789 | boot_dev = -1; |
| 2790 | EFX_LOG(efx, "Booted from internal ASIC settings;" |
| 2791 | " setting SPI config\n"); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2792 | EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0, |
Ben Hutchings | 2f7f573 | 2008-12-12 21:34:25 -0800 | [diff] [blame] | 2793 | /* 125 MHz / 7 ~= 20 MHz */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2794 | FRF_AB_EE_SF_CLOCK_DIV, 7, |
Ben Hutchings | 2f7f573 | 2008-12-12 21:34:25 -0800 | [diff] [blame] | 2795 | /* 125 MHz / 63 ~= 2 MHz */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2796 | FRF_AB_EE_EE_CLOCK_DIV, 63); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2797 | efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 2798 | } |
| 2799 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2800 | if (boot_dev == FFE_AB_SPI_DEVICE_FLASH) |
| 2801 | falcon_spi_device_init(efx, &efx->spi_flash, |
| 2802 | FFE_AB_SPI_DEVICE_FLASH, |
Ben Hutchings | 2f7f573 | 2008-12-12 21:34:25 -0800 | [diff] [blame] | 2803 | default_flash_type); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2804 | if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM) |
| 2805 | falcon_spi_device_init(efx, &efx->spi_eeprom, |
| 2806 | FFE_AB_SPI_DEVICE_EEPROM, |
Ben Hutchings | 2f7f573 | 2008-12-12 21:34:25 -0800 | [diff] [blame] | 2807 | large_eeprom_type); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 2808 | } |
| 2809 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2810 | int falcon_probe_nic(struct efx_nic *efx) |
| 2811 | { |
| 2812 | struct falcon_nic_data *nic_data; |
| 2813 | int rc; |
| 2814 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2815 | /* Allocate storage for hardware specific data */ |
| 2816 | nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); |
Ben Hutchings | 88c5942 | 2008-09-03 15:07:50 +0100 | [diff] [blame] | 2817 | if (!nic_data) |
| 2818 | return -ENOMEM; |
Ben Hutchings | 5daab96 | 2008-05-16 21:19:43 +0100 | [diff] [blame] | 2819 | efx->nic_data = nic_data; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2820 | |
| 2821 | /* Determine number of ports etc. */ |
| 2822 | rc = falcon_probe_nic_variant(efx); |
| 2823 | if (rc) |
| 2824 | goto fail1; |
| 2825 | |
| 2826 | /* Probe secondary function if expected */ |
| 2827 | if (FALCON_IS_DUAL_FUNC(efx)) { |
| 2828 | struct pci_dev *dev = pci_dev_get(efx->pci_dev); |
| 2829 | |
| 2830 | while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID, |
| 2831 | dev))) { |
| 2832 | if (dev->bus == efx->pci_dev->bus && |
| 2833 | dev->devfn == efx->pci_dev->devfn + 1) { |
| 2834 | nic_data->pci_dev2 = dev; |
| 2835 | break; |
| 2836 | } |
| 2837 | } |
| 2838 | if (!nic_data->pci_dev2) { |
| 2839 | EFX_ERR(efx, "failed to find secondary function\n"); |
| 2840 | rc = -ENODEV; |
| 2841 | goto fail2; |
| 2842 | } |
| 2843 | } |
| 2844 | |
| 2845 | /* Now we can reset the NIC */ |
| 2846 | rc = falcon_reset_hw(efx, RESET_TYPE_ALL); |
| 2847 | if (rc) { |
| 2848 | EFX_ERR(efx, "failed to reset NIC\n"); |
| 2849 | goto fail3; |
| 2850 | } |
| 2851 | |
| 2852 | /* Allocate memory for INT_KER */ |
| 2853 | rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t)); |
| 2854 | if (rc) |
| 2855 | goto fail4; |
| 2856 | BUG_ON(efx->irq_status.dma_addr & 0x0f); |
| 2857 | |
Jaswinder Singh Rajput | 9c8976a | 2009-02-11 23:49:52 +0530 | [diff] [blame] | 2858 | EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n", |
| 2859 | (u64)efx->irq_status.dma_addr, |
| 2860 | efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr)); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2861 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 2862 | falcon_probe_spi_devices(efx); |
| 2863 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2864 | /* Read in the non-volatile configuration */ |
| 2865 | rc = falcon_probe_nvconfig(efx); |
| 2866 | if (rc) |
| 2867 | goto fail5; |
| 2868 | |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 2869 | /* Initialise I2C adapter */ |
Ben Hutchings | b453193 | 2008-12-12 22:05:01 -0800 | [diff] [blame] | 2870 | efx->i2c_adap.owner = THIS_MODULE; |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 2871 | nic_data->i2c_data = falcon_i2c_bit_operations; |
| 2872 | nic_data->i2c_data.data = efx; |
Ben Hutchings | b453193 | 2008-12-12 22:05:01 -0800 | [diff] [blame] | 2873 | efx->i2c_adap.algo_data = &nic_data->i2c_data; |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 2874 | efx->i2c_adap.dev.parent = &efx->pci_dev->dev; |
Ben Hutchings | 9dadae6 | 2008-07-18 18:59:12 +0100 | [diff] [blame] | 2875 | strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name)); |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 2876 | rc = i2c_bit_add_bus(&efx->i2c_adap); |
| 2877 | if (rc) |
| 2878 | goto fail5; |
| 2879 | |
Ben Hutchings | 278c062 | 2009-11-23 16:05:12 +0000 | [diff] [blame^] | 2880 | rc = falcon_board(efx)->init(efx); |
| 2881 | if (rc) { |
| 2882 | EFX_ERR(efx, "failed to initialise board\n"); |
| 2883 | goto fail6; |
| 2884 | } |
| 2885 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2886 | return 0; |
| 2887 | |
Ben Hutchings | 278c062 | 2009-11-23 16:05:12 +0000 | [diff] [blame^] | 2888 | fail6: |
| 2889 | BUG_ON(i2c_del_adapter(&efx->i2c_adap)); |
| 2890 | memset(&efx->i2c_adap, 0, sizeof(efx->i2c_adap)); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2891 | fail5: |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 2892 | falcon_remove_spi_devices(efx); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2893 | falcon_free_buffer(efx, &efx->irq_status); |
| 2894 | fail4: |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2895 | fail3: |
| 2896 | if (nic_data->pci_dev2) { |
| 2897 | pci_dev_put(nic_data->pci_dev2); |
| 2898 | nic_data->pci_dev2 = NULL; |
| 2899 | } |
| 2900 | fail2: |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2901 | fail1: |
| 2902 | kfree(efx->nic_data); |
| 2903 | return rc; |
| 2904 | } |
| 2905 | |
Ben Hutchings | 56241ce | 2009-10-23 08:30:06 +0000 | [diff] [blame] | 2906 | static void falcon_init_rx_cfg(struct efx_nic *efx) |
| 2907 | { |
| 2908 | /* Prior to Siena the RX DMA engine will split each frame at |
| 2909 | * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to |
| 2910 | * be so large that that never happens. */ |
| 2911 | const unsigned huge_buf_size = (3 * 4096) >> 5; |
| 2912 | /* RX control FIFO thresholds (32 entries) */ |
| 2913 | const unsigned ctrl_xon_thr = 20; |
| 2914 | const unsigned ctrl_xoff_thr = 25; |
| 2915 | /* RX data FIFO thresholds (256-byte units; size varies) */ |
Ben Hutchings | 625b451 | 2009-10-23 08:30:17 +0000 | [diff] [blame] | 2916 | int data_xon_thr = rx_xon_thresh_bytes >> 8; |
| 2917 | int data_xoff_thr = rx_xoff_thresh_bytes >> 8; |
Ben Hutchings | 56241ce | 2009-10-23 08:30:06 +0000 | [diff] [blame] | 2918 | efx_oword_t reg; |
| 2919 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2920 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
Ben Hutchings | 56241ce | 2009-10-23 08:30:06 +0000 | [diff] [blame] | 2921 | if (falcon_rev(efx) <= FALCON_REV_A1) { |
Ben Hutchings | 625b451 | 2009-10-23 08:30:17 +0000 | [diff] [blame] | 2922 | /* Data FIFO size is 5.5K */ |
| 2923 | if (data_xon_thr < 0) |
| 2924 | data_xon_thr = 512 >> 8; |
| 2925 | if (data_xoff_thr < 0) |
| 2926 | data_xoff_thr = 2048 >> 8; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2927 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0); |
| 2928 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE, |
| 2929 | huge_buf_size); |
| 2930 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr); |
| 2931 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr); |
| 2932 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr); |
| 2933 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr); |
Ben Hutchings | 56241ce | 2009-10-23 08:30:06 +0000 | [diff] [blame] | 2934 | } else { |
Ben Hutchings | 625b451 | 2009-10-23 08:30:17 +0000 | [diff] [blame] | 2935 | /* Data FIFO size is 80K; register fields moved */ |
| 2936 | if (data_xon_thr < 0) |
| 2937 | data_xon_thr = 27648 >> 8; /* ~3*max MTU */ |
| 2938 | if (data_xoff_thr < 0) |
| 2939 | data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2940 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0); |
| 2941 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE, |
| 2942 | huge_buf_size); |
| 2943 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr); |
| 2944 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr); |
| 2945 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr); |
| 2946 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr); |
| 2947 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); |
Ben Hutchings | 56241ce | 2009-10-23 08:30:06 +0000 | [diff] [blame] | 2948 | } |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2949 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
Ben Hutchings | 56241ce | 2009-10-23 08:30:06 +0000 | [diff] [blame] | 2950 | } |
| 2951 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2952 | /* This call performs hardware-specific global initialisation, such as |
| 2953 | * defining the descriptor cache sizes and number of RSS channels. |
| 2954 | * It does not set up any buffers, descriptor rings or event queues. |
| 2955 | */ |
| 2956 | int falcon_init_nic(struct efx_nic *efx) |
| 2957 | { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2958 | efx_oword_t temp; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2959 | int rc; |
| 2960 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2961 | /* Use on-chip SRAM */ |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2962 | efx_reado(efx, &temp, FR_AB_NIC_STAT); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2963 | EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2964 | efx_writeo(efx, &temp, FR_AB_NIC_STAT); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2965 | |
Ben Hutchings | 6f158d5 | 2008-12-12 22:00:49 -0800 | [diff] [blame] | 2966 | /* Set the source of the GMAC clock */ |
| 2967 | if (falcon_rev(efx) == FALCON_REV_B0) { |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2968 | efx_reado(efx, &temp, FR_AB_GPIO_CTL); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2969 | EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2970 | efx_writeo(efx, &temp, FR_AB_GPIO_CTL); |
Ben Hutchings | 6f158d5 | 2008-12-12 22:00:49 -0800 | [diff] [blame] | 2971 | } |
| 2972 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2973 | rc = falcon_reset_sram(efx); |
| 2974 | if (rc) |
| 2975 | return rc; |
| 2976 | |
| 2977 | /* Set positions of descriptor caches in SRAM. */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2978 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2979 | efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2980 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2981 | efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2982 | |
| 2983 | /* Set TX descriptor cache size. */ |
| 2984 | BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER)); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2985 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2986 | efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2987 | |
| 2988 | /* Set RX descriptor cache size. Set low watermark to size-8, as |
| 2989 | * this allows most efficient prefetching. |
| 2990 | */ |
| 2991 | BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER)); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2992 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2993 | efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 2994 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 2995 | efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 2996 | |
| 2997 | /* Clear the parity enables on the TX data fifos as |
| 2998 | * they produce false parity errors because of timing issues |
| 2999 | */ |
| 3000 | if (EFX_WORKAROUND_5129(efx)) { |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 3001 | efx_reado(efx, &temp, FR_AZ_CSR_SPARE); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 3002 | EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 3003 | efx_writeo(efx, &temp, FR_AZ_CSR_SPARE); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3004 | } |
| 3005 | |
| 3006 | /* Enable all the genuinely fatal interrupts. (They are still |
| 3007 | * masked by the overall interrupt mask, controlled by |
| 3008 | * falcon_interrupts()). |
| 3009 | * |
| 3010 | * Note: All other fatal interrupts are enabled |
| 3011 | */ |
| 3012 | EFX_POPULATE_OWORD_3(temp, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 3013 | FRF_AZ_ILL_ADR_INT_KER_EN, 1, |
| 3014 | FRF_AZ_RBUF_OWN_INT_KER_EN, 1, |
| 3015 | FRF_AZ_TBUF_OWN_INT_KER_EN, 1); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3016 | EFX_INVERT_OWORD(temp); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 3017 | efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3018 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3019 | if (EFX_WORKAROUND_7244(efx)) { |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 3020 | efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 3021 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8); |
| 3022 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8); |
| 3023 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8); |
| 3024 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 3025 | efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3026 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3027 | |
| 3028 | falcon_setup_rss_indir_table(efx); |
| 3029 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 3030 | /* XXX This is documented only for Falcon A0/A1 */ |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3031 | /* Setup RX. Wait for descriptor is broken and must |
| 3032 | * be disabled. RXDP recovery shouldn't be needed, but is. |
| 3033 | */ |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 3034 | efx_reado(efx, &temp, FR_AA_RX_SELF_RST); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 3035 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1); |
| 3036 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3037 | if (EFX_WORKAROUND_5583(efx)) |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 3038 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 3039 | efx_writeo(efx, &temp, FR_AA_RX_SELF_RST); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3040 | |
| 3041 | /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be |
| 3042 | * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q. |
| 3043 | */ |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 3044 | efx_reado(efx, &temp, FR_AZ_TX_RESERVED); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 3045 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe); |
| 3046 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1); |
| 3047 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1); |
| 3048 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0); |
| 3049 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3050 | /* Enable SW_EV to inherit in char driver - assume harmless here */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 3051 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3052 | /* Prefetch threshold 2 => fetch when descriptor cache half empty */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 3053 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3054 | /* Squash TX of packets of 16 bytes or less */ |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 3055 | if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx)) |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 3056 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 3057 | efx_writeo(efx, &temp, FR_AZ_TX_RESERVED); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3058 | |
| 3059 | /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 |
| 3060 | * descriptors (which is bad). |
| 3061 | */ |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 3062 | efx_reado(efx, &temp, FR_AZ_TX_CFG); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 3063 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 3064 | efx_writeo(efx, &temp, FR_AZ_TX_CFG); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3065 | |
Ben Hutchings | 56241ce | 2009-10-23 08:30:06 +0000 | [diff] [blame] | 3066 | falcon_init_rx_cfg(efx); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3067 | |
| 3068 | /* Set destination of both TX and RX Flush events */ |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 3069 | if (falcon_rev(efx) >= FALCON_REV_B0) { |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 3070 | EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 3071 | efx_writeo(efx, &temp, FR_BZ_DP_CTRL); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3072 | } |
| 3073 | |
| 3074 | return 0; |
| 3075 | } |
| 3076 | |
| 3077 | void falcon_remove_nic(struct efx_nic *efx) |
| 3078 | { |
| 3079 | struct falcon_nic_data *nic_data = efx->nic_data; |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 3080 | int rc; |
| 3081 | |
Ben Hutchings | 278c062 | 2009-11-23 16:05:12 +0000 | [diff] [blame^] | 3082 | falcon_board(efx)->fini(efx); |
| 3083 | |
Ben Hutchings | 8c87037 | 2009-03-04 09:53:02 +0000 | [diff] [blame] | 3084 | /* Remove I2C adapter and clear it in preparation for a retry */ |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 3085 | rc = i2c_del_adapter(&efx->i2c_adap); |
| 3086 | BUG_ON(rc); |
Ben Hutchings | 8c87037 | 2009-03-04 09:53:02 +0000 | [diff] [blame] | 3087 | memset(&efx->i2c_adap, 0, sizeof(efx->i2c_adap)); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3088 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 3089 | falcon_remove_spi_devices(efx); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3090 | falcon_free_buffer(efx, &efx->irq_status); |
| 3091 | |
Ben Hutchings | 91ad757 | 2008-05-16 21:14:27 +0100 | [diff] [blame] | 3092 | falcon_reset_hw(efx, RESET_TYPE_ALL); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3093 | |
| 3094 | /* Release the second function after the reset */ |
| 3095 | if (nic_data->pci_dev2) { |
| 3096 | pci_dev_put(nic_data->pci_dev2); |
| 3097 | nic_data->pci_dev2 = NULL; |
| 3098 | } |
| 3099 | |
| 3100 | /* Tear down the private nic state */ |
| 3101 | kfree(efx->nic_data); |
| 3102 | efx->nic_data = NULL; |
| 3103 | } |
| 3104 | |
| 3105 | void falcon_update_nic_stats(struct efx_nic *efx) |
| 3106 | { |
| 3107 | efx_oword_t cnt; |
| 3108 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 3109 | efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 3110 | efx->n_rx_nodesc_drop_cnt += |
| 3111 | EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3112 | } |
| 3113 | |
| 3114 | /************************************************************************** |
| 3115 | * |
| 3116 | * Revision-dependent attributes used by efx.c |
| 3117 | * |
| 3118 | ************************************************************************** |
| 3119 | */ |
| 3120 | |
| 3121 | struct efx_nic_type falcon_a_nic_type = { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3122 | .mem_map_size = 0x20000, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 3123 | .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER, |
| 3124 | .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER, |
| 3125 | .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER, |
| 3126 | .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER, |
| 3127 | .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER, |
Ben Hutchings | 6d51d30 | 2009-10-23 08:31:07 +0000 | [diff] [blame] | 3128 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3129 | .rx_buffer_padding = 0x24, |
| 3130 | .max_interrupt_mode = EFX_INT_MODE_MSI, |
| 3131 | .phys_addr_channels = 4, |
| 3132 | }; |
| 3133 | |
| 3134 | struct efx_nic_type falcon_b_nic_type = { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3135 | /* Map everything up to and including the RSS indirection |
| 3136 | * table. Don't map MSI-X table, MSI-X PBA since Linux |
| 3137 | * requires that they not be mapped. */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 3138 | .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL + |
| 3139 | FR_BZ_RX_INDIRECTION_TBL_STEP * |
| 3140 | FR_BZ_RX_INDIRECTION_TBL_ROWS), |
| 3141 | .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL, |
| 3142 | .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL, |
| 3143 | .buf_tbl_base = FR_BZ_BUF_FULL_TBL, |
| 3144 | .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL, |
| 3145 | .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR, |
Ben Hutchings | 6d51d30 | 2009-10-23 08:31:07 +0000 | [diff] [blame] | 3146 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 3147 | .rx_buffer_padding = 0, |
| 3148 | .max_interrupt_mode = EFX_INT_MODE_MSIX, |
| 3149 | .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy |
| 3150 | * interrupt handler only supports 32 |
| 3151 | * channels */ |
| 3152 | }; |
| 3153 | |