Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2009 Jerome Glisse. |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the |
| 7 | * "Software"), to deal in the Software without restriction, including |
| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
| 9 | * distribute, sub license, and/or sell copies of the Software, and to |
| 10 | * permit persons to whom the Software is furnished to do so, subject to |
| 11 | * the following conditions: |
| 12 | * |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 20 | * |
| 21 | * The above copyright notice and this permission notice (including the |
| 22 | * next paragraph) shall be included in all copies or substantial portions |
| 23 | * of the Software. |
| 24 | * |
| 25 | */ |
| 26 | /* |
| 27 | * Authors: |
| 28 | * Jerome Glisse <glisse@freedesktop.org> |
| 29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> |
| 30 | * Dave Airlie |
| 31 | */ |
| 32 | #include <linux/list.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 33 | #include <linux/slab.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 34 | #include <drm/drmP.h> |
| 35 | #include "radeon_drm.h" |
| 36 | #include "radeon.h" |
Dave Airlie | 99ee7fa | 2010-11-23 11:47:49 +1000 | [diff] [blame] | 37 | #include "radeon_trace.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 38 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 39 | |
| 40 | int radeon_ttm_init(struct radeon_device *rdev); |
| 41 | void radeon_ttm_fini(struct radeon_device *rdev); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 42 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 43 | |
| 44 | /* |
| 45 | * To exclude mutual BO access we rely on bo_reserve exclusion, as all |
| 46 | * function are calling it. |
| 47 | */ |
| 48 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 49 | void radeon_bo_clear_va(struct radeon_bo *bo) |
| 50 | { |
| 51 | struct radeon_bo_va *bo_va, *tmp; |
| 52 | |
| 53 | list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) { |
| 54 | /* remove from all vm address space */ |
| 55 | mutex_lock(&bo_va->vm->mutex); |
| 56 | list_del(&bo_va->vm_list); |
| 57 | mutex_unlock(&bo_va->vm->mutex); |
| 58 | list_del(&bo_va->bo_list); |
| 59 | kfree(bo_va); |
| 60 | } |
| 61 | } |
| 62 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 63 | static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 64 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 65 | struct radeon_bo *bo; |
| 66 | |
| 67 | bo = container_of(tbo, struct radeon_bo, tbo); |
| 68 | mutex_lock(&bo->rdev->gem.mutex); |
| 69 | list_del_init(&bo->list); |
| 70 | mutex_unlock(&bo->rdev->gem.mutex); |
| 71 | radeon_bo_clear_surface_reg(bo); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 72 | radeon_bo_clear_va(bo); |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 73 | drm_gem_object_release(&bo->gem_base); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 74 | kfree(bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 75 | } |
| 76 | |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 77 | bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) |
| 78 | { |
| 79 | if (bo->destroy == &radeon_ttm_bo_destroy) |
| 80 | return true; |
| 81 | return false; |
| 82 | } |
| 83 | |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 84 | void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) |
| 85 | { |
| 86 | u32 c = 0; |
| 87 | |
| 88 | rbo->placement.fpfn = 0; |
Jerome Glisse | 93225b0 | 2010-12-03 16:38:19 -0500 | [diff] [blame] | 89 | rbo->placement.lpfn = 0; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 90 | rbo->placement.placement = rbo->placements; |
| 91 | rbo->placement.busy_placement = rbo->placements; |
| 92 | if (domain & RADEON_GEM_DOMAIN_VRAM) |
| 93 | rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | |
| 94 | TTM_PL_FLAG_VRAM; |
| 95 | if (domain & RADEON_GEM_DOMAIN_GTT) |
| 96 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; |
| 97 | if (domain & RADEON_GEM_DOMAIN_CPU) |
| 98 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; |
Jerome Glisse | 9fb03e6 | 2009-12-11 15:13:22 +0100 | [diff] [blame] | 99 | if (!c) |
| 100 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 101 | rbo->placement.num_placement = c; |
| 102 | rbo->placement.num_busy_placement = c; |
| 103 | } |
| 104 | |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 105 | int radeon_bo_create(struct radeon_device *rdev, |
Alex Deucher | 268b251 | 2010-11-17 19:00:26 -0500 | [diff] [blame] | 106 | unsigned long size, int byte_align, bool kernel, u32 domain, |
| 107 | struct radeon_bo **bo_ptr) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 108 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 109 | struct radeon_bo *bo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 110 | enum ttm_bo_type type; |
Jerome Glisse | 93225b0 | 2010-12-03 16:38:19 -0500 | [diff] [blame] | 111 | unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; |
| 112 | unsigned long max_size = 0; |
Jerome Glisse | 57de4ba | 2011-11-11 15:42:57 -0500 | [diff] [blame] | 113 | size_t acc_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 114 | int r; |
| 115 | |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 116 | size = ALIGN(size, PAGE_SIZE); |
| 117 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 118 | if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { |
| 119 | rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; |
| 120 | } |
| 121 | if (kernel) { |
| 122 | type = ttm_bo_type_kernel; |
| 123 | } else { |
| 124 | type = ttm_bo_type_device; |
| 125 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 126 | *bo_ptr = NULL; |
Michel Dänzer | 2b66b50 | 2010-11-09 11:50:05 +0100 | [diff] [blame] | 127 | |
Jerome Glisse | 93225b0 | 2010-12-03 16:38:19 -0500 | [diff] [blame] | 128 | /* maximun bo size is the minimun btw visible vram and gtt size */ |
| 129 | max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size); |
| 130 | if ((page_align << PAGE_SHIFT) >= max_size) { |
| 131 | printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n", |
| 132 | __func__, __LINE__, page_align >> (20 - PAGE_SHIFT), max_size >> 20); |
| 133 | return -ENOMEM; |
| 134 | } |
| 135 | |
Jerome Glisse | 57de4ba | 2011-11-11 15:42:57 -0500 | [diff] [blame] | 136 | acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, |
| 137 | sizeof(struct radeon_bo)); |
| 138 | |
Michel Dänzer | 2b66b50 | 2010-11-09 11:50:05 +0100 | [diff] [blame] | 139 | retry: |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 140 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); |
| 141 | if (bo == NULL) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 142 | return -ENOMEM; |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 143 | r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size); |
| 144 | if (unlikely(r)) { |
| 145 | kfree(bo); |
| 146 | return r; |
| 147 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 148 | bo->rdev = rdev; |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 149 | bo->gem_base.driver_private = NULL; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 150 | bo->surface_reg = -1; |
| 151 | INIT_LIST_HEAD(&bo->list); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 152 | INIT_LIST_HEAD(&bo->va); |
Jerome Glisse | 1fb107f | 2009-12-10 17:16:28 +0100 | [diff] [blame] | 153 | radeon_ttm_placement_from_domain(bo, domain); |
Thomas Hellstrom | 5cc6fba | 2009-12-07 18:36:19 +0100 | [diff] [blame] | 154 | /* Kernel allocation are uninterruptible */ |
Matthew Garrett | 5876dd2 | 2010-04-26 15:52:20 -0400 | [diff] [blame] | 155 | mutex_lock(&rdev->vram_mutex); |
Jerome Glisse | 1fb107f | 2009-12-10 17:16:28 +0100 | [diff] [blame] | 156 | r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, |
Jerome Glisse | 57de4ba | 2011-11-11 15:42:57 -0500 | [diff] [blame] | 157 | &bo->placement, page_align, 0, !kernel, NULL, |
| 158 | acc_size, &radeon_ttm_bo_destroy); |
Matthew Garrett | 5876dd2 | 2010-04-26 15:52:20 -0400 | [diff] [blame] | 159 | mutex_unlock(&rdev->vram_mutex); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 160 | if (unlikely(r != 0)) { |
Michel Dänzer | e376573 | 2010-07-08 12:43:28 +1000 | [diff] [blame] | 161 | if (r != -ERESTARTSYS) { |
| 162 | if (domain == RADEON_GEM_DOMAIN_VRAM) { |
| 163 | domain |= RADEON_GEM_DOMAIN_GTT; |
| 164 | goto retry; |
| 165 | } |
Thomas Hellstrom | 5cc6fba | 2009-12-07 18:36:19 +0100 | [diff] [blame] | 166 | dev_err(rdev->dev, |
Jerome Glisse | 1fb107f | 2009-12-10 17:16:28 +0100 | [diff] [blame] | 167 | "object_init failed for (%lu, 0x%08X)\n", |
| 168 | size, domain); |
Michel Dänzer | e376573 | 2010-07-08 12:43:28 +1000 | [diff] [blame] | 169 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 170 | return r; |
| 171 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 172 | *bo_ptr = bo; |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 173 | |
Dave Airlie | 99ee7fa | 2010-11-23 11:47:49 +1000 | [diff] [blame] | 174 | trace_radeon_bo_create(bo); |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 175 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 176 | return 0; |
| 177 | } |
| 178 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 179 | int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 180 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 181 | bool is_iomem; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 182 | int r; |
| 183 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 184 | if (bo->kptr) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 185 | if (ptr) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 186 | *ptr = bo->kptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 187 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 188 | return 0; |
| 189 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 190 | r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 191 | if (r) { |
| 192 | return r; |
| 193 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 194 | bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 195 | if (ptr) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 196 | *ptr = bo->kptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 197 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 198 | radeon_bo_check_tiling(bo, 0, 0); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 199 | return 0; |
| 200 | } |
| 201 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 202 | void radeon_bo_kunmap(struct radeon_bo *bo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 203 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 204 | if (bo->kptr == NULL) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 205 | return; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 206 | bo->kptr = NULL; |
| 207 | radeon_bo_check_tiling(bo, 0, 0); |
| 208 | ttm_bo_kunmap(&bo->kmap); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 209 | } |
| 210 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 211 | void radeon_bo_unref(struct radeon_bo **bo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 212 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 213 | struct ttm_buffer_object *tbo; |
Dave Airlie | f4b7fb9 | 2010-04-29 18:37:59 +1000 | [diff] [blame] | 214 | struct radeon_device *rdev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 215 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 216 | if ((*bo) == NULL) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 217 | return; |
Dave Airlie | f4b7fb9 | 2010-04-29 18:37:59 +1000 | [diff] [blame] | 218 | rdev = (*bo)->rdev; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 219 | tbo = &((*bo)->tbo); |
Dave Airlie | f4b7fb9 | 2010-04-29 18:37:59 +1000 | [diff] [blame] | 220 | mutex_lock(&rdev->vram_mutex); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 221 | ttm_bo_unref(&tbo); |
Dave Airlie | f4b7fb9 | 2010-04-29 18:37:59 +1000 | [diff] [blame] | 222 | mutex_unlock(&rdev->vram_mutex); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 223 | if (tbo == NULL) |
| 224 | *bo = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 225 | } |
| 226 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 227 | int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 228 | { |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 229 | int r, i; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 230 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 231 | if (bo->pin_count) { |
| 232 | bo->pin_count++; |
| 233 | if (gpu_addr) |
| 234 | *gpu_addr = radeon_bo_gpu_offset(bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 235 | return 0; |
| 236 | } |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 237 | radeon_ttm_placement_from_domain(bo, domain); |
Michel Dänzer | 3ca82da | 2010-03-26 19:18:55 +0000 | [diff] [blame] | 238 | if (domain == RADEON_GEM_DOMAIN_VRAM) { |
| 239 | /* force to pin into visible video ram */ |
| 240 | bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; |
| 241 | } |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 242 | for (i = 0; i < bo->placement.num_placement; i++) |
| 243 | bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 244 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 245 | if (likely(r == 0)) { |
| 246 | bo->pin_count = 1; |
| 247 | if (gpu_addr != NULL) |
| 248 | *gpu_addr = radeon_bo_gpu_offset(bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 249 | } |
Thomas Hellstrom | 5cc6fba | 2009-12-07 18:36:19 +0100 | [diff] [blame] | 250 | if (unlikely(r != 0)) |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 251 | dev_err(bo->rdev->dev, "%p pin failed\n", bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 252 | return r; |
| 253 | } |
| 254 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 255 | int radeon_bo_unpin(struct radeon_bo *bo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 256 | { |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 257 | int r, i; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 258 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 259 | if (!bo->pin_count) { |
| 260 | dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); |
| 261 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 262 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 263 | bo->pin_count--; |
| 264 | if (bo->pin_count) |
| 265 | return 0; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 266 | for (i = 0; i < bo->placement.num_placement; i++) |
| 267 | bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 268 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false); |
Thomas Hellstrom | 5cc6fba | 2009-12-07 18:36:19 +0100 | [diff] [blame] | 269 | if (unlikely(r != 0)) |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 270 | dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); |
Thomas Hellstrom | 5cc6fba | 2009-12-07 18:36:19 +0100 | [diff] [blame] | 271 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 272 | } |
| 273 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 274 | int radeon_bo_evict_vram(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 275 | { |
Dave Airlie | d796d84 | 2010-01-25 13:08:08 +1000 | [diff] [blame] | 276 | /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ |
| 277 | if (0 && (rdev->flags & RADEON_IS_IGP)) { |
Alex Deucher | 06b6476 | 2010-01-05 11:27:29 -0500 | [diff] [blame] | 278 | if (rdev->mc.igp_sideport_enabled == false) |
| 279 | /* Useless to evict on IGP chips */ |
| 280 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 281 | } |
| 282 | return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); |
| 283 | } |
| 284 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 285 | void radeon_bo_force_delete(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 286 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 287 | struct radeon_bo *bo, *n; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 288 | |
| 289 | if (list_empty(&rdev->gem.objects)) { |
| 290 | return; |
| 291 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 292 | dev_err(rdev->dev, "Userspace still has active objects !\n"); |
| 293 | list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 294 | mutex_lock(&rdev->ddev->struct_mutex); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 295 | dev_err(rdev->dev, "%p %p %lu %lu force free\n", |
Daniel Vetter | 31c3603 | 2011-02-18 17:59:18 +0100 | [diff] [blame] | 296 | &bo->gem_base, bo, (unsigned long)bo->gem_base.size, |
| 297 | *((unsigned long *)&bo->gem_base.refcount)); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 298 | mutex_lock(&bo->rdev->gem.mutex); |
| 299 | list_del_init(&bo->list); |
| 300 | mutex_unlock(&bo->rdev->gem.mutex); |
Dave Airlie | 91132d6 | 2011-03-01 13:40:06 +1000 | [diff] [blame] | 301 | /* this should unref the ttm bo */ |
Daniel Vetter | 31c3603 | 2011-02-18 17:59:18 +0100 | [diff] [blame] | 302 | drm_gem_object_unreference(&bo->gem_base); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 303 | mutex_unlock(&rdev->ddev->struct_mutex); |
| 304 | } |
| 305 | } |
| 306 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 307 | int radeon_bo_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 308 | { |
Jerome Glisse | a4d6827 | 2009-09-11 13:00:43 +0200 | [diff] [blame] | 309 | /* Add an MTRR for the VRAM */ |
| 310 | rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, |
| 311 | MTRR_TYPE_WRCOMB, 1); |
| 312 | DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", |
| 313 | rdev->mc.mc_vram_size >> 20, |
| 314 | (unsigned long long)rdev->mc.aper_size >> 20); |
| 315 | DRM_INFO("RAM width %dbits %cDR\n", |
| 316 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 317 | return radeon_ttm_init(rdev); |
| 318 | } |
| 319 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 320 | void radeon_bo_fini(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 321 | { |
| 322 | radeon_ttm_fini(rdev); |
| 323 | } |
| 324 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 325 | void radeon_bo_list_add_object(struct radeon_bo_list *lobj, |
| 326 | struct list_head *head) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 327 | { |
| 328 | if (lobj->wdomain) { |
Thomas Hellstrom | 147666f | 2010-11-17 12:38:32 +0000 | [diff] [blame] | 329 | list_add(&lobj->tv.head, head); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 330 | } else { |
Thomas Hellstrom | 147666f | 2010-11-17 12:38:32 +0000 | [diff] [blame] | 331 | list_add_tail(&lobj->tv.head, head); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 332 | } |
| 333 | } |
| 334 | |
Jerome Glisse | 6cb8e1f | 2010-02-15 21:36:33 +0100 | [diff] [blame] | 335 | int radeon_bo_list_validate(struct list_head *head) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 336 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 337 | struct radeon_bo_list *lobj; |
| 338 | struct radeon_bo *bo; |
Michel Dänzer | e376573 | 2010-07-08 12:43:28 +1000 | [diff] [blame] | 339 | u32 domain; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 340 | int r; |
| 341 | |
Thomas Hellstrom | 147666f | 2010-11-17 12:38:32 +0000 | [diff] [blame] | 342 | r = ttm_eu_reserve_buffers(head); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 343 | if (unlikely(r != 0)) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 344 | return r; |
| 345 | } |
Thomas Hellstrom | 147666f | 2010-11-17 12:38:32 +0000 | [diff] [blame] | 346 | list_for_each_entry(lobj, head, tv.head) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 347 | bo = lobj->bo; |
| 348 | if (!bo->pin_count) { |
Michel Dänzer | e376573 | 2010-07-08 12:43:28 +1000 | [diff] [blame] | 349 | domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain; |
| 350 | |
| 351 | retry: |
| 352 | radeon_ttm_placement_from_domain(bo, domain); |
Jerome Glisse | 1fb107f | 2009-12-10 17:16:28 +0100 | [diff] [blame] | 353 | r = ttm_bo_validate(&bo->tbo, &bo->placement, |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 354 | true, false, false); |
Michel Dänzer | e376573 | 2010-07-08 12:43:28 +1000 | [diff] [blame] | 355 | if (unlikely(r)) { |
| 356 | if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) { |
| 357 | domain |= RADEON_GEM_DOMAIN_GTT; |
| 358 | goto retry; |
| 359 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 360 | return r; |
Michel Dänzer | e376573 | 2010-07-08 12:43:28 +1000 | [diff] [blame] | 361 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 362 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 363 | lobj->gpu_offset = radeon_bo_gpu_offset(bo); |
| 364 | lobj->tiling_flags = bo->tiling_flags; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 365 | } |
| 366 | return 0; |
| 367 | } |
| 368 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 369 | int radeon_bo_fbdev_mmap(struct radeon_bo *bo, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 370 | struct vm_area_struct *vma) |
| 371 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 372 | return ttm_fbdev_mmap(vma, &bo->tbo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 373 | } |
| 374 | |
Dave Airlie | 550e2d9 | 2009-12-09 14:15:38 +1000 | [diff] [blame] | 375 | int radeon_bo_get_surface_reg(struct radeon_bo *bo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 376 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 377 | struct radeon_device *rdev = bo->rdev; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 378 | struct radeon_surface_reg *reg; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 379 | struct radeon_bo *old_object; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 380 | int steal; |
| 381 | int i; |
| 382 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 383 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
| 384 | |
| 385 | if (!bo->tiling_flags) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 386 | return 0; |
| 387 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 388 | if (bo->surface_reg >= 0) { |
| 389 | reg = &rdev->surface_regs[bo->surface_reg]; |
| 390 | i = bo->surface_reg; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 391 | goto out; |
| 392 | } |
| 393 | |
| 394 | steal = -1; |
| 395 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
| 396 | |
| 397 | reg = &rdev->surface_regs[i]; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 398 | if (!reg->bo) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 399 | break; |
| 400 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 401 | old_object = reg->bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 402 | if (old_object->pin_count == 0) |
| 403 | steal = i; |
| 404 | } |
| 405 | |
| 406 | /* if we are all out */ |
| 407 | if (i == RADEON_GEM_MAX_SURFACES) { |
| 408 | if (steal == -1) |
| 409 | return -ENOMEM; |
| 410 | /* find someone with a surface reg and nuke their BO */ |
| 411 | reg = &rdev->surface_regs[steal]; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 412 | old_object = reg->bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 413 | /* blow away the mapping */ |
| 414 | DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 415 | ttm_bo_unmap_virtual(&old_object->tbo); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 416 | old_object->surface_reg = -1; |
| 417 | i = steal; |
| 418 | } |
| 419 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 420 | bo->surface_reg = i; |
| 421 | reg->bo = bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 422 | |
| 423 | out: |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 424 | radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 425 | bo->tbo.mem.start << PAGE_SHIFT, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 426 | bo->tbo.num_pages << PAGE_SHIFT); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 427 | return 0; |
| 428 | } |
| 429 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 430 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 431 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 432 | struct radeon_device *rdev = bo->rdev; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 433 | struct radeon_surface_reg *reg; |
| 434 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 435 | if (bo->surface_reg == -1) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 436 | return; |
| 437 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 438 | reg = &rdev->surface_regs[bo->surface_reg]; |
| 439 | radeon_clear_surface_reg(rdev, bo->surface_reg); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 440 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 441 | reg->bo = NULL; |
| 442 | bo->surface_reg = -1; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 443 | } |
| 444 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 445 | int radeon_bo_set_tiling_flags(struct radeon_bo *bo, |
| 446 | uint32_t tiling_flags, uint32_t pitch) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 447 | { |
Jerome Glisse | 285484e | 2011-12-16 17:03:42 -0500 | [diff] [blame^] | 448 | struct radeon_device *rdev = bo->rdev; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 449 | int r; |
| 450 | |
Jerome Glisse | 285484e | 2011-12-16 17:03:42 -0500 | [diff] [blame^] | 451 | if (rdev->family >= CHIP_CEDAR) { |
| 452 | unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; |
| 453 | |
| 454 | bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; |
| 455 | bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; |
| 456 | mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; |
| 457 | tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; |
| 458 | stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; |
| 459 | switch (bankw) { |
| 460 | case 0: |
| 461 | case 1: |
| 462 | case 2: |
| 463 | case 4: |
| 464 | case 8: |
| 465 | break; |
| 466 | default: |
| 467 | return -EINVAL; |
| 468 | } |
| 469 | switch (bankh) { |
| 470 | case 0: |
| 471 | case 1: |
| 472 | case 2: |
| 473 | case 4: |
| 474 | case 8: |
| 475 | break; |
| 476 | default: |
| 477 | return -EINVAL; |
| 478 | } |
| 479 | switch (mtaspect) { |
| 480 | case 0: |
| 481 | case 1: |
| 482 | case 2: |
| 483 | case 4: |
| 484 | case 8: |
| 485 | break; |
| 486 | default: |
| 487 | return -EINVAL; |
| 488 | } |
| 489 | if (tilesplit > 6) { |
| 490 | return -EINVAL; |
| 491 | } |
| 492 | if (stilesplit > 6) { |
| 493 | return -EINVAL; |
| 494 | } |
| 495 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 496 | r = radeon_bo_reserve(bo, false); |
| 497 | if (unlikely(r != 0)) |
| 498 | return r; |
| 499 | bo->tiling_flags = tiling_flags; |
| 500 | bo->pitch = pitch; |
| 501 | radeon_bo_unreserve(bo); |
| 502 | return 0; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 503 | } |
| 504 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 505 | void radeon_bo_get_tiling_flags(struct radeon_bo *bo, |
| 506 | uint32_t *tiling_flags, |
| 507 | uint32_t *pitch) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 508 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 509 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 510 | if (tiling_flags) |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 511 | *tiling_flags = bo->tiling_flags; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 512 | if (pitch) |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 513 | *pitch = bo->pitch; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 514 | } |
| 515 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 516 | int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, |
| 517 | bool force_drop) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 518 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 519 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
| 520 | |
| 521 | if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 522 | return 0; |
| 523 | |
| 524 | if (force_drop) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 525 | radeon_bo_clear_surface_reg(bo); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 526 | return 0; |
| 527 | } |
| 528 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 529 | if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 530 | if (!has_moved) |
| 531 | return 0; |
| 532 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 533 | if (bo->surface_reg >= 0) |
| 534 | radeon_bo_clear_surface_reg(bo); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 535 | return 0; |
| 536 | } |
| 537 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 538 | if ((bo->surface_reg >= 0) && !has_moved) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 539 | return 0; |
| 540 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 541 | return radeon_bo_get_surface_reg(bo); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 542 | } |
| 543 | |
| 544 | void radeon_bo_move_notify(struct ttm_buffer_object *bo, |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 545 | struct ttm_mem_reg *mem) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 546 | { |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 547 | struct radeon_bo *rbo; |
| 548 | if (!radeon_ttm_bo_is_radeon_bo(bo)) |
| 549 | return; |
| 550 | rbo = container_of(bo, struct radeon_bo, tbo); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 551 | radeon_bo_check_tiling(rbo, 0, 1); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 552 | radeon_vm_bo_invalidate(rbo->rdev, rbo); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 553 | } |
| 554 | |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 555 | int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 556 | { |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 557 | struct radeon_device *rdev; |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 558 | struct radeon_bo *rbo; |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 559 | unsigned long offset, size; |
| 560 | int r; |
| 561 | |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 562 | if (!radeon_ttm_bo_is_radeon_bo(bo)) |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 563 | return 0; |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 564 | rbo = container_of(bo, struct radeon_bo, tbo); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 565 | radeon_bo_check_tiling(rbo, 0, 0); |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 566 | rdev = rbo->rdev; |
| 567 | if (bo->mem.mem_type == TTM_PL_VRAM) { |
| 568 | size = bo->mem.num_pages << PAGE_SHIFT; |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 569 | offset = bo->mem.start << PAGE_SHIFT; |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 570 | if ((offset + size) > rdev->mc.visible_vram_size) { |
| 571 | /* hurrah the memory is not visible ! */ |
| 572 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); |
| 573 | rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; |
| 574 | r = ttm_bo_validate(bo, &rbo->placement, false, true, false); |
| 575 | if (unlikely(r != 0)) |
| 576 | return r; |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 577 | offset = bo->mem.start << PAGE_SHIFT; |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 578 | /* this should not happen */ |
| 579 | if ((offset + size) > rdev->mc.visible_vram_size) |
| 580 | return -EINVAL; |
| 581 | } |
| 582 | } |
| 583 | return 0; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 584 | } |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 585 | |
Dave Airlie | 83f30d0 | 2011-10-27 18:15:10 +0200 | [diff] [blame] | 586 | int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 587 | { |
| 588 | int r; |
| 589 | |
| 590 | r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0); |
| 591 | if (unlikely(r != 0)) |
| 592 | return r; |
| 593 | spin_lock(&bo->tbo.bdev->fence_lock); |
| 594 | if (mem_type) |
| 595 | *mem_type = bo->tbo.mem.mem_type; |
| 596 | if (bo->tbo.sync_obj) |
Dave Airlie | 1717c0e | 2011-10-27 18:28:37 +0200 | [diff] [blame] | 597 | r = ttm_bo_wait(&bo->tbo, true, true, no_wait); |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 598 | spin_unlock(&bo->tbo.bdev->fence_lock); |
| 599 | ttm_bo_unreserve(&bo->tbo); |
| 600 | return r; |
| 601 | } |
| 602 | |
| 603 | |
| 604 | /** |
| 605 | * radeon_bo_reserve - reserve bo |
| 606 | * @bo: bo structure |
| 607 | * @no_wait: don't sleep while trying to reserve (return -EBUSY) |
| 608 | * |
| 609 | * Returns: |
| 610 | * -EBUSY: buffer is busy and @no_wait is true |
| 611 | * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by |
| 612 | * a signal. Release all buffer reservations and return to user-space. |
| 613 | */ |
| 614 | int radeon_bo_reserve(struct radeon_bo *bo, bool no_wait) |
| 615 | { |
| 616 | int r; |
| 617 | |
| 618 | r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0); |
| 619 | if (unlikely(r != 0)) { |
| 620 | if (r != -ERESTARTSYS) |
| 621 | dev_err(bo->rdev->dev, "%p reserve failed\n", bo); |
| 622 | return r; |
| 623 | } |
| 624 | return 0; |
| 625 | } |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 626 | |
| 627 | /* object have to be reserved */ |
| 628 | struct radeon_bo_va *radeon_bo_va(struct radeon_bo *rbo, struct radeon_vm *vm) |
| 629 | { |
| 630 | struct radeon_bo_va *bo_va; |
| 631 | |
| 632 | list_for_each_entry(bo_va, &rbo->va, bo_list) { |
| 633 | if (bo_va->vm == vm) { |
| 634 | return bo_va; |
| 635 | } |
| 636 | } |
| 637 | return NULL; |
| 638 | } |