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Bard Liao07cf7cba2014-06-20 14:41:13 +08001/*
2 * rt286.c -- RT286 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
Bard Liao6c67cde2014-11-06 09:59:59 +080020#include <linux/dmi.h>
Bard Liao07cf7cba2014-06-20 14:41:13 +080021#include <linux/acpi.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29#include <sound/jack.h>
30#include <linux/workqueue.h>
31#include <sound/rt286.h>
32#include <sound/hda_verbs.h>
33
34#include "rt286.h"
35
36#define RT286_VENDOR_ID 0x10ec0286
37
38struct rt286_priv {
39 struct regmap *regmap;
Bard Liao6879db72014-10-31 14:52:16 +080040 struct snd_soc_codec *codec;
Bard Liao07cf7cba2014-06-20 14:41:13 +080041 struct rt286_platform_data pdata;
42 struct i2c_client *i2c;
43 struct snd_soc_jack *jack;
44 struct delayed_work jack_detect_work;
45 int sys_clk;
Bard Liao6879db72014-10-31 14:52:16 +080046 int clk_id;
Bard Liao07cf7cba2014-06-20 14:41:13 +080047 struct reg_default *index_cache;
48};
49
50static struct reg_default rt286_index_def[] = {
51 { 0x01, 0xaaaa },
52 { 0x02, 0x8aaa },
53 { 0x03, 0x0002 },
54 { 0x04, 0xaf01 },
55 { 0x08, 0x000d },
56 { 0x09, 0xd810 },
Bard Liaob7a29762014-09-26 11:06:39 +080057 { 0x0a, 0x0120 },
Bard Liao07cf7cba2014-06-20 14:41:13 +080058 { 0x0b, 0x0000 },
Bard Liaobc6c4e42014-07-07 19:15:30 +080059 { 0x0d, 0x2800 },
Bard Liao07cf7cba2014-06-20 14:41:13 +080060 { 0x0f, 0x0000 },
61 { 0x19, 0x0a17 },
62 { 0x20, 0x0020 },
63 { 0x33, 0x0208 },
64 { 0x49, 0x0004 },
65 { 0x4f, 0x50e9 },
Bard Liaob7a29762014-09-26 11:06:39 +080066 { 0x50, 0x2000 },
Bard Liao07cf7cba2014-06-20 14:41:13 +080067 { 0x63, 0x2902 },
Bard Liaobc6c4e42014-07-07 19:15:30 +080068 { 0x67, 0x1111 },
69 { 0x68, 0x1016 },
70 { 0x69, 0x273f },
Bard Liao07cf7cba2014-06-20 14:41:13 +080071};
72#define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def)
73
74static const struct reg_default rt286_reg[] = {
75 { 0x00170500, 0x00000400 },
76 { 0x00220000, 0x00000031 },
77 { 0x00239000, 0x0000007f },
78 { 0x0023a000, 0x0000007f },
79 { 0x00270500, 0x00000400 },
80 { 0x00370500, 0x00000400 },
81 { 0x00870500, 0x00000400 },
82 { 0x00920000, 0x00000031 },
83 { 0x00935000, 0x000000c3 },
84 { 0x00936000, 0x000000c3 },
85 { 0x00970500, 0x00000400 },
86 { 0x00b37000, 0x00000097 },
87 { 0x00b37200, 0x00000097 },
88 { 0x00b37300, 0x00000097 },
89 { 0x00c37000, 0x00000000 },
90 { 0x00c37100, 0x00000080 },
91 { 0x01270500, 0x00000400 },
92 { 0x01370500, 0x00000400 },
93 { 0x01371f00, 0x411111f0 },
94 { 0x01439000, 0x00000080 },
95 { 0x0143a000, 0x00000080 },
96 { 0x01470700, 0x00000000 },
97 { 0x01470500, 0x00000400 },
98 { 0x01470c00, 0x00000000 },
99 { 0x01470100, 0x00000000 },
100 { 0x01837000, 0x00000000 },
101 { 0x01870500, 0x00000400 },
102 { 0x02050000, 0x00000000 },
103 { 0x02139000, 0x00000080 },
104 { 0x0213a000, 0x00000080 },
105 { 0x02170100, 0x00000000 },
106 { 0x02170500, 0x00000400 },
107 { 0x02170700, 0x00000000 },
108 { 0x02270100, 0x00000000 },
109 { 0x02370100, 0x00000000 },
Bard Liao07cf7cba2014-06-20 14:41:13 +0800110 { 0x01870700, 0x00000020 },
111 { 0x00830000, 0x000000c3 },
112 { 0x00930000, 0x000000c3 },
113 { 0x01270700, 0x00000000 },
114};
115
116static bool rt286_volatile_register(struct device *dev, unsigned int reg)
117{
118 switch (reg) {
119 case 0 ... 0xff:
120 case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
121 case RT286_GET_HP_SENSE:
122 case RT286_GET_MIC1_SENSE:
123 case RT286_PROC_COEF:
124 return true;
125 default:
126 return false;
127 }
128
129
130}
131
132static bool rt286_readable_register(struct device *dev, unsigned int reg)
133{
134 switch (reg) {
135 case 0 ... 0xff:
136 case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
137 case RT286_GET_HP_SENSE:
138 case RT286_GET_MIC1_SENSE:
139 case RT286_SET_AUDIO_POWER:
140 case RT286_SET_HPO_POWER:
141 case RT286_SET_SPK_POWER:
142 case RT286_SET_DMIC1_POWER:
143 case RT286_SPK_MUX:
144 case RT286_HPO_MUX:
145 case RT286_ADC0_MUX:
146 case RT286_ADC1_MUX:
147 case RT286_SET_MIC1:
148 case RT286_SET_PIN_HPO:
149 case RT286_SET_PIN_SPK:
150 case RT286_SET_PIN_DMIC1:
151 case RT286_SPK_EAPD:
152 case RT286_SET_AMP_GAIN_HPO:
153 case RT286_SET_DMIC2_DEFAULT:
154 case RT286_DACL_GAIN:
155 case RT286_DACR_GAIN:
156 case RT286_ADCL_GAIN:
157 case RT286_ADCR_GAIN:
158 case RT286_MIC_GAIN:
159 case RT286_SPOL_GAIN:
160 case RT286_SPOR_GAIN:
161 case RT286_HPOL_GAIN:
162 case RT286_HPOR_GAIN:
163 case RT286_F_DAC_SWITCH:
164 case RT286_F_RECMIX_SWITCH:
165 case RT286_REC_MIC_SWITCH:
166 case RT286_REC_I2S_SWITCH:
167 case RT286_REC_LINE_SWITCH:
168 case RT286_REC_BEEP_SWITCH:
169 case RT286_DAC_FORMAT:
170 case RT286_ADC_FORMAT:
171 case RT286_COEF_INDEX:
172 case RT286_PROC_COEF:
173 case RT286_SET_AMP_GAIN_ADC_IN1:
174 case RT286_SET_AMP_GAIN_ADC_IN2:
175 case RT286_SET_POWER(RT286_DAC_OUT1):
176 case RT286_SET_POWER(RT286_DAC_OUT2):
177 case RT286_SET_POWER(RT286_ADC_IN1):
178 case RT286_SET_POWER(RT286_ADC_IN2):
179 case RT286_SET_POWER(RT286_DMIC2):
180 case RT286_SET_POWER(RT286_MIC1):
181 return true;
182 default:
183 return false;
184 }
185}
186
187static int rt286_hw_write(void *context, unsigned int reg, unsigned int value)
188{
189 struct i2c_client *client = context;
190 struct rt286_priv *rt286 = i2c_get_clientdata(client);
191 u8 data[4];
192 int ret, i;
193
Bard Liaof8c101b2014-11-06 10:00:00 +0800194 /* handle index registers */
Bard Liao07cf7cba2014-06-20 14:41:13 +0800195 if (reg <= 0xff) {
196 rt286_hw_write(client, RT286_COEF_INDEX, reg);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800197 for (i = 0; i < INDEX_CACHE_SIZE; i++) {
198 if (reg == rt286->index_cache[i].reg) {
199 rt286->index_cache[i].def = value;
200 break;
201 }
202
203 }
Bard Liao66d627d2014-09-26 11:06:40 +0800204 reg = RT286_PROC_COEF;
Bard Liao07cf7cba2014-06-20 14:41:13 +0800205 }
206
207 data[0] = (reg >> 24) & 0xff;
208 data[1] = (reg >> 16) & 0xff;
209 /*
210 * 4 bit VID: reg should be 0
211 * 12 bit VID: value should be 0
212 * So we use an OR operator to handle it rather than use if condition.
213 */
214 data[2] = ((reg >> 8) & 0xff) | ((value >> 8) & 0xff);
215 data[3] = value & 0xff;
216
217 ret = i2c_master_send(client, data, 4);
218
219 if (ret == 4)
220 return 0;
221 else
222 pr_err("ret=%d\n", ret);
223 if (ret < 0)
224 return ret;
225 else
226 return -EIO;
227}
228
229static int rt286_hw_read(void *context, unsigned int reg, unsigned int *value)
230{
231 struct i2c_client *client = context;
232 struct i2c_msg xfer[2];
233 int ret;
234 __be32 be_reg;
235 unsigned int index, vid, buf = 0x0;
236
Bard Liaof8c101b2014-11-06 10:00:00 +0800237 /* handle index registers */
Bard Liao07cf7cba2014-06-20 14:41:13 +0800238 if (reg <= 0xff) {
239 rt286_hw_write(client, RT286_COEF_INDEX, reg);
240 reg = RT286_PROC_COEF;
241 }
242
243 reg = reg | 0x80000;
244 vid = (reg >> 8) & 0xfff;
245
246 if (AC_VERB_GET_AMP_GAIN_MUTE == (vid & 0xf00)) {
247 index = (reg >> 8) & 0xf;
248 reg = (reg & ~0xf0f) | index;
249 }
250 be_reg = cpu_to_be32(reg);
251
252 /* Write register */
253 xfer[0].addr = client->addr;
254 xfer[0].flags = 0;
255 xfer[0].len = 4;
256 xfer[0].buf = (u8 *)&be_reg;
257
258 /* Read data */
259 xfer[1].addr = client->addr;
260 xfer[1].flags = I2C_M_RD;
261 xfer[1].len = 4;
262 xfer[1].buf = (u8 *)&buf;
263
264 ret = i2c_transfer(client->adapter, xfer, 2);
265 if (ret < 0)
266 return ret;
267 else if (ret != 2)
268 return -EIO;
269
270 *value = be32_to_cpu(buf);
271
272 return 0;
273}
274
Thierry Reding81f3dfe2014-10-02 09:27:03 +0200275#ifdef CONFIG_PM
Bard Liao07cf7cba2014-06-20 14:41:13 +0800276static void rt286_index_sync(struct snd_soc_codec *codec)
277{
278 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
279 int i;
280
281 for (i = 0; i < INDEX_CACHE_SIZE; i++) {
282 snd_soc_write(codec, rt286->index_cache[i].reg,
283 rt286->index_cache[i].def);
284 }
285}
Thierry Reding81f3dfe2014-10-02 09:27:03 +0200286#endif
Bard Liao07cf7cba2014-06-20 14:41:13 +0800287
288static int rt286_support_power_controls[] = {
289 RT286_DAC_OUT1,
290 RT286_DAC_OUT2,
291 RT286_ADC_IN1,
292 RT286_ADC_IN2,
293 RT286_MIC1,
294 RT286_DMIC1,
295 RT286_DMIC2,
296 RT286_SPK_OUT,
297 RT286_HP_OUT,
298};
299#define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls)
300
Bard Liao90f601e2014-07-29 13:50:57 +0800301static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic)
Bard Liao07cf7cba2014-06-20 14:41:13 +0800302{
Bard Liao07cf7cba2014-06-20 14:41:13 +0800303 unsigned int val, buf;
Bard Liao07cf7cba2014-06-20 14:41:13 +0800304
305 *hp = false;
306 *mic = false;
307
Bard Liao28d1ad02015-02-05 16:40:33 +0800308 if (!rt286->codec)
309 return -EINVAL;
Bard Liao07cf7cba2014-06-20 14:41:13 +0800310 if (rt286->pdata.cbj_en) {
Bard Liao90f601e2014-07-29 13:50:57 +0800311 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800312 *hp = buf & 0x80000000;
313 if (*hp) {
314 /* power on HV,VERF */
Bard Liao90f601e2014-07-29 13:50:57 +0800315 regmap_update_bits(rt286->regmap,
Bard Liao6879db72014-10-31 14:52:16 +0800316 RT286_DC_GAIN, 0x200, 0x200);
317
318 snd_soc_dapm_force_enable_pin(&rt286->codec->dapm,
319 "HV");
320 snd_soc_dapm_force_enable_pin(&rt286->codec->dapm,
321 "VREF");
Bard Liao07cf7cba2014-06-20 14:41:13 +0800322 /* power LDO1 */
Bard Liao6879db72014-10-31 14:52:16 +0800323 snd_soc_dapm_force_enable_pin(&rt286->codec->dapm,
324 "LDO1");
325 snd_soc_dapm_sync(&rt286->codec->dapm);
326
Bard Liao90f601e2014-07-29 13:50:57 +0800327 regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24);
Bard Liao6879db72014-10-31 14:52:16 +0800328 msleep(50);
329
330 regmap_update_bits(rt286->regmap,
331 RT286_CBJ_CTRL1, 0xfcc0, 0xd400);
332 msleep(300);
Bard Liao90f601e2014-07-29 13:50:57 +0800333 regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800334
Bard Liao6879db72014-10-31 14:52:16 +0800335 if (0x0070 == (val & 0x0070)) {
336 *mic = true;
337 } else {
338 regmap_update_bits(rt286->regmap,
339 RT286_CBJ_CTRL1, 0xfcc0, 0xe400);
340 msleep(300);
Bard Liao90f601e2014-07-29 13:50:57 +0800341 regmap_read(rt286->regmap,
342 RT286_CBJ_CTRL2, &val);
Bard Liao6879db72014-10-31 14:52:16 +0800343 if (0x0070 == (val & 0x0070))
344 *mic = true;
345 else
346 *mic = false;
Bard Liao07cf7cba2014-06-20 14:41:13 +0800347 }
Bard Liao90f601e2014-07-29 13:50:57 +0800348 regmap_update_bits(rt286->regmap,
Bard Liao6879db72014-10-31 14:52:16 +0800349 RT286_DC_GAIN, 0x200, 0x0);
350
Bard Liao07cf7cba2014-06-20 14:41:13 +0800351 } else {
Bard Liao07cf7cba2014-06-20 14:41:13 +0800352 *mic = false;
Bard Liao6879db72014-10-31 14:52:16 +0800353 regmap_write(rt286->regmap, RT286_SET_MIC1, 0x20);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800354 }
355 } else {
Bard Liao90f601e2014-07-29 13:50:57 +0800356 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800357 *hp = buf & 0x80000000;
Bard Liao90f601e2014-07-29 13:50:57 +0800358 regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800359 *mic = buf & 0x80000000;
360 }
361
Bard Liao6879db72014-10-31 14:52:16 +0800362 snd_soc_dapm_disable_pin(&rt286->codec->dapm, "HV");
363 snd_soc_dapm_disable_pin(&rt286->codec->dapm, "VREF");
364 if (!*hp)
365 snd_soc_dapm_disable_pin(&rt286->codec->dapm, "LDO1");
366 snd_soc_dapm_sync(&rt286->codec->dapm);
367
Bard Liao07cf7cba2014-06-20 14:41:13 +0800368 return 0;
369}
370
371static void rt286_jack_detect_work(struct work_struct *work)
372{
373 struct rt286_priv *rt286 =
374 container_of(work, struct rt286_priv, jack_detect_work.work);
375 int status = 0;
376 bool hp = false;
377 bool mic = false;
378
Bard Liao90f601e2014-07-29 13:50:57 +0800379 rt286_jack_detect(rt286, &hp, &mic);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800380
381 if (hp == true)
382 status |= SND_JACK_HEADPHONE;
383
384 if (mic == true)
385 status |= SND_JACK_MICROPHONE;
386
387 snd_soc_jack_report(rt286->jack, status,
388 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
389}
390
391int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
392{
393 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
394
395 rt286->jack = jack;
396
397 /* Send an initial empty report */
398 snd_soc_jack_report(rt286->jack, 0,
399 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
400
401 return 0;
402}
403EXPORT_SYMBOL_GPL(rt286_mic_detect);
404
Bard Liao6879db72014-10-31 14:52:16 +0800405static int is_mclk_mode(struct snd_soc_dapm_widget *source,
406 struct snd_soc_dapm_widget *sink)
407{
408 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(source->codec);
409
410 if (rt286->clk_id == RT286_SCLK_S_MCLK)
411 return 1;
412 else
413 return 0;
414}
415
Bard Liao07cf7cba2014-06-20 14:41:13 +0800416static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
417static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
418
419static const struct snd_kcontrol_new rt286_snd_controls[] = {
420 SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN,
421 RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
Bard Liao54d96a42015-01-23 14:51:09 +0800422 SOC_DOUBLE_R("ADC0 Capture Switch", RT286_ADCL_GAIN,
423 RT286_ADCR_GAIN, 7, 1, 1),
Bard Liao07cf7cba2014-06-20 14:41:13 +0800424 SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN,
425 RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
426 SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN,
427 0, 0x3, 0, mic_vol_tlv),
428 SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN,
429 RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1),
430};
431
432/* Digital Mixer */
433static const struct snd_kcontrol_new rt286_front_mix[] = {
434 SOC_DAPM_SINGLE("DAC Switch", RT286_F_DAC_SWITCH,
435 RT286_MUTE_SFT, 1, 1),
436 SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH,
437 RT286_MUTE_SFT, 1, 1),
438};
439
440/* Analog Input Mixer */
441static const struct snd_kcontrol_new rt286_rec_mix[] = {
442 SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH,
443 RT286_MUTE_SFT, 1, 1),
444 SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH,
445 RT286_MUTE_SFT, 1, 1),
446 SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH,
447 RT286_MUTE_SFT, 1, 1),
448 SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH,
449 RT286_MUTE_SFT, 1, 1),
450};
451
452static const struct snd_kcontrol_new spo_enable_control =
453 SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK,
454 RT286_SET_PIN_SFT, 1, 0);
455
456static const struct snd_kcontrol_new hpol_enable_control =
457 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN,
458 RT286_MUTE_SFT, 1, 1);
459
460static const struct snd_kcontrol_new hpor_enable_control =
461 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN,
462 RT286_MUTE_SFT, 1, 1);
463
464/* ADC0 source */
465static const char * const rt286_adc_src[] = {
466 "Mic", "RECMIX", "Dmic"
467};
468
469static const int rt286_adc_values[] = {
470 0, 4, 5,
471};
472
473static SOC_VALUE_ENUM_SINGLE_DECL(
474 rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT,
475 RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
476
477static const struct snd_kcontrol_new rt286_adc0_mux =
478 SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum);
479
480static SOC_VALUE_ENUM_SINGLE_DECL(
481 rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT,
482 RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
483
484static const struct snd_kcontrol_new rt286_adc1_mux =
485 SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum);
486
487static const char * const rt286_dac_src[] = {
488 "Front", "Surround"
489};
490/* HP-OUT source */
491static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX,
492 0, rt286_dac_src);
493
494static const struct snd_kcontrol_new rt286_hpo_mux =
495SOC_DAPM_ENUM("HPO source", rt286_hpo_enum);
496
497/* SPK-OUT source */
498static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX,
499 0, rt286_dac_src);
500
501static const struct snd_kcontrol_new rt286_spo_mux =
502SOC_DAPM_ENUM("SPO source", rt286_spo_enum);
503
504static int rt286_spk_event(struct snd_soc_dapm_widget *w,
505 struct snd_kcontrol *kcontrol, int event)
506{
507 struct snd_soc_codec *codec = w->codec;
508
509 switch (event) {
510 case SND_SOC_DAPM_POST_PMU:
511 snd_soc_write(codec,
512 RT286_SPK_EAPD, RT286_SET_EAPD_HIGH);
513 break;
514 case SND_SOC_DAPM_PRE_PMD:
515 snd_soc_write(codec,
516 RT286_SPK_EAPD, RT286_SET_EAPD_LOW);
517 break;
518
519 default:
520 return 0;
521 }
522
523 return 0;
524}
525
526static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w,
527 struct snd_kcontrol *kcontrol, int event)
528{
529 struct snd_soc_codec *codec = w->codec;
530
531 switch (event) {
532 case SND_SOC_DAPM_POST_PMU:
533 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0x20);
534 break;
535 case SND_SOC_DAPM_PRE_PMD:
536 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0);
537 break;
538 default:
539 return 0;
540 }
541
542 return 0;
543}
544
Bard Liao6879db72014-10-31 14:52:16 +0800545static int rt286_vref_event(struct snd_soc_dapm_widget *w,
546 struct snd_kcontrol *kcontrol, int event)
547{
548 struct snd_soc_codec *codec = w->codec;
549
550 switch (event) {
551 case SND_SOC_DAPM_PRE_PMU:
552 snd_soc_update_bits(codec,
553 RT286_CBJ_CTRL1, 0x0400, 0x0000);
554 mdelay(50);
555 break;
556 default:
557 return 0;
558 }
559
560 return 0;
561}
562
563static int rt286_ldo2_event(struct snd_soc_dapm_widget *w,
564 struct snd_kcontrol *kcontrol, int event)
565{
566 struct snd_soc_codec *codec = w->codec;
567
568 switch (event) {
569 case SND_SOC_DAPM_POST_PMU:
570 snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x08);
571 break;
572 case SND_SOC_DAPM_PRE_PMD:
573 snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x30);
574 break;
575 default:
576 return 0;
577 }
578
579 return 0;
580}
581
582static int rt286_mic1_event(struct snd_soc_dapm_widget *w,
583 struct snd_kcontrol *kcontrol, int event)
584{
585 struct snd_soc_codec *codec = w->codec;
586
587 switch (event) {
588 case SND_SOC_DAPM_PRE_PMU:
589 snd_soc_update_bits(codec,
590 RT286_A_BIAS_CTRL3, 0xc000, 0x8000);
591 snd_soc_update_bits(codec,
592 RT286_A_BIAS_CTRL2, 0xc000, 0x8000);
593 break;
594 case SND_SOC_DAPM_POST_PMD:
595 snd_soc_update_bits(codec,
596 RT286_A_BIAS_CTRL3, 0xc000, 0x0000);
597 snd_soc_update_bits(codec,
598 RT286_A_BIAS_CTRL2, 0xc000, 0x0000);
599 break;
600 default:
601 return 0;
602 }
603
604 return 0;
605}
606
Bard Liao07cf7cba2014-06-20 14:41:13 +0800607static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = {
Bard Liao6879db72014-10-31 14:52:16 +0800608 SND_SOC_DAPM_SUPPLY_S("HV", 1, RT286_POWER_CTRL1,
609 12, 1, NULL, 0),
610 SND_SOC_DAPM_SUPPLY("VREF", RT286_POWER_CTRL1,
611 0, 1, rt286_vref_event, SND_SOC_DAPM_PRE_PMU),
612 SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT286_POWER_CTRL2,
613 2, 0, NULL, 0),
614 SND_SOC_DAPM_SUPPLY_S("LDO2", 2, RT286_POWER_CTRL1,
615 13, 1, rt286_ldo2_event, SND_SOC_DAPM_PRE_PMD |
616 SND_SOC_DAPM_POST_PMU),
617 SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1,
618 5, 0, NULL, 0),
619 SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
620 0, 0, rt286_mic1_event, SND_SOC_DAPM_PRE_PMU |
621 SND_SOC_DAPM_POST_PMD),
622
Bard Liao07cf7cba2014-06-20 14:41:13 +0800623 /* Input Lines */
624 SND_SOC_DAPM_INPUT("DMIC1 Pin"),
625 SND_SOC_DAPM_INPUT("DMIC2 Pin"),
626 SND_SOC_DAPM_INPUT("MIC1"),
627 SND_SOC_DAPM_INPUT("LINE1"),
628 SND_SOC_DAPM_INPUT("Beep"),
629
630 /* DMIC */
631 SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1,
632 NULL, 0, rt286_set_dmic1_event,
633 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
634 SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1,
635 NULL, 0),
636 SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
637 0, 0, NULL, 0),
638
639 /* REC Mixer */
640 SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
641 rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)),
642
643 /* ADCs */
644 SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
645 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
646
647 /* ADC Mux */
Bard Liao54d96a42015-01-23 14:51:09 +0800648 SND_SOC_DAPM_MUX("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1,
649 &rt286_adc0_mux),
650 SND_SOC_DAPM_MUX("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1,
651 &rt286_adc1_mux),
Bard Liao07cf7cba2014-06-20 14:41:13 +0800652
653 /* Audio Interface */
654 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
655 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
656 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
657 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
658
659 /* Output Side */
660 /* DACs */
661 SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
662 SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
663
664 /* Output Mux */
665 SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux),
666 SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux),
667
668 SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO,
669 RT286_SET_PIN_SFT, 0, NULL, 0),
670
671 /* Output Mixer */
672 SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1,
673 rt286_front_mix, ARRAY_SIZE(rt286_front_mix)),
674 SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1,
675 NULL, 0),
676
677 /* Output Pga */
678 SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
679 &spo_enable_control, rt286_spk_event,
680 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
681 SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
682 &hpol_enable_control),
683 SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
684 &hpor_enable_control),
685
686 /* Output Lines */
687 SND_SOC_DAPM_OUTPUT("SPOL"),
688 SND_SOC_DAPM_OUTPUT("SPOR"),
689 SND_SOC_DAPM_OUTPUT("HPO Pin"),
690 SND_SOC_DAPM_OUTPUT("SPDIF"),
691};
692
693static const struct snd_soc_dapm_route rt286_dapm_routes[] = {
Bard Liao6879db72014-10-31 14:52:16 +0800694 {"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
695 {"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
696 {"Front", NULL, "MCLK MODE", is_mclk_mode},
697 {"Surround", NULL, "MCLK MODE", is_mclk_mode},
698
699 {"HP Power", NULL, "LDO1"},
700 {"HP Power", NULL, "LDO2"},
701
702 {"MIC1", NULL, "LDO1"},
703 {"MIC1", NULL, "LDO2"},
704 {"MIC1", NULL, "HV"},
705 {"MIC1", NULL, "VREF"},
706 {"MIC1", NULL, "MIC1 Input Buffer"},
707
708 {"SPO", NULL, "LDO1"},
709 {"SPO", NULL, "LDO2"},
710 {"SPO", NULL, "HV"},
711 {"SPO", NULL, "VREF"},
712
Bard Liao07cf7cba2014-06-20 14:41:13 +0800713 {"DMIC1", NULL, "DMIC1 Pin"},
714 {"DMIC2", NULL, "DMIC2 Pin"},
715 {"DMIC1", NULL, "DMIC Receiver"},
716 {"DMIC2", NULL, "DMIC Receiver"},
717
718 {"RECMIX", "Beep Switch", "Beep"},
719 {"RECMIX", "Line1 Switch", "LINE1"},
720 {"RECMIX", "Mic1 Switch", "MIC1"},
721
722 {"ADC 0 Mux", "Dmic", "DMIC1"},
723 {"ADC 0 Mux", "RECMIX", "RECMIX"},
724 {"ADC 0 Mux", "Mic", "MIC1"},
725 {"ADC 1 Mux", "Dmic", "DMIC2"},
726 {"ADC 1 Mux", "RECMIX", "RECMIX"},
727 {"ADC 1 Mux", "Mic", "MIC1"},
728
729 {"ADC 0", NULL, "ADC 0 Mux"},
730 {"ADC 1", NULL, "ADC 1 Mux"},
731
732 {"AIF1TX", NULL, "ADC 0"},
733 {"AIF2TX", NULL, "ADC 1"},
734
735 {"DAC 0", NULL, "AIF1RX"},
736 {"DAC 1", NULL, "AIF2RX"},
737
738 {"Front", "DAC Switch", "DAC 0"},
739 {"Front", "RECMIX Switch", "RECMIX"},
740
741 {"Surround", NULL, "DAC 1"},
742
743 {"SPK Mux", "Front", "Front"},
744 {"SPK Mux", "Surround", "Surround"},
745
746 {"HPO Mux", "Front", "Front"},
747 {"HPO Mux", "Surround", "Surround"},
748
749 {"SPO", "Switch", "SPK Mux"},
750 {"HPO L", "Switch", "HPO Mux"},
751 {"HPO R", "Switch", "HPO Mux"},
752 {"HPO L", NULL, "HP Power"},
753 {"HPO R", NULL, "HP Power"},
754
755 {"SPOL", NULL, "SPO"},
756 {"SPOR", NULL, "SPO"},
757 {"HPO Pin", NULL, "HPO L"},
758 {"HPO Pin", NULL, "HPO R"},
759};
760
761static int rt286_hw_params(struct snd_pcm_substream *substream,
762 struct snd_pcm_hw_params *params,
763 struct snd_soc_dai *dai)
764{
765 struct snd_soc_codec *codec = dai->codec;
766 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
767 unsigned int val = 0;
768 int d_len_code;
769
770 switch (params_rate(params)) {
771 /* bit 14 0:48K 1:44.1K */
772 case 44100:
773 val |= 0x4000;
774 break;
775 case 48000:
776 break;
777 default:
778 dev_err(codec->dev, "Unsupported sample rate %d\n",
779 params_rate(params));
780 return -EINVAL;
781 }
782 switch (rt286->sys_clk) {
783 case 12288000:
784 case 24576000:
785 if (params_rate(params) != 48000) {
786 dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
787 params_rate(params), rt286->sys_clk);
788 return -EINVAL;
789 }
790 break;
791 case 11289600:
792 case 22579200:
793 if (params_rate(params) != 44100) {
794 dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
795 params_rate(params), rt286->sys_clk);
796 return -EINVAL;
797 }
798 break;
799 }
800
801 if (params_channels(params) <= 16) {
802 /* bit 3:0 Number of Channel */
803 val |= (params_channels(params) - 1);
804 } else {
805 dev_err(codec->dev, "Unsupported channels %d\n",
806 params_channels(params));
807 return -EINVAL;
808 }
809
810 d_len_code = 0;
811 switch (params_width(params)) {
812 /* bit 6:4 Bits per Sample */
813 case 16:
814 d_len_code = 0;
815 val |= (0x1 << 4);
816 break;
817 case 32:
818 d_len_code = 2;
819 val |= (0x4 << 4);
820 break;
821 case 20:
822 d_len_code = 1;
823 val |= (0x2 << 4);
824 break;
825 case 24:
826 d_len_code = 2;
827 val |= (0x3 << 4);
828 break;
829 case 8:
830 d_len_code = 3;
831 break;
832 default:
833 return -EINVAL;
834 }
835
836 snd_soc_update_bits(codec,
837 RT286_I2S_CTRL1, 0x0018, d_len_code << 3);
838 dev_dbg(codec->dev, "format val = 0x%x\n", val);
839
Bard Liao45437fa2015-01-15 10:49:25 +0800840 snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x407f, val);
841 snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x407f, val);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800842
843 return 0;
844}
845
846static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
847{
848 struct snd_soc_codec *codec = dai->codec;
849
850 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
851 case SND_SOC_DAIFMT_CBM_CFM:
852 snd_soc_update_bits(codec,
853 RT286_I2S_CTRL1, 0x800, 0x800);
854 break;
855 case SND_SOC_DAIFMT_CBS_CFS:
856 snd_soc_update_bits(codec,
857 RT286_I2S_CTRL1, 0x800, 0x0);
858 break;
859 default:
860 return -EINVAL;
861 }
862
863 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
864 case SND_SOC_DAIFMT_I2S:
865 snd_soc_update_bits(codec,
866 RT286_I2S_CTRL1, 0x300, 0x0);
867 break;
868 case SND_SOC_DAIFMT_LEFT_J:
869 snd_soc_update_bits(codec,
870 RT286_I2S_CTRL1, 0x300, 0x1 << 8);
871 break;
872 case SND_SOC_DAIFMT_DSP_A:
873 snd_soc_update_bits(codec,
874 RT286_I2S_CTRL1, 0x300, 0x2 << 8);
875 break;
876 case SND_SOC_DAIFMT_DSP_B:
877 snd_soc_update_bits(codec,
878 RT286_I2S_CTRL1, 0x300, 0x3 << 8);
879 break;
880 default:
881 return -EINVAL;
882 }
883 /* bit 15 Stream Type 0:PCM 1:Non-PCM */
884 snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x8000, 0);
885 snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x8000, 0);
886
887 return 0;
888}
889
890static int rt286_set_dai_sysclk(struct snd_soc_dai *dai,
891 int clk_id, unsigned int freq, int dir)
892{
893 struct snd_soc_codec *codec = dai->codec;
894 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
895
896 dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq);
897
898 if (RT286_SCLK_S_MCLK == clk_id) {
899 snd_soc_update_bits(codec,
900 RT286_I2S_CTRL2, 0x0100, 0x0);
901 snd_soc_update_bits(codec,
902 RT286_PLL_CTRL1, 0x20, 0x20);
903 } else {
904 snd_soc_update_bits(codec,
905 RT286_I2S_CTRL2, 0x0100, 0x0100);
906 snd_soc_update_bits(codec,
907 RT286_PLL_CTRL, 0x4, 0x4);
908 snd_soc_update_bits(codec,
909 RT286_PLL_CTRL1, 0x20, 0x0);
910 }
911
912 switch (freq) {
913 case 19200000:
914 if (RT286_SCLK_S_MCLK == clk_id) {
915 dev_err(codec->dev, "Should not use MCLK\n");
916 return -EINVAL;
917 }
918 snd_soc_update_bits(codec,
919 RT286_I2S_CTRL2, 0x40, 0x40);
920 break;
921 case 24000000:
922 if (RT286_SCLK_S_MCLK == clk_id) {
923 dev_err(codec->dev, "Should not use MCLK\n");
924 return -EINVAL;
925 }
926 snd_soc_update_bits(codec,
927 RT286_I2S_CTRL2, 0x40, 0x0);
928 break;
929 case 12288000:
930 case 11289600:
931 snd_soc_update_bits(codec,
932 RT286_I2S_CTRL2, 0x8, 0x0);
933 snd_soc_update_bits(codec,
934 RT286_CLK_DIV, 0xfc1e, 0x0004);
935 break;
936 case 24576000:
937 case 22579200:
938 snd_soc_update_bits(codec,
939 RT286_I2S_CTRL2, 0x8, 0x8);
940 snd_soc_update_bits(codec,
941 RT286_CLK_DIV, 0xfc1e, 0x5406);
942 break;
943 default:
944 dev_err(codec->dev, "Unsupported system clock\n");
945 return -EINVAL;
946 }
947
948 rt286->sys_clk = freq;
Bard Liao6879db72014-10-31 14:52:16 +0800949 rt286->clk_id = clk_id;
Bard Liao07cf7cba2014-06-20 14:41:13 +0800950
951 return 0;
952}
953
954static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
955{
956 struct snd_soc_codec *codec = dai->codec;
957
958 dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
959 if (50 == ratio)
960 snd_soc_update_bits(codec,
961 RT286_I2S_CTRL1, 0x1000, 0x1000);
962 else
963 snd_soc_update_bits(codec,
964 RT286_I2S_CTRL1, 0x1000, 0x0);
965
966
967 return 0;
968}
969
970static int rt286_set_bias_level(struct snd_soc_codec *codec,
971 enum snd_soc_bias_level level)
972{
973 switch (level) {
974 case SND_SOC_BIAS_PREPARE:
Bard Liaobc6c4e42014-07-07 19:15:30 +0800975 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
Bard Liao07cf7cba2014-06-20 14:41:13 +0800976 snd_soc_write(codec,
977 RT286_SET_AUDIO_POWER, AC_PWRST_D0);
Bard Liaobc6c4e42014-07-07 19:15:30 +0800978 snd_soc_update_bits(codec,
979 RT286_DC_GAIN, 0x200, 0x200);
980 }
981 break;
982
983 case SND_SOC_BIAS_ON:
984 mdelay(10);
Bard Liao6879db72014-10-31 14:52:16 +0800985 snd_soc_update_bits(codec,
986 RT286_CBJ_CTRL1, 0x0400, 0x0400);
987 snd_soc_update_bits(codec,
988 RT286_DC_GAIN, 0x200, 0x0);
989
Bard Liao07cf7cba2014-06-20 14:41:13 +0800990 break;
991
992 case SND_SOC_BIAS_STANDBY:
993 snd_soc_write(codec,
994 RT286_SET_AUDIO_POWER, AC_PWRST_D3);
Bard Liaobc6c4e42014-07-07 19:15:30 +0800995 snd_soc_update_bits(codec,
Bard Liao6879db72014-10-31 14:52:16 +0800996 RT286_CBJ_CTRL1, 0x0400, 0x0000);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800997 break;
998
999 default:
1000 break;
1001 }
1002 codec->dapm.bias_level = level;
1003
1004 return 0;
1005}
1006
1007static irqreturn_t rt286_irq(int irq, void *data)
1008{
1009 struct rt286_priv *rt286 = data;
1010 bool hp = false;
1011 bool mic = false;
1012 int status = 0;
1013
Bard Liao90f601e2014-07-29 13:50:57 +08001014 rt286_jack_detect(rt286, &hp, &mic);
Bard Liao07cf7cba2014-06-20 14:41:13 +08001015
1016 /* Clear IRQ */
Bard Liao90f601e2014-07-29 13:50:57 +08001017 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1);
Bard Liao07cf7cba2014-06-20 14:41:13 +08001018
1019 if (hp == true)
1020 status |= SND_JACK_HEADPHONE;
1021
1022 if (mic == true)
1023 status |= SND_JACK_MICROPHONE;
1024
1025 snd_soc_jack_report(rt286->jack, status,
1026 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
1027
1028 pm_wakeup_event(&rt286->i2c->dev, 300);
1029
1030 return IRQ_HANDLED;
1031}
1032
1033static int rt286_probe(struct snd_soc_codec *codec)
1034{
1035 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
Bard Liao07cf7cba2014-06-20 14:41:13 +08001036
Bard Liao6879db72014-10-31 14:52:16 +08001037 rt286->codec = codec;
Bard Liao07cf7cba2014-06-20 14:41:13 +08001038 codec->dapm.bias_level = SND_SOC_BIAS_OFF;
Bard Liao90f601e2014-07-29 13:50:57 +08001039
1040 if (rt286->i2c->irq) {
1041 regmap_update_bits(rt286->regmap,
1042 RT286_IRQ_CTRL, 0x2, 0x2);
1043
1044 INIT_DELAYED_WORK(&rt286->jack_detect_work,
1045 rt286_jack_detect_work);
1046 schedule_delayed_work(&rt286->jack_detect_work,
1047 msecs_to_jiffies(1250));
1048 }
Bard Liao07cf7cba2014-06-20 14:41:13 +08001049
Bard Liao07cf7cba2014-06-20 14:41:13 +08001050 return 0;
1051}
1052
1053static int rt286_remove(struct snd_soc_codec *codec)
1054{
1055 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1056
1057 cancel_delayed_work_sync(&rt286->jack_detect_work);
1058
1059 return 0;
1060}
1061
1062#ifdef CONFIG_PM
1063static int rt286_suspend(struct snd_soc_codec *codec)
1064{
1065 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1066
1067 regcache_cache_only(rt286->regmap, true);
1068 regcache_mark_dirty(rt286->regmap);
1069
1070 return 0;
1071}
1072
1073static int rt286_resume(struct snd_soc_codec *codec)
1074{
1075 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1076
1077 regcache_cache_only(rt286->regmap, false);
1078 rt286_index_sync(codec);
1079 regcache_sync(rt286->regmap);
1080
1081 return 0;
1082}
1083#else
1084#define rt286_suspend NULL
1085#define rt286_resume NULL
1086#endif
1087
1088#define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1089#define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1090 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1091
1092static const struct snd_soc_dai_ops rt286_aif_dai_ops = {
1093 .hw_params = rt286_hw_params,
1094 .set_fmt = rt286_set_dai_fmt,
1095 .set_sysclk = rt286_set_dai_sysclk,
1096 .set_bclk_ratio = rt286_set_bclk_ratio,
1097};
1098
1099static struct snd_soc_dai_driver rt286_dai[] = {
1100 {
1101 .name = "rt286-aif1",
1102 .id = RT286_AIF1,
1103 .playback = {
1104 .stream_name = "AIF1 Playback",
1105 .channels_min = 1,
1106 .channels_max = 2,
1107 .rates = RT286_STEREO_RATES,
1108 .formats = RT286_FORMATS,
1109 },
1110 .capture = {
1111 .stream_name = "AIF1 Capture",
1112 .channels_min = 1,
1113 .channels_max = 2,
1114 .rates = RT286_STEREO_RATES,
1115 .formats = RT286_FORMATS,
1116 },
1117 .ops = &rt286_aif_dai_ops,
1118 .symmetric_rates = 1,
1119 },
1120 {
1121 .name = "rt286-aif2",
1122 .id = RT286_AIF2,
1123 .playback = {
1124 .stream_name = "AIF2 Playback",
1125 .channels_min = 1,
1126 .channels_max = 2,
1127 .rates = RT286_STEREO_RATES,
1128 .formats = RT286_FORMATS,
1129 },
1130 .capture = {
1131 .stream_name = "AIF2 Capture",
1132 .channels_min = 1,
1133 .channels_max = 2,
1134 .rates = RT286_STEREO_RATES,
1135 .formats = RT286_FORMATS,
1136 },
1137 .ops = &rt286_aif_dai_ops,
1138 .symmetric_rates = 1,
1139 },
1140
1141};
1142
1143static struct snd_soc_codec_driver soc_codec_dev_rt286 = {
1144 .probe = rt286_probe,
1145 .remove = rt286_remove,
1146 .suspend = rt286_suspend,
1147 .resume = rt286_resume,
1148 .set_bias_level = rt286_set_bias_level,
1149 .idle_bias_off = true,
1150 .controls = rt286_snd_controls,
1151 .num_controls = ARRAY_SIZE(rt286_snd_controls),
1152 .dapm_widgets = rt286_dapm_widgets,
1153 .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets),
1154 .dapm_routes = rt286_dapm_routes,
1155 .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes),
1156};
1157
1158static const struct regmap_config rt286_regmap = {
1159 .reg_bits = 32,
1160 .val_bits = 32,
1161 .max_register = 0x02370100,
1162 .volatile_reg = rt286_volatile_register,
1163 .readable_reg = rt286_readable_register,
1164 .reg_write = rt286_hw_write,
1165 .reg_read = rt286_hw_read,
1166 .cache_type = REGCACHE_RBTREE,
1167 .reg_defaults = rt286_reg,
1168 .num_reg_defaults = ARRAY_SIZE(rt286_reg),
1169};
1170
1171static const struct i2c_device_id rt286_i2c_id[] = {
1172 {"rt286", 0},
1173 {}
1174};
1175MODULE_DEVICE_TABLE(i2c, rt286_i2c_id);
1176
1177static const struct acpi_device_id rt286_acpi_match[] = {
1178 { "INT343A", 0 },
1179 {},
1180};
1181MODULE_DEVICE_TABLE(acpi, rt286_acpi_match);
1182
Sudip Mukherjeea5a267c2014-11-18 17:42:54 +05301183static struct dmi_system_id force_combo_jack_table[] = {
Bard Liao6c67cde2014-11-06 09:59:59 +08001184 {
1185 .ident = "Intel Wilson Beach",
1186 .matches = {
1187 DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS")
1188 }
1189 },
1190 { }
1191};
1192
Bard Liao07cf7cba2014-06-20 14:41:13 +08001193static int rt286_i2c_probe(struct i2c_client *i2c,
1194 const struct i2c_device_id *id)
1195{
1196 struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev);
1197 struct rt286_priv *rt286;
Bard Liao61a414c2014-07-07 16:48:38 +08001198 int i, ret;
Bard Liao07cf7cba2014-06-20 14:41:13 +08001199
1200 rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286),
1201 GFP_KERNEL);
1202 if (NULL == rt286)
1203 return -ENOMEM;
1204
1205 rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap);
1206 if (IS_ERR(rt286->regmap)) {
1207 ret = PTR_ERR(rt286->regmap);
1208 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1209 ret);
1210 return ret;
1211 }
1212
Bard Liao4b21768a2014-07-07 16:48:37 +08001213 regmap_read(rt286->regmap,
1214 RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &ret);
1215 if (ret != RT286_VENDOR_ID) {
1216 dev_err(&i2c->dev,
1217 "Device with ID register %x is not rt286\n", ret);
1218 return -ENODEV;
1219 }
1220
Bard Liao07cf7cba2014-06-20 14:41:13 +08001221 rt286->index_cache = rt286_index_def;
1222 rt286->i2c = i2c;
1223 i2c_set_clientdata(i2c, rt286);
1224
1225 if (pdata)
1226 rt286->pdata = *pdata;
1227
Bard Liao6c67cde2014-11-06 09:59:59 +08001228 if (dmi_check_system(force_combo_jack_table))
1229 rt286->pdata.cbj_en = true;
1230
Bard Liao61a414c2014-07-07 16:48:38 +08001231 regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3);
1232
1233 for (i = 0; i < RT286_POWER_REG_LEN; i++)
1234 regmap_write(rt286->regmap,
1235 RT286_SET_POWER(rt286_support_power_controls[i]),
1236 AC_PWRST_D1);
1237
1238 if (!rt286->pdata.cbj_en) {
1239 regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000);
1240 regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816);
Bard Liao61a414c2014-07-07 16:48:38 +08001241 regmap_update_bits(rt286->regmap,
1242 RT286_CBJ_CTRL1, 0xf000, 0xb000);
1243 } else {
1244 regmap_update_bits(rt286->regmap,
1245 RT286_CBJ_CTRL1, 0xf000, 0x5000);
1246 }
1247
1248 mdelay(10);
1249
1250 if (!rt286->pdata.gpio2_en)
1251 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x4000);
1252 else
1253 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0);
1254
1255 mdelay(10);
1256
Bard Liao6879db72014-10-31 14:52:16 +08001257 regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000);
Bard Liaof8c101b2014-11-06 10:00:00 +08001258 /* Power down LDO, VREF */
Bard Liao6879db72014-10-31 14:52:16 +08001259 regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0xc, 0x0);
1260 regmap_update_bits(rt286->regmap, RT286_POWER_CTRL1, 0x1001, 0x1001);
Bard Liao61a414c2014-07-07 16:48:38 +08001261
Bard Liaof8c101b2014-11-06 10:00:00 +08001262 /* Set depop parameter */
Bard Liaobc6c4e42014-07-07 19:15:30 +08001263 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a);
1264 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737);
1265 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
1266
Bard Liao61a414c2014-07-07 16:48:38 +08001267 if (rt286->i2c->irq) {
Bard Liao61a414c2014-07-07 16:48:38 +08001268 ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq,
1269 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286);
1270 if (ret != 0) {
1271 dev_err(&i2c->dev,
1272 "Failed to reguest IRQ: %d\n", ret);
1273 return ret;
1274 }
1275 }
1276
Bard Liao07cf7cba2014-06-20 14:41:13 +08001277 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt286,
1278 rt286_dai, ARRAY_SIZE(rt286_dai));
1279
1280 return ret;
1281}
1282
1283static int rt286_i2c_remove(struct i2c_client *i2c)
1284{
1285 struct rt286_priv *rt286 = i2c_get_clientdata(i2c);
1286
1287 if (i2c->irq)
1288 free_irq(i2c->irq, rt286);
1289 snd_soc_unregister_codec(&i2c->dev);
1290
1291 return 0;
1292}
1293
1294
Bard Liao23c4fd52014-07-14 10:18:04 +08001295static struct i2c_driver rt286_i2c_driver = {
Bard Liao07cf7cba2014-06-20 14:41:13 +08001296 .driver = {
1297 .name = "rt286",
1298 .owner = THIS_MODULE,
1299 .acpi_match_table = ACPI_PTR(rt286_acpi_match),
1300 },
1301 .probe = rt286_i2c_probe,
1302 .remove = rt286_i2c_remove,
1303 .id_table = rt286_i2c_id,
1304};
1305
1306module_i2c_driver(rt286_i2c_driver);
1307
1308MODULE_DESCRIPTION("ASoC RT286 driver");
1309MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1310MODULE_LICENSE("GPL");