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gerrit-public.fairphone.software / kernel / msm-4.9 / 2a5fdc9adde8476751b63a795e3d66ae2ee3979d / . / arch / arm / boot / dts / tegra-cardhu.dts
blob: e14bb450c3289000966c10326a06087d91ed13f3 [file] [log] [blame]
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]1/dts-v1/;
2
3/include/ "tegra30.dtsi"
4
5/ {
6 model = "NVIDIA Tegra30 Cardhu evaluation board";
7 compatible = "nvidia,cardhu", "nvidia,tegra30";
8
9 memory {
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]10 reg = <0x80000000 0x40000000>;
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]11 };
12
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]13 pinmux {
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 sdmmc1_clk_pz0 {
19 nvidia,pins = "sdmmc1_clk_pz0";
20 nvidia,function = "sdmmc1";
21 nvidia,pull = <0>;
22 nvidia,tristate = <0>;
23 };
24 sdmmc1_cmd_pz1 {
25 nvidia,pins = "sdmmc1_cmd_pz1",
26 "sdmmc1_dat0_py7",
27 "sdmmc1_dat1_py6",
28 "sdmmc1_dat2_py5",
29 "sdmmc1_dat3_py4";
30 nvidia,function = "sdmmc1";
31 nvidia,pull = <2>;
32 nvidia,tristate = <0>;
33 };
34 sdmmc4_clk_pcc4 {
35 nvidia,pins = "sdmmc4_clk_pcc4",
36 "sdmmc4_rst_n_pcc3";
37 nvidia,function = "sdmmc4";
38 nvidia,pull = <0>;
39 nvidia,tristate = <0>;
40 };
41 sdmmc4_dat0_paa0 {
42 nvidia,pins = "sdmmc4_dat0_paa0",
43 "sdmmc4_dat1_paa1",
44 "sdmmc4_dat2_paa2",
45 "sdmmc4_dat3_paa3",
46 "sdmmc4_dat4_paa4",
47 "sdmmc4_dat5_paa5",
48 "sdmmc4_dat6_paa6",
49 "sdmmc4_dat7_paa7";
50 nvidia,function = "sdmmc4";
51 nvidia,pull = <2>;
52 nvidia,tristate = <0>;
53 };
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]54 dap2_fs_pa2 {
55 nvidia,pins = "dap2_fs_pa2",
56 "dap2_sclk_pa3",
57 "dap2_din_pa4",
58 "dap2_dout_pa5";
59 nvidia,function = "i2s1";
60 nvidia,pull = <0>;
61 nvidia,tristate = <0>;
62 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]63 };
64 };
65
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]66 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame^]67 status = "okay";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]68 clock-frequency = <408000000>;
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]69 };
70
71 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame^]72 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]73 clock-frequency = <100000>;
74 };
75
76 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame^]77 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]78 clock-frequency = <100000>;
79 };
80
81 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame^]82 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]83 clock-frequency = <100000>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530[diff] [blame]84
85 /* ALS and Proximity sensor */
86 isl29028@44 {
87 compatible = "isil,isl29028";
88 reg = <0x44>;
89 interrupt-parent = <&gpio>;
90 interrupts = <88 0x04>; /*gpio PL0 */
91 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]92 };
93
94 i2c@7000c700 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame^]95 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]96 clock-frequency = <100000>;
97 };
98
99 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame^]100 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]101 clock-frequency = <100000>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]102
103 wm8903: wm8903@1a {
104 compatible = "wlf,wm8903";
105 reg = <0x1a>;
106 interrupt-parent = <&gpio>;
107 interrupts = <179 0x04>; /* gpio PW3 */
108
109 gpio-controller;
110 #gpio-cells = <2>;
111
112 micdet-cfg = <0>;
113 micdet-delay = <100>;
114 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
115 };
Laxman Dewangan331da582012-05-10 20:38:45 +0000[diff] [blame]116
117 tps62361 {
118 compatible = "ti,tps62361";
119 reg = <0x60>;
120
121 regulator-name = "tps62361-vout";
122 regulator-min-microvolt = <500000>;
123 regulator-max-microvolt = <1500000>;
124 regulator-boot-on;
125 regulator-always-on;
126 ti,vsel0-state-high;
127 ti,vsel1-state-high;
128 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]129 };
Stephen Warren850c4c82012-02-01 16:29:57 -0700[diff] [blame]130
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]131 ahub {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame^]132 i2s@70080400 {
133 status = "okay";
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]134 };
135 };
136
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]137 sdhci@78000000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame^]138 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]139 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
140 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
141 power-gpios = <&gpio 31 0>; /* gpio PD7 */
142 };
143
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]144 sdhci@78000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame^]145 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]146 support-8bit;
147 };
148
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]149 sound {
150 compatible = "nvidia,tegra-audio-wm8903-cardhu",
151 "nvidia,tegra-audio-wm8903";
152 nvidia,model = "NVIDIA Tegra Cardhu";
153
154 nvidia,audio-routing =
155 "Headphone Jack", "HPOUTR",
156 "Headphone Jack", "HPOUTL",
157 "Int Spk", "ROP",
158 "Int Spk", "RON",
159 "Int Spk", "LOP",
160 "Int Spk", "LON",
161 "Mic Jack", "MICBIAS",
162 "IN1L", "Mic Jack";
163
164 nvidia,i2s-controller = <&tegra_i2s1>;
165 nvidia,audio-codec = <&wm8903>;
166
167 nvidia,spkr-en-gpios = <&wm8903 2 0>;
168 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
169 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]170};