Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2018 The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #define pr_fmt(fmt) "QG-K: %s: " fmt, __func__ |
| 14 | |
| 15 | #include <linux/alarmtimer.h> |
| 16 | #include <linux/cdev.h> |
| 17 | #include <linux/device.h> |
| 18 | #include <linux/interrupt.h> |
| 19 | #include <linux/ktime.h> |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/of.h> |
| 22 | #include <linux/of_irq.h> |
| 23 | #include <linux/of_batterydata.h> |
| 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/power_supply.h> |
| 26 | #include <linux/regmap.h> |
| 27 | #include <linux/uaccess.h> |
| 28 | #include <linux/pmic-voter.h> |
| 29 | #include <linux/qpnp/qpnp-adc.h> |
| 30 | #include <uapi/linux/qg.h> |
| 31 | #include "qg-sdam.h" |
| 32 | #include "qg-core.h" |
| 33 | #include "qg-reg.h" |
| 34 | #include "qg-util.h" |
| 35 | #include "qg-soc.h" |
| 36 | #include "qg-battery-profile.h" |
| 37 | #include "qg-defs.h" |
| 38 | |
| 39 | static int qg_debug_mask; |
| 40 | module_param_named( |
| 41 | debug_mask, qg_debug_mask, int, 0600 |
| 42 | ); |
| 43 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 44 | static bool is_battery_present(struct qpnp_qg *chip) |
| 45 | { |
| 46 | u8 reg = 0; |
| 47 | int rc; |
| 48 | |
| 49 | rc = qg_read(chip, chip->qg_base + QG_STATUS1_REG, ®, 1); |
| 50 | if (rc < 0) |
| 51 | pr_err("Failed to read battery presence, rc=%d\n", rc); |
| 52 | |
| 53 | return !!(reg & BATTERY_PRESENT_BIT); |
| 54 | } |
| 55 | |
| 56 | #define DEBUG_BATT_ID_LOW 6000 |
| 57 | #define DEBUG_BATT_ID_HIGH 8500 |
| 58 | static bool is_debug_batt_id(struct qpnp_qg *chip) |
| 59 | { |
| 60 | if (is_between(DEBUG_BATT_ID_LOW, DEBUG_BATT_ID_HIGH, |
| 61 | chip->batt_id_ohm)) |
| 62 | return true; |
| 63 | |
| 64 | return false; |
| 65 | } |
| 66 | |
| 67 | static int qg_read_ocv(struct qpnp_qg *chip, u32 *ocv_uv, u8 type) |
| 68 | { |
| 69 | int rc, addr; |
| 70 | u64 temp = 0; |
| 71 | |
| 72 | switch (type) { |
| 73 | case GOOD_OCV: |
| 74 | addr = QG_S3_GOOD_OCV_V_DATA0_REG; |
| 75 | break; |
| 76 | case PON_OCV: |
| 77 | addr = QG_S7_PON_OCV_V_DATA0_REG; |
| 78 | break; |
| 79 | default: |
| 80 | pr_err("Invalid OCV type %d\n", type); |
| 81 | return -EINVAL; |
| 82 | } |
| 83 | |
| 84 | rc = qg_read(chip, chip->qg_base + addr, (u8 *)&temp, 2); |
| 85 | if (rc < 0) { |
| 86 | pr_err("Failed to read ocv, rc=%d\n", rc); |
| 87 | return rc; |
| 88 | } |
| 89 | |
| 90 | *ocv_uv = V_RAW_TO_UV(temp); |
| 91 | |
| 92 | pr_debug("%s: OCV=%duV\n", |
| 93 | type == GOOD_OCV ? "GOOD_OCV" : "PON_OCV", *ocv_uv); |
| 94 | |
| 95 | return rc; |
| 96 | } |
| 97 | |
| 98 | static int qg_update_fifo_length(struct qpnp_qg *chip, u8 length) |
| 99 | { |
| 100 | int rc; |
| 101 | |
| 102 | if (!length || length > 8) { |
| 103 | pr_err("Invalid FIFO length %d\n", length); |
| 104 | return -EINVAL; |
| 105 | } |
| 106 | |
| 107 | rc = qg_masked_write(chip, chip->qg_base + QG_S2_NORMAL_MEAS_CTL2_REG, |
| 108 | FIFO_LENGTH_MASK, (length - 1) << FIFO_LENGTH_SHIFT); |
| 109 | if (rc < 0) |
| 110 | pr_err("Failed to write S2 FIFO length, rc=%d\n", rc); |
| 111 | |
| 112 | return rc; |
| 113 | } |
| 114 | |
| 115 | static int qg_master_hold(struct qpnp_qg *chip, bool hold) |
| 116 | { |
| 117 | int rc; |
| 118 | |
| 119 | /* clear the master */ |
| 120 | rc = qg_masked_write(chip, chip->qg_base + QG_DATA_CTL1_REG, |
| 121 | MASTER_HOLD_OR_CLR_BIT, 0); |
| 122 | if (rc < 0) |
| 123 | return rc; |
| 124 | |
| 125 | if (hold) { |
| 126 | /* 0 -> 1, hold the master */ |
| 127 | rc = qg_masked_write(chip, chip->qg_base + QG_DATA_CTL1_REG, |
| 128 | MASTER_HOLD_OR_CLR_BIT, |
| 129 | MASTER_HOLD_OR_CLR_BIT); |
| 130 | if (rc < 0) |
| 131 | return rc; |
| 132 | } |
| 133 | |
| 134 | qg_dbg(chip, QG_DEBUG_STATUS, "Master hold = %d\n", hold); |
| 135 | |
| 136 | return rc; |
| 137 | } |
| 138 | |
| 139 | static void qg_notify_charger(struct qpnp_qg *chip) |
| 140 | { |
| 141 | union power_supply_propval prop = {0, }; |
| 142 | int rc; |
| 143 | |
| 144 | if (!chip->batt_psy) |
| 145 | return; |
| 146 | |
| 147 | if (is_debug_batt_id(chip)) { |
| 148 | prop.intval = 1; |
| 149 | power_supply_set_property(chip->batt_psy, |
| 150 | POWER_SUPPLY_PROP_DEBUG_BATTERY, &prop); |
| 151 | return; |
| 152 | } |
| 153 | |
| 154 | if (!chip->profile_loaded) |
| 155 | return; |
| 156 | |
| 157 | prop.intval = chip->bp.float_volt_uv; |
| 158 | rc = power_supply_set_property(chip->batt_psy, |
| 159 | POWER_SUPPLY_PROP_VOLTAGE_MAX, &prop); |
| 160 | if (rc < 0) { |
| 161 | pr_err("Failed to set voltage_max property on batt_psy, rc=%d\n", |
| 162 | rc); |
| 163 | return; |
| 164 | } |
| 165 | |
| 166 | prop.intval = chip->bp.fastchg_curr_ma * 1000; |
| 167 | rc = power_supply_set_property(chip->batt_psy, |
| 168 | POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX, &prop); |
| 169 | if (rc < 0) { |
| 170 | pr_err("Failed to set constant_charge_current_max property on batt_psy, rc=%d\n", |
| 171 | rc); |
| 172 | return; |
| 173 | } |
| 174 | |
| 175 | pr_debug("Notified charger on float voltage and FCC\n"); |
| 176 | } |
| 177 | |
| 178 | static bool is_batt_available(struct qpnp_qg *chip) |
| 179 | { |
| 180 | if (chip->batt_psy) |
| 181 | return true; |
| 182 | |
| 183 | chip->batt_psy = power_supply_get_by_name("battery"); |
| 184 | if (!chip->batt_psy) |
| 185 | return false; |
| 186 | |
| 187 | /* batt_psy is initialized, set the fcc and fv */ |
| 188 | qg_notify_charger(chip); |
| 189 | |
| 190 | return true; |
| 191 | } |
| 192 | |
| 193 | static int qg_update_sdam_params(struct qpnp_qg *chip) |
| 194 | { |
| 195 | int rc, batt_temp = 0, i; |
| 196 | unsigned long rtc_sec = 0; |
| 197 | |
| 198 | rc = get_rtc_time(&rtc_sec); |
| 199 | if (rc < 0) |
| 200 | pr_err("Failed to get RTC time, rc=%d\n", rc); |
| 201 | else |
| 202 | chip->sdam_data[SDAM_TIME_SEC] = rtc_sec; |
| 203 | |
| 204 | rc = qg_get_battery_temp(chip, &batt_temp); |
| 205 | if (rc < 0) |
| 206 | pr_err("Failed to get battery-temp, rc = %d\n", rc); |
| 207 | else |
| 208 | chip->sdam_data[SDAM_TEMP] = (u32)batt_temp; |
| 209 | |
| 210 | rc = qg_sdam_write_all(chip->sdam_data); |
| 211 | if (rc < 0) |
| 212 | pr_err("Failed to write to SDAM rc=%d\n", rc); |
| 213 | |
| 214 | for (i = 0; i < SDAM_MAX; i++) |
| 215 | qg_dbg(chip, QG_DEBUG_STATUS, "SDAM write param %d value=%d\n", |
| 216 | i, chip->sdam_data[i]); |
| 217 | |
| 218 | return rc; |
| 219 | } |
| 220 | |
| 221 | static int qg_process_fifo(struct qpnp_qg *chip, u32 fifo_length) |
| 222 | { |
| 223 | int rc = 0, i, j = 0, temp; |
| 224 | u8 v_fifo[MAX_FIFO_LENGTH * 2], i_fifo[MAX_FIFO_LENGTH * 2]; |
| 225 | u32 sample_interval = 0, sample_count = 0, fifo_v = 0, fifo_i = 0; |
| 226 | |
Anirudh Ghayal | 07fbf79 | 2018-02-26 11:38:33 +0530 | [diff] [blame] | 227 | chip->kdata.fifo_time = (u32)ktime_get_seconds(); |
| 228 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 229 | if (!fifo_length) { |
| 230 | pr_debug("No FIFO data\n"); |
| 231 | return 0; |
| 232 | } |
| 233 | |
| 234 | qg_dbg(chip, QG_DEBUG_FIFO, "FIFO length=%d\n", fifo_length); |
| 235 | |
| 236 | rc = get_sample_interval(chip, &sample_interval); |
| 237 | if (rc < 0) { |
| 238 | pr_err("Failed to get FIFO sample interval, rc=%d\n", rc); |
| 239 | return rc; |
| 240 | } |
| 241 | |
| 242 | rc = get_sample_count(chip, &sample_count); |
| 243 | if (rc < 0) { |
| 244 | pr_err("Failed to get FIFO sample count, rc=%d\n", rc); |
| 245 | return rc; |
| 246 | } |
| 247 | |
Anirudh Ghayal | c609639 | 2018-03-07 19:57:05 +0530 | [diff] [blame] | 248 | /* |
| 249 | * If there is pending data from suspend, append the new FIFO |
| 250 | * data to it. |
| 251 | */ |
| 252 | if (chip->suspend_data) { |
| 253 | j = chip->kdata.fifo_length; /* append the data */ |
| 254 | chip->suspend_data = false; |
| 255 | qg_dbg(chip, QG_DEBUG_FIFO, |
| 256 | "Pending suspend-data FIFO length=%d\n", j); |
| 257 | } else { |
| 258 | /* clear any old pending data */ |
| 259 | chip->kdata.fifo_length = 0; |
| 260 | } |
| 261 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 262 | for (i = 0; i < fifo_length * 2; i = i + 2, j++) { |
| 263 | rc = qg_read(chip, chip->qg_base + QG_V_FIFO0_DATA0_REG + i, |
| 264 | &v_fifo[i], 2); |
| 265 | if (rc < 0) { |
| 266 | pr_err("Failed to read QG_V_FIFO, rc=%d\n", rc); |
| 267 | return rc; |
| 268 | } |
| 269 | rc = qg_read(chip, chip->qg_base + QG_I_FIFO0_DATA0_REG + i, |
| 270 | &i_fifo[i], 2); |
| 271 | if (rc < 0) { |
| 272 | pr_err("Failed to read QG_I_FIFO, rc=%d\n", rc); |
| 273 | return rc; |
| 274 | } |
| 275 | |
| 276 | fifo_v = v_fifo[i] | (v_fifo[i + 1] << 8); |
| 277 | fifo_i = i_fifo[i] | (i_fifo[i + 1] << 8); |
| 278 | |
| 279 | temp = sign_extend32(fifo_i, 15); |
| 280 | |
| 281 | chip->kdata.fifo[j].v = V_RAW_TO_UV(fifo_v); |
| 282 | chip->kdata.fifo[j].i = I_RAW_TO_UA(temp); |
| 283 | chip->kdata.fifo[j].interval = sample_interval; |
| 284 | chip->kdata.fifo[j].count = sample_count; |
| 285 | |
| 286 | qg_dbg(chip, QG_DEBUG_FIFO, "FIFO %d raw_v=%d uV=%d raw_i=%d uA=%d interval=%d count=%d\n", |
| 287 | j, fifo_v, |
| 288 | chip->kdata.fifo[j].v, |
| 289 | fifo_i, |
| 290 | (int)chip->kdata.fifo[j].i, |
| 291 | chip->kdata.fifo[j].interval, |
| 292 | chip->kdata.fifo[j].count); |
| 293 | } |
| 294 | |
Anirudh Ghayal | c609639 | 2018-03-07 19:57:05 +0530 | [diff] [blame] | 295 | chip->kdata.fifo_length += fifo_length; |
Anirudh Ghayal | 07fbf79 | 2018-02-26 11:38:33 +0530 | [diff] [blame] | 296 | chip->kdata.seq_no = chip->seq_no++ % U32_MAX; |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 297 | |
| 298 | return rc; |
| 299 | } |
| 300 | |
| 301 | static int qg_process_accumulator(struct qpnp_qg *chip) |
| 302 | { |
| 303 | int rc, sample_interval = 0; |
| 304 | u8 count, index = chip->kdata.fifo_length; |
| 305 | u64 acc_v = 0, acc_i = 0; |
| 306 | s64 temp = 0; |
| 307 | |
| 308 | rc = qg_read(chip, chip->qg_base + QG_ACCUM_CNT_RT_REG, |
| 309 | &count, 1); |
| 310 | if (rc < 0) { |
| 311 | pr_err("Failed to read ACC count, rc=%d\n", rc); |
| 312 | return rc; |
| 313 | } |
| 314 | |
| 315 | if (!count) { |
| 316 | pr_debug("No ACCUMULATOR data!\n"); |
| 317 | return 0; |
| 318 | } |
| 319 | |
| 320 | rc = get_sample_interval(chip, &sample_interval); |
| 321 | if (rc < 0) { |
| 322 | pr_err("Failed to get ACC sample interval, rc=%d\n", rc); |
| 323 | return 0; |
| 324 | } |
| 325 | |
| 326 | rc = qg_read(chip, chip->qg_base + QG_V_ACCUM_DATA0_RT_REG, |
| 327 | (u8 *)&acc_v, 3); |
| 328 | if (rc < 0) { |
| 329 | pr_err("Failed to read ACC RT V data, rc=%d\n", rc); |
| 330 | return rc; |
| 331 | } |
| 332 | |
| 333 | rc = qg_read(chip, chip->qg_base + QG_I_ACCUM_DATA0_RT_REG, |
| 334 | (u8 *)&acc_i, 3); |
| 335 | if (rc < 0) { |
| 336 | pr_err("Failed to read ACC RT I data, rc=%d\n", rc); |
| 337 | return rc; |
| 338 | } |
| 339 | |
| 340 | temp = sign_extend64(acc_i, 23); |
| 341 | |
| 342 | chip->kdata.fifo[index].v = V_RAW_TO_UV(div_u64(acc_v, count)); |
| 343 | chip->kdata.fifo[index].i = I_RAW_TO_UA(div_s64(temp, count)); |
| 344 | chip->kdata.fifo[index].interval = sample_interval; |
| 345 | chip->kdata.fifo[index].count = count; |
| 346 | chip->kdata.fifo_length++; |
| 347 | |
Anirudh Ghayal | 07fbf79 | 2018-02-26 11:38:33 +0530 | [diff] [blame] | 348 | if (chip->kdata.fifo_length == 1) /* Only accumulator data */ |
| 349 | chip->kdata.seq_no = chip->seq_no++ % U32_MAX; |
| 350 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 351 | qg_dbg(chip, QG_DEBUG_FIFO, "ACC v_avg=%duV i_avg=%duA interval=%d count=%d\n", |
| 352 | chip->kdata.fifo[index].v, |
| 353 | (int)chip->kdata.fifo[index].i, |
| 354 | chip->kdata.fifo[index].interval, |
| 355 | chip->kdata.fifo[index].count); |
| 356 | |
| 357 | return rc; |
| 358 | } |
| 359 | |
| 360 | static int qg_process_rt_fifo(struct qpnp_qg *chip) |
| 361 | { |
| 362 | int rc; |
| 363 | u32 fifo_length = 0; |
| 364 | |
| 365 | /* Get the real-time FIFO length */ |
| 366 | rc = get_fifo_length(chip, &fifo_length, true); |
| 367 | if (rc < 0) { |
| 368 | pr_err("Failed to read RT FIFO length, rc=%d\n", rc); |
| 369 | return rc; |
| 370 | } |
| 371 | |
| 372 | rc = qg_process_fifo(chip, fifo_length); |
| 373 | if (rc < 0) { |
| 374 | pr_err("Failed to process FIFO data, rc=%d\n", rc); |
| 375 | return rc; |
| 376 | } |
| 377 | |
| 378 | rc = qg_process_accumulator(chip); |
| 379 | if (rc < 0) { |
| 380 | pr_err("Failed to process ACC data, rc=%d\n", rc); |
| 381 | return rc; |
| 382 | } |
| 383 | |
| 384 | return rc; |
| 385 | } |
| 386 | |
| 387 | #define VBAT_LOW_HYST_UV 50000 /* 50mV */ |
| 388 | static int qg_vbat_low_wa(struct qpnp_qg *chip) |
| 389 | { |
| 390 | int rc, i; |
| 391 | u32 vbat_low_uv = chip->dt.vbatt_low_mv * 1000 + VBAT_LOW_HYST_UV; |
| 392 | |
| 393 | if (!(chip->wa_flags & QG_VBAT_LOW_WA) || !chip->vbat_low) |
| 394 | return 0; |
| 395 | |
| 396 | /* |
| 397 | * PMI632 1.0 does not generate a falling VBAT_LOW IRQ. |
| 398 | * To exit from VBAT_LOW config, check if any of the FIFO |
| 399 | * averages is > vbat_low threshold and reconfigure the |
| 400 | * FIFO length to normal. |
| 401 | */ |
| 402 | for (i = 0; i < chip->kdata.fifo_length; i++) { |
| 403 | if (chip->kdata.fifo[i].v > vbat_low_uv) { |
| 404 | rc = qg_master_hold(chip, true); |
| 405 | if (rc < 0) { |
| 406 | pr_err("Failed to hold master, rc=%d\n", rc); |
| 407 | goto done; |
| 408 | } |
| 409 | rc = qg_update_fifo_length(chip, |
| 410 | chip->dt.s2_fifo_length); |
| 411 | if (rc < 0) |
| 412 | goto done; |
| 413 | |
| 414 | rc = qg_master_hold(chip, false); |
| 415 | if (rc < 0) { |
| 416 | pr_err("Failed to release master, rc=%d\n", rc); |
| 417 | goto done; |
| 418 | } |
| 419 | /* FIFOs restarted */ |
| 420 | chip->last_fifo_update_time = ktime_get(); |
| 421 | |
| 422 | chip->vbat_low = false; |
| 423 | pr_info("Exit VBAT_LOW vbat_avg=%duV vbat_low=%duV updated fifo_length=%d\n", |
| 424 | chip->kdata.fifo[i].v, vbat_low_uv, |
| 425 | chip->dt.s2_fifo_length); |
| 426 | break; |
| 427 | } |
| 428 | } |
| 429 | |
| 430 | return 0; |
| 431 | |
| 432 | done: |
| 433 | qg_master_hold(chip, false); |
| 434 | return rc; |
| 435 | } |
| 436 | |
| 437 | #define MIN_FIFO_FULL_TIME_MS 12000 |
| 438 | static int process_rt_fifo_data(struct qpnp_qg *chip, |
| 439 | bool vbat_low, bool update_smb) |
| 440 | { |
| 441 | int rc = 0; |
| 442 | ktime_t now = ktime_get(); |
| 443 | s64 time_delta; |
| 444 | |
| 445 | /* |
| 446 | * Reject the FIFO read event if there are back-to-back requests |
| 447 | * This is done to gaurantee that there is always a minimum FIFO |
| 448 | * data to be processed, ignore this if vbat_low is set. |
| 449 | */ |
| 450 | time_delta = ktime_ms_delta(now, chip->last_user_update_time); |
| 451 | |
| 452 | qg_dbg(chip, QG_DEBUG_FIFO, "time_delta=%lld ms vbat_low=%d\n", |
| 453 | time_delta, vbat_low); |
| 454 | |
| 455 | if (time_delta > MIN_FIFO_FULL_TIME_MS || vbat_low || update_smb) { |
| 456 | rc = qg_master_hold(chip, true); |
| 457 | if (rc < 0) { |
| 458 | pr_err("Failed to hold master, rc=%d\n", rc); |
| 459 | goto done; |
| 460 | } |
| 461 | |
| 462 | rc = qg_process_rt_fifo(chip); |
| 463 | if (rc < 0) { |
| 464 | pr_err("Failed to process FIFO real-time, rc=%d\n", rc); |
| 465 | goto done; |
| 466 | } |
| 467 | |
| 468 | if (vbat_low) { |
| 469 | /* change FIFO length */ |
| 470 | rc = qg_update_fifo_length(chip, |
| 471 | chip->dt.s2_vbat_low_fifo_length); |
| 472 | if (rc < 0) |
| 473 | goto done; |
| 474 | |
| 475 | qg_dbg(chip, QG_DEBUG_STATUS, |
| 476 | "FIFO length updated to %d vbat_low=%d\n", |
| 477 | chip->dt.s2_vbat_low_fifo_length, |
| 478 | vbat_low); |
| 479 | } |
| 480 | |
| 481 | if (update_smb) { |
| 482 | rc = qg_masked_write(chip, chip->qg_base + |
| 483 | QG_MODE_CTL1_REG, PARALLEL_IBAT_SENSE_EN_BIT, |
| 484 | chip->parallel_enabled ? |
| 485 | PARALLEL_IBAT_SENSE_EN_BIT : 0); |
| 486 | if (rc < 0) { |
| 487 | pr_err("Failed to update SMB_EN, rc=%d\n", rc); |
| 488 | goto done; |
| 489 | } |
| 490 | qg_dbg(chip, QG_DEBUG_STATUS, "Parallel SENSE %d\n", |
| 491 | chip->parallel_enabled); |
| 492 | } |
| 493 | |
| 494 | rc = qg_master_hold(chip, false); |
| 495 | if (rc < 0) { |
| 496 | pr_err("Failed to release master, rc=%d\n", rc); |
| 497 | goto done; |
| 498 | } |
| 499 | /* FIFOs restarted */ |
| 500 | chip->last_fifo_update_time = ktime_get(); |
| 501 | |
| 502 | /* signal the read thread */ |
| 503 | chip->data_ready = true; |
| 504 | wake_up_interruptible(&chip->qg_wait_q); |
| 505 | chip->last_user_update_time = now; |
| 506 | |
| 507 | /* vote to stay awake until userspace reads data */ |
| 508 | vote(chip->awake_votable, FIFO_RT_DONE_VOTER, true, 0); |
| 509 | } else { |
| 510 | qg_dbg(chip, QG_DEBUG_FIFO, "FIFO processing too early time_delta=%lld\n", |
| 511 | time_delta); |
| 512 | } |
| 513 | done: |
| 514 | qg_master_hold(chip, false); |
| 515 | return rc; |
| 516 | } |
| 517 | |
| 518 | static void process_udata_work(struct work_struct *work) |
| 519 | { |
| 520 | struct qpnp_qg *chip = container_of(work, |
| 521 | struct qpnp_qg, udata_work); |
| 522 | int rc; |
| 523 | |
| 524 | if (chip->udata.param[QG_SOC].valid) { |
| 525 | qg_dbg(chip, QG_DEBUG_SOC, "udata SOC=%d last SOC=%d\n", |
| 526 | chip->udata.param[QG_SOC].data, chip->catch_up_soc); |
| 527 | |
Anirudh Ghayal | 07fbf79 | 2018-02-26 11:38:33 +0530 | [diff] [blame] | 528 | chip->catch_up_soc = chip->udata.param[QG_SOC].data; |
| 529 | qg_scale_soc(chip, false); |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 530 | |
| 531 | /* update parameters to SDAM */ |
Vamshi Krishna B V | 2585580 | 2018-02-21 15:26:30 +0530 | [diff] [blame] | 532 | chip->sdam_data[SDAM_SOC] = chip->msoc; |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 533 | chip->sdam_data[SDAM_OCV_UV] = |
| 534 | chip->udata.param[QG_OCV_UV].data; |
| 535 | chip->sdam_data[SDAM_RBAT_MOHM] = |
| 536 | chip->udata.param[QG_RBAT_MOHM].data; |
| 537 | chip->sdam_data[SDAM_VALID] = 1; |
| 538 | |
| 539 | rc = qg_update_sdam_params(chip); |
| 540 | if (rc < 0) |
| 541 | pr_err("Failed to update SDAM params, rc=%d\n", rc); |
| 542 | } |
| 543 | |
Anirudh Ghayal | 07fbf79 | 2018-02-26 11:38:33 +0530 | [diff] [blame] | 544 | if (chip->udata.param[QG_CHARGE_COUNTER].valid) |
| 545 | chip->charge_counter_uah = |
| 546 | chip->udata.param[QG_CHARGE_COUNTER].data; |
| 547 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 548 | vote(chip->awake_votable, UDATA_READY_VOTER, false, 0); |
| 549 | } |
| 550 | |
| 551 | static irqreturn_t qg_default_irq_handler(int irq, void *data) |
| 552 | { |
| 553 | struct qpnp_qg *chip = data; |
| 554 | |
| 555 | qg_dbg(chip, QG_DEBUG_IRQ, "IRQ triggered\n"); |
| 556 | |
| 557 | return IRQ_HANDLED; |
| 558 | } |
| 559 | |
| 560 | #define MAX_FIFO_DELTA_PERCENT 10 |
| 561 | static irqreturn_t qg_fifo_update_done_handler(int irq, void *data) |
| 562 | { |
| 563 | ktime_t now = ktime_get(); |
| 564 | int rc, hw_delta_ms = 0, margin_ms = 0; |
| 565 | u32 fifo_length = 0; |
| 566 | s64 time_delta_ms = 0; |
| 567 | struct qpnp_qg *chip = data; |
| 568 | |
| 569 | time_delta_ms = ktime_ms_delta(now, chip->last_fifo_update_time); |
| 570 | chip->last_fifo_update_time = now; |
| 571 | |
| 572 | qg_dbg(chip, QG_DEBUG_IRQ, "IRQ triggered\n"); |
| 573 | mutex_lock(&chip->data_lock); |
| 574 | |
| 575 | rc = get_fifo_length(chip, &fifo_length, false); |
| 576 | if (rc < 0) { |
| 577 | pr_err("Failed to get FIFO length, rc=%d\n", rc); |
| 578 | goto done; |
| 579 | } |
| 580 | |
| 581 | rc = qg_process_fifo(chip, fifo_length); |
| 582 | if (rc < 0) { |
| 583 | pr_err("Failed to process QG FIFO, rc=%d\n", rc); |
| 584 | goto done; |
| 585 | } |
| 586 | |
| 587 | rc = qg_vbat_low_wa(chip); |
| 588 | if (rc < 0) { |
| 589 | pr_err("Failed to apply VBAT LOW WA, rc=%d\n", rc); |
| 590 | goto done; |
| 591 | } |
| 592 | |
| 593 | rc = get_fifo_done_time(chip, false, &hw_delta_ms); |
| 594 | if (rc < 0) |
| 595 | hw_delta_ms = 0; |
| 596 | else |
| 597 | margin_ms = (hw_delta_ms * MAX_FIFO_DELTA_PERCENT) / 100; |
| 598 | |
| 599 | if (abs(hw_delta_ms - time_delta_ms) < margin_ms) { |
| 600 | chip->kdata.param[QG_FIFO_TIME_DELTA].data = time_delta_ms; |
| 601 | chip->kdata.param[QG_FIFO_TIME_DELTA].valid = true; |
| 602 | qg_dbg(chip, QG_DEBUG_FIFO, "FIFO_done time_delta_ms=%lld\n", |
| 603 | time_delta_ms); |
| 604 | } |
| 605 | |
| 606 | /* signal the read thread */ |
| 607 | chip->data_ready = true; |
| 608 | wake_up_interruptible(&chip->qg_wait_q); |
| 609 | |
| 610 | /* vote to stay awake until userspace reads data */ |
| 611 | vote(chip->awake_votable, FIFO_DONE_VOTER, true, 0); |
| 612 | |
| 613 | done: |
| 614 | mutex_unlock(&chip->data_lock); |
| 615 | return IRQ_HANDLED; |
| 616 | } |
| 617 | |
| 618 | static irqreturn_t qg_vbat_low_handler(int irq, void *data) |
| 619 | { |
| 620 | int rc; |
| 621 | struct qpnp_qg *chip = data; |
| 622 | u8 status = 0; |
| 623 | |
| 624 | qg_dbg(chip, QG_DEBUG_IRQ, "IRQ triggered\n"); |
| 625 | mutex_lock(&chip->data_lock); |
| 626 | |
| 627 | rc = qg_read(chip, chip->qg_base + QG_INT_RT_STS_REG, &status, 1); |
| 628 | if (rc < 0) { |
| 629 | pr_err("Failed to read RT status, rc=%d\n", rc); |
| 630 | goto done; |
| 631 | } |
| 632 | chip->vbat_low = !!(status & VBAT_LOW_INT_RT_STS_BIT); |
| 633 | |
| 634 | rc = process_rt_fifo_data(chip, chip->vbat_low, false); |
| 635 | if (rc < 0) |
| 636 | pr_err("Failed to process RT FIFO data, rc=%d\n", rc); |
| 637 | |
| 638 | qg_dbg(chip, QG_DEBUG_IRQ, "VBAT_LOW = %d\n", chip->vbat_low); |
| 639 | done: |
| 640 | mutex_unlock(&chip->data_lock); |
| 641 | return IRQ_HANDLED; |
| 642 | } |
| 643 | |
| 644 | static irqreturn_t qg_vbat_empty_handler(int irq, void *data) |
| 645 | { |
| 646 | struct qpnp_qg *chip = data; |
| 647 | u32 ocv_uv = 0; |
| 648 | |
| 649 | qg_dbg(chip, QG_DEBUG_IRQ, "IRQ triggered\n"); |
| 650 | pr_warn("VBATT EMPTY SOC = 0\n"); |
| 651 | |
| 652 | chip->catch_up_soc = 0; |
| 653 | qg_scale_soc(chip, true); |
| 654 | |
| 655 | qg_sdam_read(SDAM_OCV_UV, &ocv_uv); |
| 656 | chip->sdam_data[SDAM_SOC] = 0; |
| 657 | chip->sdam_data[SDAM_OCV_UV] = ocv_uv; |
| 658 | chip->sdam_data[SDAM_VALID] = 1; |
| 659 | |
| 660 | qg_update_sdam_params(chip); |
| 661 | |
| 662 | if (chip->qg_psy) |
| 663 | power_supply_changed(chip->qg_psy); |
| 664 | |
| 665 | return IRQ_HANDLED; |
| 666 | } |
| 667 | |
| 668 | static irqreturn_t qg_good_ocv_handler(int irq, void *data) |
| 669 | { |
| 670 | int rc; |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 671 | u8 status = 0; |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 672 | u32 ocv_uv; |
| 673 | struct qpnp_qg *chip = data; |
| 674 | |
| 675 | qg_dbg(chip, QG_DEBUG_IRQ, "IRQ triggered\n"); |
| 676 | |
| 677 | mutex_lock(&chip->data_lock); |
| 678 | |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 679 | rc = qg_read(chip, chip->qg_base + QG_STATUS2_REG, &status, 1); |
| 680 | if (rc < 0) { |
| 681 | pr_err("Failed to read status2 register rc=%d\n", rc); |
| 682 | goto done; |
| 683 | } |
| 684 | |
| 685 | if (!(status & GOOD_OCV_BIT)) |
| 686 | goto done; |
| 687 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 688 | rc = qg_read_ocv(chip, &ocv_uv, GOOD_OCV); |
| 689 | if (rc < 0) { |
| 690 | pr_err("Failed to read good_ocv, rc=%d\n", rc); |
| 691 | goto done; |
| 692 | } |
| 693 | |
| 694 | chip->kdata.param[QG_GOOD_OCV_UV].data = ocv_uv; |
| 695 | chip->kdata.param[QG_GOOD_OCV_UV].valid = true; |
| 696 | |
| 697 | vote(chip->awake_votable, GOOD_OCV_VOTER, true, 0); |
| 698 | |
| 699 | /* signal the readd thread */ |
| 700 | chip->data_ready = true; |
| 701 | wake_up_interruptible(&chip->qg_wait_q); |
| 702 | done: |
| 703 | mutex_unlock(&chip->data_lock); |
| 704 | return IRQ_HANDLED; |
| 705 | } |
| 706 | |
| 707 | static struct qg_irq_info qg_irqs[] = { |
| 708 | [QG_BATT_MISSING_IRQ] = { |
| 709 | .name = "qg-batt-missing", |
| 710 | .handler = qg_default_irq_handler, |
| 711 | }, |
| 712 | [QG_VBATT_LOW_IRQ] = { |
| 713 | .name = "qg-vbat-low", |
| 714 | .handler = qg_vbat_low_handler, |
| 715 | .wake = true, |
| 716 | }, |
| 717 | [QG_VBATT_EMPTY_IRQ] = { |
| 718 | .name = "qg-vbat-empty", |
| 719 | .handler = qg_vbat_empty_handler, |
| 720 | .wake = true, |
| 721 | }, |
| 722 | [QG_FIFO_UPDATE_DONE_IRQ] = { |
| 723 | .name = "qg-fifo-done", |
| 724 | .handler = qg_fifo_update_done_handler, |
| 725 | .wake = true, |
| 726 | }, |
| 727 | [QG_GOOD_OCV_IRQ] = { |
| 728 | .name = "qg-good-ocv", |
| 729 | .handler = qg_good_ocv_handler, |
| 730 | .wake = true, |
| 731 | }, |
| 732 | [QG_FSM_STAT_CHG_IRQ] = { |
| 733 | .name = "qg-fsm-state-chg", |
| 734 | .handler = qg_default_irq_handler, |
| 735 | }, |
| 736 | [QG_EVENT_IRQ] = { |
| 737 | .name = "qg-event", |
| 738 | .handler = qg_default_irq_handler, |
| 739 | }, |
| 740 | }; |
| 741 | |
| 742 | static int qg_awake_cb(struct votable *votable, void *data, int awake, |
| 743 | const char *client) |
| 744 | { |
| 745 | struct qpnp_qg *chip = data; |
| 746 | |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 747 | /* ignore if the QG device is not open */ |
| 748 | if (!chip->qg_device_open) |
| 749 | return 0; |
| 750 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 751 | if (awake) |
| 752 | pm_stay_awake(chip->dev); |
| 753 | else |
| 754 | pm_relax(chip->dev); |
| 755 | |
| 756 | pr_debug("client: %s awake: %d\n", client, awake); |
| 757 | return 0; |
| 758 | } |
| 759 | |
| 760 | static int qg_fifo_irq_disable_cb(struct votable *votable, void *data, |
| 761 | int disable, const char *client) |
| 762 | { |
| 763 | if (disable) { |
| 764 | if (qg_irqs[QG_FIFO_UPDATE_DONE_IRQ].wake) |
| 765 | disable_irq_wake( |
| 766 | qg_irqs[QG_FIFO_UPDATE_DONE_IRQ].irq); |
| 767 | if (qg_irqs[QG_FIFO_UPDATE_DONE_IRQ].irq) |
| 768 | disable_irq_nosync( |
| 769 | qg_irqs[QG_FIFO_UPDATE_DONE_IRQ].irq); |
| 770 | } else { |
| 771 | if (qg_irqs[QG_FIFO_UPDATE_DONE_IRQ].irq) |
| 772 | enable_irq(qg_irqs[QG_FIFO_UPDATE_DONE_IRQ].irq); |
| 773 | if (qg_irqs[QG_FIFO_UPDATE_DONE_IRQ].wake) |
| 774 | enable_irq_wake( |
| 775 | qg_irqs[QG_FIFO_UPDATE_DONE_IRQ].irq); |
| 776 | } |
| 777 | |
| 778 | return 0; |
| 779 | } |
| 780 | |
| 781 | static int qg_vbatt_irq_disable_cb(struct votable *votable, void *data, |
| 782 | int disable, const char *client) |
| 783 | { |
| 784 | if (disable) { |
| 785 | if (qg_irqs[QG_VBATT_LOW_IRQ].wake) |
| 786 | disable_irq_wake(qg_irqs[QG_VBATT_LOW_IRQ].irq); |
| 787 | if (qg_irqs[QG_VBATT_EMPTY_IRQ].wake) |
| 788 | disable_irq_wake(qg_irqs[QG_VBATT_EMPTY_IRQ].irq); |
| 789 | if (qg_irqs[QG_VBATT_LOW_IRQ].irq) |
| 790 | disable_irq_nosync(qg_irqs[QG_VBATT_LOW_IRQ].irq); |
| 791 | if (qg_irqs[QG_VBATT_EMPTY_IRQ].irq) |
| 792 | disable_irq_nosync(qg_irqs[QG_VBATT_EMPTY_IRQ].irq); |
| 793 | } else { |
| 794 | if (qg_irqs[QG_VBATT_LOW_IRQ].irq) |
| 795 | enable_irq(qg_irqs[QG_VBATT_LOW_IRQ].irq); |
| 796 | if (qg_irqs[QG_VBATT_EMPTY_IRQ].irq) |
| 797 | enable_irq(qg_irqs[QG_VBATT_EMPTY_IRQ].irq); |
| 798 | if (qg_irqs[QG_VBATT_LOW_IRQ].wake) |
| 799 | enable_irq_wake(qg_irqs[QG_VBATT_LOW_IRQ].irq); |
| 800 | if (qg_irqs[QG_VBATT_EMPTY_IRQ].wake) |
| 801 | enable_irq_wake(qg_irqs[QG_VBATT_EMPTY_IRQ].irq); |
| 802 | } |
| 803 | |
| 804 | return 0; |
| 805 | } |
| 806 | |
| 807 | static int qg_good_ocv_irq_disable_cb(struct votable *votable, void *data, |
| 808 | int disable, const char *client) |
| 809 | { |
| 810 | if (disable) { |
| 811 | if (qg_irqs[QG_GOOD_OCV_IRQ].wake) |
| 812 | disable_irq_wake(qg_irqs[QG_GOOD_OCV_IRQ].irq); |
| 813 | if (qg_irqs[QG_GOOD_OCV_IRQ].irq) |
| 814 | disable_irq_nosync(qg_irqs[QG_GOOD_OCV_IRQ].irq); |
| 815 | } else { |
| 816 | if (qg_irqs[QG_GOOD_OCV_IRQ].irq) |
| 817 | enable_irq(qg_irqs[QG_GOOD_OCV_IRQ].irq); |
| 818 | if (qg_irqs[QG_GOOD_OCV_IRQ].wake) |
| 819 | enable_irq_wake(qg_irqs[QG_GOOD_OCV_IRQ].irq); |
| 820 | } |
| 821 | |
| 822 | return 0; |
| 823 | } |
| 824 | |
| 825 | #define DEFAULT_BATT_TYPE "Unknown Battery" |
| 826 | #define MISSING_BATT_TYPE "Missing Battery" |
| 827 | #define DEBUG_BATT_TYPE "Debug Board" |
| 828 | static const char *qg_get_battery_type(struct qpnp_qg *chip) |
| 829 | { |
| 830 | if (chip->battery_missing) |
| 831 | return MISSING_BATT_TYPE; |
| 832 | |
| 833 | if (is_debug_batt_id(chip)) |
| 834 | return DEBUG_BATT_TYPE; |
| 835 | |
| 836 | if (chip->bp.batt_type_str) { |
| 837 | if (chip->profile_loaded) |
| 838 | return chip->bp.batt_type_str; |
| 839 | } |
| 840 | |
| 841 | return DEFAULT_BATT_TYPE; |
| 842 | } |
| 843 | |
| 844 | static int qg_get_battery_current(struct qpnp_qg *chip, int *ibat_ua) |
| 845 | { |
| 846 | int rc = 0, last_ibat = 0; |
| 847 | |
| 848 | if (chip->battery_missing) { |
| 849 | *ibat_ua = 0; |
| 850 | return 0; |
| 851 | } |
| 852 | |
| 853 | rc = qg_read(chip, chip->qg_base + QG_LAST_ADC_I_DATA0_REG, |
| 854 | (u8 *)&last_ibat, 2); |
| 855 | if (rc < 0) { |
| 856 | pr_err("Failed to read LAST_ADV_I reg, rc=%d\n", rc); |
| 857 | return rc; |
| 858 | } |
| 859 | |
| 860 | last_ibat = sign_extend32(last_ibat, 15); |
| 861 | *ibat_ua = I_RAW_TO_UA(last_ibat); |
| 862 | |
| 863 | return rc; |
| 864 | } |
| 865 | |
| 866 | static int qg_get_battery_voltage(struct qpnp_qg *chip, int *vbat_uv) |
| 867 | { |
| 868 | int rc = 0; |
| 869 | u64 last_vbat = 0; |
| 870 | |
| 871 | if (chip->battery_missing) { |
| 872 | *vbat_uv = 3700000; |
| 873 | return 0; |
| 874 | } |
| 875 | |
| 876 | rc = qg_read(chip, chip->qg_base + QG_LAST_ADC_V_DATA0_REG, |
| 877 | (u8 *)&last_vbat, 2); |
| 878 | if (rc < 0) { |
| 879 | pr_err("Failed to read LAST_ADV_V reg, rc=%d\n", rc); |
| 880 | return rc; |
| 881 | } |
| 882 | |
| 883 | *vbat_uv = V_RAW_TO_UV(last_vbat); |
| 884 | |
| 885 | return rc; |
| 886 | } |
| 887 | |
| 888 | #define DEBUG_BATT_SOC 67 |
| 889 | #define BATT_MISSING_SOC 50 |
| 890 | #define EMPTY_SOC 0 |
Vamshi Krishna B V | 2585580 | 2018-02-21 15:26:30 +0530 | [diff] [blame] | 891 | #define FULL_SOC 100 |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 892 | static int qg_get_battery_capacity(struct qpnp_qg *chip, int *soc) |
| 893 | { |
| 894 | if (is_debug_batt_id(chip)) { |
| 895 | *soc = DEBUG_BATT_SOC; |
| 896 | return 0; |
| 897 | } |
| 898 | |
| 899 | if (chip->battery_missing || !chip->profile_loaded) { |
| 900 | *soc = BATT_MISSING_SOC; |
| 901 | return 0; |
| 902 | } |
| 903 | |
Vamshi Krishna B V | 2585580 | 2018-02-21 15:26:30 +0530 | [diff] [blame] | 904 | if (chip->charge_full) { |
| 905 | *soc = FULL_SOC; |
| 906 | return 0; |
| 907 | } |
| 908 | |
Vamshi Krishna B V | 2b61cf6 | 2018-03-13 13:54:33 +0530 | [diff] [blame^] | 909 | mutex_lock(&chip->soc_lock); |
| 910 | |
| 911 | if (chip->dt.linearize_soc && chip->maint_soc > 0) |
| 912 | *soc = chip->maint_soc; |
| 913 | else |
| 914 | *soc = chip->msoc; |
| 915 | |
| 916 | mutex_unlock(&chip->soc_lock); |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 917 | |
| 918 | return 0; |
| 919 | } |
| 920 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 921 | static int qg_psy_set_property(struct power_supply *psy, |
| 922 | enum power_supply_property psp, |
| 923 | const union power_supply_propval *pval) |
| 924 | { |
| 925 | return 0; |
| 926 | } |
| 927 | |
| 928 | static int qg_psy_get_property(struct power_supply *psy, |
| 929 | enum power_supply_property psp, |
| 930 | union power_supply_propval *pval) |
| 931 | { |
| 932 | struct qpnp_qg *chip = power_supply_get_drvdata(psy); |
| 933 | int rc = 0; |
| 934 | |
| 935 | pval->intval = 0; |
| 936 | |
| 937 | switch (psp) { |
| 938 | case POWER_SUPPLY_PROP_CAPACITY: |
| 939 | rc = qg_get_battery_capacity(chip, &pval->intval); |
| 940 | break; |
| 941 | case POWER_SUPPLY_PROP_VOLTAGE_NOW: |
| 942 | rc = qg_get_battery_voltage(chip, &pval->intval); |
| 943 | break; |
| 944 | case POWER_SUPPLY_PROP_CURRENT_NOW: |
| 945 | rc = qg_get_battery_current(chip, &pval->intval); |
| 946 | break; |
| 947 | case POWER_SUPPLY_PROP_VOLTAGE_OCV: |
| 948 | rc = qg_sdam_read(SDAM_OCV_UV, &pval->intval); |
| 949 | break; |
| 950 | case POWER_SUPPLY_PROP_TEMP: |
| 951 | rc = qg_get_battery_temp(chip, &pval->intval); |
| 952 | break; |
| 953 | case POWER_SUPPLY_PROP_RESISTANCE_ID: |
| 954 | pval->intval = chip->batt_id_ohm; |
| 955 | break; |
| 956 | case POWER_SUPPLY_PROP_DEBUG_BATTERY: |
| 957 | pval->intval = is_debug_batt_id(chip); |
| 958 | break; |
| 959 | case POWER_SUPPLY_PROP_RESISTANCE: |
| 960 | rc = qg_sdam_read(SDAM_RBAT_MOHM, &pval->intval); |
| 961 | if (!rc) |
| 962 | pval->intval *= 1000; |
| 963 | break; |
| 964 | case POWER_SUPPLY_PROP_RESISTANCE_CAPACITIVE: |
| 965 | pval->intval = chip->dt.rbat_conn_mohm; |
| 966 | break; |
| 967 | case POWER_SUPPLY_PROP_BATTERY_TYPE: |
| 968 | pval->strval = qg_get_battery_type(chip); |
| 969 | break; |
| 970 | case POWER_SUPPLY_PROP_VOLTAGE_MIN: |
| 971 | pval->intval = chip->dt.vbatt_cutoff_mv * 1000; |
| 972 | break; |
| 973 | case POWER_SUPPLY_PROP_VOLTAGE_MAX: |
| 974 | pval->intval = chip->bp.float_volt_uv; |
| 975 | break; |
| 976 | case POWER_SUPPLY_PROP_BATT_FULL_CURRENT: |
| 977 | pval->intval = chip->dt.iterm_ma * 1000; |
| 978 | break; |
| 979 | case POWER_SUPPLY_PROP_BATT_PROFILE_VERSION: |
| 980 | pval->intval = chip->bp.qg_profile_version; |
| 981 | break; |
Anirudh Ghayal | 07fbf79 | 2018-02-26 11:38:33 +0530 | [diff] [blame] | 982 | case POWER_SUPPLY_PROP_CHARGE_COUNTER: |
| 983 | pval->intval = chip->charge_counter_uah; |
| 984 | break; |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 985 | default: |
| 986 | pr_debug("Unsupported property %d\n", psp); |
| 987 | break; |
| 988 | } |
| 989 | |
| 990 | return rc; |
| 991 | } |
| 992 | |
| 993 | static int qg_property_is_writeable(struct power_supply *psy, |
| 994 | enum power_supply_property psp) |
| 995 | { |
| 996 | return 0; |
| 997 | } |
| 998 | |
| 999 | static enum power_supply_property qg_psy_props[] = { |
| 1000 | POWER_SUPPLY_PROP_CAPACITY, |
| 1001 | POWER_SUPPLY_PROP_TEMP, |
| 1002 | POWER_SUPPLY_PROP_VOLTAGE_NOW, |
| 1003 | POWER_SUPPLY_PROP_VOLTAGE_OCV, |
| 1004 | POWER_SUPPLY_PROP_CURRENT_NOW, |
Anirudh Ghayal | 07fbf79 | 2018-02-26 11:38:33 +0530 | [diff] [blame] | 1005 | POWER_SUPPLY_PROP_CHARGE_COUNTER, |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1006 | POWER_SUPPLY_PROP_RESISTANCE, |
| 1007 | POWER_SUPPLY_PROP_RESISTANCE_ID, |
| 1008 | POWER_SUPPLY_PROP_RESISTANCE_CAPACITIVE, |
| 1009 | POWER_SUPPLY_PROP_DEBUG_BATTERY, |
| 1010 | POWER_SUPPLY_PROP_BATTERY_TYPE, |
| 1011 | POWER_SUPPLY_PROP_VOLTAGE_MIN, |
| 1012 | POWER_SUPPLY_PROP_VOLTAGE_MAX, |
| 1013 | POWER_SUPPLY_PROP_BATT_FULL_CURRENT, |
| 1014 | POWER_SUPPLY_PROP_BATT_PROFILE_VERSION, |
| 1015 | }; |
| 1016 | |
| 1017 | static const struct power_supply_desc qg_psy_desc = { |
| 1018 | .name = "bms", |
| 1019 | .type = POWER_SUPPLY_TYPE_BMS, |
| 1020 | .properties = qg_psy_props, |
| 1021 | .num_properties = ARRAY_SIZE(qg_psy_props), |
| 1022 | .get_property = qg_psy_get_property, |
| 1023 | .set_property = qg_psy_set_property, |
| 1024 | .property_is_writeable = qg_property_is_writeable, |
| 1025 | }; |
| 1026 | |
Vamshi Krishna B V | 2585580 | 2018-02-21 15:26:30 +0530 | [diff] [blame] | 1027 | #define DEFAULT_RECHARGE_SOC 95 |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1028 | static int qg_charge_full_update(struct qpnp_qg *chip) |
| 1029 | { |
Vamshi Krishna B V | 2585580 | 2018-02-21 15:26:30 +0530 | [diff] [blame] | 1030 | union power_supply_propval prop = {0, }; |
| 1031 | int rc, recharge_soc, health; |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1032 | |
| 1033 | vote(chip->good_ocv_irq_disable_votable, |
| 1034 | QG_INIT_STATE_IRQ_DISABLE, !chip->charge_done, 0); |
| 1035 | |
Vamshi Krishna B V | 2585580 | 2018-02-21 15:26:30 +0530 | [diff] [blame] | 1036 | if (!chip->dt.hold_soc_while_full) |
| 1037 | goto out; |
| 1038 | |
| 1039 | rc = power_supply_get_property(chip->batt_psy, |
| 1040 | POWER_SUPPLY_PROP_HEALTH, &prop); |
| 1041 | if (rc < 0) { |
| 1042 | pr_err("Failed to get battery health, rc=%d\n", rc); |
| 1043 | goto out; |
| 1044 | } |
| 1045 | health = prop.intval; |
| 1046 | |
| 1047 | rc = power_supply_get_property(chip->batt_psy, |
| 1048 | POWER_SUPPLY_PROP_RECHARGE_SOC, &prop); |
| 1049 | if (rc < 0 || prop.intval < 0) { |
| 1050 | pr_debug("Failed to get recharge-soc\n"); |
| 1051 | recharge_soc = DEFAULT_RECHARGE_SOC; |
| 1052 | } |
| 1053 | recharge_soc = prop.intval; |
| 1054 | |
Vamshi Krishna B V | 2b61cf6 | 2018-03-13 13:54:33 +0530 | [diff] [blame^] | 1055 | qg_dbg(chip, QG_DEBUG_STATUS, "msoc=%d health=%d charge_full=%d\n", |
| 1056 | chip->msoc, health, chip->charge_full); |
Vamshi Krishna B V | 2585580 | 2018-02-21 15:26:30 +0530 | [diff] [blame] | 1057 | if (chip->charge_done && !chip->charge_full) { |
| 1058 | if (chip->msoc >= 99 && health == POWER_SUPPLY_HEALTH_GOOD) { |
| 1059 | chip->charge_full = true; |
| 1060 | qg_dbg(chip, QG_DEBUG_STATUS, "Setting charge_full (0->1) @ msoc=%d\n", |
| 1061 | chip->msoc); |
| 1062 | } else { |
| 1063 | qg_dbg(chip, QG_DEBUG_STATUS, "Terminated charging @ msoc=%d\n", |
| 1064 | chip->msoc); |
| 1065 | } |
| 1066 | } else if ((!chip->charge_done || chip->msoc < recharge_soc) |
| 1067 | && chip->charge_full) { |
| 1068 | /* |
Vamshi Krishna B V | 2b61cf6 | 2018-03-13 13:54:33 +0530 | [diff] [blame^] | 1069 | * If recharge or discharge has started and |
| 1070 | * if linearize soc dtsi property defined |
| 1071 | * scale msoc from 100% for better UX. |
Vamshi Krishna B V | 2585580 | 2018-02-21 15:26:30 +0530 | [diff] [blame] | 1072 | */ |
Vamshi Krishna B V | 2b61cf6 | 2018-03-13 13:54:33 +0530 | [diff] [blame^] | 1073 | if (chip->dt.linearize_soc && chip->msoc < 99) { |
| 1074 | chip->maint_soc = FULL_SOC; |
| 1075 | qg_scale_soc(chip, false); |
| 1076 | } |
Vamshi Krishna B V | 2585580 | 2018-02-21 15:26:30 +0530 | [diff] [blame] | 1077 | |
| 1078 | qg_dbg(chip, QG_DEBUG_STATUS, "msoc=%d recharge_soc=%d charge_full (1->0)\n", |
| 1079 | chip->msoc, recharge_soc); |
| 1080 | chip->charge_full = false; |
| 1081 | } |
| 1082 | out: |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1083 | return 0; |
| 1084 | } |
| 1085 | |
| 1086 | static int qg_parallel_status_update(struct qpnp_qg *chip) |
| 1087 | { |
| 1088 | int rc; |
| 1089 | bool parallel_enabled = is_parallel_enabled(chip); |
| 1090 | |
| 1091 | if (parallel_enabled == chip->parallel_enabled) |
| 1092 | return 0; |
| 1093 | |
| 1094 | chip->parallel_enabled = parallel_enabled; |
| 1095 | qg_dbg(chip, QG_DEBUG_STATUS, |
| 1096 | "Parallel status changed Enabled=%d\n", parallel_enabled); |
| 1097 | |
| 1098 | mutex_lock(&chip->data_lock); |
| 1099 | |
| 1100 | rc = process_rt_fifo_data(chip, false, true); |
| 1101 | if (rc < 0) |
| 1102 | pr_err("Failed to process RT FIFO data, rc=%d\n", rc); |
| 1103 | |
| 1104 | mutex_unlock(&chip->data_lock); |
| 1105 | |
| 1106 | return 0; |
| 1107 | } |
| 1108 | |
| 1109 | static int qg_usb_status_update(struct qpnp_qg *chip) |
| 1110 | { |
| 1111 | bool usb_present = is_usb_present(chip); |
| 1112 | |
| 1113 | if (chip->usb_present != usb_present) { |
| 1114 | qg_dbg(chip, QG_DEBUG_STATUS, |
| 1115 | "USB status changed Present=%d\n", |
| 1116 | usb_present); |
| 1117 | qg_scale_soc(chip, false); |
| 1118 | } |
| 1119 | |
| 1120 | chip->usb_present = usb_present; |
| 1121 | |
| 1122 | return 0; |
| 1123 | } |
| 1124 | |
| 1125 | static void qg_status_change_work(struct work_struct *work) |
| 1126 | { |
| 1127 | struct qpnp_qg *chip = container_of(work, |
| 1128 | struct qpnp_qg, qg_status_change_work); |
| 1129 | union power_supply_propval prop = {0, }; |
| 1130 | int rc = 0; |
| 1131 | |
| 1132 | if (!is_batt_available(chip)) { |
| 1133 | pr_debug("batt-psy not available\n"); |
| 1134 | goto out; |
| 1135 | } |
| 1136 | |
| 1137 | rc = power_supply_get_property(chip->batt_psy, |
| 1138 | POWER_SUPPLY_PROP_STATUS, &prop); |
| 1139 | if (rc < 0) |
| 1140 | pr_err("Failed to get charger status, rc=%d\n", rc); |
| 1141 | else |
| 1142 | chip->charge_status = prop.intval; |
| 1143 | |
| 1144 | rc = power_supply_get_property(chip->batt_psy, |
| 1145 | POWER_SUPPLY_PROP_CHARGE_DONE, &prop); |
| 1146 | if (rc < 0) |
| 1147 | pr_err("Failed to get charge done status, rc=%d\n", rc); |
| 1148 | else |
| 1149 | chip->charge_done = prop.intval; |
| 1150 | |
Vamshi Krishna B V | 2585580 | 2018-02-21 15:26:30 +0530 | [diff] [blame] | 1151 | qg_dbg(chip, QG_DEBUG_STATUS, "charge_status=%d charge_done=%d\n", |
| 1152 | chip->charge_status, chip->charge_done); |
| 1153 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1154 | rc = qg_parallel_status_update(chip); |
| 1155 | if (rc < 0) |
| 1156 | pr_err("Failed to update parallel-status, rc=%d\n", rc); |
| 1157 | |
| 1158 | rc = qg_usb_status_update(chip); |
| 1159 | if (rc < 0) |
| 1160 | pr_err("Failed to update usb status, rc=%d\n", rc); |
| 1161 | |
| 1162 | rc = qg_charge_full_update(chip); |
| 1163 | if (rc < 0) |
| 1164 | pr_err("Failed in charge_full_update, rc=%d\n", rc); |
| 1165 | out: |
| 1166 | pm_relax(chip->dev); |
| 1167 | } |
| 1168 | |
| 1169 | static int qg_notifier_cb(struct notifier_block *nb, |
| 1170 | unsigned long event, void *data) |
| 1171 | { |
| 1172 | struct power_supply *psy = data; |
| 1173 | struct qpnp_qg *chip = container_of(nb, struct qpnp_qg, nb); |
| 1174 | |
| 1175 | if (event != PSY_EVENT_PROP_CHANGED) |
| 1176 | return NOTIFY_OK; |
| 1177 | |
| 1178 | if (work_pending(&chip->qg_status_change_work)) |
| 1179 | return NOTIFY_OK; |
| 1180 | |
| 1181 | if ((strcmp(psy->desc->name, "battery") == 0) |
| 1182 | || (strcmp(psy->desc->name, "parallel") == 0) |
| 1183 | || (strcmp(psy->desc->name, "usb") == 0)) { |
| 1184 | /* |
| 1185 | * We cannot vote for awake votable here as that takes |
| 1186 | * a mutex lock and this is executed in an atomic context. |
| 1187 | */ |
| 1188 | pm_stay_awake(chip->dev); |
| 1189 | schedule_work(&chip->qg_status_change_work); |
| 1190 | } |
| 1191 | |
| 1192 | return NOTIFY_OK; |
| 1193 | } |
| 1194 | |
| 1195 | static int qg_init_psy(struct qpnp_qg *chip) |
| 1196 | { |
| 1197 | struct power_supply_config qg_psy_cfg; |
| 1198 | int rc; |
| 1199 | |
| 1200 | qg_psy_cfg.drv_data = chip; |
| 1201 | qg_psy_cfg.of_node = NULL; |
| 1202 | qg_psy_cfg.supplied_to = NULL; |
| 1203 | qg_psy_cfg.num_supplicants = 0; |
| 1204 | chip->qg_psy = devm_power_supply_register(chip->dev, |
| 1205 | &qg_psy_desc, &qg_psy_cfg); |
| 1206 | if (IS_ERR_OR_NULL(chip->qg_psy)) { |
| 1207 | pr_err("Failed to register qg_psy rc = %ld\n", |
| 1208 | PTR_ERR(chip->qg_psy)); |
| 1209 | return -ENODEV; |
| 1210 | } |
| 1211 | |
| 1212 | chip->nb.notifier_call = qg_notifier_cb; |
| 1213 | rc = power_supply_reg_notifier(&chip->nb); |
| 1214 | if (rc < 0) |
| 1215 | pr_err("Failed register psy notifier rc = %d\n", rc); |
| 1216 | |
| 1217 | return rc; |
| 1218 | } |
| 1219 | |
| 1220 | static ssize_t qg_device_read(struct file *file, char __user *buf, size_t count, |
| 1221 | loff_t *ppos) |
| 1222 | { |
| 1223 | int rc; |
| 1224 | struct qpnp_qg *chip = file->private_data; |
| 1225 | unsigned long data_size = sizeof(chip->kdata); |
| 1226 | |
| 1227 | /* non-blocking access, return */ |
| 1228 | if (!chip->data_ready && (file->f_flags & O_NONBLOCK)) |
Vamshi Krishna B V | 2585580 | 2018-02-21 15:26:30 +0530 | [diff] [blame] | 1229 | return 0; |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1230 | |
| 1231 | /* blocking access wait on data_ready */ |
| 1232 | if (!(file->f_flags & O_NONBLOCK)) { |
| 1233 | rc = wait_event_interruptible(chip->qg_wait_q, |
| 1234 | chip->data_ready); |
| 1235 | if (rc < 0) { |
| 1236 | pr_debug("Failed wait! rc=%d\n", rc); |
| 1237 | return rc; |
| 1238 | } |
| 1239 | } |
| 1240 | |
| 1241 | mutex_lock(&chip->data_lock); |
| 1242 | |
| 1243 | if (!chip->data_ready) { |
| 1244 | pr_debug("No Data, false wakeup\n"); |
| 1245 | rc = -EFAULT; |
| 1246 | goto fail_read; |
| 1247 | } |
| 1248 | |
Anirudh Ghayal | 07fbf79 | 2018-02-26 11:38:33 +0530 | [diff] [blame] | 1249 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1250 | if (copy_to_user(buf, &chip->kdata, data_size)) { |
| 1251 | pr_err("Failed in copy_to_user\n"); |
| 1252 | rc = -EFAULT; |
| 1253 | goto fail_read; |
| 1254 | } |
| 1255 | chip->data_ready = false; |
| 1256 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1257 | /* release all wake sources */ |
| 1258 | vote(chip->awake_votable, GOOD_OCV_VOTER, false, 0); |
| 1259 | vote(chip->awake_votable, FIFO_DONE_VOTER, false, 0); |
| 1260 | vote(chip->awake_votable, FIFO_RT_DONE_VOTER, false, 0); |
| 1261 | vote(chip->awake_votable, SUSPEND_DATA_VOTER, false, 0); |
| 1262 | |
| 1263 | qg_dbg(chip, QG_DEBUG_DEVICE, |
Anirudh Ghayal | 07fbf79 | 2018-02-26 11:38:33 +0530 | [diff] [blame] | 1264 | "QG device read complete Seq_no=%u Size=%ld\n", |
| 1265 | chip->kdata.seq_no, data_size); |
| 1266 | |
| 1267 | /* clear data */ |
| 1268 | memset(&chip->kdata, 0, sizeof(chip->kdata)); |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1269 | |
| 1270 | mutex_unlock(&chip->data_lock); |
| 1271 | |
| 1272 | return data_size; |
| 1273 | |
| 1274 | fail_read: |
| 1275 | mutex_unlock(&chip->data_lock); |
| 1276 | return rc; |
| 1277 | } |
| 1278 | |
| 1279 | static ssize_t qg_device_write(struct file *file, const char __user *buf, |
| 1280 | size_t count, loff_t *ppos) |
| 1281 | { |
| 1282 | int rc = -EINVAL; |
| 1283 | struct qpnp_qg *chip = file->private_data; |
| 1284 | unsigned long data_size = sizeof(chip->udata); |
| 1285 | |
| 1286 | mutex_lock(&chip->data_lock); |
| 1287 | if (count == 0) { |
| 1288 | pr_err("No data!\n"); |
| 1289 | goto fail; |
| 1290 | } |
| 1291 | |
| 1292 | if (count != 0 && count < data_size) { |
Kiran Gunda | 0f5de04 | 2018-03-02 13:02:22 +0530 | [diff] [blame] | 1293 | pr_err("Invalid datasize %zu expected %lu\n", count, data_size); |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1294 | goto fail; |
| 1295 | } |
| 1296 | |
| 1297 | if (copy_from_user(&chip->udata, buf, data_size)) { |
| 1298 | pr_err("Failed in copy_from_user\n"); |
| 1299 | rc = -EFAULT; |
| 1300 | goto fail; |
| 1301 | } |
| 1302 | |
| 1303 | rc = data_size; |
| 1304 | vote(chip->awake_votable, UDATA_READY_VOTER, true, 0); |
| 1305 | schedule_work(&chip->udata_work); |
| 1306 | qg_dbg(chip, QG_DEBUG_DEVICE, "QG write complete size=%d\n", rc); |
| 1307 | fail: |
| 1308 | mutex_unlock(&chip->data_lock); |
| 1309 | return rc; |
| 1310 | } |
| 1311 | |
| 1312 | static unsigned int qg_device_poll(struct file *file, poll_table *wait) |
| 1313 | { |
| 1314 | struct qpnp_qg *chip = file->private_data; |
Vamshi Krishna B V | 2585580 | 2018-02-21 15:26:30 +0530 | [diff] [blame] | 1315 | unsigned int mask = 0; |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1316 | |
| 1317 | poll_wait(file, &chip->qg_wait_q, wait); |
| 1318 | |
| 1319 | if (chip->data_ready) |
| 1320 | mask = POLLIN | POLLRDNORM; |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1321 | |
| 1322 | return mask; |
| 1323 | } |
| 1324 | |
| 1325 | static int qg_device_open(struct inode *inode, struct file *file) |
| 1326 | { |
| 1327 | struct qpnp_qg *chip = container_of(inode->i_cdev, |
| 1328 | struct qpnp_qg, qg_cdev); |
| 1329 | |
| 1330 | file->private_data = chip; |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 1331 | chip->qg_device_open = true; |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1332 | qg_dbg(chip, QG_DEBUG_DEVICE, "QG device opened!\n"); |
| 1333 | |
| 1334 | return 0; |
| 1335 | } |
| 1336 | |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 1337 | static int qg_device_release(struct inode *inode, struct file *file) |
| 1338 | { |
| 1339 | struct qpnp_qg *chip = container_of(inode->i_cdev, |
| 1340 | struct qpnp_qg, qg_cdev); |
| 1341 | |
| 1342 | file->private_data = chip; |
| 1343 | chip->qg_device_open = false; |
| 1344 | qg_dbg(chip, QG_DEBUG_DEVICE, "QG device closed!\n"); |
| 1345 | |
| 1346 | return 0; |
| 1347 | } |
| 1348 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1349 | static const struct file_operations qg_fops = { |
| 1350 | .owner = THIS_MODULE, |
| 1351 | .open = qg_device_open, |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 1352 | .release = qg_device_release, |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1353 | .read = qg_device_read, |
| 1354 | .write = qg_device_write, |
| 1355 | .poll = qg_device_poll, |
| 1356 | }; |
| 1357 | |
| 1358 | static int qg_register_device(struct qpnp_qg *chip) |
| 1359 | { |
| 1360 | int rc; |
| 1361 | |
| 1362 | rc = alloc_chrdev_region(&chip->dev_no, 0, 1, "qg"); |
| 1363 | if (rc < 0) { |
| 1364 | pr_err("Failed to allocate chardev rc=%d\n", rc); |
| 1365 | return rc; |
| 1366 | } |
| 1367 | |
| 1368 | cdev_init(&chip->qg_cdev, &qg_fops); |
| 1369 | rc = cdev_add(&chip->qg_cdev, chip->dev_no, 1); |
| 1370 | if (rc < 0) { |
| 1371 | pr_err("Failed to cdev_add rc=%d\n", rc); |
| 1372 | goto unregister_chrdev; |
| 1373 | } |
| 1374 | |
| 1375 | chip->qg_class = class_create(THIS_MODULE, "qg"); |
| 1376 | if (IS_ERR_OR_NULL(chip->qg_class)) { |
| 1377 | pr_err("Failed to create qg class\n"); |
| 1378 | rc = -EINVAL; |
| 1379 | goto delete_cdev; |
| 1380 | } |
| 1381 | chip->qg_device = device_create(chip->qg_class, NULL, chip->dev_no, |
| 1382 | NULL, "qg"); |
| 1383 | if (IS_ERR(chip->qg_device)) { |
| 1384 | pr_err("Failed to create qg_device\n"); |
| 1385 | rc = -EINVAL; |
| 1386 | goto destroy_class; |
| 1387 | } |
| 1388 | |
| 1389 | qg_dbg(chip, QG_DEBUG_DEVICE, "'/dev/qg' successfully created\n"); |
| 1390 | |
| 1391 | return 0; |
| 1392 | |
| 1393 | destroy_class: |
| 1394 | class_destroy(chip->qg_class); |
| 1395 | delete_cdev: |
| 1396 | cdev_del(&chip->qg_cdev); |
| 1397 | unregister_chrdev: |
| 1398 | unregister_chrdev_region(chip->dev_no, 1); |
| 1399 | return rc; |
| 1400 | } |
| 1401 | |
| 1402 | #define BID_RPULL_OHM 100000 |
| 1403 | #define BID_VREF_MV 1875 |
| 1404 | static int get_batt_id_ohm(struct qpnp_qg *chip, u32 *batt_id_ohm) |
| 1405 | { |
| 1406 | int rc, batt_id_mv; |
| 1407 | int64_t denom; |
| 1408 | struct qpnp_vadc_result result; |
| 1409 | |
| 1410 | /* Read battery-id */ |
| 1411 | rc = qpnp_vadc_read(chip->vadc_dev, VADC_BAT_ID_PU2, &result); |
| 1412 | if (rc) { |
| 1413 | pr_err("Failed to read BATT_ID over vadc, rc=%d\n", rc); |
| 1414 | return rc; |
| 1415 | } |
| 1416 | |
Kiran Gunda | 0f5de04 | 2018-03-02 13:02:22 +0530 | [diff] [blame] | 1417 | batt_id_mv = div_s64(result.physical, 1000); |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1418 | if (batt_id_mv == 0) { |
| 1419 | pr_debug("batt_id_mv = 0 from ADC\n"); |
| 1420 | return 0; |
| 1421 | } |
| 1422 | |
| 1423 | denom = div64_s64(BID_VREF_MV * 1000, batt_id_mv) - 1000; |
| 1424 | if (denom <= 0) { |
| 1425 | /* batt id connector might be open, return 0 kohms */ |
| 1426 | return 0; |
| 1427 | } |
| 1428 | |
| 1429 | *batt_id_ohm = div64_u64(BID_RPULL_OHM * 1000 + denom / 2, denom); |
| 1430 | |
| 1431 | qg_dbg(chip, QG_DEBUG_PROFILE, "batt_id_mv=%d, batt_id_ohm=%d\n", |
| 1432 | batt_id_mv, *batt_id_ohm); |
| 1433 | |
| 1434 | return 0; |
| 1435 | } |
| 1436 | |
| 1437 | static int qg_load_battery_profile(struct qpnp_qg *chip) |
| 1438 | { |
| 1439 | struct device_node *node = chip->dev->of_node; |
| 1440 | struct device_node *batt_node, *profile_node; |
| 1441 | int rc; |
| 1442 | |
| 1443 | batt_node = of_find_node_by_name(node, "qcom,battery-data"); |
| 1444 | if (!batt_node) { |
| 1445 | pr_err("Batterydata not available\n"); |
| 1446 | return -ENXIO; |
| 1447 | } |
| 1448 | |
| 1449 | profile_node = of_batterydata_get_best_profile(batt_node, |
| 1450 | chip->batt_id_ohm / 1000, NULL); |
| 1451 | if (IS_ERR(profile_node)) { |
| 1452 | rc = PTR_ERR(profile_node); |
| 1453 | pr_err("Failed to detect valid QG battery profile %d\n", rc); |
| 1454 | return rc; |
| 1455 | } |
| 1456 | |
| 1457 | rc = of_property_read_string(profile_node, "qcom,battery-type", |
| 1458 | &chip->bp.batt_type_str); |
| 1459 | if (rc < 0) { |
| 1460 | pr_err("Failed to detect battery type rc:%d\n", rc); |
| 1461 | return rc; |
| 1462 | } |
| 1463 | |
| 1464 | rc = qg_batterydata_init(profile_node); |
| 1465 | if (rc < 0) { |
| 1466 | pr_err("Failed to initialize battery-profile rc=%d\n", rc); |
| 1467 | return rc; |
| 1468 | } |
| 1469 | |
| 1470 | rc = of_property_read_u32(profile_node, "qcom,max-voltage-uv", |
| 1471 | &chip->bp.float_volt_uv); |
| 1472 | if (rc < 0) { |
| 1473 | pr_err("Failed to read battery float-voltage rc:%d\n", rc); |
| 1474 | chip->bp.float_volt_uv = -EINVAL; |
| 1475 | } |
| 1476 | |
| 1477 | rc = of_property_read_u32(profile_node, "qcom,fastchg-current-ma", |
| 1478 | &chip->bp.fastchg_curr_ma); |
| 1479 | if (rc < 0) { |
| 1480 | pr_err("Failed to read battery fastcharge current rc:%d\n", rc); |
| 1481 | chip->bp.fastchg_curr_ma = -EINVAL; |
| 1482 | } |
| 1483 | |
| 1484 | rc = of_property_read_u32(profile_node, "qcom,qg-batt-profile-ver", |
| 1485 | &chip->bp.qg_profile_version); |
| 1486 | if (rc < 0) { |
| 1487 | pr_err("Failed to read QG profile version rc:%d\n", rc); |
| 1488 | chip->bp.qg_profile_version = -EINVAL; |
| 1489 | } |
| 1490 | |
| 1491 | qg_dbg(chip, QG_DEBUG_PROFILE, "profile=%s FV=%duV FCC=%dma\n", |
| 1492 | chip->bp.batt_type_str, chip->bp.float_volt_uv, |
| 1493 | chip->bp.fastchg_curr_ma); |
| 1494 | |
| 1495 | return 0; |
| 1496 | } |
| 1497 | |
| 1498 | static int qg_setup_battery(struct qpnp_qg *chip) |
| 1499 | { |
| 1500 | int rc; |
| 1501 | |
| 1502 | if (!is_battery_present(chip)) { |
| 1503 | qg_dbg(chip, QG_DEBUG_PROFILE, "Battery Missing!\n"); |
| 1504 | chip->battery_missing = true; |
| 1505 | chip->profile_loaded = false; |
| 1506 | } else { |
| 1507 | /* battery present */ |
| 1508 | rc = get_batt_id_ohm(chip, &chip->batt_id_ohm); |
| 1509 | if (rc < 0) { |
| 1510 | pr_err("Failed to detect batt_id rc=%d\n", rc); |
| 1511 | chip->profile_loaded = false; |
| 1512 | } else { |
| 1513 | rc = qg_load_battery_profile(chip); |
| 1514 | if (rc < 0) |
| 1515 | pr_err("Failed to load battery-profile rc=%d\n", |
| 1516 | rc); |
| 1517 | else |
| 1518 | chip->profile_loaded = true; |
| 1519 | } |
| 1520 | } |
| 1521 | |
| 1522 | qg_dbg(chip, QG_DEBUG_PROFILE, "battery_missing=%d batt_id_ohm=%d Ohm profile_loaded=%d profile=%s\n", |
| 1523 | chip->battery_missing, chip->batt_id_ohm, |
| 1524 | chip->profile_loaded, chip->bp.batt_type_str); |
| 1525 | |
| 1526 | return 0; |
| 1527 | } |
| 1528 | |
| 1529 | static int qg_determine_pon_soc(struct qpnp_qg *chip) |
| 1530 | { |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 1531 | u8 status = 0, ocv_type = 0; |
| 1532 | int rc = 0, batt_temp = 0; |
| 1533 | bool use_pon_ocv = true, use_shutdown_ocv = false; |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1534 | unsigned long rtc_sec = 0; |
| 1535 | u32 ocv_uv = 0, soc = 0, shutdown[SDAM_MAX] = {0}; |
| 1536 | |
| 1537 | if (!chip->profile_loaded) { |
| 1538 | qg_dbg(chip, QG_DEBUG_PON, "No Profile, skipping PON soc\n"); |
| 1539 | return 0; |
| 1540 | } |
| 1541 | |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 1542 | rc = get_rtc_time(&rtc_sec); |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1543 | if (rc < 0) { |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 1544 | pr_err("Failed to read RTC time rc=%d\n", rc); |
| 1545 | goto use_pon_ocv; |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1546 | } |
| 1547 | |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 1548 | rc = qg_sdam_read_all(shutdown); |
| 1549 | if (rc < 0) { |
| 1550 | pr_err("Failed to read shutdown params rc=%d\n", rc); |
| 1551 | goto use_pon_ocv; |
| 1552 | } |
| 1553 | |
| 1554 | qg_dbg(chip, QG_DEBUG_PON, "Shutdown: Valid=%d SOC=%d OCV=%duV time=%dsecs, time_now=%ldsecs\n", |
| 1555 | shutdown[SDAM_VALID], |
| 1556 | shutdown[SDAM_SOC], |
| 1557 | shutdown[SDAM_OCV_UV], |
| 1558 | shutdown[SDAM_TIME_SEC], |
| 1559 | rtc_sec); |
| 1560 | /* |
| 1561 | * Use the shutdown SOC if |
| 1562 | * 1. The device was powered off for < ignore_shutdown_time |
| 1563 | * 2. SDAM read is a success & SDAM data is valid |
| 1564 | */ |
| 1565 | if (shutdown[SDAM_VALID] && is_between(0, |
| 1566 | chip->dt.ignore_shutdown_soc_secs, |
| 1567 | (rtc_sec - shutdown[SDAM_TIME_SEC]))) { |
| 1568 | use_pon_ocv = false; |
| 1569 | use_shutdown_ocv = true; |
| 1570 | ocv_uv = shutdown[SDAM_OCV_UV]; |
| 1571 | soc = shutdown[SDAM_SOC]; |
| 1572 | qg_dbg(chip, QG_DEBUG_PON, "Using SHUTDOWN_SOC @ PON\n"); |
| 1573 | } |
| 1574 | |
| 1575 | use_pon_ocv: |
| 1576 | if (use_pon_ocv == true) { |
| 1577 | rc = qg_get_battery_temp(chip, &batt_temp); |
| 1578 | if (rc) { |
| 1579 | pr_err("Failed to read BATT_TEMP at PON rc=%d\n", rc); |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1580 | goto done; |
| 1581 | } |
| 1582 | |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 1583 | rc = qg_read(chip, chip->qg_base + QG_STATUS2_REG, &status, 1); |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1584 | if (rc < 0) { |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 1585 | pr_err("Failed to read status2 register rc=%d\n", rc); |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1586 | goto done; |
| 1587 | } |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 1588 | |
| 1589 | if (status & GOOD_OCV_BIT) |
| 1590 | ocv_type = GOOD_OCV; |
| 1591 | else |
| 1592 | ocv_type = PON_OCV; |
| 1593 | |
| 1594 | qg_dbg(chip, QG_DEBUG_PON, "Using %s @ PON\n", |
| 1595 | ocv_type == GOOD_OCV ? "GOOD_OCV" : "PON_OCV"); |
| 1596 | |
| 1597 | rc = qg_read_ocv(chip, &ocv_uv, ocv_type); |
| 1598 | if (rc < 0) { |
| 1599 | pr_err("Failed to read ocv rc=%d\n", rc); |
| 1600 | goto done; |
| 1601 | } |
| 1602 | |
| 1603 | rc = lookup_soc_ocv(&soc, ocv_uv, batt_temp, false); |
| 1604 | if (rc < 0) { |
| 1605 | pr_err("Failed to lookup SOC@PON rc=%d\n", rc); |
| 1606 | goto done; |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1607 | } |
| 1608 | } |
| 1609 | done: |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 1610 | if (rc < 0) { |
| 1611 | pr_err("Failed to get SOC @ PON, rc=%d\n", rc); |
| 1612 | return rc; |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1613 | } |
| 1614 | |
| 1615 | chip->pon_soc = chip->catch_up_soc = chip->msoc = soc; |
| 1616 | chip->kdata.param[QG_PON_OCV_UV].data = ocv_uv; |
| 1617 | chip->kdata.param[QG_PON_OCV_UV].valid = true; |
| 1618 | |
| 1619 | /* write back to SDAM */ |
| 1620 | chip->sdam_data[SDAM_SOC] = soc; |
| 1621 | chip->sdam_data[SDAM_OCV_UV] = ocv_uv; |
| 1622 | chip->sdam_data[SDAM_VALID] = 1; |
| 1623 | |
| 1624 | rc = qg_write_monotonic_soc(chip, chip->msoc); |
| 1625 | if (rc < 0) |
| 1626 | pr_err("Failed to update MSOC register rc=%d\n", rc); |
| 1627 | |
| 1628 | rc = qg_update_sdam_params(chip); |
| 1629 | if (rc < 0) |
| 1630 | pr_err("Failed to update sdam params rc=%d\n", rc); |
| 1631 | |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 1632 | pr_info("use_pon_ocv=%d use_good_ocv=%d use_shutdown_ocv=%d ocv_uv=%duV soc=%d\n", |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1633 | use_pon_ocv, !!(status & GOOD_OCV_BIT), |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 1634 | use_shutdown_ocv, ocv_uv, chip->msoc); |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1635 | return 0; |
| 1636 | } |
| 1637 | |
| 1638 | static int qg_set_wa_flags(struct qpnp_qg *chip) |
| 1639 | { |
| 1640 | switch (chip->pmic_rev_id->pmic_subtype) { |
| 1641 | case PMI632_SUBTYPE: |
| 1642 | if (chip->pmic_rev_id->rev4 == PMI632_V1P0_REV4) |
| 1643 | chip->wa_flags |= QG_VBAT_LOW_WA; |
| 1644 | break; |
| 1645 | default: |
| 1646 | pr_err("Unsupported PMIC subtype %d\n", |
| 1647 | chip->pmic_rev_id->pmic_subtype); |
| 1648 | return -EINVAL; |
| 1649 | } |
| 1650 | |
| 1651 | qg_dbg(chip, QG_DEBUG_PON, "wa_flags = %x\n", chip->wa_flags); |
| 1652 | |
| 1653 | return 0; |
| 1654 | } |
| 1655 | |
| 1656 | static int qg_hw_init(struct qpnp_qg *chip) |
| 1657 | { |
| 1658 | int rc, temp; |
| 1659 | u8 reg; |
| 1660 | |
| 1661 | rc = qg_set_wa_flags(chip); |
| 1662 | if (rc < 0) { |
| 1663 | pr_err("Failed to update PMIC type flags, rc=%d\n", rc); |
| 1664 | return rc; |
| 1665 | } |
| 1666 | |
| 1667 | rc = qg_master_hold(chip, true); |
| 1668 | if (rc < 0) { |
| 1669 | pr_err("Failed to hold master, rc=%d\n", rc); |
| 1670 | goto done_fifo; |
| 1671 | } |
| 1672 | |
| 1673 | rc = qg_process_rt_fifo(chip); |
| 1674 | if (rc < 0) { |
| 1675 | pr_err("Failed to process FIFO real-time, rc=%d\n", rc); |
| 1676 | goto done_fifo; |
| 1677 | } |
| 1678 | |
| 1679 | /* update the changed S2 fifo DT parameters */ |
| 1680 | if (chip->dt.s2_fifo_length > 0) { |
| 1681 | rc = qg_update_fifo_length(chip, chip->dt.s2_fifo_length); |
| 1682 | if (rc < 0) |
| 1683 | goto done_fifo; |
| 1684 | } |
| 1685 | |
| 1686 | if (chip->dt.s2_acc_length > 0) { |
| 1687 | reg = ilog2(chip->dt.s2_acc_length) - 1; |
| 1688 | rc = qg_masked_write(chip, chip->qg_base + |
| 1689 | QG_S2_NORMAL_MEAS_CTL2_REG, |
| 1690 | NUM_OF_ACCUM_MASK, reg); |
| 1691 | if (rc < 0) { |
| 1692 | pr_err("Failed to write S2 ACC length, rc=%d\n", rc); |
| 1693 | goto done_fifo; |
| 1694 | } |
| 1695 | } |
| 1696 | |
| 1697 | if (chip->dt.s2_acc_intvl_ms > 0) { |
| 1698 | reg = chip->dt.s2_acc_intvl_ms / 10; |
| 1699 | rc = qg_write(chip, chip->qg_base + |
| 1700 | QG_S2_NORMAL_MEAS_CTL3_REG, |
| 1701 | ®, 1); |
| 1702 | if (rc < 0) { |
| 1703 | pr_err("Failed to write S2 ACC intrvl, rc=%d\n", rc); |
| 1704 | goto done_fifo; |
| 1705 | } |
| 1706 | } |
| 1707 | |
| 1708 | /* signal the read thread */ |
| 1709 | chip->data_ready = true; |
| 1710 | wake_up_interruptible(&chip->qg_wait_q); |
| 1711 | |
| 1712 | done_fifo: |
| 1713 | rc = qg_master_hold(chip, false); |
| 1714 | if (rc < 0) { |
| 1715 | pr_err("Failed to release master, rc=%d\n", rc); |
| 1716 | return rc; |
| 1717 | } |
| 1718 | chip->last_fifo_update_time = ktime_get(); |
| 1719 | |
| 1720 | if (chip->dt.ocv_timer_expiry_min != -EINVAL) { |
| 1721 | if (chip->dt.ocv_timer_expiry_min < 2) |
| 1722 | chip->dt.ocv_timer_expiry_min = 2; |
| 1723 | else if (chip->dt.ocv_timer_expiry_min > 30) |
| 1724 | chip->dt.ocv_timer_expiry_min = 30; |
| 1725 | |
| 1726 | reg = (chip->dt.ocv_timer_expiry_min - 2) / 4; |
| 1727 | rc = qg_masked_write(chip, |
| 1728 | chip->qg_base + QG_S3_SLEEP_OCV_MEAS_CTL4_REG, |
| 1729 | SLEEP_IBAT_QUALIFIED_LENGTH_MASK, reg); |
| 1730 | if (rc < 0) { |
| 1731 | pr_err("Failed to write OCV timer, rc=%d\n", rc); |
| 1732 | return rc; |
| 1733 | } |
| 1734 | } |
| 1735 | |
| 1736 | if (chip->dt.ocv_tol_threshold_uv != -EINVAL) { |
| 1737 | if (chip->dt.ocv_tol_threshold_uv < 0) |
| 1738 | chip->dt.ocv_tol_threshold_uv = 0; |
| 1739 | else if (chip->dt.ocv_tol_threshold_uv > 12262) |
| 1740 | chip->dt.ocv_tol_threshold_uv = 12262; |
| 1741 | |
| 1742 | reg = chip->dt.ocv_tol_threshold_uv / 195; |
| 1743 | rc = qg_masked_write(chip, |
| 1744 | chip->qg_base + QG_S3_SLEEP_OCV_TREND_CTL2_REG, |
| 1745 | TREND_TOL_MASK, reg); |
| 1746 | if (rc < 0) { |
| 1747 | pr_err("Failed to write OCV tol-thresh, rc=%d\n", rc); |
| 1748 | return rc; |
| 1749 | } |
| 1750 | } |
| 1751 | |
| 1752 | if (chip->dt.s3_entry_fifo_length != -EINVAL) { |
| 1753 | if (chip->dt.s3_entry_fifo_length < 1) |
| 1754 | chip->dt.s3_entry_fifo_length = 1; |
| 1755 | else if (chip->dt.s3_entry_fifo_length > 8) |
| 1756 | chip->dt.s3_entry_fifo_length = 8; |
| 1757 | |
| 1758 | reg = chip->dt.s3_entry_fifo_length - 1; |
| 1759 | rc = qg_masked_write(chip, |
| 1760 | chip->qg_base + QG_S3_SLEEP_OCV_IBAT_CTL1_REG, |
| 1761 | SLEEP_IBAT_QUALIFIED_LENGTH_MASK, reg); |
| 1762 | if (rc < 0) { |
| 1763 | pr_err("Failed to write S3-entry fifo-length, rc=%d\n", |
| 1764 | rc); |
| 1765 | return rc; |
| 1766 | } |
| 1767 | } |
| 1768 | |
| 1769 | if (chip->dt.s3_entry_ibat_ua != -EINVAL) { |
| 1770 | if (chip->dt.s3_entry_ibat_ua < 0) |
| 1771 | chip->dt.s3_entry_ibat_ua = 0; |
| 1772 | else if (chip->dt.s3_entry_ibat_ua > 155550) |
| 1773 | chip->dt.s3_entry_ibat_ua = 155550; |
| 1774 | |
| 1775 | reg = chip->dt.s3_entry_ibat_ua / 610; |
| 1776 | rc = qg_write(chip, chip->qg_base + |
| 1777 | QG_S3_ENTRY_IBAT_THRESHOLD_REG, |
| 1778 | ®, 1); |
| 1779 | if (rc < 0) { |
| 1780 | pr_err("Failed to write S3-entry ibat-uA, rc=%d\n", rc); |
| 1781 | return rc; |
| 1782 | } |
| 1783 | } |
| 1784 | |
| 1785 | if (chip->dt.s3_exit_ibat_ua != -EINVAL) { |
| 1786 | if (chip->dt.s3_exit_ibat_ua < 0) |
| 1787 | chip->dt.s3_exit_ibat_ua = 0; |
| 1788 | else if (chip->dt.s3_exit_ibat_ua > 155550) |
| 1789 | chip->dt.s3_exit_ibat_ua = 155550; |
| 1790 | |
| 1791 | rc = qg_read(chip, chip->qg_base + |
| 1792 | QG_S3_ENTRY_IBAT_THRESHOLD_REG, |
| 1793 | ®, 1); |
| 1794 | if (rc < 0) { |
| 1795 | pr_err("Failed to read S3-entry ibat-uA, rc=%d", rc); |
| 1796 | return rc; |
| 1797 | } |
| 1798 | temp = reg * 610; |
| 1799 | if (chip->dt.s3_exit_ibat_ua < temp) |
| 1800 | chip->dt.s3_exit_ibat_ua = temp; |
| 1801 | else |
| 1802 | chip->dt.s3_exit_ibat_ua -= temp; |
| 1803 | |
| 1804 | reg = chip->dt.s3_exit_ibat_ua / 610; |
| 1805 | rc = qg_write(chip, |
| 1806 | chip->qg_base + QG_S3_EXIT_IBAT_THRESHOLD_REG, |
| 1807 | ®, 1); |
| 1808 | if (rc < 0) { |
| 1809 | pr_err("Failed to write S3-entry ibat-uA, rc=%d\n", rc); |
| 1810 | return rc; |
| 1811 | } |
| 1812 | } |
| 1813 | |
| 1814 | /* vbat low */ |
| 1815 | if (chip->dt.vbatt_low_mv < 0) |
| 1816 | chip->dt.vbatt_low_mv = 0; |
| 1817 | else if (chip->dt.vbatt_low_mv > 12750) |
| 1818 | chip->dt.vbatt_low_mv = 12750; |
| 1819 | |
| 1820 | reg = chip->dt.vbatt_low_mv / 50; |
| 1821 | rc = qg_write(chip, chip->qg_base + QG_VBAT_LOW_THRESHOLD_REG, |
| 1822 | ®, 1); |
| 1823 | if (rc < 0) { |
| 1824 | pr_err("Failed to write vbat-low, rc=%d\n", rc); |
| 1825 | return rc; |
| 1826 | } |
| 1827 | |
| 1828 | /* vbat empty */ |
| 1829 | if (chip->dt.vbatt_empty_mv < 0) |
| 1830 | chip->dt.vbatt_empty_mv = 0; |
| 1831 | else if (chip->dt.vbatt_empty_mv > 12750) |
| 1832 | chip->dt.vbatt_empty_mv = 12750; |
| 1833 | |
| 1834 | reg = chip->dt.vbatt_empty_mv / 50; |
| 1835 | rc = qg_write(chip, chip->qg_base + QG_VBAT_EMPTY_THRESHOLD_REG, |
| 1836 | ®, 1); |
| 1837 | if (rc < 0) { |
| 1838 | pr_err("Failed to write vbat-empty, rc=%d\n", rc); |
| 1839 | return rc; |
| 1840 | } |
| 1841 | |
| 1842 | return 0; |
| 1843 | } |
| 1844 | |
| 1845 | static int qg_post_init(struct qpnp_qg *chip) |
| 1846 | { |
| 1847 | /* disable all IRQs if profile is not loaded */ |
| 1848 | if (!chip->profile_loaded) { |
| 1849 | vote(chip->vbatt_irq_disable_votable, |
| 1850 | PROFILE_IRQ_DISABLE, true, 0); |
| 1851 | vote(chip->fifo_irq_disable_votable, |
| 1852 | PROFILE_IRQ_DISABLE, true, 0); |
| 1853 | vote(chip->good_ocv_irq_disable_votable, |
| 1854 | PROFILE_IRQ_DISABLE, true, 0); |
| 1855 | } else { |
| 1856 | /* disable GOOD_OCV IRQ at init */ |
| 1857 | vote(chip->good_ocv_irq_disable_votable, |
| 1858 | QG_INIT_STATE_IRQ_DISABLE, true, 0); |
| 1859 | } |
| 1860 | |
| 1861 | return 0; |
| 1862 | } |
| 1863 | |
| 1864 | static int qg_get_irq_index_byname(const char *irq_name) |
| 1865 | { |
| 1866 | int i; |
| 1867 | |
| 1868 | for (i = 0; i < ARRAY_SIZE(qg_irqs); i++) { |
| 1869 | if (strcmp(qg_irqs[i].name, irq_name) == 0) |
| 1870 | return i; |
| 1871 | } |
| 1872 | |
| 1873 | return -ENOENT; |
| 1874 | } |
| 1875 | |
| 1876 | static int qg_request_interrupt(struct qpnp_qg *chip, |
| 1877 | struct device_node *node, const char *irq_name) |
| 1878 | { |
| 1879 | int rc, irq, irq_index; |
| 1880 | |
| 1881 | irq = of_irq_get_byname(node, irq_name); |
| 1882 | if (irq < 0) { |
| 1883 | pr_err("Failed to get irq %s byname\n", irq_name); |
| 1884 | return irq; |
| 1885 | } |
| 1886 | |
| 1887 | irq_index = qg_get_irq_index_byname(irq_name); |
| 1888 | if (irq_index < 0) { |
| 1889 | pr_err("%s is not a defined irq\n", irq_name); |
| 1890 | return irq_index; |
| 1891 | } |
| 1892 | |
| 1893 | if (!qg_irqs[irq_index].handler) |
| 1894 | return 0; |
| 1895 | |
| 1896 | rc = devm_request_threaded_irq(chip->dev, irq, NULL, |
| 1897 | qg_irqs[irq_index].handler, |
| 1898 | IRQF_ONESHOT, irq_name, chip); |
| 1899 | if (rc < 0) { |
| 1900 | pr_err("Failed to request irq %d\n", irq); |
| 1901 | return rc; |
| 1902 | } |
| 1903 | |
| 1904 | qg_irqs[irq_index].irq = irq; |
| 1905 | if (qg_irqs[irq_index].wake) |
| 1906 | enable_irq_wake(irq); |
| 1907 | |
| 1908 | qg_dbg(chip, QG_DEBUG_PON, "IRQ %s registered wakeable=%d\n", |
| 1909 | qg_irqs[irq_index].name, qg_irqs[irq_index].wake); |
| 1910 | |
| 1911 | return 0; |
| 1912 | } |
| 1913 | |
| 1914 | static int qg_request_irqs(struct qpnp_qg *chip) |
| 1915 | { |
| 1916 | struct device_node *node = chip->dev->of_node; |
| 1917 | struct device_node *child; |
| 1918 | const char *name; |
| 1919 | struct property *prop; |
| 1920 | int rc = 0; |
| 1921 | |
| 1922 | for_each_available_child_of_node(node, child) { |
| 1923 | of_property_for_each_string(child, "interrupt-names", |
| 1924 | prop, name) { |
| 1925 | rc = qg_request_interrupt(chip, child, name); |
| 1926 | if (rc < 0) |
| 1927 | return rc; |
| 1928 | } |
| 1929 | } |
| 1930 | |
| 1931 | |
| 1932 | return 0; |
| 1933 | } |
| 1934 | |
| 1935 | #define DEFAULT_VBATT_EMPTY_MV 3200 |
| 1936 | #define DEFAULT_VBATT_CUTOFF_MV 3400 |
| 1937 | #define DEFAULT_VBATT_LOW_MV 3500 |
| 1938 | #define DEFAULT_ITERM_MA 100 |
| 1939 | #define DEFAULT_S2_FIFO_LENGTH 5 |
| 1940 | #define DEFAULT_S2_VBAT_LOW_LENGTH 2 |
| 1941 | #define DEFAULT_S2_ACC_LENGTH 128 |
| 1942 | #define DEFAULT_S2_ACC_INTVL_MS 100 |
| 1943 | #define DEFAULT_DELTA_SOC 1 |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 1944 | #define DEFAULT_SHUTDOWN_SOC_SECS 360 |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1945 | static int qg_parse_dt(struct qpnp_qg *chip) |
| 1946 | { |
| 1947 | int rc = 0; |
| 1948 | struct device_node *revid_node, *child, *node = chip->dev->of_node; |
| 1949 | u32 base, temp; |
| 1950 | u8 type; |
| 1951 | |
| 1952 | if (!node) { |
| 1953 | pr_err("Failed to find device-tree node\n"); |
| 1954 | return -ENXIO; |
| 1955 | } |
| 1956 | |
| 1957 | revid_node = of_parse_phandle(node, "qcom,pmic-revid", 0); |
| 1958 | if (!revid_node) { |
| 1959 | pr_err("Missing qcom,pmic-revid property - driver failed\n"); |
| 1960 | return -EINVAL; |
| 1961 | } |
| 1962 | |
| 1963 | chip->pmic_rev_id = get_revid_data(revid_node); |
| 1964 | of_node_put(revid_node); |
| 1965 | if (IS_ERR_OR_NULL(chip->pmic_rev_id)) { |
| 1966 | pr_err("Failed to get pmic_revid, rc=%ld\n", |
| 1967 | PTR_ERR(chip->pmic_rev_id)); |
| 1968 | /* |
| 1969 | * the revid peripheral must be registered, any failure |
| 1970 | * here only indicates that the rev-id module has not |
| 1971 | * probed yet. |
| 1972 | */ |
| 1973 | return -EPROBE_DEFER; |
| 1974 | } |
| 1975 | |
| 1976 | qg_dbg(chip, QG_DEBUG_PON, "PMIC subtype %d Digital major %d\n", |
| 1977 | chip->pmic_rev_id->pmic_subtype, chip->pmic_rev_id->rev4); |
| 1978 | |
| 1979 | for_each_available_child_of_node(node, child) { |
| 1980 | rc = of_property_read_u32(child, "reg", &base); |
| 1981 | if (rc < 0) { |
| 1982 | pr_err("Failed to read base address, rc=%d\n", rc); |
| 1983 | return rc; |
| 1984 | } |
| 1985 | |
| 1986 | rc = qg_read(chip, base + PERPH_TYPE_REG, &type, 1); |
| 1987 | if (rc < 0) { |
| 1988 | pr_err("Failed to read type, rc=%d\n", rc); |
| 1989 | return rc; |
| 1990 | } |
| 1991 | |
| 1992 | switch (type) { |
| 1993 | case QG_TYPE: |
| 1994 | chip->qg_base = base; |
| 1995 | break; |
| 1996 | default: |
| 1997 | break; |
| 1998 | } |
| 1999 | } |
| 2000 | |
| 2001 | if (!chip->qg_base) { |
| 2002 | pr_err("QG device node missing\n"); |
| 2003 | return -EINVAL; |
| 2004 | } |
| 2005 | |
| 2006 | /* S2 state params */ |
| 2007 | rc = of_property_read_u32(node, "qcom,s2-fifo-length", &temp); |
| 2008 | if (rc < 0) |
| 2009 | chip->dt.s2_fifo_length = DEFAULT_S2_FIFO_LENGTH; |
| 2010 | else |
| 2011 | chip->dt.s2_fifo_length = temp; |
| 2012 | |
| 2013 | rc = of_property_read_u32(node, "qcom,s2-vbat-low-fifo-length", &temp); |
| 2014 | if (rc < 0) |
| 2015 | chip->dt.s2_vbat_low_fifo_length = DEFAULT_S2_VBAT_LOW_LENGTH; |
| 2016 | else |
| 2017 | chip->dt.s2_vbat_low_fifo_length = temp; |
| 2018 | |
| 2019 | rc = of_property_read_u32(node, "qcom,s2-acc-length", &temp); |
| 2020 | if (rc < 0) |
| 2021 | chip->dt.s2_acc_length = DEFAULT_S2_ACC_LENGTH; |
| 2022 | else |
| 2023 | chip->dt.s2_acc_length = temp; |
| 2024 | |
| 2025 | rc = of_property_read_u32(node, "qcom,s2-acc-interval-ms", &temp); |
| 2026 | if (rc < 0) |
| 2027 | chip->dt.s2_acc_intvl_ms = DEFAULT_S2_ACC_INTVL_MS; |
| 2028 | else |
| 2029 | chip->dt.s2_acc_intvl_ms = temp; |
| 2030 | |
| 2031 | qg_dbg(chip, QG_DEBUG_PON, "DT: S2 FIFO length=%d low_vbat_length=%d acc_length=%d acc_interval=%d\n", |
| 2032 | chip->dt.s2_fifo_length, chip->dt.s2_vbat_low_fifo_length, |
| 2033 | chip->dt.s2_acc_length, chip->dt.s2_acc_intvl_ms); |
| 2034 | |
| 2035 | /* OCV params */ |
| 2036 | rc = of_property_read_u32(node, "qcom,ocv-timer-expiry-min", &temp); |
| 2037 | if (rc < 0) |
| 2038 | chip->dt.ocv_timer_expiry_min = -EINVAL; |
| 2039 | else |
| 2040 | chip->dt.ocv_timer_expiry_min = temp; |
| 2041 | |
| 2042 | rc = of_property_read_u32(node, "qcom,ocv-tol-threshold-uv", &temp); |
| 2043 | if (rc < 0) |
| 2044 | chip->dt.ocv_tol_threshold_uv = -EINVAL; |
| 2045 | else |
| 2046 | chip->dt.ocv_tol_threshold_uv = temp; |
| 2047 | |
| 2048 | qg_dbg(chip, QG_DEBUG_PON, "DT: OCV timer_expiry =%dmin ocv_tol_threshold=%duV\n", |
| 2049 | chip->dt.ocv_timer_expiry_min, chip->dt.ocv_tol_threshold_uv); |
| 2050 | |
| 2051 | /* S3 sleep configuration */ |
| 2052 | rc = of_property_read_u32(node, "qcom,s3-entry-fifo-length", &temp); |
| 2053 | if (rc < 0) |
| 2054 | chip->dt.s3_entry_fifo_length = -EINVAL; |
| 2055 | else |
| 2056 | chip->dt.s3_entry_fifo_length = temp; |
| 2057 | |
| 2058 | rc = of_property_read_u32(node, "qcom,s3-entry-ibat-ua", &temp); |
| 2059 | if (rc < 0) |
| 2060 | chip->dt.s3_entry_ibat_ua = -EINVAL; |
| 2061 | else |
| 2062 | chip->dt.s3_entry_ibat_ua = temp; |
| 2063 | |
| 2064 | rc = of_property_read_u32(node, "qcom,s3-entry-ibat-ua", &temp); |
| 2065 | if (rc < 0) |
| 2066 | chip->dt.s3_exit_ibat_ua = -EINVAL; |
| 2067 | else |
| 2068 | chip->dt.s3_exit_ibat_ua = temp; |
| 2069 | |
| 2070 | /* VBAT thresholds */ |
| 2071 | rc = of_property_read_u32(node, "qcom,vbatt-empty-mv", &temp); |
| 2072 | if (rc < 0) |
| 2073 | chip->dt.vbatt_empty_mv = DEFAULT_VBATT_EMPTY_MV; |
| 2074 | else |
| 2075 | chip->dt.vbatt_empty_mv = temp; |
| 2076 | |
| 2077 | rc = of_property_read_u32(node, "qcom,vbatt-low-mv", &temp); |
| 2078 | if (rc < 0) |
| 2079 | chip->dt.vbatt_low_mv = DEFAULT_VBATT_LOW_MV; |
| 2080 | else |
| 2081 | chip->dt.vbatt_low_mv = temp; |
| 2082 | |
| 2083 | rc = of_property_read_u32(node, "qcom,vbatt-cutoff-mv", &temp); |
| 2084 | if (rc < 0) |
| 2085 | chip->dt.vbatt_cutoff_mv = DEFAULT_VBATT_CUTOFF_MV; |
| 2086 | else |
| 2087 | chip->dt.vbatt_cutoff_mv = temp; |
| 2088 | |
| 2089 | /* IBAT thresholds */ |
| 2090 | rc = of_property_read_u32(node, "qcom,qg-iterm-ma", &temp); |
| 2091 | if (rc < 0) |
| 2092 | chip->dt.iterm_ma = DEFAULT_ITERM_MA; |
| 2093 | else |
| 2094 | chip->dt.iterm_ma = temp; |
| 2095 | |
| 2096 | rc = of_property_read_u32(node, "qcom,delta-soc", &temp); |
| 2097 | if (rc < 0) |
| 2098 | chip->dt.delta_soc = DEFAULT_DELTA_SOC; |
| 2099 | else |
| 2100 | chip->dt.delta_soc = temp; |
| 2101 | |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 2102 | rc = of_property_read_u32(node, "qcom,ignore-shutdown-soc-secs", &temp); |
| 2103 | if (rc < 0) |
| 2104 | chip->dt.ignore_shutdown_soc_secs = DEFAULT_SHUTDOWN_SOC_SECS; |
| 2105 | else |
| 2106 | chip->dt.ignore_shutdown_soc_secs = temp; |
| 2107 | |
Vamshi Krishna B V | 2585580 | 2018-02-21 15:26:30 +0530 | [diff] [blame] | 2108 | chip->dt.hold_soc_while_full = of_property_read_bool(node, |
| 2109 | "qcom,hold-soc-while-full"); |
| 2110 | |
Vamshi Krishna B V | 2b61cf6 | 2018-03-13 13:54:33 +0530 | [diff] [blame^] | 2111 | chip->dt.linearize_soc = of_property_read_bool(node, |
| 2112 | "qcom,linearize-soc"); |
| 2113 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 2114 | rc = of_property_read_u32(node, "qcom,rbat-conn-mohm", &temp); |
| 2115 | if (rc < 0) |
| 2116 | chip->dt.rbat_conn_mohm = 0; |
| 2117 | else |
| 2118 | chip->dt.rbat_conn_mohm = temp; |
| 2119 | |
| 2120 | qg_dbg(chip, QG_DEBUG_PON, "DT: vbatt_empty_mv=%dmV vbatt_low_mv=%dmV delta_soc=%d\n", |
| 2121 | chip->dt.vbatt_empty_mv, chip->dt.vbatt_low_mv, |
| 2122 | chip->dt.delta_soc); |
| 2123 | |
| 2124 | return 0; |
| 2125 | } |
| 2126 | |
| 2127 | static int process_suspend(struct qpnp_qg *chip) |
| 2128 | { |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 2129 | u8 status = 0; |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 2130 | int rc; |
| 2131 | u32 fifo_rt_length = 0, sleep_fifo_length = 0; |
| 2132 | |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 2133 | /* skip if profile is not loaded */ |
| 2134 | if (!chip->profile_loaded) |
| 2135 | return 0; |
| 2136 | |
Anirudh Ghayal | c609639 | 2018-03-07 19:57:05 +0530 | [diff] [blame] | 2137 | chip->suspend_data = false; |
| 2138 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 2139 | /* ignore any suspend processing if we are charging */ |
| 2140 | if (chip->charge_status == POWER_SUPPLY_STATUS_CHARGING) { |
| 2141 | qg_dbg(chip, QG_DEBUG_PM, "Charging @ suspend - ignore processing\n"); |
| 2142 | return 0; |
| 2143 | } |
| 2144 | |
| 2145 | rc = get_fifo_length(chip, &fifo_rt_length, true); |
| 2146 | if (rc < 0) { |
| 2147 | pr_err("Failed to read FIFO RT count, rc=%d\n", rc); |
| 2148 | return rc; |
| 2149 | } |
| 2150 | |
| 2151 | rc = qg_read(chip, chip->qg_base + QG_S3_SLEEP_OCV_IBAT_CTL1_REG, |
| 2152 | (u8 *)&sleep_fifo_length, 1); |
| 2153 | if (rc < 0) { |
| 2154 | pr_err("Failed to read sleep FIFO count, rc=%d\n", rc); |
| 2155 | return rc; |
| 2156 | } |
| 2157 | sleep_fifo_length &= SLEEP_IBAT_QUALIFIED_LENGTH_MASK; |
| 2158 | /* |
| 2159 | * If the real-time FIFO count is greater than |
| 2160 | * the the #fifo to enter sleep, save the FIFO data |
| 2161 | * and reset the fifo count. |
| 2162 | */ |
| 2163 | if (fifo_rt_length >= (chip->dt.s2_fifo_length - sleep_fifo_length)) { |
| 2164 | rc = qg_master_hold(chip, true); |
| 2165 | if (rc < 0) { |
| 2166 | pr_err("Failed to hold master, rc=%d\n", rc); |
| 2167 | return rc; |
| 2168 | } |
| 2169 | |
| 2170 | rc = qg_process_rt_fifo(chip); |
| 2171 | if (rc < 0) { |
| 2172 | pr_err("Failed to process FIFO real-time, rc=%d\n", rc); |
| 2173 | qg_master_hold(chip, false); |
| 2174 | return rc; |
| 2175 | } |
| 2176 | |
| 2177 | rc = qg_master_hold(chip, false); |
| 2178 | if (rc < 0) { |
| 2179 | pr_err("Failed to release master, rc=%d\n", rc); |
| 2180 | return rc; |
| 2181 | } |
| 2182 | /* FIFOs restarted */ |
| 2183 | chip->last_fifo_update_time = ktime_get(); |
| 2184 | |
| 2185 | chip->suspend_data = true; |
| 2186 | } |
| 2187 | |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 2188 | /* read STATUS2 register to clear its last state */ |
| 2189 | qg_read(chip, chip->qg_base + QG_STATUS2_REG, &status, 1); |
| 2190 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 2191 | qg_dbg(chip, QG_DEBUG_PM, "FIFO rt_length=%d sleep_fifo_length=%d default_s2_count=%d suspend_data=%d\n", |
| 2192 | fifo_rt_length, sleep_fifo_length, |
| 2193 | chip->dt.s2_fifo_length, chip->suspend_data); |
| 2194 | |
| 2195 | return rc; |
| 2196 | } |
| 2197 | |
| 2198 | static int process_resume(struct qpnp_qg *chip) |
| 2199 | { |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 2200 | u8 status2 = 0, rt_status = 0; |
Anirudh Ghayal | c609639 | 2018-03-07 19:57:05 +0530 | [diff] [blame] | 2201 | u32 ocv_uv = 0; |
| 2202 | int rc, batt_temp = 0; |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 2203 | |
Anirudh Ghayal | e492338 | 2018-03-11 20:32:10 +0530 | [diff] [blame] | 2204 | /* skip if profile is not loaded */ |
| 2205 | if (!chip->profile_loaded) |
| 2206 | return 0; |
| 2207 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 2208 | rc = qg_read(chip, chip->qg_base + QG_STATUS2_REG, &status2, 1); |
| 2209 | if (rc < 0) { |
| 2210 | pr_err("Failed to read status2 register, rc=%d\n", rc); |
| 2211 | return rc; |
| 2212 | } |
| 2213 | |
| 2214 | if (status2 & GOOD_OCV_BIT) { |
| 2215 | rc = qg_read_ocv(chip, &ocv_uv, GOOD_OCV); |
| 2216 | if (rc < 0) { |
| 2217 | pr_err("Failed to read good_ocv, rc=%d\n", rc); |
| 2218 | return rc; |
| 2219 | } |
| 2220 | rc = qg_get_battery_temp(chip, &batt_temp); |
| 2221 | if (rc < 0) { |
| 2222 | pr_err("Failed to read BATT_TEMP, rc=%d\n", rc); |
| 2223 | return rc; |
| 2224 | } |
| 2225 | |
| 2226 | chip->kdata.param[QG_GOOD_OCV_UV].data = ocv_uv; |
| 2227 | chip->kdata.param[QG_GOOD_OCV_UV].valid = true; |
Anirudh Ghayal | c609639 | 2018-03-07 19:57:05 +0530 | [diff] [blame] | 2228 | /* Clear suspend data as there has been a GOOD OCV */ |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 2229 | chip->suspend_data = false; |
Anirudh Ghayal | c609639 | 2018-03-07 19:57:05 +0530 | [diff] [blame] | 2230 | qg_dbg(chip, QG_DEBUG_PM, "GOOD OCV @ resume good_ocv=%d uV\n", |
| 2231 | ocv_uv); |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 2232 | } |
Anirudh Ghayal | c609639 | 2018-03-07 19:57:05 +0530 | [diff] [blame] | 2233 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 2234 | rc = qg_read(chip, chip->qg_base + QG_INT_LATCHED_STS_REG, |
| 2235 | &rt_status, 1); |
| 2236 | if (rc < 0) { |
| 2237 | pr_err("Failed to read latched status register, rc=%d\n", rc); |
| 2238 | return rc; |
| 2239 | } |
| 2240 | rt_status &= FIFO_UPDATE_DONE_INT_LAT_STS_BIT; |
| 2241 | |
Anirudh Ghayal | c609639 | 2018-03-07 19:57:05 +0530 | [diff] [blame] | 2242 | qg_dbg(chip, QG_DEBUG_PM, "FIFO_DONE_STS=%d suspend_data=%d good_ocv=%d\n", |
| 2243 | !!rt_status, chip->suspend_data, |
| 2244 | chip->kdata.param[QG_GOOD_OCV_UV].valid); |
| 2245 | /* |
| 2246 | * If this is not a wakeup from FIFO-done, |
| 2247 | * process the data immediately if - we have data from |
| 2248 | * suspend or there is a good OCV. |
| 2249 | */ |
| 2250 | if (!rt_status && (chip->suspend_data || |
| 2251 | chip->kdata.param[QG_GOOD_OCV_UV].valid)) { |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 2252 | vote(chip->awake_votable, SUSPEND_DATA_VOTER, true, 0); |
| 2253 | /* signal the read thread */ |
| 2254 | chip->data_ready = true; |
| 2255 | wake_up_interruptible(&chip->qg_wait_q); |
Anirudh Ghayal | c609639 | 2018-03-07 19:57:05 +0530 | [diff] [blame] | 2256 | chip->suspend_data = false; |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 2257 | } |
| 2258 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 2259 | return rc; |
| 2260 | } |
| 2261 | |
| 2262 | static int qpnp_qg_suspend_noirq(struct device *dev) |
| 2263 | { |
| 2264 | int rc; |
| 2265 | struct qpnp_qg *chip = dev_get_drvdata(dev); |
| 2266 | |
| 2267 | mutex_lock(&chip->data_lock); |
| 2268 | |
| 2269 | rc = process_suspend(chip); |
| 2270 | if (rc < 0) |
| 2271 | pr_err("Failed to process QG suspend, rc=%d\n", rc); |
| 2272 | |
| 2273 | mutex_unlock(&chip->data_lock); |
| 2274 | |
| 2275 | return 0; |
| 2276 | } |
| 2277 | |
| 2278 | static int qpnp_qg_resume_noirq(struct device *dev) |
| 2279 | { |
| 2280 | int rc; |
| 2281 | struct qpnp_qg *chip = dev_get_drvdata(dev); |
| 2282 | |
| 2283 | mutex_lock(&chip->data_lock); |
| 2284 | |
| 2285 | rc = process_resume(chip); |
| 2286 | if (rc < 0) |
| 2287 | pr_err("Failed to process QG resume, rc=%d\n", rc); |
| 2288 | |
| 2289 | mutex_unlock(&chip->data_lock); |
| 2290 | |
| 2291 | return 0; |
| 2292 | } |
| 2293 | |
| 2294 | static const struct dev_pm_ops qpnp_qg_pm_ops = { |
| 2295 | .suspend_noirq = qpnp_qg_suspend_noirq, |
| 2296 | .resume_noirq = qpnp_qg_resume_noirq, |
| 2297 | }; |
| 2298 | |
| 2299 | static int qpnp_qg_probe(struct platform_device *pdev) |
| 2300 | { |
| 2301 | int rc = 0, soc = 0; |
| 2302 | struct qpnp_qg *chip; |
| 2303 | |
| 2304 | chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); |
| 2305 | if (!chip) |
| 2306 | return -ENOMEM; |
| 2307 | |
| 2308 | chip->regmap = dev_get_regmap(pdev->dev.parent, NULL); |
| 2309 | if (!chip->regmap) { |
| 2310 | pr_err("Parent regmap is unavailable\n"); |
| 2311 | return -ENXIO; |
| 2312 | } |
| 2313 | |
| 2314 | /* VADC for BID */ |
| 2315 | chip->vadc_dev = qpnp_get_vadc(&pdev->dev, "qg"); |
| 2316 | if (IS_ERR(chip->vadc_dev)) { |
| 2317 | rc = PTR_ERR(chip->vadc_dev); |
| 2318 | if (rc != -EPROBE_DEFER) |
| 2319 | pr_err("Failed to find VADC node, rc=%d\n", rc); |
| 2320 | |
| 2321 | return rc; |
| 2322 | } |
| 2323 | |
| 2324 | chip->dev = &pdev->dev; |
| 2325 | chip->debug_mask = &qg_debug_mask; |
| 2326 | platform_set_drvdata(pdev, chip); |
| 2327 | INIT_WORK(&chip->udata_work, process_udata_work); |
| 2328 | INIT_WORK(&chip->qg_status_change_work, qg_status_change_work); |
| 2329 | mutex_init(&chip->bus_lock); |
| 2330 | mutex_init(&chip->soc_lock); |
| 2331 | mutex_init(&chip->data_lock); |
| 2332 | init_waitqueue_head(&chip->qg_wait_q); |
Vamshi Krishna B V | 2b61cf6 | 2018-03-13 13:54:33 +0530 | [diff] [blame^] | 2333 | chip->maint_soc = -EINVAL; |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 2334 | |
| 2335 | rc = qg_parse_dt(chip); |
| 2336 | if (rc < 0) { |
| 2337 | pr_err("Failed to parse DT, rc=%d\n", rc); |
| 2338 | return rc; |
| 2339 | } |
| 2340 | |
| 2341 | rc = qg_hw_init(chip); |
| 2342 | if (rc < 0) { |
| 2343 | pr_err("Failed to hw_init, rc=%d\n", rc); |
| 2344 | return rc; |
| 2345 | } |
| 2346 | |
| 2347 | rc = qg_setup_battery(chip); |
| 2348 | if (rc < 0) { |
| 2349 | pr_err("Failed to setup battery, rc=%d\n", rc); |
| 2350 | return rc; |
| 2351 | } |
| 2352 | |
| 2353 | rc = qg_register_device(chip); |
| 2354 | if (rc < 0) { |
| 2355 | pr_err("Failed to register QG char device, rc=%d\n", rc); |
| 2356 | return rc; |
| 2357 | } |
| 2358 | |
| 2359 | rc = qg_sdam_init(chip->dev); |
| 2360 | if (rc < 0) { |
| 2361 | pr_err("Failed to initialize QG SDAM, rc=%d\n", rc); |
| 2362 | return rc; |
| 2363 | } |
| 2364 | |
| 2365 | rc = qg_soc_init(chip); |
| 2366 | if (rc < 0) { |
| 2367 | pr_err("Failed to initialize SOC scaling init rc=%d\n", rc); |
| 2368 | return rc; |
| 2369 | } |
| 2370 | |
| 2371 | rc = qg_determine_pon_soc(chip); |
| 2372 | if (rc < 0) { |
| 2373 | pr_err("Failed to determine initial state, rc=%d\n", rc); |
| 2374 | goto fail_device; |
| 2375 | } |
| 2376 | |
| 2377 | chip->awake_votable = create_votable("QG_WS", VOTE_SET_ANY, |
| 2378 | qg_awake_cb, chip); |
| 2379 | if (IS_ERR(chip->awake_votable)) { |
| 2380 | rc = PTR_ERR(chip->awake_votable); |
| 2381 | chip->awake_votable = NULL; |
| 2382 | goto fail_device; |
| 2383 | } |
| 2384 | |
| 2385 | chip->vbatt_irq_disable_votable = create_votable("QG_VBATT_IRQ_DISABLE", |
| 2386 | VOTE_SET_ANY, qg_vbatt_irq_disable_cb, chip); |
| 2387 | if (IS_ERR(chip->vbatt_irq_disable_votable)) { |
| 2388 | rc = PTR_ERR(chip->vbatt_irq_disable_votable); |
| 2389 | chip->vbatt_irq_disable_votable = NULL; |
| 2390 | goto fail_device; |
| 2391 | } |
| 2392 | |
| 2393 | chip->fifo_irq_disable_votable = create_votable("QG_FIFO_IRQ_DISABLE", |
| 2394 | VOTE_SET_ANY, qg_fifo_irq_disable_cb, chip); |
| 2395 | if (IS_ERR(chip->fifo_irq_disable_votable)) { |
| 2396 | rc = PTR_ERR(chip->fifo_irq_disable_votable); |
| 2397 | chip->fifo_irq_disable_votable = NULL; |
| 2398 | goto fail_device; |
| 2399 | } |
| 2400 | |
| 2401 | chip->good_ocv_irq_disable_votable = |
| 2402 | create_votable("QG_GOOD_IRQ_DISABLE", |
| 2403 | VOTE_SET_ANY, qg_good_ocv_irq_disable_cb, chip); |
| 2404 | if (IS_ERR(chip->good_ocv_irq_disable_votable)) { |
| 2405 | rc = PTR_ERR(chip->good_ocv_irq_disable_votable); |
| 2406 | chip->good_ocv_irq_disable_votable = NULL; |
| 2407 | goto fail_device; |
| 2408 | } |
| 2409 | |
| 2410 | rc = qg_init_psy(chip); |
| 2411 | if (rc < 0) { |
| 2412 | pr_err("Failed to initialize QG psy, rc=%d\n", rc); |
| 2413 | goto fail_votable; |
| 2414 | } |
| 2415 | |
| 2416 | rc = qg_request_irqs(chip); |
| 2417 | if (rc < 0) { |
| 2418 | pr_err("Failed to register QG interrupts, rc=%d\n", rc); |
| 2419 | goto fail_votable; |
| 2420 | } |
| 2421 | |
| 2422 | rc = qg_post_init(chip); |
| 2423 | if (rc < 0) { |
| 2424 | pr_err("Failed in qg_post_init rc=%d\n", rc); |
| 2425 | goto fail_votable; |
| 2426 | } |
| 2427 | |
| 2428 | qg_get_battery_capacity(chip, &soc); |
| 2429 | pr_info("QG initialized! battery_profile=%s SOC=%d\n", |
| 2430 | qg_get_battery_type(chip), soc); |
| 2431 | |
| 2432 | return rc; |
| 2433 | |
| 2434 | fail_votable: |
| 2435 | destroy_votable(chip->awake_votable); |
| 2436 | fail_device: |
| 2437 | device_destroy(chip->qg_class, chip->dev_no); |
| 2438 | cdev_del(&chip->qg_cdev); |
| 2439 | unregister_chrdev_region(chip->dev_no, 1); |
| 2440 | return rc; |
| 2441 | } |
| 2442 | |
| 2443 | static int qpnp_qg_remove(struct platform_device *pdev) |
| 2444 | { |
| 2445 | struct qpnp_qg *chip = platform_get_drvdata(pdev); |
| 2446 | |
| 2447 | qg_batterydata_exit(); |
| 2448 | qg_soc_exit(chip); |
| 2449 | |
| 2450 | cancel_work_sync(&chip->udata_work); |
| 2451 | cancel_work_sync(&chip->qg_status_change_work); |
| 2452 | device_destroy(chip->qg_class, chip->dev_no); |
| 2453 | cdev_del(&chip->qg_cdev); |
| 2454 | unregister_chrdev_region(chip->dev_no, 1); |
| 2455 | mutex_destroy(&chip->bus_lock); |
| 2456 | mutex_destroy(&chip->data_lock); |
| 2457 | mutex_destroy(&chip->soc_lock); |
| 2458 | if (chip->awake_votable) |
| 2459 | destroy_votable(chip->awake_votable); |
| 2460 | |
| 2461 | return 0; |
| 2462 | } |
| 2463 | |
| 2464 | static const struct of_device_id match_table[] = { |
| 2465 | { .compatible = "qcom,qpnp-qg", }, |
| 2466 | { }, |
| 2467 | }; |
| 2468 | |
| 2469 | static struct platform_driver qpnp_qg_driver = { |
| 2470 | .driver = { |
| 2471 | .name = "qcom,qpnp-qg", |
| 2472 | .owner = THIS_MODULE, |
| 2473 | .of_match_table = match_table, |
| 2474 | .pm = &qpnp_qg_pm_ops, |
| 2475 | }, |
| 2476 | .probe = qpnp_qg_probe, |
| 2477 | .remove = qpnp_qg_remove, |
| 2478 | }; |
| 2479 | module_platform_driver(qpnp_qg_driver); |
| 2480 | |
| 2481 | MODULE_DESCRIPTION("QPNP QG Driver"); |
| 2482 | MODULE_LICENSE("GPL v2"); |