Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2015, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/delay.h> |
| 14 | #include <linux/highmem.h> |
| 15 | #include <linux/io.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/dma-mapping.h> |
| 18 | #include <linux/slab.h> |
| 19 | #include <linux/scatterlist.h> |
| 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/blkdev.h> |
| 22 | |
| 23 | #include <linux/mmc/mmc.h> |
| 24 | #include <linux/mmc/host.h> |
| 25 | #include <linux/mmc/card.h> |
Konstantin Dorfman | 4d40cf2 | 2015-06-11 11:41:53 +0300 | [diff] [blame] | 26 | #include <linux/pm_runtime.h> |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 27 | |
| 28 | #include "cmdq_hci.h" |
| 29 | |
| 30 | #define DCMD_SLOT 31 |
| 31 | #define NUM_SLOTS 32 |
| 32 | |
Asutosh Das | aa1e1c7 | 2015-05-21 17:22:10 +0530 | [diff] [blame] | 33 | /* 1 sec */ |
| 34 | #define HALT_TIMEOUT_MS 1000 |
| 35 | |
Konstantin Dorfman | 4d40cf2 | 2015-06-11 11:41:53 +0300 | [diff] [blame] | 36 | #ifdef CONFIG_PM_RUNTIME |
| 37 | static int cmdq_runtime_pm_get(struct cmdq_host *host) |
| 38 | { |
| 39 | return pm_runtime_get_sync(host->mmc->parent); |
| 40 | } |
| 41 | static int cmdq_runtime_pm_put(struct cmdq_host *host) |
| 42 | { |
| 43 | pm_runtime_mark_last_busy(host->mmc->parent); |
| 44 | return pm_runtime_put_autosuspend(host->mmc->parent); |
| 45 | } |
| 46 | #else |
| 47 | static inline int cmdq_runtime_pm_get(struct cmdq_host *host) |
| 48 | { |
| 49 | return 0; |
| 50 | } |
| 51 | static inline int cmdq_runtime_pm_put(struct cmdq_host *host) |
| 52 | { |
| 53 | return 0; |
| 54 | } |
| 55 | #endif |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 56 | static inline struct mmc_request *get_req_by_tag(struct cmdq_host *cq_host, |
| 57 | unsigned int tag) |
| 58 | { |
| 59 | return cq_host->mrq_slot[tag]; |
| 60 | } |
| 61 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 62 | static inline u8 *get_desc(struct cmdq_host *cq_host, u8 tag) |
| 63 | { |
| 64 | return cq_host->desc_base + (tag * cq_host->slot_sz); |
| 65 | } |
| 66 | |
| 67 | static inline u8 *get_link_desc(struct cmdq_host *cq_host, u8 tag) |
| 68 | { |
| 69 | u8 *desc = get_desc(cq_host, tag); |
| 70 | |
| 71 | return desc + cq_host->task_desc_len; |
| 72 | } |
| 73 | |
| 74 | static inline dma_addr_t get_trans_desc_dma(struct cmdq_host *cq_host, u8 tag) |
| 75 | { |
| 76 | return cq_host->trans_desc_dma_base + |
| 77 | (cq_host->mmc->max_segs * tag * |
| 78 | cq_host->trans_desc_len); |
| 79 | } |
| 80 | |
| 81 | static inline u8 *get_trans_desc(struct cmdq_host *cq_host, u8 tag) |
| 82 | { |
| 83 | return cq_host->trans_desc_base + |
| 84 | (cq_host->trans_desc_len * cq_host->mmc->max_segs * tag); |
| 85 | } |
| 86 | |
| 87 | static void setup_trans_desc(struct cmdq_host *cq_host, u8 tag) |
| 88 | { |
| 89 | u8 *link_temp; |
| 90 | dma_addr_t trans_temp; |
| 91 | |
| 92 | link_temp = get_link_desc(cq_host, tag); |
| 93 | trans_temp = get_trans_desc_dma(cq_host, tag); |
| 94 | |
| 95 | memset(link_temp, 0, cq_host->link_desc_len); |
| 96 | if (cq_host->link_desc_len > 8) |
| 97 | *(link_temp + 8) = 0; |
| 98 | |
| 99 | if (tag == DCMD_SLOT) { |
| 100 | *link_temp = VALID(0) | ACT(0) | END(1); |
| 101 | return; |
| 102 | } |
| 103 | |
| 104 | *link_temp = VALID(1) | ACT(0x6) | END(0); |
| 105 | |
| 106 | if (cq_host->dma64) { |
| 107 | __le64 *data_addr = (__le64 __force *)(link_temp + 4); |
| 108 | data_addr[0] = cpu_to_le64(trans_temp); |
| 109 | } else { |
| 110 | __le32 *data_addr = (__le32 __force *)(link_temp + 4); |
| 111 | data_addr[0] = cpu_to_le32(trans_temp); |
| 112 | } |
| 113 | } |
| 114 | |
| 115 | static void cmdq_clear_set_irqs(struct cmdq_host *cq_host, u32 clear, u32 set) |
| 116 | { |
| 117 | u32 ier; |
| 118 | |
| 119 | ier = cmdq_readl(cq_host, CQISTE); |
| 120 | ier &= ~clear; |
| 121 | ier |= set; |
| 122 | cmdq_writel(cq_host, ier, CQISTE); |
| 123 | cmdq_writel(cq_host, ier, CQISGE); |
| 124 | /* ensure the writes are done */ |
| 125 | mb(); |
| 126 | } |
| 127 | |
| 128 | |
| 129 | #define DRV_NAME "cmdq-host" |
| 130 | |
| 131 | static void cmdq_dump_debug_ram(struct cmdq_host *cq_host) |
| 132 | { |
| 133 | int i = 0; |
| 134 | |
| 135 | pr_err("---- Debug RAM dump ----\n"); |
| 136 | pr_err(DRV_NAME ": Debug RAM wrap-around: 0x%08x | Debug RAM overlap: 0x%08x\n", |
| 137 | cmdq_readl(cq_host, CQ_CMD_DBG_RAM_WA), |
| 138 | cmdq_readl(cq_host, CQ_CMD_DBG_RAM_OL)); |
| 139 | |
| 140 | while (i < 16) { |
| 141 | pr_err(DRV_NAME ": Debug RAM dump [%d]: 0x%08x\n", i, |
| 142 | cmdq_readl(cq_host, CQ_CMD_DBG_RAM + (0x4 * i))); |
| 143 | i++; |
| 144 | } |
| 145 | pr_err("-------------------------\n"); |
| 146 | } |
| 147 | |
| 148 | static void cmdq_dumpregs(struct cmdq_host *cq_host) |
| 149 | { |
| 150 | struct mmc_host *mmc = cq_host->mmc; |
| 151 | |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 152 | pr_err(DRV_NAME ": ========== REGISTER DUMP (%s)==========\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 153 | mmc_hostname(mmc)); |
| 154 | |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 155 | pr_err(DRV_NAME ": Caps: 0x%08x | Version: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 156 | cmdq_readl(cq_host, CQCAP), |
| 157 | cmdq_readl(cq_host, CQVER)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 158 | pr_err(DRV_NAME ": Queing config: 0x%08x | Queue Ctrl: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 159 | cmdq_readl(cq_host, CQCFG), |
| 160 | cmdq_readl(cq_host, CQCTL)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 161 | pr_err(DRV_NAME ": Int stat: 0x%08x | Int enab: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 162 | cmdq_readl(cq_host, CQIS), |
| 163 | cmdq_readl(cq_host, CQISTE)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 164 | pr_err(DRV_NAME ": Int sig: 0x%08x | Int Coal: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 165 | cmdq_readl(cq_host, CQISGE), |
| 166 | cmdq_readl(cq_host, CQIC)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 167 | pr_err(DRV_NAME ": TDL base: 0x%08x | TDL up32: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 168 | cmdq_readl(cq_host, CQTDLBA), |
| 169 | cmdq_readl(cq_host, CQTDLBAU)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 170 | pr_err(DRV_NAME ": Doorbell: 0x%08x | Comp Notif: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 171 | cmdq_readl(cq_host, CQTDBR), |
| 172 | cmdq_readl(cq_host, CQTCN)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 173 | pr_err(DRV_NAME ": Dev queue: 0x%08x | Dev Pend: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 174 | cmdq_readl(cq_host, CQDQS), |
| 175 | cmdq_readl(cq_host, CQDPT)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 176 | pr_err(DRV_NAME ": Task clr: 0x%08x | Send stat 1: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 177 | cmdq_readl(cq_host, CQTCLR), |
| 178 | cmdq_readl(cq_host, CQSSC1)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 179 | pr_err(DRV_NAME ": Send stat 2: 0x%08x | DCMD resp: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 180 | cmdq_readl(cq_host, CQSSC2), |
| 181 | cmdq_readl(cq_host, CQCRDCT)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 182 | pr_err(DRV_NAME ": Resp err mask: 0x%08x | Task err: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 183 | cmdq_readl(cq_host, CQRMEM), |
| 184 | cmdq_readl(cq_host, CQTERRI)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 185 | pr_err(DRV_NAME ": Resp idx 0x%08x | Resp arg: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 186 | cmdq_readl(cq_host, CQCRI), |
| 187 | cmdq_readl(cq_host, CQCRA)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 188 | pr_err(DRV_NAME ": ===========================================\n"); |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 189 | |
| 190 | cmdq_dump_debug_ram(cq_host); |
| 191 | if (cq_host->ops->dump_vendor_regs) |
| 192 | cq_host->ops->dump_vendor_regs(mmc); |
| 193 | } |
| 194 | |
| 195 | /** |
| 196 | * The allocated descriptor table for task, link & transfer descritors |
| 197 | * looks like: |
| 198 | * |----------| |
| 199 | * |task desc | |->|----------| |
| 200 | * |----------| | |trans desc| |
| 201 | * |link desc-|->| |----------| |
| 202 | * |----------| . |
| 203 | * . . |
| 204 | * no. of slots max-segs |
| 205 | * . |----------| |
| 206 | * |----------| |
| 207 | * The idea here is to create the [task+trans] table and mark & point the |
| 208 | * link desc to the transfer desc table on a per slot basis. |
| 209 | */ |
| 210 | static int cmdq_host_alloc_tdl(struct cmdq_host *cq_host) |
| 211 | { |
| 212 | |
| 213 | size_t desc_size; |
| 214 | size_t data_size; |
| 215 | int i = 0; |
| 216 | |
| 217 | /* task descriptor can be 64/128 bit irrespective of arch */ |
| 218 | if (cq_host->caps & CMDQ_TASK_DESC_SZ_128) { |
| 219 | cmdq_writel(cq_host, cmdq_readl(cq_host, CQCFG) | |
| 220 | CQ_TASK_DESC_SZ, CQCFG); |
| 221 | cq_host->task_desc_len = 16; |
| 222 | } else { |
| 223 | cq_host->task_desc_len = 8; |
| 224 | } |
| 225 | |
| 226 | /* |
| 227 | * 96 bits length of transfer desc instead of 128 bits which means |
| 228 | * ADMA would expect next valid descriptor at the 96th bit |
| 229 | * or 128th bit |
| 230 | */ |
| 231 | if (cq_host->dma64) { |
| 232 | if (cq_host->quirks & CMDQ_QUIRK_SHORT_TXFR_DESC_SZ) |
| 233 | cq_host->trans_desc_len = 12; |
| 234 | else |
| 235 | cq_host->trans_desc_len = 16; |
| 236 | cq_host->link_desc_len = 16; |
| 237 | } else { |
| 238 | cq_host->trans_desc_len = 8; |
| 239 | cq_host->link_desc_len = 8; |
| 240 | } |
| 241 | |
| 242 | /* total size of a slot: 1 task & 1 transfer (link) */ |
| 243 | cq_host->slot_sz = cq_host->task_desc_len + cq_host->link_desc_len; |
| 244 | |
| 245 | desc_size = cq_host->slot_sz * cq_host->num_slots; |
| 246 | |
| 247 | data_size = cq_host->trans_desc_len * cq_host->mmc->max_segs * |
| 248 | (cq_host->num_slots - 1); |
| 249 | |
| 250 | pr_info("%s: desc_size: %d data_sz: %d slot-sz: %d\n", __func__, |
| 251 | (int)desc_size, (int)data_size, cq_host->slot_sz); |
| 252 | |
| 253 | /* |
| 254 | * allocate a dma-mapped chunk of memory for the descriptors |
| 255 | * allocate a dma-mapped chunk of memory for link descriptors |
| 256 | * setup each link-desc memory offset per slot-number to |
| 257 | * the descriptor table. |
| 258 | */ |
| 259 | cq_host->desc_base = dmam_alloc_coherent(mmc_dev(cq_host->mmc), |
| 260 | desc_size, |
| 261 | &cq_host->desc_dma_base, |
| 262 | GFP_KERNEL); |
| 263 | cq_host->trans_desc_base = dmam_alloc_coherent(mmc_dev(cq_host->mmc), |
| 264 | data_size, |
| 265 | &cq_host->trans_desc_dma_base, |
| 266 | GFP_KERNEL); |
| 267 | if (!cq_host->desc_base || !cq_host->trans_desc_base) |
| 268 | return -ENOMEM; |
| 269 | |
| 270 | pr_info("desc-base: 0x%p trans-base: 0x%p\n desc_dma 0x%llx trans_dma: 0x%llx\n", |
| 271 | cq_host->desc_base, cq_host->trans_desc_base, |
| 272 | (unsigned long long)cq_host->desc_dma_base, |
| 273 | (unsigned long long) cq_host->trans_desc_dma_base); |
| 274 | |
| 275 | for (; i < (cq_host->num_slots); i++) |
| 276 | setup_trans_desc(cq_host, i); |
| 277 | |
| 278 | return 0; |
| 279 | } |
| 280 | |
| 281 | static int cmdq_enable(struct mmc_host *mmc) |
| 282 | { |
| 283 | int err = 0; |
| 284 | u32 cqcfg; |
| 285 | bool dcmd_enable; |
| 286 | struct cmdq_host *cq_host = mmc_cmdq_private(mmc); |
| 287 | |
| 288 | if (!cq_host || !mmc->card || !mmc_card_cmdq(mmc->card)) { |
| 289 | err = -EINVAL; |
| 290 | goto out; |
| 291 | } |
| 292 | |
| 293 | if (cq_host->enabled) |
| 294 | goto out; |
| 295 | |
Konstantin Dorfman | 4d40cf2 | 2015-06-11 11:41:53 +0300 | [diff] [blame] | 296 | cmdq_runtime_pm_get(cq_host); |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 297 | cqcfg = cmdq_readl(cq_host, CQCFG); |
| 298 | if (cqcfg & 0x1) { |
| 299 | pr_info("%s: %s: cq_host is already enabled\n", |
| 300 | mmc_hostname(mmc), __func__); |
| 301 | WARN_ON(1); |
| 302 | goto out; |
| 303 | } |
| 304 | |
| 305 | if (cq_host->quirks & CMDQ_QUIRK_NO_DCMD) |
| 306 | dcmd_enable = false; |
| 307 | else |
| 308 | dcmd_enable = true; |
| 309 | |
| 310 | cqcfg = ((cq_host->caps & CMDQ_TASK_DESC_SZ_128 ? CQ_TASK_DESC_SZ : 0) | |
| 311 | (dcmd_enable ? CQ_DCMD : 0)); |
| 312 | |
| 313 | cmdq_writel(cq_host, cqcfg, CQCFG); |
| 314 | /* enable CQ_HOST */ |
| 315 | cmdq_writel(cq_host, cmdq_readl(cq_host, CQCFG) | CQ_ENABLE, |
| 316 | CQCFG); |
| 317 | |
| 318 | if (!cq_host->desc_base || |
| 319 | !cq_host->trans_desc_base) { |
| 320 | err = cmdq_host_alloc_tdl(cq_host); |
| 321 | if (err) |
| 322 | goto out; |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 323 | } |
| 324 | |
Konstantin Dorfman | 14c902d | 2015-06-11 11:33:23 +0300 | [diff] [blame] | 325 | cmdq_writel(cq_host, lower_32_bits(cq_host->desc_dma_base), CQTDLBA); |
| 326 | cmdq_writel(cq_host, upper_32_bits(cq_host->desc_dma_base), CQTDLBAU); |
| 327 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 328 | /* |
| 329 | * disable all vendor interrupts |
| 330 | * enable CMDQ interrupts |
| 331 | * enable the vendor error interrupts |
| 332 | */ |
| 333 | if (cq_host->ops->clear_set_irqs) |
| 334 | cq_host->ops->clear_set_irqs(mmc, true); |
| 335 | |
| 336 | cmdq_clear_set_irqs(cq_host, 0x0, CQ_INT_ALL); |
| 337 | |
| 338 | /* cq_host would use this rca to address the card */ |
| 339 | cmdq_writel(cq_host, mmc->card->rca, CQSSC2); |
| 340 | |
| 341 | /* send QSR at lesser intervals than the default */ |
| 342 | cmdq_writel(cq_host, cmdq_readl(cq_host, CQSSC1) | SEND_QSR_INTERVAL, |
| 343 | CQSSC1); |
| 344 | |
Dov Levenglick | 2b67830 | 2015-07-01 14:24:20 +0300 | [diff] [blame^] | 345 | /* enable bkops exception indication */ |
| 346 | if (mmc_card_configured_manual_bkops(mmc->card)) |
| 347 | cmdq_writel(cq_host, cmdq_readl(cq_host, CQRMEM) | CQ_EXCEPTION, |
| 348 | CQRMEM); |
| 349 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 350 | /* ensure the writes are done before enabling CQE */ |
| 351 | mb(); |
| 352 | |
| 353 | cq_host->enabled = true; |
| 354 | |
| 355 | if (cq_host->ops->set_block_size) |
| 356 | cq_host->ops->set_block_size(cq_host->mmc); |
| 357 | |
| 358 | if (cq_host->ops->set_data_timeout) |
| 359 | cq_host->ops->set_data_timeout(mmc, 0xf); |
| 360 | |
| 361 | if (cq_host->ops->clear_set_dumpregs) |
| 362 | cq_host->ops->clear_set_dumpregs(mmc, 1); |
| 363 | |
| 364 | out: |
Konstantin Dorfman | 4d40cf2 | 2015-06-11 11:41:53 +0300 | [diff] [blame] | 365 | cmdq_runtime_pm_put(cq_host); |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 366 | return err; |
| 367 | } |
| 368 | |
| 369 | static void cmdq_disable(struct mmc_host *mmc, bool soft) |
| 370 | { |
| 371 | struct cmdq_host *cq_host = (struct cmdq_host *)mmc_cmdq_private(mmc); |
| 372 | |
Konstantin Dorfman | 4d40cf2 | 2015-06-11 11:41:53 +0300 | [diff] [blame] | 373 | cmdq_runtime_pm_get(cq_host); |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 374 | if (soft) { |
| 375 | cmdq_writel(cq_host, cmdq_readl( |
| 376 | cq_host, CQCFG) & ~(CQ_ENABLE), |
| 377 | CQCFG); |
| 378 | } |
Konstantin Dorfman | 4d40cf2 | 2015-06-11 11:41:53 +0300 | [diff] [blame] | 379 | cmdq_runtime_pm_put(cq_host); |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 380 | cq_host->enabled = false; |
| 381 | } |
| 382 | |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 383 | static void cmdq_reset(struct mmc_host *mmc, bool soft) |
| 384 | { |
| 385 | struct cmdq_host *cq_host = (struct cmdq_host *)mmc_cmdq_private(mmc); |
| 386 | unsigned int cqcfg; |
| 387 | unsigned int tdlba; |
| 388 | unsigned int tdlbau; |
| 389 | unsigned int rca; |
| 390 | int ret; |
| 391 | |
Konstantin Dorfman | 4d40cf2 | 2015-06-11 11:41:53 +0300 | [diff] [blame] | 392 | cmdq_runtime_pm_get(cq_host); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 393 | cqcfg = cmdq_readl(cq_host, CQCFG); |
| 394 | tdlba = cmdq_readl(cq_host, CQTDLBA); |
| 395 | tdlbau = cmdq_readl(cq_host, CQTDLBAU); |
| 396 | rca = cmdq_readl(cq_host, CQSSC2); |
| 397 | |
| 398 | cmdq_disable(mmc, true); |
| 399 | |
| 400 | if (cq_host->ops->reset) { |
| 401 | ret = cq_host->ops->reset(mmc); |
| 402 | if (ret) { |
| 403 | pr_crit("%s: reset CMDQ controller: failed\n", |
| 404 | mmc_hostname(mmc)); |
| 405 | BUG(); |
| 406 | } |
| 407 | } |
| 408 | |
| 409 | cmdq_writel(cq_host, tdlba, CQTDLBA); |
| 410 | cmdq_writel(cq_host, tdlbau, CQTDLBAU); |
| 411 | |
| 412 | if (cq_host->ops->clear_set_irqs) |
| 413 | cq_host->ops->clear_set_irqs(mmc, true); |
| 414 | |
| 415 | cmdq_clear_set_irqs(cq_host, 0x0, CQ_INT_ALL); |
| 416 | |
| 417 | /* cq_host would use this rca to address the card */ |
| 418 | cmdq_writel(cq_host, rca, CQSSC2); |
| 419 | |
| 420 | /* ensure the writes are done before enabling CQE */ |
| 421 | mb(); |
| 422 | |
| 423 | cmdq_writel(cq_host, cqcfg, CQCFG); |
Konstantin Dorfman | 4d40cf2 | 2015-06-11 11:41:53 +0300 | [diff] [blame] | 424 | cmdq_runtime_pm_put(cq_host); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 425 | cq_host->enabled = true; |
| 426 | } |
| 427 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 428 | static void cmdq_prep_task_desc(struct mmc_request *mrq, |
| 429 | u64 *data, bool intr, bool qbr) |
| 430 | { |
| 431 | struct mmc_cmdq_req *cmdq_req = mrq->cmdq_req; |
| 432 | u32 req_flags = cmdq_req->cmdq_req_flags; |
| 433 | |
| 434 | pr_debug("%s: %s: data-tag: 0x%08x - dir: %d - prio: %d - cnt: 0x%08x - addr: 0x%llx\n", |
| 435 | mmc_hostname(mrq->host), __func__, |
| 436 | !!(req_flags & DAT_TAG), !!(req_flags & DIR), |
| 437 | !!(req_flags & PRIO), cmdq_req->data.blocks, |
| 438 | (u64)mrq->cmdq_req->blk_addr); |
| 439 | |
| 440 | *data = VALID(1) | |
| 441 | END(1) | |
| 442 | INT(intr) | |
| 443 | ACT(0x5) | |
| 444 | FORCED_PROG(!!(req_flags & FORCED_PRG)) | |
| 445 | CONTEXT(mrq->cmdq_req->ctx_id) | |
| 446 | DATA_TAG(!!(req_flags & DAT_TAG)) | |
| 447 | DATA_DIR(!!(req_flags & DIR)) | |
| 448 | PRIORITY(!!(req_flags & PRIO)) | |
| 449 | QBAR(qbr) | |
| 450 | REL_WRITE(!!(req_flags & REL_WR)) | |
| 451 | BLK_COUNT(mrq->cmdq_req->data.blocks) | |
| 452 | BLK_ADDR((u64)mrq->cmdq_req->blk_addr); |
| 453 | } |
| 454 | |
| 455 | static int cmdq_dma_map(struct mmc_host *host, struct mmc_request *mrq) |
| 456 | { |
| 457 | int sg_count; |
| 458 | struct mmc_data *data = mrq->data; |
| 459 | |
| 460 | if (!data) |
| 461 | return -EINVAL; |
| 462 | |
| 463 | sg_count = dma_map_sg(mmc_dev(host), data->sg, |
| 464 | data->sg_len, |
| 465 | (data->flags & MMC_DATA_WRITE) ? |
| 466 | DMA_TO_DEVICE : DMA_FROM_DEVICE); |
| 467 | if (!sg_count) { |
| 468 | pr_err("%s: sg-len: %d\n", __func__, data->sg_len); |
| 469 | return -ENOMEM; |
| 470 | } |
| 471 | |
| 472 | return sg_count; |
| 473 | } |
| 474 | |
| 475 | static void cmdq_set_tran_desc(u8 *desc, |
| 476 | dma_addr_t addr, int len, bool end) |
| 477 | { |
| 478 | __le64 *dataddr = (__le64 __force *)(desc + 4); |
| 479 | __le32 *attr = (__le32 __force *)desc; |
| 480 | |
| 481 | *attr = (VALID(1) | |
| 482 | END(end ? 1 : 0) | |
| 483 | INT(0) | |
| 484 | ACT(0x4) | |
| 485 | DAT_LENGTH(len)); |
| 486 | |
| 487 | dataddr[0] = cpu_to_le64(addr); |
| 488 | } |
| 489 | |
| 490 | static int cmdq_prep_tran_desc(struct mmc_request *mrq, |
| 491 | struct cmdq_host *cq_host, int tag) |
| 492 | { |
| 493 | struct mmc_data *data = mrq->data; |
| 494 | int i, sg_count, len; |
| 495 | bool end = false; |
| 496 | dma_addr_t addr; |
| 497 | u8 *desc; |
| 498 | struct scatterlist *sg; |
| 499 | |
| 500 | sg_count = cmdq_dma_map(mrq->host, mrq); |
| 501 | if (sg_count < 0) { |
| 502 | pr_err("%s: %s: unable to map sg lists, %d\n", |
| 503 | mmc_hostname(mrq->host), __func__, sg_count); |
| 504 | return sg_count; |
| 505 | } |
| 506 | |
| 507 | desc = get_trans_desc(cq_host, tag); |
| 508 | memset(desc, 0, cq_host->trans_desc_len * cq_host->mmc->max_segs); |
| 509 | |
| 510 | for_each_sg(data->sg, sg, sg_count, i) { |
| 511 | addr = sg_dma_address(sg); |
| 512 | len = sg_dma_len(sg); |
| 513 | |
| 514 | if ((i+1) == sg_count) |
| 515 | end = true; |
| 516 | cmdq_set_tran_desc(desc, addr, len, end); |
| 517 | desc += cq_host->trans_desc_len; |
| 518 | } |
| 519 | |
| 520 | pr_debug("%s: req: 0x%p tag: %d calc_trans_des: 0x%p sg-cnt: %d\n", |
| 521 | __func__, mrq->req, tag, desc, sg_count); |
| 522 | |
| 523 | return 0; |
| 524 | } |
| 525 | |
| 526 | static void cmdq_prep_dcmd_desc(struct mmc_host *mmc, |
| 527 | struct mmc_request *mrq) |
| 528 | { |
| 529 | u64 *task_desc = NULL; |
| 530 | u64 data = 0; |
| 531 | u8 resp_type; |
| 532 | u8 *desc; |
| 533 | __le64 *dataddr; |
| 534 | struct cmdq_host *cq_host = mmc_cmdq_private(mmc); |
| 535 | u8 timing; |
| 536 | |
| 537 | if (!(mrq->cmd->flags & MMC_RSP_PRESENT)) { |
| 538 | resp_type = 0x0; |
| 539 | timing = 0x1; |
| 540 | } else { |
Sahitya Tummala | 72bd840 | 2015-05-29 13:27:38 +0530 | [diff] [blame] | 541 | if (mrq->cmd->flags & MMC_RSP_BUSY) { |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 542 | resp_type = 0x3; |
| 543 | timing = 0x0; |
| 544 | } else { |
| 545 | resp_type = 0x2; |
| 546 | timing = 0x1; |
| 547 | } |
| 548 | } |
| 549 | |
| 550 | task_desc = (__le64 __force *)get_desc(cq_host, cq_host->dcmd_slot); |
| 551 | memset(task_desc, 0, cq_host->task_desc_len); |
| 552 | data |= (VALID(1) | |
| 553 | END(1) | |
| 554 | INT(1) | |
| 555 | QBAR(1) | |
| 556 | ACT(0x5) | |
| 557 | CMD_INDEX(mrq->cmd->opcode) | |
| 558 | CMD_TIMING(timing) | RESP_TYPE(resp_type)); |
| 559 | *task_desc |= data; |
| 560 | desc = (u8 *)task_desc; |
| 561 | pr_debug("cmdq: dcmd: cmd: %d timing: %d resp: %d\n", |
| 562 | mrq->cmd->opcode, timing, resp_type); |
| 563 | dataddr = (__le64 __force *)(desc + 4); |
| 564 | dataddr[0] = cpu_to_le64((u64)mrq->cmd->arg); |
| 565 | |
| 566 | } |
| 567 | |
| 568 | static int cmdq_request(struct mmc_host *mmc, struct mmc_request *mrq) |
| 569 | { |
Konstantin Dorfman | 4d40cf2 | 2015-06-11 11:41:53 +0300 | [diff] [blame] | 570 | int err = 0; |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 571 | u64 data = 0; |
| 572 | u64 *task_desc = NULL; |
| 573 | u32 tag = mrq->cmdq_req->tag; |
| 574 | struct cmdq_host *cq_host = (struct cmdq_host *)mmc_cmdq_private(mmc); |
| 575 | |
| 576 | if (!cq_host->enabled) { |
| 577 | pr_err("%s: CMDQ host not enabled yet !!!\n", |
| 578 | mmc_hostname(mmc)); |
| 579 | err = -EINVAL; |
| 580 | goto out; |
| 581 | } |
| 582 | |
Konstantin Dorfman | 4d40cf2 | 2015-06-11 11:41:53 +0300 | [diff] [blame] | 583 | cmdq_runtime_pm_get(cq_host); |
| 584 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 585 | if (mrq->cmdq_req->cmdq_req_flags & DCMD) { |
| 586 | cmdq_prep_dcmd_desc(mmc, mrq); |
| 587 | cq_host->mrq_slot[DCMD_SLOT] = mrq; |
| 588 | cmdq_writel(cq_host, 1 << DCMD_SLOT, CQTDBR); |
Konstantin Dorfman | 4d40cf2 | 2015-06-11 11:41:53 +0300 | [diff] [blame] | 589 | goto out; |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 590 | } |
| 591 | |
| 592 | task_desc = (__le64 __force *)get_desc(cq_host, tag); |
| 593 | |
| 594 | cmdq_prep_task_desc(mrq, &data, 1, |
| 595 | (mrq->cmdq_req->cmdq_req_flags & QBR)); |
| 596 | *task_desc = cpu_to_le64(data); |
| 597 | |
| 598 | err = cmdq_prep_tran_desc(mrq, cq_host, tag); |
| 599 | if (err) { |
| 600 | pr_err("%s: %s: failed to setup tx desc: %d\n", |
| 601 | mmc_hostname(mmc), __func__, err); |
Konstantin Dorfman | 4d40cf2 | 2015-06-11 11:41:53 +0300 | [diff] [blame] | 602 | goto out; |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 603 | } |
| 604 | |
| 605 | BUG_ON(cmdq_readl(cq_host, CQTDBR) & (1 << tag)); |
| 606 | |
| 607 | cq_host->mrq_slot[tag] = mrq; |
| 608 | if (cq_host->ops->set_tranfer_params) |
| 609 | cq_host->ops->set_tranfer_params(mmc); |
| 610 | |
| 611 | cmdq_writel(cq_host, 1 << tag, CQTDBR); |
| 612 | |
| 613 | out: |
Konstantin Dorfman | 4d40cf2 | 2015-06-11 11:41:53 +0300 | [diff] [blame] | 614 | cmdq_runtime_pm_put(cq_host); |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 615 | return err; |
| 616 | } |
| 617 | |
| 618 | static void cmdq_finish_data(struct mmc_host *mmc, unsigned int tag) |
| 619 | { |
| 620 | struct mmc_request *mrq; |
| 621 | struct cmdq_host *cq_host = (struct cmdq_host *)mmc_cmdq_private(mmc); |
| 622 | |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 623 | mrq = get_req_by_tag(cq_host, tag); |
Sahitya Tummala | 9549d56 | 2015-05-29 15:41:18 +0530 | [diff] [blame] | 624 | if (tag == cq_host->dcmd_slot) |
| 625 | mrq->cmd->resp[0] = cmdq_readl(cq_host, CQCRDCT); |
| 626 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 627 | mrq->done(mrq); |
| 628 | } |
| 629 | |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 630 | irqreturn_t cmdq_irq(struct mmc_host *mmc, int err) |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 631 | { |
| 632 | u32 status; |
| 633 | unsigned long tag = 0, comp_status; |
| 634 | struct cmdq_host *cq_host = (struct cmdq_host *)mmc_cmdq_private(mmc); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 635 | unsigned long err_info = 0; |
| 636 | struct mmc_request *mrq; |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 637 | |
| 638 | status = cmdq_readl(cq_host, CQIS); |
| 639 | cmdq_writel(cq_host, status, CQIS); |
| 640 | |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 641 | if (!status && !err) |
| 642 | return IRQ_NONE; |
| 643 | |
| 644 | if (err || (status & CQIS_RED)) { |
| 645 | err_info = cmdq_readl(cq_host, CQTERRI); |
| 646 | pr_err("%s: err: %d status: 0x%08x task-err-info (0x%08lx)\n", |
| 647 | mmc_hostname(mmc), err, status, err_info); |
| 648 | |
| 649 | cmdq_dumpregs(cq_host); |
| 650 | |
| 651 | if (err_info & CQ_RMEFV) { |
| 652 | tag = GET_CMD_ERR_TAG(err_info); |
| 653 | pr_err("%s: CMD err tag: %lu\n", __func__, tag); |
| 654 | |
| 655 | mrq = get_req_by_tag(cq_host, tag); |
| 656 | /* CMD44/45/46/47 will not have a valid cmd */ |
| 657 | if (mrq->cmd) |
| 658 | mrq->cmd->error = err; |
| 659 | else |
| 660 | mrq->data->error = err; |
| 661 | } else { |
| 662 | tag = GET_DAT_ERR_TAG(err_info); |
| 663 | pr_err("%s: Dat err tag: %lu\n", __func__, tag); |
| 664 | mrq = get_req_by_tag(cq_host, tag); |
| 665 | mrq->data->error = err; |
| 666 | } |
| 667 | |
| 668 | tag = 0; |
| 669 | /* |
| 670 | * CQE detected a response error from device |
| 671 | * In most cases, this would require a reset. |
| 672 | */ |
| 673 | if (status & CQIS_RED) { |
Dov Levenglick | 2b67830 | 2015-07-01 14:24:20 +0300 | [diff] [blame^] | 674 | /* |
| 675 | * will check if the RED error is due to a bkops |
| 676 | * exception once the queue is empty |
| 677 | */ |
| 678 | BUG_ON(!mmc->card); |
| 679 | if (mmc_card_configured_manual_bkops(mmc->card) && |
| 680 | !mmc_card_configured_auto_bkops(mmc->card)) |
| 681 | mmc->card->bkops.needs_check = true; |
| 682 | |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 683 | mrq->cmdq_req->resp_err = true; |
| 684 | pr_err("%s: Response error (0x%08x) from card !!!", |
Dov Levenglick | 2b67830 | 2015-07-01 14:24:20 +0300 | [diff] [blame^] | 685 | mmc_hostname(mmc), status); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 686 | } else { |
| 687 | mrq->cmdq_req->resp_idx = cmdq_readl(cq_host, CQCRI); |
| 688 | mrq->cmdq_req->resp_arg = cmdq_readl(cq_host, CQCRA); |
| 689 | } |
| 690 | |
| 691 | mmc->err_mrq = mrq; |
| 692 | cmdq_finish_data(mmc, tag); |
| 693 | } |
| 694 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 695 | if (status & CQIS_TCC) { |
| 696 | /* read QCTCN and complete the request */ |
| 697 | comp_status = cmdq_readl(cq_host, CQTCN); |
| 698 | if (!comp_status) |
| 699 | goto out; |
| 700 | |
| 701 | for_each_set_bit(tag, &comp_status, cq_host->num_slots) { |
| 702 | /* complete the corresponding mrq */ |
| 703 | pr_debug("%s: completing tag -> %lu\n", |
| 704 | mmc_hostname(mmc), tag); |
| 705 | cmdq_finish_data(mmc, tag); |
| 706 | } |
| 707 | cmdq_writel(cq_host, comp_status, CQTCN); |
| 708 | } |
| 709 | |
Asutosh Das | aa1e1c7 | 2015-05-21 17:22:10 +0530 | [diff] [blame] | 710 | if (status & CQIS_HAC) { |
Konstantin Dorfman | fa32107 | 2015-05-31 10:10:13 +0300 | [diff] [blame] | 711 | if (cq_host->ops->post_cqe_halt) |
| 712 | cq_host->ops->post_cqe_halt(mmc); |
Asutosh Das | aa1e1c7 | 2015-05-21 17:22:10 +0530 | [diff] [blame] | 713 | /* halt is completed, wakeup waiting thread */ |
| 714 | complete(&cq_host->halt_comp); |
| 715 | } |
| 716 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 717 | out: |
| 718 | return IRQ_HANDLED; |
| 719 | } |
| 720 | EXPORT_SYMBOL(cmdq_irq); |
| 721 | |
Asutosh Das | aa1e1c7 | 2015-05-21 17:22:10 +0530 | [diff] [blame] | 722 | /* May sleep */ |
| 723 | static int cmdq_halt(struct mmc_host *mmc, bool halt) |
| 724 | { |
| 725 | struct cmdq_host *cq_host = (struct cmdq_host *)mmc_cmdq_private(mmc); |
Konstantin Dorfman | 4d40cf2 | 2015-06-11 11:41:53 +0300 | [diff] [blame] | 726 | u32 ret = 0; |
Asutosh Das | aa1e1c7 | 2015-05-21 17:22:10 +0530 | [diff] [blame] | 727 | |
Konstantin Dorfman | 4d40cf2 | 2015-06-11 11:41:53 +0300 | [diff] [blame] | 728 | cmdq_runtime_pm_get(cq_host); |
Asutosh Das | aa1e1c7 | 2015-05-21 17:22:10 +0530 | [diff] [blame] | 729 | if (halt) { |
| 730 | cmdq_writel(cq_host, cmdq_readl(cq_host, CQCTL) | HALT, |
| 731 | CQCTL); |
Konstantin Dorfman | 4d40cf2 | 2015-06-11 11:41:53 +0300 | [diff] [blame] | 732 | ret = wait_for_completion_timeout(&cq_host->halt_comp, |
Asutosh Das | aa1e1c7 | 2015-05-21 17:22:10 +0530 | [diff] [blame] | 733 | msecs_to_jiffies(HALT_TIMEOUT_MS)); |
| 734 | /* halt done: re-enable legacy interrupts */ |
| 735 | if (cq_host->ops->clear_set_irqs) |
| 736 | cq_host->ops->clear_set_irqs(mmc, false); |
Konstantin Dorfman | 4d40cf2 | 2015-06-11 11:41:53 +0300 | [diff] [blame] | 737 | ret = ret ? 0 : -ETIMEDOUT; |
Asutosh Das | aa1e1c7 | 2015-05-21 17:22:10 +0530 | [diff] [blame] | 738 | } else { |
| 739 | if (cq_host->ops->clear_set_irqs) |
| 740 | cq_host->ops->clear_set_irqs(mmc, true); |
| 741 | cmdq_writel(cq_host, cmdq_readl(cq_host, CQCTL) & ~HALT, |
| 742 | CQCTL); |
| 743 | } |
Konstantin Dorfman | 4d40cf2 | 2015-06-11 11:41:53 +0300 | [diff] [blame] | 744 | cmdq_runtime_pm_put(cq_host); |
| 745 | return ret; |
Asutosh Das | aa1e1c7 | 2015-05-21 17:22:10 +0530 | [diff] [blame] | 746 | } |
| 747 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 748 | static void cmdq_post_req(struct mmc_host *host, struct mmc_request *mrq, |
| 749 | int err) |
| 750 | { |
| 751 | struct mmc_data *data = mrq->data; |
| 752 | |
| 753 | if (data) { |
| 754 | data->error = err; |
| 755 | dma_unmap_sg(mmc_dev(host), data->sg, data->sg_len, |
| 756 | (data->flags & MMC_DATA_READ) ? |
| 757 | DMA_FROM_DEVICE : DMA_TO_DEVICE); |
| 758 | if (err) |
| 759 | data->bytes_xfered = 0; |
| 760 | else |
| 761 | data->bytes_xfered = blk_rq_bytes(mrq->req); |
| 762 | } |
| 763 | } |
| 764 | |
Asutosh Das | fa8836b | 2015-03-02 23:14:05 +0530 | [diff] [blame] | 765 | static void cmdq_dumpstate(struct mmc_host *mmc) |
| 766 | { |
| 767 | struct cmdq_host *cq_host = (struct cmdq_host *)mmc_cmdq_private(mmc); |
Konstantin Dorfman | 4d40cf2 | 2015-06-11 11:41:53 +0300 | [diff] [blame] | 768 | cmdq_runtime_pm_get(cq_host); |
Asutosh Das | fa8836b | 2015-03-02 23:14:05 +0530 | [diff] [blame] | 769 | cmdq_dumpregs(cq_host); |
Konstantin Dorfman | 4d40cf2 | 2015-06-11 11:41:53 +0300 | [diff] [blame] | 770 | cmdq_runtime_pm_put(cq_host); |
Asutosh Das | fa8836b | 2015-03-02 23:14:05 +0530 | [diff] [blame] | 771 | } |
| 772 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 773 | static const struct mmc_cmdq_host_ops cmdq_host_ops = { |
| 774 | .enable = cmdq_enable, |
| 775 | .disable = cmdq_disable, |
| 776 | .request = cmdq_request, |
| 777 | .post_req = cmdq_post_req, |
Asutosh Das | aa1e1c7 | 2015-05-21 17:22:10 +0530 | [diff] [blame] | 778 | .halt = cmdq_halt, |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 779 | .reset = cmdq_reset, |
Asutosh Das | fa8836b | 2015-03-02 23:14:05 +0530 | [diff] [blame] | 780 | .dumpstate = cmdq_dumpstate, |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 781 | }; |
| 782 | |
| 783 | struct cmdq_host *cmdq_pltfm_init(struct platform_device *pdev) |
| 784 | { |
| 785 | struct cmdq_host *cq_host; |
| 786 | struct resource *cmdq_memres = NULL; |
| 787 | |
| 788 | /* check and setup CMDQ interface */ |
| 789 | cmdq_memres = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 790 | "cmdq_mem"); |
| 791 | if (!cmdq_memres) { |
| 792 | dev_dbg(&pdev->dev, "CMDQ not supported\n"); |
| 793 | return ERR_PTR(-EINVAL); |
| 794 | } |
| 795 | |
| 796 | cq_host = kzalloc(sizeof(*cq_host), GFP_KERNEL); |
| 797 | if (!cq_host) { |
| 798 | dev_err(&pdev->dev, "failed to allocate memory for CMDQ\n"); |
| 799 | return ERR_PTR(-ENOMEM); |
| 800 | } |
| 801 | cq_host->mmio = devm_ioremap(&pdev->dev, |
| 802 | cmdq_memres->start, |
| 803 | resource_size(cmdq_memres)); |
| 804 | if (!cq_host->mmio) { |
| 805 | dev_err(&pdev->dev, "failed to remap cmdq regs\n"); |
| 806 | kfree(cq_host); |
| 807 | return ERR_PTR(-EBUSY); |
| 808 | } |
| 809 | dev_dbg(&pdev->dev, "CMDQ ioremap: done\n"); |
| 810 | |
| 811 | return cq_host; |
| 812 | } |
| 813 | EXPORT_SYMBOL(cmdq_pltfm_init); |
| 814 | |
| 815 | int cmdq_init(struct cmdq_host *cq_host, struct mmc_host *mmc, |
| 816 | bool dma64) |
| 817 | { |
| 818 | int err = 0; |
| 819 | |
| 820 | cq_host->dma64 = dma64; |
| 821 | cq_host->mmc = mmc; |
| 822 | cq_host->mmc->cmdq_private = cq_host; |
| 823 | |
| 824 | cq_host->num_slots = NUM_SLOTS; |
| 825 | cq_host->dcmd_slot = DCMD_SLOT; |
| 826 | |
| 827 | mmc->cmdq_ops = &cmdq_host_ops; |
| 828 | |
| 829 | cq_host->mrq_slot = kzalloc(sizeof(cq_host->mrq_slot) * |
| 830 | cq_host->num_slots, GFP_KERNEL); |
| 831 | if (!cq_host->mrq_slot) |
| 832 | return -ENOMEM; |
| 833 | |
| 834 | init_completion(&cq_host->halt_comp); |
| 835 | return err; |
| 836 | } |
| 837 | EXPORT_SYMBOL(cmdq_init); |