blob: 8cc62289a63ed9958c9623acaa5462048cc9287b [file] [log] [blame]
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001config ARM64
2 def_bool y
Suthikulpanit, Suraveeb6197b92015-06-10 11:08:53 -05003 select ACPI_CCA_REQUIRED if ACPI
Lorenzo Pieralisid8f4f162015-03-24 17:58:51 +00004 select ACPI_GENERIC_GSI if ACPI
Al Stone6933de02015-03-24 14:02:51 +00005 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
Dan Williams21266be2015-11-19 18:19:29 -08006 select ARCH_HAS_DEVMEM_IS_ALLOWED
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01007 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
Kees Cook2b68f6c2015-04-14 15:48:00 -07008 select ARCH_HAS_ELF_RANDOMIZE
Riku Voipio957e3fa2014-12-12 16:57:44 -08009 select ARCH_HAS_GCOV_PROFILE_ALL
Laura Abbott308c09f2014-08-08 14:23:25 -070010 select ARCH_HAS_SG_CHAIN
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010011 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
Sudeep Hollac63c8702014-05-09 10:33:01 +010012 select ARCH_USE_CMPXCHG_LOCKREF
Peter Zijlstra4badad32014-06-06 19:53:16 +020013 select ARCH_SUPPORTS_ATOMIC_RMW
Arnd Bergmann91701002013-02-21 11:42:57 +010014 select ARCH_WANT_OPTIONAL_GPIOLIB
Will Deacon6212a512012-11-07 14:16:28 +000015 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
Catalin Marinasb6f35982013-01-29 18:25:41 +000016 select ARCH_WANT_FRAME_POINTERS
Catalin Marinas25c92a32012-12-18 15:26:13 +000017 select ARM_AMBA
Mark Rutland1aee5d72012-11-20 10:06:00 +000018 select ARM_ARCH_TIMER
Catalin Marinasc4188ed2013-01-14 12:39:31 +000019 select ARM_GIC
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010020 select AUDIT_ARCH_COMPAT_GENERIC
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000021 select ARM_GIC_V2M if PCI_MSI
Marc Zyngier021f6532014-06-30 16:01:31 +010022 select ARM_GIC_V3
Marc Zyngier19812722014-11-24 14:35:19 +000023 select ARM_GIC_V3_ITS if PCI_MSI
Mark Rutlandbff60792015-07-31 15:46:16 +010024 select ARM_PSCI_FW
Will Deaconadace892013-05-08 17:29:24 +010025 select BUILDTIME_EXTABLE_SORT
Catalin Marinasdb2789b2012-12-18 15:27:25 +000026 select CLONE_BACKWARDS
Deepak Saxena7ca2ef32012-09-22 10:33:36 -070027 select COMMON_CLK
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +000028 select CPU_PM if (SUSPEND || CPU_IDLE)
Will Deacon7bc13fd2013-11-06 19:32:13 +000029 select DCACHE_WORD_ACCESS
Catalin Marinasef375662015-07-07 17:15:39 +010030 select EDAC_SUPPORT
Yang Shi2f34f172015-11-09 10:09:55 -080031 select FRAME_POINTER
Laura Abbottd4932f92014-10-09 15:26:44 -070032 select GENERIC_ALLOCATOR
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010033 select GENERIC_CLOCKEVENTS
Will Deacon4b3dc962015-05-29 18:28:44 +010034 select GENERIC_CLOCKEVENTS_BROADCAST
Ard Biesheuvel3be1a5c2014-03-04 01:10:04 +000035 select GENERIC_CPU_AUTOPROBE
Mark Salterbf4b5582014-04-07 15:39:52 -070036 select GENERIC_EARLY_IOREMAP
Leo Yan2314ee42015-08-21 04:40:22 +010037 select GENERIC_IDLE_POLL_SETUP
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010038 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
Sudeep Holla6544e672015-04-22 18:16:33 +010040 select GENERIC_IRQ_SHOW_LEVEL
Arnd Bergmanncb61f672014-11-19 14:09:07 +010041 select GENERIC_PCI_IOMAP
Stephen Boyd65cd4f62013-07-18 16:21:18 -070042 select GENERIC_SCHED_CLOCK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010043 select GENERIC_SMP_IDLE_THREAD
Will Deacon12a0ef72013-11-06 17:20:22 +000044 select GENERIC_STRNCPY_FROM_USER
45 select GENERIC_STRNLEN_USER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010046 select GENERIC_TIME_VSYSCALL
Marc Zyngiera1ddc742014-08-26 11:03:17 +010047 select HANDLE_DOMAIN_IRQ
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010048 select HARDIRQS_SW_RESEND
Steve Capper5284e1b2014-10-24 13:22:20 +010049 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010050 select HAVE_ARCH_AUDITSYSCALL
Yalin Wang8e7a4ce2014-11-03 03:02:23 +010051 select HAVE_ARCH_BITREVERSE
Jiang Liu9732caf2014-01-07 22:17:13 +080052 select HAVE_ARCH_JUMP_LABEL
Andrey Ryabininf1b90322015-11-17 18:47:08 +030053 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
Vijaya Kumar K95292472014-01-28 11:20:22 +000054 select HAVE_ARCH_KGDB
Daniel Cashman8f0d3aa2016-01-14 15:20:01 -080055 select HAVE_ARCH_MMAP_RND_BITS
56 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +000057 select HAVE_ARCH_SECCOMP_FILTER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010058 select HAVE_ARCH_TRACEHOOK
Zi Shen Lime54bcde2014-08-26 21:15:30 -070059 select HAVE_BPF_JIT
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010060 select HAVE_C_RECORDMCOUNT
Laura Abbottc0c264a2014-06-25 23:55:03 +010061 select HAVE_CC_STACKPROTECTOR
Steve Capper5284e1b2014-10-24 13:22:20 +010062 select HAVE_CMPXCHG_DOUBLE
Will Deacon95eff6b2015-05-29 14:57:47 +010063 select HAVE_CMPXCHG_LOCAL
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070064 select HAVE_DEBUG_BUGVERBOSE
Catalin Marinasb69ec422012-10-08 16:28:11 -070065 select HAVE_DEBUG_KMEMLEAK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010066 select HAVE_DMA_API_DEBUG
Laura Abbott6ac21042013-12-12 19:28:33 +000067 select HAVE_DMA_CONTIGUOUS
AKASHI Takahirobd7d38d2014-04-30 10:54:34 +010068 select HAVE_DYNAMIC_FTRACE
Will Deacon50afc332013-12-16 17:50:08 +000069 select HAVE_EFFICIENT_UNALIGNED_ACCESS
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010070 select HAVE_FTRACE_MCOUNT_RECORD
AKASHI Takahiro819e50e2014-04-30 18:54:33 +090071 select HAVE_FUNCTION_TRACER
72 select HAVE_FUNCTION_GRAPH_TRACER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010073 select HAVE_GENERIC_DMA_COHERENT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010074 select HAVE_HW_BREAKPOINT if PERF_EVENTS
Will Deacon24da2082015-11-23 15:12:59 +000075 select HAVE_IRQ_TIME_ACCOUNTING
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010076 select HAVE_MEMBLOCK
Mark Rutland55834a72014-02-07 17:12:45 +000077 select HAVE_PATA_PLATFORM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010078 select HAVE_PERF_EVENTS
Jean Pihet2ee0d7f2014-02-03 19:18:27 +010079 select HAVE_PERF_REGS
80 select HAVE_PERF_USER_STACK_DUMP
Steve Capper5e5f6dc2014-10-09 15:29:23 -070081 select HAVE_RCU_TABLE_FREE
AKASHI Takahiro055b1212014-04-30 10:54:36 +010082 select HAVE_SYSCALL_TRACEPOINTS
Robin Murphy876945d2015-10-01 20:14:00 +010083 select IOMMU_DMA if IOMMU_SUPPORT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010084 select IRQ_DOMAIN
Anders Roxelle8557d12015-04-27 22:53:09 +020085 select IRQ_FORCED_THREADING
Catalin Marinasfea2aca2012-10-16 11:26:57 +010086 select MODULES_USE_ELF_RELA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010087 select NO_BOOTMEM
88 select OF
89 select OF_EARLY_FLATTREE
Marek Szyprowski9bf14b72014-02-28 14:42:55 +010090 select OF_RESERVED_MEM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010091 select PERF_USE_VMALLOC
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +000092 select POWER_RESET
93 select POWER_SUPPLY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010094 select RTC_LIB
95 select SPARSE_IRQ
Catalin Marinas7ac57a82012-10-08 16:28:16 -070096 select SYSCTL_EXCEPTION_TRACE
Larry Bassel6c81fe72014-05-30 12:34:15 -070097 select HAVE_CONTEXT_TRACKING
Jens Wiklander14457452016-01-04 15:44:32 +010098 select HAVE_ARM_SMCCC
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010099 help
100 ARM 64-bit (AArch64) Linux support.
101
102config 64BIT
103 def_bool y
104
105config ARCH_PHYS_ADDR_T_64BIT
106 def_bool y
107
108config MMU
109 def_bool y
110
Daniel Cashman8f0d3aa2016-01-14 15:20:01 -0800111config ARCH_MMAP_RND_BITS_MIN
112 default 14 if ARM64_64K_PAGES
113 default 16 if ARM64_16K_PAGES
114 default 18
115
116# max bits determined by the following formula:
117# VA_BITS - PAGE_SHIFT - 3
118config ARCH_MMAP_RND_BITS_MAX
119 default 19 if ARM64_VA_BITS=36
120 default 24 if ARM64_VA_BITS=39
121 default 27 if ARM64_VA_BITS=42
122 default 30 if ARM64_VA_BITS=47
123 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
124 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
125 default 33 if ARM64_VA_BITS=48
126 default 14 if ARM64_64K_PAGES
127 default 16 if ARM64_16K_PAGES
128 default 18
129
130config ARCH_MMAP_RND_COMPAT_BITS_MIN
131 default 7 if ARM64_64K_PAGES
132 default 9 if ARM64_16K_PAGES
133 default 11
134
135config ARCH_MMAP_RND_COMPAT_BITS_MAX
136 default 16
137
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -0700138config NO_IOPORT_MAP
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100139 def_bool y if !PCI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100140
141config STACKTRACE_SUPPORT
142 def_bool y
143
Jeff Vander Stoepbf0c4e02015-08-18 20:50:10 +0100144config ILLEGAL_POINTER_VALUE
145 hex
146 default 0xdead000000000000
147
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100148config LOCKDEP_SUPPORT
149 def_bool y
150
151config TRACE_IRQFLAGS_SUPPORT
152 def_bool y
153
Will Deaconc209f792014-03-14 17:47:05 +0000154config RWSEM_XCHGADD_ALGORITHM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100155 def_bool y
156
Dave P Martin9fb74102015-07-24 16:37:48 +0100157config GENERIC_BUG
158 def_bool y
159 depends on BUG
160
161config GENERIC_BUG_RELATIVE_POINTERS
162 def_bool y
163 depends on GENERIC_BUG
164
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100165config GENERIC_HWEIGHT
166 def_bool y
167
168config GENERIC_CSUM
169 def_bool y
170
171config GENERIC_CALIBRATE_DELAY
172 def_bool y
173
Catalin Marinas19e76402014-02-27 12:09:22 +0000174config ZONE_DMA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100175 def_bool y
176
Steve Capper29e56942014-10-09 15:29:25 -0700177config HAVE_GENERIC_RCU_GUP
178 def_bool y
179
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100180config ARCH_DMA_ADDR_T_64BIT
181 def_bool y
182
183config NEED_DMA_MAP_STATE
184 def_bool y
185
186config NEED_SG_DMA_LENGTH
187 def_bool y
188
Will Deacon4b3dc962015-05-29 18:28:44 +0100189config SMP
190 def_bool y
191
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100192config SWIOTLB
193 def_bool y
194
195config IOMMU_HELPER
196 def_bool SWIOTLB
197
Ard Biesheuvel4cfb3612013-07-09 14:18:12 +0100198config KERNEL_MODE_NEON
199 def_bool y
200
Rob Herring92cc15f2014-04-18 17:19:59 -0500201config FIX_EARLYCON_MEM
202 def_bool y
203
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700204config PGTABLE_LEVELS
205 int
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100206 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700207 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
208 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
209 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100210 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
211 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700212
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100213source "init/Kconfig"
214
215source "kernel/Kconfig.freezer"
216
Olof Johansson6a377492015-07-20 12:09:16 -0700217source "arch/arm64/Kconfig.platforms"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100218
219menu "Bus support"
220
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100221config PCI
222 bool "PCI support"
223 help
224 This feature enables support for PCI bus system. If you say Y
225 here, the kernel will include drivers and infrastructure code
226 to support PCI bus devices.
227
228config PCI_DOMAINS
229 def_bool PCI
230
231config PCI_DOMAINS_GENERIC
232 def_bool PCI
233
234config PCI_SYSCALL
235 def_bool PCI
236
237source "drivers/pci/Kconfig"
238source "drivers/pci/pcie/Kconfig"
239source "drivers/pci/hotplug/Kconfig"
240
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100241endmenu
242
243menu "Kernel Features"
244
Andre Przywarac0a01b82014-11-14 15:54:12 +0000245menu "ARM errata workarounds via the alternatives framework"
246
247config ARM64_ERRATUM_826319
248 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
249 default y
250 help
251 This option adds an alternative code sequence to work around ARM
252 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
253 AXI master interface and an L2 cache.
254
255 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
256 and is unable to accept a certain write via this interface, it will
257 not progress on read data presented on the read data channel and the
258 system can deadlock.
259
260 The workaround promotes data cache clean instructions to
261 data cache clean-and-invalidate.
262 Please note that this does not necessarily enable the workaround,
263 as it depends on the alternative framework, which will only patch
264 the kernel if an affected CPU is detected.
265
266 If unsure, say Y.
267
268config ARM64_ERRATUM_827319
269 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
270 default y
271 help
272 This option adds an alternative code sequence to work around ARM
273 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
274 master interface and an L2 cache.
275
276 Under certain conditions this erratum can cause a clean line eviction
277 to occur at the same time as another transaction to the same address
278 on the AMBA 5 CHI interface, which can cause data corruption if the
279 interconnect reorders the two transactions.
280
281 The workaround promotes data cache clean instructions to
282 data cache clean-and-invalidate.
283 Please note that this does not necessarily enable the workaround,
284 as it depends on the alternative framework, which will only patch
285 the kernel if an affected CPU is detected.
286
287 If unsure, say Y.
288
289config ARM64_ERRATUM_824069
290 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
291 default y
292 help
293 This option adds an alternative code sequence to work around ARM
294 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
295 to a coherent interconnect.
296
297 If a Cortex-A53 processor is executing a store or prefetch for
298 write instruction at the same time as a processor in another
299 cluster is executing a cache maintenance operation to the same
300 address, then this erratum might cause a clean cache line to be
301 incorrectly marked as dirty.
302
303 The workaround promotes data cache clean instructions to
304 data cache clean-and-invalidate.
305 Please note that this option does not necessarily enable the
306 workaround, as it depends on the alternative framework, which will
307 only patch the kernel if an affected CPU is detected.
308
309 If unsure, say Y.
310
311config ARM64_ERRATUM_819472
312 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
313 default y
314 help
315 This option adds an alternative code sequence to work around ARM
316 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
317 present when it is connected to a coherent interconnect.
318
319 If the processor is executing a load and store exclusive sequence at
320 the same time as a processor in another cluster is executing a cache
321 maintenance operation to the same address, then this erratum might
322 cause data corruption.
323
324 The workaround promotes data cache clean instructions to
325 data cache clean-and-invalidate.
326 Please note that this does not necessarily enable the workaround,
327 as it depends on the alternative framework, which will only patch
328 the kernel if an affected CPU is detected.
329
330 If unsure, say Y.
331
332config ARM64_ERRATUM_832075
333 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
334 default y
335 help
336 This option adds an alternative code sequence to work around ARM
337 erratum 832075 on Cortex-A57 parts up to r1p2.
338
339 Affected Cortex-A57 parts might deadlock when exclusive load/store
340 instructions to Write-Back memory are mixed with Device loads.
341
342 The workaround is to promote device loads to use Load-Acquire
343 semantics.
344 Please note that this does not necessarily enable the workaround,
345 as it depends on the alternative framework, which will only patch
346 the kernel if an affected CPU is detected.
347
348 If unsure, say Y.
349
Marc Zyngier498cd5c2015-11-16 10:28:18 +0000350config ARM64_ERRATUM_834220
351 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
352 depends on KVM
353 default y
354 help
355 This option adds an alternative code sequence to work around ARM
356 erratum 834220 on Cortex-A57 parts up to r1p2.
357
358 Affected Cortex-A57 parts might report a Stage 2 translation
359 fault as the result of a Stage 1 fault for load crossing a
360 page boundary when there is a permission or device memory
361 alignment fault at Stage 1 and a translation fault at Stage 2.
362
363 The workaround is to verify that the Stage 1 translation
364 doesn't generate a fault before handling the Stage 2 fault.
365 Please note that this does not necessarily enable the workaround,
366 as it depends on the alternative framework, which will only patch
367 the kernel if an affected CPU is detected.
368
369 If unsure, say Y.
370
Will Deacon905e8c52015-03-23 19:07:02 +0000371config ARM64_ERRATUM_845719
372 bool "Cortex-A53: 845719: a load might read incorrect data"
373 depends on COMPAT
374 default y
375 help
376 This option adds an alternative code sequence to work around ARM
377 erratum 845719 on Cortex-A53 parts up to r0p4.
378
379 When running a compat (AArch32) userspace on an affected Cortex-A53
380 part, a load at EL0 from a virtual address that matches the bottom 32
381 bits of the virtual address used by a recent load at (AArch64) EL1
382 might return incorrect data.
383
384 The workaround is to write the contextidr_el1 register on exception
385 return to a 32-bit task.
386 Please note that this does not necessarily enable the workaround,
387 as it depends on the alternative framework, which will only patch
388 the kernel if an affected CPU is detected.
389
390 If unsure, say Y.
391
Will Deacondf057cc2015-03-17 12:15:02 +0000392config ARM64_ERRATUM_843419
393 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
394 depends on MODULES
395 default y
396 help
397 This option builds kernel modules using the large memory model in
398 order to avoid the use of the ADRP instruction, which can cause
399 a subsequent memory access to use an incorrect address on Cortex-A53
400 parts up to r0p4.
401
402 Note that the kernel itself must be linked with a version of ld
403 which fixes potentially affected ADRP instructions through the
404 use of veneers.
405
406 If unsure, say Y.
407
Robert Richter94100972015-09-21 22:58:38 +0200408config CAVIUM_ERRATUM_22375
409 bool "Cavium erratum 22375, 24313"
410 default y
411 help
412 Enable workaround for erratum 22375, 24313.
413
414 This implements two gicv3-its errata workarounds for ThunderX. Both
415 with small impact affecting only ITS table allocation.
416
417 erratum 22375: only alloc 8MB table size
418 erratum 24313: ignore memory access type
419
420 The fixes are in ITS initialization and basically ignore memory access
421 type and table size provided by the TYPER and BASER registers.
422
423 If unsure, say Y.
424
Robert Richter6d4e11c2015-09-21 22:58:35 +0200425config CAVIUM_ERRATUM_23154
426 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
427 default y
428 help
429 The gicv3 of ThunderX requires a modified version for
430 reading the IAR status to ensure data synchronization
431 (access to icc_iar1_el1 is not sync'ed before and after).
432
433 If unsure, say Y.
434
Andre Przywarac0a01b82014-11-14 15:54:12 +0000435endmenu
436
437
Jungseok Leee41ceed2014-05-12 10:40:38 +0100438choice
439 prompt "Page size"
440 default ARM64_4K_PAGES
441 help
442 Page size (translation granule) configuration.
443
444config ARM64_4K_PAGES
445 bool "4KB"
446 help
447 This feature enables 4KB pages support.
448
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100449config ARM64_16K_PAGES
450 bool "16KB"
451 help
452 The system will use 16KB pages support. AArch32 emulation
453 requires applications compiled with 16K (or a multiple of 16K)
454 aligned segments.
455
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100456config ARM64_64K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100457 bool "64KB"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100458 help
459 This feature enables 64KB pages support (4KB by default)
460 allowing only two levels of page tables and faster TLB
Suzuki K. Poulosedb488be2015-10-19 14:19:34 +0100461 look-up. AArch32 emulation requires applications compiled
462 with 64K aligned segments.
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100463
Jungseok Leee41ceed2014-05-12 10:40:38 +0100464endchoice
465
466choice
467 prompt "Virtual address space size"
468 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100469 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100470 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
471 help
472 Allows choosing one of multiple possible virtual address
473 space sizes. The level of translation table is determined by
474 a combination of page size and virtual address space size.
475
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100476config ARM64_VA_BITS_36
Catalin Marinas56a3f302015-10-20 14:59:20 +0100477 bool "36-bit" if EXPERT
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100478 depends on ARM64_16K_PAGES
479
Jungseok Leee41ceed2014-05-12 10:40:38 +0100480config ARM64_VA_BITS_39
481 bool "39-bit"
482 depends on ARM64_4K_PAGES
483
484config ARM64_VA_BITS_42
485 bool "42-bit"
486 depends on ARM64_64K_PAGES
487
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100488config ARM64_VA_BITS_47
489 bool "47-bit"
490 depends on ARM64_16K_PAGES
491
Jungseok Leec79b9542014-05-12 18:40:51 +0900492config ARM64_VA_BITS_48
493 bool "48-bit"
Jungseok Leec79b9542014-05-12 18:40:51 +0900494
Jungseok Leee41ceed2014-05-12 10:40:38 +0100495endchoice
496
497config ARM64_VA_BITS
498 int
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100499 default 36 if ARM64_VA_BITS_36
Jungseok Leee41ceed2014-05-12 10:40:38 +0100500 default 39 if ARM64_VA_BITS_39
501 default 42 if ARM64_VA_BITS_42
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100502 default 47 if ARM64_VA_BITS_47
Jungseok Leec79b9542014-05-12 18:40:51 +0900503 default 48 if ARM64_VA_BITS_48
Jungseok Leee41ceed2014-05-12 10:40:38 +0100504
Will Deacona8720132013-10-11 14:52:19 +0100505config CPU_BIG_ENDIAN
506 bool "Build big-endian kernel"
507 help
508 Say Y if you plan on running a kernel in big-endian mode.
509
Mark Brownf6e763b2014-03-04 07:51:17 +0000510config SCHED_MC
511 bool "Multi-core scheduler support"
Mark Brownf6e763b2014-03-04 07:51:17 +0000512 help
513 Multi-core scheduler support improves the CPU scheduler's decision
514 making when dealing with multi-core CPU chips at a cost of slightly
515 increased overhead in some places. If unsure say N here.
516
517config SCHED_SMT
518 bool "SMT scheduler support"
Mark Brownf6e763b2014-03-04 07:51:17 +0000519 help
520 Improves the CPU scheduler's decision making when dealing with
521 MultiThreading at a cost of slightly increased overhead in some
522 places. If unsure say N here.
523
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100524config NR_CPUS
Ganapatrao Kulkarni62aa9652015-03-18 11:01:18 +0000525 int "Maximum number of CPUs (2-4096)"
526 range 2 4096
Vinayak Kale15942852013-04-24 10:06:57 +0100527 # These have to remain sorted largest to smallest
Robert Richtere3672642014-09-08 12:44:48 +0100528 default "64"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100529
Mark Rutland9327e2c2013-10-24 20:30:18 +0100530config HOTPLUG_CPU
531 bool "Support for hot-pluggable CPUs"
Yang Yingliang217d4532015-09-24 17:32:14 +0800532 select GENERIC_IRQ_MIGRATION
Mark Rutland9327e2c2013-10-24 20:30:18 +0100533 help
534 Say Y here to experiment with turning CPUs off and on. CPUs
535 can be controlled through /sys/devices/system/cpu.
536
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100537source kernel/Kconfig.preempt
Kefeng Wangf90df5e2015-10-26 11:48:16 +0800538source kernel/Kconfig.hz
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100539
540config ARCH_HAS_HOLES_MEMORYMODEL
541 def_bool y if SPARSEMEM
542
543config ARCH_SPARSEMEM_ENABLE
544 def_bool y
545 select SPARSEMEM_VMEMMAP_ENABLE
546
547config ARCH_SPARSEMEM_DEFAULT
548 def_bool ARCH_SPARSEMEM_ENABLE
549
550config ARCH_SELECT_MEMORY_MODEL
551 def_bool ARCH_SPARSEMEM_ENABLE
552
553config HAVE_ARCH_PFN_VALID
554 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
555
556config HW_PERF_EVENTS
Mark Rutland6475b2d2015-10-02 10:55:03 +0100557 def_bool y
558 depends on ARM_PMU
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100559
Steve Capper084bd292013-04-10 13:48:00 +0100560config SYS_SUPPORTS_HUGETLBFS
561 def_bool y
562
Steve Capper084bd292013-04-10 13:48:00 +0100563config ARCH_WANT_HUGE_PMD_SHARE
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100564 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
Steve Capper084bd292013-04-10 13:48:00 +0100565
Steve Capperaf074842013-04-19 16:23:57 +0100566config HAVE_ARCH_TRANSPARENT_HUGEPAGE
567 def_bool y
568
Catalin Marinasa41dc0e2014-04-03 17:48:54 +0100569config ARCH_HAS_CACHE_LINE_SIZE
570 def_bool y
571
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100572source "mm/Kconfig"
573
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +0000574config SECCOMP
575 bool "Enable seccomp to safely compute untrusted bytecode"
576 ---help---
577 This kernel feature is useful for number crunching applications
578 that may need to compute untrusted bytecode during their
579 execution. By using pipes or other transports made available to
580 the process as file descriptors supporting the read/write
581 syscalls, it's possible to isolate those applications in
582 their own address space using seccomp. Once seccomp is
583 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
584 and the task is only allowed to execute a few safe syscalls
585 defined by each seccomp mode.
586
Stefano Stabellinidfd57bc2015-11-23 10:33:49 +0000587config PARAVIRT
588 bool "Enable paravirtualization code"
589 help
590 This changes the kernel so it can modify itself when it is run
591 under a hypervisor, potentially improving performance significantly
592 over full virtualization.
593
594config PARAVIRT_TIME_ACCOUNTING
595 bool "Paravirtual steal time accounting"
596 select PARAVIRT
597 default n
598 help
599 Select this option to enable fine granularity task steal time
600 accounting. Time spent executing other tasks in parallel with
601 the current vCPU is discounted from the vCPU power. To account for
602 that, there can be a small performance impact.
603
604 If in doubt, say N here.
605
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000606config XEN_DOM0
607 def_bool y
608 depends on XEN
609
610config XEN
Julien Grallc2ba1f72014-09-17 14:07:06 -0700611 bool "Xen guest support on ARM64"
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000612 depends on ARM64 && OF
Stefano Stabellini83862cc2013-10-10 13:40:44 +0000613 select SWIOTLB_XEN
Stefano Stabellinidfd57bc2015-11-23 10:33:49 +0000614 select PARAVIRT
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000615 help
616 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
617
Steve Capperd03bb142013-04-25 15:19:21 +0100618config FORCE_MAX_ZONEORDER
619 int
620 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100621 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
Steve Capperd03bb142013-04-25 15:19:21 +0100622 default "11"
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100623 help
624 The kernel memory allocator divides physically contiguous memory
625 blocks into "zones", where each zone is a power of two number of
626 pages. This option selects the largest power of two that the kernel
627 keeps in the memory allocator. If you need to allocate very large
628 blocks of physically contiguous memory, then you may need to
629 increase this value.
630
631 This config option is actually maximum order plus one. For example,
632 a value of 11 means that the largest free memory block is 2^10 pages.
633
634 We make sure that we can allocate upto a HugePage size for each configuration.
635 Hence we have :
636 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
637
638 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
639 4M allocations matching the default size used by generic code.
Steve Capperd03bb142013-04-25 15:19:21 +0100640
Will Deacon1b907f42014-11-20 16:51:10 +0000641menuconfig ARMV8_DEPRECATED
642 bool "Emulate deprecated/obsolete ARMv8 instructions"
643 depends on COMPAT
644 help
645 Legacy software support may require certain instructions
646 that have been deprecated or obsoleted in the architecture.
647
648 Enable this config to enable selective emulation of these
649 features.
650
651 If unsure, say Y
652
653if ARMV8_DEPRECATED
654
655config SWP_EMULATION
656 bool "Emulate SWP/SWPB instructions"
657 help
658 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
659 they are always undefined. Say Y here to enable software
660 emulation of these instructions for userspace using LDXR/STXR.
661
662 In some older versions of glibc [<=2.8] SWP is used during futex
663 trylock() operations with the assumption that the code will not
664 be preempted. This invalid assumption may be more likely to fail
665 with SWP emulation enabled, leading to deadlock of the user
666 application.
667
668 NOTE: when accessing uncached shared regions, LDXR/STXR rely
669 on an external transaction monitoring block called a global
670 monitor to maintain update atomicity. If your system does not
671 implement a global monitor, this option can cause programs that
672 perform SWP operations to uncached memory to deadlock.
673
674 If unsure, say Y
675
676config CP15_BARRIER_EMULATION
677 bool "Emulate CP15 Barrier instructions"
678 help
679 The CP15 barrier instructions - CP15ISB, CP15DSB, and
680 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
681 strongly recommended to use the ISB, DSB, and DMB
682 instructions instead.
683
684 Say Y here to enable software emulation of these
685 instructions for AArch32 userspace code. When this option is
686 enabled, CP15 barrier usage is traced which can help
687 identify software that needs updating.
688
689 If unsure, say Y
690
Suzuki K. Poulose2d888f42015-01-21 12:43:11 +0000691config SETEND_EMULATION
692 bool "Emulate SETEND instruction"
693 help
694 The SETEND instruction alters the data-endianness of the
695 AArch32 EL0, and is deprecated in ARMv8.
696
697 Say Y here to enable software emulation of the instruction
698 for AArch32 userspace code.
699
700 Note: All the cpus on the system must have mixed endian support at EL0
701 for this feature to be enabled. If a new CPU - which doesn't support mixed
702 endian - is hotplugged in after this feature has been enabled, there could
703 be unexpected results in the applications.
704
705 If unsure, say Y
Will Deacon1b907f42014-11-20 16:51:10 +0000706endif
707
Will Deacon0e4a0702015-07-27 15:54:13 +0100708menu "ARMv8.1 architectural features"
709
710config ARM64_HW_AFDBM
711 bool "Support for hardware updates of the Access and Dirty page flags"
712 default y
713 help
714 The ARMv8.1 architecture extensions introduce support for
715 hardware updates of the access and dirty information in page
716 table entries. When enabled in TCR_EL1 (HA and HD bits) on
717 capable processors, accesses to pages with PTE_AF cleared will
718 set this bit instead of raising an access flag fault.
719 Similarly, writes to read-only pages with the DBM bit set will
720 clear the read-only bit (AP[2]) instead of raising a
721 permission fault.
722
723 Kernels built with this configuration option enabled continue
724 to work on pre-ARMv8.1 hardware and the performance impact is
725 minimal. If unsure, say Y.
726
727config ARM64_PAN
728 bool "Enable support for Privileged Access Never (PAN)"
729 default y
730 help
731 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
732 prevents the kernel or hypervisor from accessing user-space (EL0)
733 memory directly.
734
735 Choosing this option will cause any unprotected (not using
736 copy_to_user et al) memory access to fail with a permission fault.
737
738 The feature is detected at runtime, and will remain as a 'nop'
739 instruction if the cpu does not implement the feature.
740
741config ARM64_LSE_ATOMICS
742 bool "Atomic instructions"
743 help
744 As part of the Large System Extensions, ARMv8.1 introduces new
745 atomic instructions that are designed specifically to scale in
746 very large systems.
747
748 Say Y here to make use of these instructions for the in-kernel
749 atomic routines. This incurs a small overhead on CPUs that do
750 not support these instructions and requires the kernel to be
751 built with binutils >= 2.25.
752
753endmenu
754
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100755endmenu
756
757menu "Boot options"
758
759config CMDLINE
760 string "Default kernel command string"
761 default ""
762 help
763 Provide a set of default command-line options at build time by
764 entering them here. As a minimum, you should specify the the
765 root device (e.g. root=/dev/nfs).
766
767config CMDLINE_FORCE
768 bool "Always use the default kernel command string"
769 help
770 Always use the default kernel command string, even if the boot
771 loader passes other arguments to the kernel.
772 This is useful if you cannot or don't want to change the
773 command-line options your boot loader passes to the kernel.
774
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200775config EFI_STUB
776 bool
777
Mark Salterf84d0272014-04-15 21:59:30 -0400778config EFI
779 bool "UEFI runtime support"
780 depends on OF && !CPU_BIG_ENDIAN
781 select LIBFDT
782 select UCS2_STRING
783 select EFI_PARAMS_FROM_FDT
Ard Biesheuvele15dd492014-07-04 19:41:53 +0200784 select EFI_RUNTIME_WRAPPERS
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200785 select EFI_STUB
786 select EFI_ARMSTUB
Mark Salterf84d0272014-04-15 21:59:30 -0400787 default y
788 help
789 This option provides support for runtime services provided
790 by UEFI firmware (such as non-volatile variables, realtime
Mark Salter3c7f2552014-04-15 22:47:52 -0400791 clock, and platform reset). A UEFI stub is also provided to
792 allow the kernel to be booted as an EFI application. This
793 is only useful on systems that have UEFI firmware.
Mark Salterf84d0272014-04-15 21:59:30 -0400794
Yi Lid1ae8c02014-10-04 23:46:43 +0800795config DMI
796 bool "Enable support for SMBIOS (DMI) tables"
797 depends on EFI
798 default y
799 help
800 This enables SMBIOS/DMI feature for systems.
801
802 This option is only useful on systems that have UEFI firmware.
803 However, even with this option, the resultant kernel should
804 continue to boot on existing non-UEFI platforms.
805
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100806endmenu
807
808menu "Userspace binary formats"
809
810source "fs/Kconfig.binfmt"
811
812config COMPAT
813 bool "Kernel support for 32-bit EL0"
Suzuki K. Poulose755e70b2015-10-19 14:19:32 +0100814 depends on ARM64_4K_PAGES || EXPERT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100815 select COMPAT_BINFMT_ELF
Catalin Marinasaf1839e2012-10-08 16:28:08 -0700816 select HAVE_UID16
Al Viro84b9e9b2012-12-25 16:29:11 -0500817 select OLD_SIGSUSPEND3
Al Viro51682032012-12-25 19:31:29 -0500818 select COMPAT_OLD_SIGACTION
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100819 help
820 This option enables support for a 32-bit EL0 running under a 64-bit
821 kernel at EL1. AArch32-specific components such as system calls,
822 the user helper functions, VFP support and the ptrace interface are
823 handled appropriately by the kernel.
824
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100825 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
826 that you will only be able to execute AArch32 binaries that were compiled
827 with page size aligned segments.
Alexander Grafa8fcd8b2015-03-16 16:32:23 +0000828
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100829 If you want to execute 32-bit userspace applications, say Y.
830
831config SYSVIPC_COMPAT
832 def_bool y
833 depends on COMPAT && SYSVIPC
834
835endmenu
836
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000837menu "Power management options"
838
839source "kernel/power/Kconfig"
840
841config ARCH_SUSPEND_POSSIBLE
842 def_bool y
843
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000844endmenu
845
Lorenzo Pieralisi13072202013-07-17 14:54:21 +0100846menu "CPU Power Management"
847
848source "drivers/cpuidle/Kconfig"
849
Rob Herring52e7e812014-02-24 11:27:57 +0900850source "drivers/cpufreq/Kconfig"
851
852endmenu
853
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100854source "net/Kconfig"
855
856source "drivers/Kconfig"
857
Mark Salterf84d0272014-04-15 21:59:30 -0400858source "drivers/firmware/Kconfig"
859
Graeme Gregoryb6a02172015-03-24 14:02:53 +0000860source "drivers/acpi/Kconfig"
861
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100862source "fs/Kconfig"
863
Marc Zyngierc3eb5b12013-07-04 13:34:32 +0100864source "arch/arm64/kvm/Kconfig"
865
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100866source "arch/arm64/Kconfig.debug"
867
868source "security/Kconfig"
869
870source "crypto/Kconfig"
Ard Biesheuvel2c988332014-03-06 16:23:33 +0800871if CRYPTO
872source "arch/arm64/crypto/Kconfig"
873endif
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100874
875source "lib/Kconfig"