Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1 | /* |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 2 | * File: arch/blackfin/mach-common/ints-priority.c |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 3 | * Based on: |
| 4 | * Author: |
| 5 | * |
| 6 | * Created: ? |
Simon Arlott | d2d50aa | 2007-06-11 15:31:30 +0800 | [diff] [blame] | 7 | * Description: Set up the interrupt priorities |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 8 | * |
| 9 | * Modified: |
| 10 | * 1996 Roman Zippel |
| 11 | * 1999 D. Jeff Dionne <jeff@uclinux.org> |
| 12 | * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca> |
| 13 | * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca> |
| 14 | * 2003 Metrowerks/Motorola |
| 15 | * 2003 Bas Vermeulen <bas@buyways.nl> |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 16 | * Copyright 2004-2008 Analog Devices Inc. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 17 | * |
| 18 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 19 | * |
| 20 | * This program is free software; you can redistribute it and/or modify |
| 21 | * it under the terms of the GNU General Public License as published by |
| 22 | * the Free Software Foundation; either version 2 of the License, or |
| 23 | * (at your option) any later version. |
| 24 | * |
| 25 | * This program is distributed in the hope that it will be useful, |
| 26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 28 | * GNU General Public License for more details. |
| 29 | * |
| 30 | * You should have received a copy of the GNU General Public License |
| 31 | * along with this program; if not, see the file COPYING, or write |
| 32 | * to the Free Software Foundation, Inc., |
| 33 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 34 | */ |
| 35 | |
| 36 | #include <linux/module.h> |
| 37 | #include <linux/kernel_stat.h> |
| 38 | #include <linux/seq_file.h> |
| 39 | #include <linux/irq.h> |
| 40 | #ifdef CONFIG_KGDB |
| 41 | #include <linux/kgdb.h> |
| 42 | #endif |
| 43 | #include <asm/traps.h> |
| 44 | #include <asm/blackfin.h> |
| 45 | #include <asm/gpio.h> |
| 46 | #include <asm/irq_handler.h> |
| 47 | |
| 48 | #ifdef BF537_FAMILY |
| 49 | # define BF537_GENERIC_ERROR_INT_DEMUX |
| 50 | #else |
| 51 | # undef BF537_GENERIC_ERROR_INT_DEMUX |
| 52 | #endif |
| 53 | |
| 54 | /* |
| 55 | * NOTES: |
| 56 | * - we have separated the physical Hardware interrupt from the |
| 57 | * levels that the LINUX kernel sees (see the description in irq.h) |
| 58 | * - |
| 59 | */ |
| 60 | |
Mike Frysinger | a99bbcc | 2007-10-22 00:19:31 +0800 | [diff] [blame] | 61 | /* Initialize this to an actual value to force it into the .data |
| 62 | * section so that we know it is properly initialized at entry into |
| 63 | * the kernel but before bss is initialized to zero (which is where |
| 64 | * it would live otherwise). The 0x1f magic represents the IRQs we |
| 65 | * cannot actually mask out in hardware. |
| 66 | */ |
| 67 | unsigned long irq_flags = 0x1f; |
Mike Frysinger | fe8015c | 2008-10-28 11:07:15 +0800 | [diff] [blame] | 68 | EXPORT_SYMBOL(irq_flags); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 69 | |
| 70 | /* The number of spurious interrupts */ |
| 71 | atomic_t num_spurious; |
| 72 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 73 | #ifdef CONFIG_PM |
| 74 | unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */ |
Michael Hennerich | 4a88d0c | 2008-08-05 17:38:41 +0800 | [diff] [blame] | 75 | unsigned vr_wakeup; |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 76 | #endif |
| 77 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 78 | struct ivgx { |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 79 | /* irq number for request_irq, available in mach-bf5xx/irq.h */ |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 80 | unsigned int irqno; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 81 | /* corresponding bit in the SIC_ISR register */ |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 82 | unsigned int isrflag; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 83 | } ivg_table[NR_PERI_INTS]; |
| 84 | |
| 85 | struct ivg_slice { |
| 86 | /* position of first irq in ivg_table for given ivg */ |
| 87 | struct ivgx *ifirst; |
| 88 | struct ivgx *istop; |
| 89 | } ivg7_13[IVG13 - IVG7 + 1]; |
| 90 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 91 | |
| 92 | /* |
| 93 | * Search SIC_IAR and fill tables with the irqvalues |
| 94 | * and their positions in the SIC_ISR register. |
| 95 | */ |
| 96 | static void __init search_IAR(void) |
| 97 | { |
| 98 | unsigned ivg, irq_pos = 0; |
| 99 | for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) { |
| 100 | int irqn; |
| 101 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 102 | ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos]; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 103 | |
| 104 | for (irqn = 0; irqn < NR_PERI_INTS; irqn++) { |
| 105 | int iar_shift = (irqn & 7) * 4; |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 106 | if (ivg == (0xf & |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame^] | 107 | #if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \ |
| 108 | || defined(CONFIG_BF539) || defined(CONFIG_BF51x) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 109 | bfin_read32((unsigned long *)SIC_IAR0 + |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 110 | ((irqn % 32) >> 3) + ((irqn / 32) * |
| 111 | ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) { |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 112 | #else |
| 113 | bfin_read32((unsigned long *)SIC_IAR0 + |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 114 | (irqn >> 3)) >> iar_shift)) { |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 115 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 116 | ivg_table[irq_pos].irqno = IVG7 + irqn; |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 117 | ivg_table[irq_pos].isrflag = 1 << (irqn % 32); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 118 | ivg7_13[ivg].istop++; |
| 119 | irq_pos++; |
| 120 | } |
| 121 | } |
| 122 | } |
| 123 | } |
| 124 | |
| 125 | /* |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 126 | * This is for core internal IRQs |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 127 | */ |
| 128 | |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 129 | static void bfin_ack_noop(unsigned int irq) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 130 | { |
| 131 | /* Dummy function. */ |
| 132 | } |
| 133 | |
| 134 | static void bfin_core_mask_irq(unsigned int irq) |
| 135 | { |
| 136 | irq_flags &= ~(1 << irq); |
| 137 | if (!irqs_disabled()) |
| 138 | local_irq_enable(); |
| 139 | } |
| 140 | |
| 141 | static void bfin_core_unmask_irq(unsigned int irq) |
| 142 | { |
| 143 | irq_flags |= 1 << irq; |
| 144 | /* |
| 145 | * If interrupts are enabled, IMASK must contain the same value |
| 146 | * as irq_flags. Make sure that invariant holds. If interrupts |
| 147 | * are currently disabled we need not do anything; one of the |
| 148 | * callers will take care of setting IMASK to the proper value |
| 149 | * when reenabling interrupts. |
| 150 | * local_irq_enable just does "STI irq_flags", so it's exactly |
| 151 | * what we need. |
| 152 | */ |
| 153 | if (!irqs_disabled()) |
| 154 | local_irq_enable(); |
| 155 | return; |
| 156 | } |
| 157 | |
| 158 | static void bfin_internal_mask_irq(unsigned int irq) |
| 159 | { |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 160 | #ifdef CONFIG_BF53x |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 161 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 162 | ~(1 << SIC_SYSIRQ(irq))); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 163 | #else |
| 164 | unsigned mask_bank, mask_bit; |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 165 | mask_bank = SIC_SYSIRQ(irq) / 32; |
| 166 | mask_bit = SIC_SYSIRQ(irq) % 32; |
Bryan Wu | c04d66b | 2007-07-12 17:26:31 +0800 | [diff] [blame] | 167 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & |
| 168 | ~(1 << mask_bit)); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 169 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 170 | SSYNC(); |
| 171 | } |
| 172 | |
| 173 | static void bfin_internal_unmask_irq(unsigned int irq) |
| 174 | { |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 175 | #ifdef CONFIG_BF53x |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 176 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 177 | (1 << SIC_SYSIRQ(irq))); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 178 | #else |
| 179 | unsigned mask_bank, mask_bit; |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 180 | mask_bank = SIC_SYSIRQ(irq) / 32; |
| 181 | mask_bit = SIC_SYSIRQ(irq) % 32; |
Bryan Wu | c04d66b | 2007-07-12 17:26:31 +0800 | [diff] [blame] | 182 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | |
| 183 | (1 << mask_bit)); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 184 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 185 | SSYNC(); |
| 186 | } |
| 187 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 188 | #ifdef CONFIG_PM |
| 189 | int bfin_internal_set_wake(unsigned int irq, unsigned int state) |
| 190 | { |
Michael Hennerich | 4a88d0c | 2008-08-05 17:38:41 +0800 | [diff] [blame] | 191 | unsigned bank, bit, wakeup = 0; |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 192 | unsigned long flags; |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 193 | bank = SIC_SYSIRQ(irq) / 32; |
| 194 | bit = SIC_SYSIRQ(irq) % 32; |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 195 | |
Michael Hennerich | 4a88d0c | 2008-08-05 17:38:41 +0800 | [diff] [blame] | 196 | switch (irq) { |
| 197 | #ifdef IRQ_RTC |
| 198 | case IRQ_RTC: |
| 199 | wakeup |= WAKE; |
| 200 | break; |
| 201 | #endif |
| 202 | #ifdef IRQ_CAN0_RX |
| 203 | case IRQ_CAN0_RX: |
| 204 | wakeup |= CANWE; |
| 205 | break; |
| 206 | #endif |
| 207 | #ifdef IRQ_CAN1_RX |
| 208 | case IRQ_CAN1_RX: |
| 209 | wakeup |= CANWE; |
| 210 | break; |
| 211 | #endif |
| 212 | #ifdef IRQ_USB_INT0 |
| 213 | case IRQ_USB_INT0: |
| 214 | wakeup |= USBWE; |
| 215 | break; |
| 216 | #endif |
| 217 | #ifdef IRQ_KEY |
| 218 | case IRQ_KEY: |
| 219 | wakeup |= KPADWE; |
| 220 | break; |
| 221 | #endif |
Michael Hennerich | d310fb4 | 2008-08-28 17:32:01 +0800 | [diff] [blame] | 222 | #ifdef CONFIG_BF54x |
Michael Hennerich | 4a88d0c | 2008-08-05 17:38:41 +0800 | [diff] [blame] | 223 | case IRQ_CNT: |
| 224 | wakeup |= ROTWE; |
| 225 | break; |
| 226 | #endif |
| 227 | default: |
| 228 | break; |
| 229 | } |
| 230 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 231 | local_irq_save(flags); |
| 232 | |
Michael Hennerich | 4a88d0c | 2008-08-05 17:38:41 +0800 | [diff] [blame] | 233 | if (state) { |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 234 | bfin_sic_iwr[bank] |= (1 << bit); |
Michael Hennerich | 4a88d0c | 2008-08-05 17:38:41 +0800 | [diff] [blame] | 235 | vr_wakeup |= wakeup; |
| 236 | |
| 237 | } else { |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 238 | bfin_sic_iwr[bank] &= ~(1 << bit); |
Michael Hennerich | 4a88d0c | 2008-08-05 17:38:41 +0800 | [diff] [blame] | 239 | vr_wakeup &= ~wakeup; |
| 240 | } |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 241 | |
| 242 | local_irq_restore(flags); |
| 243 | |
| 244 | return 0; |
| 245 | } |
| 246 | #endif |
| 247 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 248 | static struct irq_chip bfin_core_irqchip = { |
Graf Yang | 763e63c | 2008-10-08 17:08:15 +0800 | [diff] [blame] | 249 | .name = "CORE", |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 250 | .ack = bfin_ack_noop, |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 251 | .mask = bfin_core_mask_irq, |
| 252 | .unmask = bfin_core_unmask_irq, |
| 253 | }; |
| 254 | |
| 255 | static struct irq_chip bfin_internal_irqchip = { |
Graf Yang | 763e63c | 2008-10-08 17:08:15 +0800 | [diff] [blame] | 256 | .name = "INTN", |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 257 | .ack = bfin_ack_noop, |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 258 | .mask = bfin_internal_mask_irq, |
| 259 | .unmask = bfin_internal_unmask_irq, |
Michael Hennerich | ce3b7bb | 2008-02-25 13:48:47 +0800 | [diff] [blame] | 260 | .mask_ack = bfin_internal_mask_irq, |
| 261 | .disable = bfin_internal_mask_irq, |
| 262 | .enable = bfin_internal_unmask_irq, |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 263 | #ifdef CONFIG_PM |
| 264 | .set_wake = bfin_internal_set_wake, |
| 265 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 266 | }; |
| 267 | |
| 268 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
| 269 | static int error_int_mask; |
| 270 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 271 | static void bfin_generic_error_mask_irq(unsigned int irq) |
| 272 | { |
| 273 | error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR)); |
| 274 | |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 275 | if (!error_int_mask) |
| 276 | bfin_internal_mask_irq(IRQ_GENERIC_ERROR); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 277 | } |
| 278 | |
| 279 | static void bfin_generic_error_unmask_irq(unsigned int irq) |
| 280 | { |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 281 | bfin_internal_unmask_irq(IRQ_GENERIC_ERROR); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 282 | error_int_mask |= 1L << (irq - IRQ_PPI_ERROR); |
| 283 | } |
| 284 | |
| 285 | static struct irq_chip bfin_generic_error_irqchip = { |
Graf Yang | 763e63c | 2008-10-08 17:08:15 +0800 | [diff] [blame] | 286 | .name = "ERROR", |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 287 | .ack = bfin_ack_noop, |
| 288 | .mask_ack = bfin_generic_error_mask_irq, |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 289 | .mask = bfin_generic_error_mask_irq, |
| 290 | .unmask = bfin_generic_error_unmask_irq, |
| 291 | }; |
| 292 | |
| 293 | static void bfin_demux_error_irq(unsigned int int_err_irq, |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 294 | struct irq_desc *inta_desc) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 295 | { |
| 296 | int irq = 0; |
| 297 | |
| 298 | SSYNC(); |
| 299 | |
| 300 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) |
| 301 | if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK) |
| 302 | irq = IRQ_MAC_ERROR; |
| 303 | else |
| 304 | #endif |
| 305 | if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK) |
| 306 | irq = IRQ_SPORT0_ERROR; |
| 307 | else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK) |
| 308 | irq = IRQ_SPORT1_ERROR; |
| 309 | else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK) |
| 310 | irq = IRQ_PPI_ERROR; |
| 311 | else if (bfin_read_CAN_GIF() & CAN_ERR_MASK) |
| 312 | irq = IRQ_CAN_ERROR; |
| 313 | else if (bfin_read_SPI_STAT() & SPI_ERR_MASK) |
| 314 | irq = IRQ_SPI_ERROR; |
| 315 | else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) && |
| 316 | (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0)) |
| 317 | irq = IRQ_UART0_ERROR; |
| 318 | else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) && |
| 319 | (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0)) |
| 320 | irq = IRQ_UART1_ERROR; |
| 321 | |
| 322 | if (irq) { |
| 323 | if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) { |
| 324 | struct irq_desc *desc = irq_desc + irq; |
| 325 | desc->handle_irq(irq, desc); |
| 326 | } else { |
| 327 | |
| 328 | switch (irq) { |
| 329 | case IRQ_PPI_ERROR: |
| 330 | bfin_write_PPI_STATUS(PPI_ERR_MASK); |
| 331 | break; |
| 332 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) |
| 333 | case IRQ_MAC_ERROR: |
| 334 | bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK); |
| 335 | break; |
| 336 | #endif |
| 337 | case IRQ_SPORT0_ERROR: |
| 338 | bfin_write_SPORT0_STAT(SPORT_ERR_MASK); |
| 339 | break; |
| 340 | |
| 341 | case IRQ_SPORT1_ERROR: |
| 342 | bfin_write_SPORT1_STAT(SPORT_ERR_MASK); |
| 343 | break; |
| 344 | |
| 345 | case IRQ_CAN_ERROR: |
| 346 | bfin_write_CAN_GIS(CAN_ERR_MASK); |
| 347 | break; |
| 348 | |
| 349 | case IRQ_SPI_ERROR: |
| 350 | bfin_write_SPI_STAT(SPI_ERR_MASK); |
| 351 | break; |
| 352 | |
| 353 | default: |
| 354 | break; |
| 355 | } |
| 356 | |
| 357 | pr_debug("IRQ %d:" |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 358 | " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n", |
| 359 | irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 360 | } |
| 361 | } else |
| 362 | printk(KERN_ERR |
| 363 | "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR" |
| 364 | " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n", |
Harvey Harrison | b85d858 | 2008-04-23 09:39:01 +0800 | [diff] [blame] | 365 | __func__, __FILE__, __LINE__); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 366 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 367 | } |
| 368 | #endif /* BF537_GENERIC_ERROR_INT_DEMUX */ |
| 369 | |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 370 | static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle) |
| 371 | { |
| 372 | struct irq_desc *desc = irq_desc + irq; |
| 373 | /* May not call generic set_irq_handler() due to spinlock |
| 374 | recursion. */ |
| 375 | desc->handle_irq = handle; |
| 376 | } |
| 377 | |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 378 | #if !defined(CONFIG_BF54x) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 379 | |
| 380 | static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; |
| 381 | static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)]; |
| 382 | |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 383 | extern void bfin_gpio_irq_prepare(unsigned gpio); |
Michael Hennerich | 6fce6a8 | 2007-12-24 16:56:12 +0800 | [diff] [blame] | 384 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 385 | static void bfin_gpio_ack_irq(unsigned int irq) |
| 386 | { |
| 387 | u16 gpionr = irq - IRQ_PF0; |
| 388 | |
| 389 | if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) { |
| 390 | set_gpio_data(gpionr, 0); |
| 391 | SSYNC(); |
| 392 | } |
| 393 | } |
| 394 | |
| 395 | static void bfin_gpio_mask_ack_irq(unsigned int irq) |
| 396 | { |
| 397 | u16 gpionr = irq - IRQ_PF0; |
| 398 | |
| 399 | if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) { |
| 400 | set_gpio_data(gpionr, 0); |
| 401 | SSYNC(); |
| 402 | } |
| 403 | |
| 404 | set_gpio_maska(gpionr, 0); |
| 405 | SSYNC(); |
| 406 | } |
| 407 | |
| 408 | static void bfin_gpio_mask_irq(unsigned int irq) |
| 409 | { |
| 410 | set_gpio_maska(irq - IRQ_PF0, 0); |
| 411 | SSYNC(); |
| 412 | } |
| 413 | |
| 414 | static void bfin_gpio_unmask_irq(unsigned int irq) |
| 415 | { |
| 416 | set_gpio_maska(irq - IRQ_PF0, 1); |
| 417 | SSYNC(); |
| 418 | } |
| 419 | |
| 420 | static unsigned int bfin_gpio_irq_startup(unsigned int irq) |
| 421 | { |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 422 | u16 gpionr = irq - IRQ_PF0; |
| 423 | |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 424 | if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) |
| 425 | bfin_gpio_irq_prepare(gpionr); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 426 | |
| 427 | gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); |
| 428 | bfin_gpio_unmask_irq(irq); |
| 429 | |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 430 | return 0; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 431 | } |
| 432 | |
| 433 | static void bfin_gpio_irq_shutdown(unsigned int irq) |
| 434 | { |
| 435 | bfin_gpio_mask_irq(irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 436 | gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0); |
| 437 | } |
| 438 | |
| 439 | static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) |
| 440 | { |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 441 | u16 gpionr = irq - IRQ_PF0; |
| 442 | |
| 443 | if (type == IRQ_TYPE_PROBE) { |
| 444 | /* only probe unenabled GPIO interrupt lines */ |
| 445 | if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)) |
| 446 | return 0; |
| 447 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
| 448 | } |
| 449 | |
| 450 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 451 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 452 | if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) |
| 453 | bfin_gpio_irq_prepare(gpionr); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 454 | |
| 455 | gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); |
| 456 | } else { |
| 457 | gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr); |
| 458 | return 0; |
| 459 | } |
| 460 | |
Michael Hennerich | f1bceb4 | 2008-02-02 16:17:52 +0800 | [diff] [blame] | 461 | set_gpio_inen(gpionr, 0); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 462 | set_gpio_dir(gpionr, 0); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 463 | |
| 464 | if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
| 465 | == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
| 466 | set_gpio_both(gpionr, 1); |
| 467 | else |
| 468 | set_gpio_both(gpionr, 0); |
| 469 | |
| 470 | if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) |
| 471 | set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */ |
| 472 | else |
| 473 | set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */ |
| 474 | |
Michael Hennerich | f1bceb4 | 2008-02-02 16:17:52 +0800 | [diff] [blame] | 475 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
| 476 | set_gpio_edge(gpionr, 1); |
| 477 | set_gpio_inen(gpionr, 1); |
| 478 | gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr); |
| 479 | set_gpio_data(gpionr, 0); |
| 480 | |
| 481 | } else { |
| 482 | set_gpio_edge(gpionr, 0); |
| 483 | gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr); |
| 484 | set_gpio_inen(gpionr, 1); |
| 485 | } |
| 486 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 487 | SSYNC(); |
| 488 | |
| 489 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 490 | bfin_set_irq_handler(irq, handle_edge_irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 491 | else |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 492 | bfin_set_irq_handler(irq, handle_level_irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 493 | |
| 494 | return 0; |
| 495 | } |
| 496 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 497 | #ifdef CONFIG_PM |
| 498 | int bfin_gpio_set_wake(unsigned int irq, unsigned int state) |
| 499 | { |
| 500 | unsigned gpio = irq_to_gpio(irq); |
| 501 | |
| 502 | if (state) |
| 503 | gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE); |
| 504 | else |
| 505 | gpio_pm_wakeup_free(gpio); |
| 506 | |
| 507 | return 0; |
| 508 | } |
| 509 | #endif |
| 510 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 511 | static struct irq_chip bfin_gpio_irqchip = { |
Graf Yang | 763e63c | 2008-10-08 17:08:15 +0800 | [diff] [blame] | 512 | .name = "GPIO", |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 513 | .ack = bfin_gpio_ack_irq, |
| 514 | .mask = bfin_gpio_mask_irq, |
| 515 | .mask_ack = bfin_gpio_mask_ack_irq, |
| 516 | .unmask = bfin_gpio_unmask_irq, |
Michael Hennerich | 1f2d186 | 2008-07-14 16:31:22 +0800 | [diff] [blame] | 517 | .disable = bfin_gpio_mask_irq, |
| 518 | .enable = bfin_gpio_unmask_irq, |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 519 | .set_type = bfin_gpio_irq_type, |
| 520 | .startup = bfin_gpio_irq_startup, |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 521 | .shutdown = bfin_gpio_irq_shutdown, |
| 522 | #ifdef CONFIG_PM |
| 523 | .set_wake = bfin_gpio_set_wake, |
| 524 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 525 | }; |
| 526 | |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 527 | static void bfin_demux_gpio_irq(unsigned int inta_irq, |
| 528 | struct irq_desc *desc) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 529 | { |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 530 | unsigned int i, gpio, mask, irq, search = 0; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 531 | |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 532 | switch (inta_irq) { |
| 533 | #if defined(CONFIG_BF53x) |
| 534 | case IRQ_PROG_INTA: |
| 535 | irq = IRQ_PF0; |
| 536 | search = 1; |
| 537 | break; |
| 538 | # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) |
| 539 | case IRQ_MAC_RX: |
| 540 | irq = IRQ_PH0; |
| 541 | break; |
| 542 | # endif |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 543 | #elif defined(CONFIG_BF538) || defined(CONFIG_BF539) |
| 544 | case IRQ_PORTF_INTA: |
| 545 | irq = IRQ_PF0; |
| 546 | break; |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame^] | 547 | #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 548 | case IRQ_PORTF_INTA: |
| 549 | irq = IRQ_PF0; |
| 550 | break; |
| 551 | case IRQ_PORTG_INTA: |
| 552 | irq = IRQ_PG0; |
| 553 | break; |
| 554 | case IRQ_PORTH_INTA: |
| 555 | irq = IRQ_PH0; |
| 556 | break; |
| 557 | #elif defined(CONFIG_BF561) |
| 558 | case IRQ_PROG0_INTA: |
| 559 | irq = IRQ_PF0; |
| 560 | break; |
| 561 | case IRQ_PROG1_INTA: |
| 562 | irq = IRQ_PF16; |
| 563 | break; |
| 564 | case IRQ_PROG2_INTA: |
| 565 | irq = IRQ_PF32; |
| 566 | break; |
| 567 | #endif |
| 568 | default: |
| 569 | BUG(); |
| 570 | return; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 571 | } |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 572 | |
| 573 | if (search) { |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 574 | for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 575 | irq += i; |
| 576 | |
| 577 | mask = get_gpiop_data(i) & |
| 578 | (gpio_enabled[gpio_bank(i)] & |
| 579 | get_gpiop_maska(i)); |
| 580 | |
| 581 | while (mask) { |
| 582 | if (mask & 1) { |
| 583 | desc = irq_desc + irq; |
| 584 | desc->handle_irq(irq, desc); |
| 585 | } |
| 586 | irq++; |
| 587 | mask >>= 1; |
| 588 | } |
| 589 | } |
| 590 | } else { |
| 591 | gpio = irq_to_gpio(irq); |
| 592 | mask = get_gpiop_data(gpio) & |
| 593 | (gpio_enabled[gpio_bank(gpio)] & |
| 594 | get_gpiop_maska(gpio)); |
| 595 | |
| 596 | do { |
| 597 | if (mask & 1) { |
| 598 | desc = irq_desc + irq; |
| 599 | desc->handle_irq(irq, desc); |
| 600 | } |
| 601 | irq++; |
| 602 | mask >>= 1; |
| 603 | } while (mask); |
| 604 | } |
| 605 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 606 | } |
| 607 | |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 608 | #else /* CONFIG_BF54x */ |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 609 | |
| 610 | #define NR_PINT_SYS_IRQS 4 |
| 611 | #define NR_PINT_BITS 32 |
| 612 | #define NR_PINTS 160 |
| 613 | #define IRQ_NOT_AVAIL 0xFF |
| 614 | |
| 615 | #define PINT_2_BANK(x) ((x) >> 5) |
| 616 | #define PINT_2_BIT(x) ((x) & 0x1F) |
| 617 | #define PINT_BIT(x) (1 << (PINT_2_BIT(x))) |
| 618 | |
| 619 | static unsigned char irq2pint_lut[NR_PINTS]; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 620 | static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS]; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 621 | |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 622 | static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS]; |
| 623 | static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; |
| 624 | |
| 625 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 626 | struct pin_int_t { |
| 627 | unsigned int mask_set; |
| 628 | unsigned int mask_clear; |
| 629 | unsigned int request; |
| 630 | unsigned int assign; |
| 631 | unsigned int edge_set; |
| 632 | unsigned int edge_clear; |
| 633 | unsigned int invert_set; |
| 634 | unsigned int invert_clear; |
| 635 | unsigned int pinstate; |
| 636 | unsigned int latch; |
| 637 | }; |
| 638 | |
| 639 | static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = { |
| 640 | (struct pin_int_t *)PINT0_MASK_SET, |
| 641 | (struct pin_int_t *)PINT1_MASK_SET, |
| 642 | (struct pin_int_t *)PINT2_MASK_SET, |
| 643 | (struct pin_int_t *)PINT3_MASK_SET, |
| 644 | }; |
| 645 | |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 646 | extern void bfin_gpio_irq_prepare(unsigned gpio); |
| 647 | |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 648 | inline unsigned short get_irq_base(u8 bank, u8 bmap) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 649 | { |
| 650 | |
| 651 | u16 irq_base; |
| 652 | |
| 653 | if (bank < 2) { /*PA-PB */ |
| 654 | irq_base = IRQ_PA0 + bmap * 16; |
| 655 | } else { /*PC-PJ */ |
| 656 | irq_base = IRQ_PC0 + bmap * 16; |
| 657 | } |
| 658 | |
| 659 | return irq_base; |
| 660 | |
| 661 | } |
| 662 | |
| 663 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ |
| 664 | void init_pint_lut(void) |
| 665 | { |
| 666 | u16 bank, bit, irq_base, bit_pos; |
| 667 | u32 pint_assign; |
| 668 | u8 bmap; |
| 669 | |
| 670 | memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut)); |
| 671 | |
| 672 | for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) { |
| 673 | |
| 674 | pint_assign = pint[bank]->assign; |
| 675 | |
| 676 | for (bit = 0; bit < NR_PINT_BITS; bit++) { |
| 677 | |
| 678 | bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF; |
| 679 | |
| 680 | irq_base = get_irq_base(bank, bmap); |
| 681 | |
| 682 | irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0); |
| 683 | bit_pos = bit + bank * NR_PINT_BITS; |
| 684 | |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 685 | pint2irq_lut[bit_pos] = irq_base - SYS_IRQS; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 686 | irq2pint_lut[irq_base - SYS_IRQS] = bit_pos; |
| 687 | |
| 688 | } |
| 689 | |
| 690 | } |
| 691 | |
| 692 | } |
| 693 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 694 | static void bfin_gpio_ack_irq(unsigned int irq) |
| 695 | { |
| 696 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 697 | u32 pintbit = PINT_BIT(pint_val); |
| 698 | u8 bank = PINT_2_BANK(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 699 | |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 700 | if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) { |
| 701 | if (pint[bank]->invert_set & pintbit) |
| 702 | pint[bank]->invert_clear = pintbit; |
| 703 | else |
| 704 | pint[bank]->invert_set = pintbit; |
| 705 | } |
| 706 | pint[bank]->request = pintbit; |
| 707 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 708 | SSYNC(); |
| 709 | } |
| 710 | |
| 711 | static void bfin_gpio_mask_ack_irq(unsigned int irq) |
| 712 | { |
| 713 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 714 | u32 pintbit = PINT_BIT(pint_val); |
| 715 | u8 bank = PINT_2_BANK(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 716 | |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 717 | if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) { |
| 718 | if (pint[bank]->invert_set & pintbit) |
| 719 | pint[bank]->invert_clear = pintbit; |
| 720 | else |
| 721 | pint[bank]->invert_set = pintbit; |
| 722 | } |
| 723 | |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 724 | pint[bank]->request = pintbit; |
| 725 | pint[bank]->mask_clear = pintbit; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 726 | SSYNC(); |
| 727 | } |
| 728 | |
| 729 | static void bfin_gpio_mask_irq(unsigned int irq) |
| 730 | { |
| 731 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
| 732 | |
| 733 | pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val); |
| 734 | SSYNC(); |
| 735 | } |
| 736 | |
| 737 | static void bfin_gpio_unmask_irq(unsigned int irq) |
| 738 | { |
| 739 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 740 | u32 pintbit = PINT_BIT(pint_val); |
| 741 | u8 bank = PINT_2_BANK(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 742 | |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 743 | pint[bank]->request = pintbit; |
| 744 | pint[bank]->mask_set = pintbit; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 745 | SSYNC(); |
| 746 | } |
| 747 | |
| 748 | static unsigned int bfin_gpio_irq_startup(unsigned int irq) |
| 749 | { |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 750 | u16 gpionr = irq_to_gpio(irq); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 751 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
| 752 | |
Michael Hennerich | 50e163c | 2007-07-24 16:17:28 +0800 | [diff] [blame] | 753 | if (pint_val == IRQ_NOT_AVAIL) { |
| 754 | printk(KERN_ERR |
| 755 | "GPIO IRQ %d :Not in PINT Assign table " |
| 756 | "Reconfigure Interrupt to Port Assignemt\n", irq); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 757 | return -ENODEV; |
Michael Hennerich | 50e163c | 2007-07-24 16:17:28 +0800 | [diff] [blame] | 758 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 759 | |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 760 | if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) |
| 761 | bfin_gpio_irq_prepare(gpionr); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 762 | |
| 763 | gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); |
| 764 | bfin_gpio_unmask_irq(irq); |
| 765 | |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 766 | return 0; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 767 | } |
| 768 | |
| 769 | static void bfin_gpio_irq_shutdown(unsigned int irq) |
| 770 | { |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 771 | u16 gpionr = irq_to_gpio(irq); |
| 772 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 773 | bfin_gpio_mask_irq(irq); |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 774 | gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 775 | } |
| 776 | |
| 777 | static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) |
| 778 | { |
| 779 | |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 780 | u16 gpionr = irq_to_gpio(irq); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 781 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 782 | u32 pintbit = PINT_BIT(pint_val); |
| 783 | u8 bank = PINT_2_BANK(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 784 | |
| 785 | if (pint_val == IRQ_NOT_AVAIL) |
| 786 | return -ENODEV; |
| 787 | |
| 788 | if (type == IRQ_TYPE_PROBE) { |
| 789 | /* only probe unenabled GPIO interrupt lines */ |
| 790 | if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)) |
| 791 | return 0; |
| 792 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
| 793 | } |
| 794 | |
| 795 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | |
| 796 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 797 | if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) |
| 798 | bfin_gpio_irq_prepare(gpionr); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 799 | |
| 800 | gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); |
| 801 | } else { |
| 802 | gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr); |
| 803 | return 0; |
| 804 | } |
| 805 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 806 | if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 807 | pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */ |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 808 | else |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 809 | pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */ |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 810 | |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 811 | if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
| 812 | == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
| 813 | |
| 814 | gpio_both_edge_triggered[bank] |= pintbit; |
| 815 | |
| 816 | if (gpio_get_value(gpionr)) |
| 817 | pint[bank]->invert_set = pintbit; |
| 818 | else |
| 819 | pint[bank]->invert_clear = pintbit; |
| 820 | } else { |
| 821 | gpio_both_edge_triggered[bank] &= ~pintbit; |
| 822 | } |
| 823 | |
| 824 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
| 825 | pint[bank]->edge_set = pintbit; |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 826 | bfin_set_irq_handler(irq, handle_edge_irq); |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 827 | } else { |
| 828 | pint[bank]->edge_clear = pintbit; |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 829 | bfin_set_irq_handler(irq, handle_level_irq); |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 830 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 831 | |
| 832 | SSYNC(); |
| 833 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 834 | return 0; |
| 835 | } |
| 836 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 837 | #ifdef CONFIG_PM |
| 838 | u32 pint_saved_masks[NR_PINT_SYS_IRQS]; |
| 839 | u32 pint_wakeup_masks[NR_PINT_SYS_IRQS]; |
| 840 | |
| 841 | int bfin_gpio_set_wake(unsigned int irq, unsigned int state) |
| 842 | { |
| 843 | u32 pint_irq; |
| 844 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
| 845 | u32 bank = PINT_2_BANK(pint_val); |
| 846 | u32 pintbit = PINT_BIT(pint_val); |
| 847 | |
| 848 | switch (bank) { |
| 849 | case 0: |
| 850 | pint_irq = IRQ_PINT0; |
| 851 | break; |
| 852 | case 2: |
| 853 | pint_irq = IRQ_PINT2; |
| 854 | break; |
| 855 | case 3: |
| 856 | pint_irq = IRQ_PINT3; |
| 857 | break; |
| 858 | case 1: |
| 859 | pint_irq = IRQ_PINT1; |
| 860 | break; |
| 861 | default: |
| 862 | return -EINVAL; |
| 863 | } |
| 864 | |
| 865 | bfin_internal_set_wake(pint_irq, state); |
| 866 | |
| 867 | if (state) |
| 868 | pint_wakeup_masks[bank] |= pintbit; |
| 869 | else |
| 870 | pint_wakeup_masks[bank] &= ~pintbit; |
| 871 | |
| 872 | return 0; |
| 873 | } |
| 874 | |
| 875 | u32 bfin_pm_setup(void) |
| 876 | { |
| 877 | u32 val, i; |
| 878 | |
| 879 | for (i = 0; i < NR_PINT_SYS_IRQS; i++) { |
| 880 | val = pint[i]->mask_clear; |
| 881 | pint_saved_masks[i] = val; |
| 882 | if (val ^ pint_wakeup_masks[i]) { |
| 883 | pint[i]->mask_clear = val; |
| 884 | pint[i]->mask_set = pint_wakeup_masks[i]; |
| 885 | } |
| 886 | } |
| 887 | |
| 888 | return 0; |
| 889 | } |
| 890 | |
| 891 | void bfin_pm_restore(void) |
| 892 | { |
| 893 | u32 i, val; |
| 894 | |
| 895 | for (i = 0; i < NR_PINT_SYS_IRQS; i++) { |
| 896 | val = pint_saved_masks[i]; |
| 897 | if (val ^ pint_wakeup_masks[i]) { |
| 898 | pint[i]->mask_clear = pint[i]->mask_clear; |
| 899 | pint[i]->mask_set = val; |
| 900 | } |
| 901 | } |
| 902 | } |
| 903 | #endif |
| 904 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 905 | static struct irq_chip bfin_gpio_irqchip = { |
Graf Yang | 763e63c | 2008-10-08 17:08:15 +0800 | [diff] [blame] | 906 | .name = "GPIO", |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 907 | .ack = bfin_gpio_ack_irq, |
| 908 | .mask = bfin_gpio_mask_irq, |
| 909 | .mask_ack = bfin_gpio_mask_ack_irq, |
| 910 | .unmask = bfin_gpio_unmask_irq, |
Michael Hennerich | 1f2d186 | 2008-07-14 16:31:22 +0800 | [diff] [blame] | 911 | .disable = bfin_gpio_mask_irq, |
| 912 | .enable = bfin_gpio_unmask_irq, |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 913 | .set_type = bfin_gpio_irq_type, |
| 914 | .startup = bfin_gpio_irq_startup, |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 915 | .shutdown = bfin_gpio_irq_shutdown, |
| 916 | #ifdef CONFIG_PM |
| 917 | .set_wake = bfin_gpio_set_wake, |
| 918 | #endif |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 919 | }; |
| 920 | |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 921 | static void bfin_demux_gpio_irq(unsigned int inta_irq, |
| 922 | struct irq_desc *desc) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 923 | { |
| 924 | u8 bank, pint_val; |
| 925 | u32 request, irq; |
| 926 | |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 927 | switch (inta_irq) { |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 928 | case IRQ_PINT0: |
| 929 | bank = 0; |
| 930 | break; |
| 931 | case IRQ_PINT2: |
| 932 | bank = 2; |
| 933 | break; |
| 934 | case IRQ_PINT3: |
| 935 | bank = 3; |
| 936 | break; |
| 937 | case IRQ_PINT1: |
| 938 | bank = 1; |
| 939 | break; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 940 | default: |
| 941 | return; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 942 | } |
| 943 | |
| 944 | pint_val = bank * NR_PINT_BITS; |
| 945 | |
| 946 | request = pint[bank]->request; |
| 947 | |
| 948 | while (request) { |
| 949 | if (request & 1) { |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 950 | irq = pint2irq_lut[pint_val] + SYS_IRQS; |
| 951 | desc = irq_desc + irq; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 952 | desc->handle_irq(irq, desc); |
| 953 | } |
| 954 | pint_val++; |
| 955 | request >>= 1; |
| 956 | } |
| 957 | |
| 958 | } |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 959 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 960 | |
Bernd Schmidt | 8be80ed | 2007-07-25 14:44:49 +0800 | [diff] [blame] | 961 | void __init init_exception_vectors(void) |
| 962 | { |
| 963 | SSYNC(); |
| 964 | |
Mike Frysinger | f0b5d12 | 2007-08-05 17:03:59 +0800 | [diff] [blame] | 965 | /* cannot program in software: |
| 966 | * evt0 - emulation (jtag) |
| 967 | * evt1 - reset |
| 968 | */ |
| 969 | bfin_write_EVT2(evt_nmi); |
Bernd Schmidt | 8be80ed | 2007-07-25 14:44:49 +0800 | [diff] [blame] | 970 | bfin_write_EVT3(trap); |
| 971 | bfin_write_EVT5(evt_ivhw); |
| 972 | bfin_write_EVT6(evt_timer); |
| 973 | bfin_write_EVT7(evt_evt7); |
| 974 | bfin_write_EVT8(evt_evt8); |
| 975 | bfin_write_EVT9(evt_evt9); |
| 976 | bfin_write_EVT10(evt_evt10); |
| 977 | bfin_write_EVT11(evt_evt11); |
| 978 | bfin_write_EVT12(evt_evt12); |
| 979 | bfin_write_EVT13(evt_evt13); |
| 980 | bfin_write_EVT14(evt14_softirq); |
| 981 | bfin_write_EVT15(evt_system_call); |
| 982 | CSYNC(); |
| 983 | } |
| 984 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 985 | /* |
| 986 | * This function should be called during kernel startup to initialize |
| 987 | * the BFin IRQ handling routines. |
| 988 | */ |
| 989 | int __init init_arch_irq(void) |
| 990 | { |
| 991 | int irq; |
| 992 | unsigned long ilat = 0; |
| 993 | /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame^] | 994 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \ |
| 995 | || defined(BF538_FAMILY) || defined(CONFIG_BF51x) |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 996 | bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); |
| 997 | bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 998 | # ifdef CONFIG_BF54x |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 999 | bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1000 | # endif |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 1001 | #else |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1002 | bfin_write_SIC_IMASK(SIC_UNMASK_ALL); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 1003 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1004 | |
| 1005 | local_irq_disable(); |
| 1006 | |
Mike Frysinger | d70536e | 2008-08-25 17:37:35 +0800 | [diff] [blame] | 1007 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) |
Mike Frysinger | 95a86b5 | 2008-08-14 15:05:01 +0800 | [diff] [blame] | 1008 | /* Clear EMAC Interrupt Status bits so we can demux it later */ |
| 1009 | bfin_write_EMAC_SYSTAT(-1); |
| 1010 | #endif |
| 1011 | |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1012 | #ifdef CONFIG_BF54x |
| 1013 | # ifdef CONFIG_PINTx_REASSIGN |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1014 | pint[0]->assign = CONFIG_PINT0_ASSIGN; |
| 1015 | pint[1]->assign = CONFIG_PINT1_ASSIGN; |
| 1016 | pint[2]->assign = CONFIG_PINT2_ASSIGN; |
| 1017 | pint[3]->assign = CONFIG_PINT3_ASSIGN; |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1018 | # endif |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1019 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ |
| 1020 | init_pint_lut(); |
| 1021 | #endif |
| 1022 | |
| 1023 | for (irq = 0; irq <= SYS_IRQS; irq++) { |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1024 | if (irq <= IRQ_CORETMR) |
| 1025 | set_irq_chip(irq, &bfin_core_irqchip); |
| 1026 | else |
| 1027 | set_irq_chip(irq, &bfin_internal_irqchip); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1028 | |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1029 | switch (irq) { |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 1030 | #if defined(CONFIG_BF53x) |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1031 | case IRQ_PROG_INTA: |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1032 | # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1033 | case IRQ_MAC_RX: |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1034 | # endif |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 1035 | #elif defined(CONFIG_BF54x) |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1036 | case IRQ_PINT0: |
| 1037 | case IRQ_PINT1: |
| 1038 | case IRQ_PINT2: |
| 1039 | case IRQ_PINT3: |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame^] | 1040 | #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1041 | case IRQ_PORTF_INTA: |
| 1042 | case IRQ_PORTG_INTA: |
| 1043 | case IRQ_PORTH_INTA: |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 1044 | #elif defined(CONFIG_BF561) |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1045 | case IRQ_PROG0_INTA: |
| 1046 | case IRQ_PROG1_INTA: |
| 1047 | case IRQ_PROG2_INTA: |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1048 | #elif defined(CONFIG_BF538) || defined(CONFIG_BF539) |
| 1049 | case IRQ_PORTF_INTA: |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 1050 | #endif |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1051 | |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1052 | set_irq_chained_handler(irq, |
| 1053 | bfin_demux_gpio_irq); |
| 1054 | break; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1055 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1056 | case IRQ_GENERIC_ERROR: |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1057 | set_irq_handler(irq, bfin_demux_error_irq); |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1058 | |
| 1059 | break; |
| 1060 | #endif |
| 1061 | default: |
| 1062 | set_irq_handler(irq, handle_simple_irq); |
| 1063 | break; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1064 | } |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1065 | } |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1066 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1067 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1068 | for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) |
| 1069 | set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip, |
| 1070 | handle_level_irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1071 | #endif |
| 1072 | |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1073 | /* if configured as edge, then will be changed to do_edge_IRQ */ |
| 1074 | for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++) |
| 1075 | set_irq_chip_and_handler(irq, &bfin_gpio_irqchip, |
| 1076 | handle_level_irq); |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 1077 | |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1078 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1079 | bfin_write_IMASK(0); |
| 1080 | CSYNC(); |
| 1081 | ilat = bfin_read_ILAT(); |
| 1082 | CSYNC(); |
| 1083 | bfin_write_ILAT(ilat); |
| 1084 | CSYNC(); |
| 1085 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1086 | printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n"); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1087 | /* IMASK=xxx is equivalent to STI xx or irq_flags=xx, |
| 1088 | * local_irq_enable() |
| 1089 | */ |
| 1090 | program_IAR(); |
| 1091 | /* Therefore it's better to setup IARs before interrupts enabled */ |
| 1092 | search_IAR(); |
| 1093 | |
| 1094 | /* Enable interrupts IVG7-15 */ |
| 1095 | irq_flags = irq_flags | IMASK_IVG15 | |
| 1096 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1097 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1098 | |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame^] | 1099 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \ |
| 1100 | || defined(BF538_FAMILY) || defined(CONFIG_BF51x) |
Michael Hennerich | 56f5f59 | 2008-08-06 17:55:32 +0800 | [diff] [blame] | 1101 | bfin_write_SIC_IWR0(IWR_DISABLE_ALL); |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame^] | 1102 | #if defined(CONFIG_BF52x) || defined(CONFIG_BF51x) |
| 1103 | /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which |
Michael Hennerich | 55546ac | 2008-08-13 17:41:13 +0800 | [diff] [blame] | 1104 | * will screw up the bootrom as it relies on MDMA0/1 waking it |
| 1105 | * up from IDLE instructions. See this report for more info: |
| 1106 | * http://blackfin.uclinux.org/gf/tracker/4323 |
| 1107 | */ |
| 1108 | bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); |
| 1109 | #else |
Michael Hennerich | 56f5f59 | 2008-08-06 17:55:32 +0800 | [diff] [blame] | 1110 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); |
Michael Hennerich | 55546ac | 2008-08-13 17:41:13 +0800 | [diff] [blame] | 1111 | #endif |
Michael Hennerich | fe9ec9b | 2008-02-25 12:04:57 +0800 | [diff] [blame] | 1112 | # ifdef CONFIG_BF54x |
Michael Hennerich | 56f5f59 | 2008-08-06 17:55:32 +0800 | [diff] [blame] | 1113 | bfin_write_SIC_IWR2(IWR_DISABLE_ALL); |
Michael Hennerich | fe9ec9b | 2008-02-25 12:04:57 +0800 | [diff] [blame] | 1114 | # endif |
| 1115 | #else |
Michael Hennerich | 56f5f59 | 2008-08-06 17:55:32 +0800 | [diff] [blame] | 1116 | bfin_write_SIC_IWR(IWR_DISABLE_ALL); |
Michael Hennerich | fe9ec9b | 2008-02-25 12:04:57 +0800 | [diff] [blame] | 1117 | #endif |
| 1118 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1119 | return 0; |
| 1120 | } |
| 1121 | |
| 1122 | #ifdef CONFIG_DO_IRQ_L1 |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1123 | __attribute__((l1_text)) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1124 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1125 | void do_irq(int vec, struct pt_regs *fp) |
| 1126 | { |
| 1127 | if (vec == EVT_IVTMR_P) { |
| 1128 | vec = IRQ_CORETMR; |
| 1129 | } else { |
| 1130 | struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; |
| 1131 | struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame^] | 1132 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \ |
| 1133 | || defined(BF538_FAMILY) || defined(CONFIG_BF51x) |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 1134 | unsigned long sic_status[3]; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1135 | |
Michael Hennerich | 4fb4524 | 2007-10-21 16:53:53 +0800 | [diff] [blame] | 1136 | sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); |
| 1137 | sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1(); |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 1138 | #ifdef CONFIG_BF54x |
Michael Hennerich | 4fb4524 | 2007-10-21 16:53:53 +0800 | [diff] [blame] | 1139 | sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2(); |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 1140 | #endif |
Mike Frysinger | 1f83b8f | 2007-07-12 22:58:21 +0800 | [diff] [blame] | 1141 | for (;; ivg++) { |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 1142 | if (ivg >= ivg_stop) { |
| 1143 | atomic_inc(&num_spurious); |
| 1144 | return; |
| 1145 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1146 | if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 1147 | break; |
| 1148 | } |
| 1149 | #else |
| 1150 | unsigned long sic_status; |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1151 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1152 | sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); |
| 1153 | |
| 1154 | for (;; ivg++) { |
| 1155 | if (ivg >= ivg_stop) { |
| 1156 | atomic_inc(&num_spurious); |
| 1157 | return; |
| 1158 | } else if (sic_status & ivg->isrflag) |
| 1159 | break; |
| 1160 | } |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 1161 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1162 | vec = ivg->irqno; |
| 1163 | } |
| 1164 | asm_do_IRQ(vec, fp); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1165 | } |