blob: 9d2c9e7374dcef910d1b444a61b43ce560520dbc [file] [log] [blame]
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001/*
2 * drivers/dma/imx-dma.c
3 *
4 * This file contains a driver for the Freescale i.MX DMA engine
5 * found on i.MX1/21/27
6 *
7 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
Javier Martin9e15db72012-03-02 09:28:47 +01008 * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
Sascha Hauer1f1846c2010-10-06 10:25:55 +02009 *
10 * The code contained herein is licensed under the GNU General Public
11 * License. You may obtain a copy of the GNU General Public License
12 * Version 2 or later at the following locations:
13 *
14 * http://www.opensource.org/licenses/gpl-license.html
15 * http://www.gnu.org/copyleft/gpl.html
16 */
Thierry Reding73312052013-01-21 11:09:00 +010017#include <linux/err.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020018#include <linux/init.h>
19#include <linux/types.h>
20#include <linux/mm.h>
21#include <linux/interrupt.h>
22#include <linux/spinlock.h>
23#include <linux/device.h>
24#include <linux/dma-mapping.h>
25#include <linux/slab.h>
26#include <linux/platform_device.h>
Javier Martin6bd08122012-03-22 14:54:01 +010027#include <linux/clk.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020028#include <linux/dmaengine.h>
Paul Gortmaker5c45ad72011-07-31 16:14:17 -040029#include <linux/module.h>
Markus Pargmann290ad0f2013-05-26 11:53:20 +020030#include <linux/of_device.h>
31#include <linux/of_dma.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020032
33#include <asm/irq.h>
Arnd Bergmann82906b12012-08-24 15:14:29 +020034#include <linux/platform_data/dma-imx.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020035
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000036#include "dmaengine.h"
Javier Martin9e15db72012-03-02 09:28:47 +010037#define IMXDMA_MAX_CHAN_DESCRIPTORS 16
Javier Martin6bd08122012-03-22 14:54:01 +010038#define IMX_DMA_CHANNELS 16
39
Javier Martinf606ab82012-03-22 14:54:14 +010040#define IMX_DMA_2D_SLOTS 2
41#define IMX_DMA_2D_SLOT_A 0
42#define IMX_DMA_2D_SLOT_B 1
43
Javier Martin6bd08122012-03-22 14:54:01 +010044#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
45#define IMX_DMA_MEMSIZE_32 (0 << 4)
46#define IMX_DMA_MEMSIZE_8 (1 << 4)
47#define IMX_DMA_MEMSIZE_16 (2 << 4)
48#define IMX_DMA_TYPE_LINEAR (0 << 10)
49#define IMX_DMA_TYPE_2D (1 << 10)
50#define IMX_DMA_TYPE_FIFO (2 << 10)
51
52#define IMX_DMA_ERR_BURST (1 << 0)
53#define IMX_DMA_ERR_REQUEST (1 << 1)
54#define IMX_DMA_ERR_TRANSFER (1 << 2)
55#define IMX_DMA_ERR_BUFFER (1 << 3)
56#define IMX_DMA_ERR_TIMEOUT (1 << 4)
57
58#define DMA_DCR 0x00 /* Control Register */
59#define DMA_DISR 0x04 /* Interrupt status Register */
60#define DMA_DIMR 0x08 /* Interrupt mask Register */
61#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
62#define DMA_DRTOSR 0x10 /* Request timeout Register */
63#define DMA_DSESR 0x14 /* Transfer Error Status Register */
64#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
65#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
66#define DMA_WSRA 0x40 /* W-Size Register A */
67#define DMA_XSRA 0x44 /* X-Size Register A */
68#define DMA_YSRA 0x48 /* Y-Size Register A */
69#define DMA_WSRB 0x4c /* W-Size Register B */
70#define DMA_XSRB 0x50 /* X-Size Register B */
71#define DMA_YSRB 0x54 /* Y-Size Register B */
72#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
73#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
74#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
75#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
76#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
77#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
78#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
79#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
80#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
81
82#define DCR_DRST (1<<1)
83#define DCR_DEN (1<<0)
84#define DBTOCR_EN (1<<15)
85#define DBTOCR_CNT(x) ((x) & 0x7fff)
86#define CNTR_CNT(x) ((x) & 0xffffff)
87#define CCR_ACRPT (1<<14)
88#define CCR_DMOD_LINEAR (0x0 << 12)
89#define CCR_DMOD_2D (0x1 << 12)
90#define CCR_DMOD_FIFO (0x2 << 12)
91#define CCR_DMOD_EOBFIFO (0x3 << 12)
92#define CCR_SMOD_LINEAR (0x0 << 10)
93#define CCR_SMOD_2D (0x1 << 10)
94#define CCR_SMOD_FIFO (0x2 << 10)
95#define CCR_SMOD_EOBFIFO (0x3 << 10)
96#define CCR_MDIR_DEC (1<<9)
97#define CCR_MSEL_B (1<<8)
98#define CCR_DSIZ_32 (0x0 << 6)
99#define CCR_DSIZ_8 (0x1 << 6)
100#define CCR_DSIZ_16 (0x2 << 6)
101#define CCR_SSIZ_32 (0x0 << 4)
102#define CCR_SSIZ_8 (0x1 << 4)
103#define CCR_SSIZ_16 (0x2 << 4)
104#define CCR_REN (1<<3)
105#define CCR_RPT (1<<2)
106#define CCR_FRC (1<<1)
107#define CCR_CEN (1<<0)
108#define RTOR_EN (1<<15)
109#define RTOR_CLK (1<<14)
110#define RTOR_PSC (1<<13)
Javier Martin9e15db72012-03-02 09:28:47 +0100111
112enum imxdma_prep_type {
113 IMXDMA_DESC_MEMCPY,
114 IMXDMA_DESC_INTERLEAVED,
115 IMXDMA_DESC_SLAVE_SG,
116 IMXDMA_DESC_CYCLIC,
117};
118
Javier Martinf606ab82012-03-22 14:54:14 +0100119struct imx_dma_2d_config {
120 u16 xsr;
121 u16 ysr;
122 u16 wsr;
123 int count;
124};
125
Javier Martin9e15db72012-03-02 09:28:47 +0100126struct imxdma_desc {
127 struct list_head node;
128 struct dma_async_tx_descriptor desc;
129 enum dma_status status;
130 dma_addr_t src;
131 dma_addr_t dest;
132 size_t len;
Javier Martin2efc3442012-03-22 14:54:03 +0100133 enum dma_transfer_direction direction;
Javier Martin9e15db72012-03-02 09:28:47 +0100134 enum imxdma_prep_type type;
135 /* For memcpy and interleaved */
136 unsigned int config_port;
137 unsigned int config_mem;
138 /* For interleaved transfers */
139 unsigned int x;
140 unsigned int y;
141 unsigned int w;
142 /* For slave sg and cyclic */
143 struct scatterlist *sg;
144 unsigned int sgcount;
145};
146
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200147struct imxdma_channel {
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100148 int hw_chaining;
149 struct timer_list watchdog;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200150 struct imxdma_engine *imxdma;
151 unsigned int channel;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200152
Javier Martin9e15db72012-03-02 09:28:47 +0100153 struct tasklet_struct dma_tasklet;
154 struct list_head ld_free;
155 struct list_head ld_queue;
156 struct list_head ld_active;
157 int descs_allocated;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200158 enum dma_slave_buswidth word_size;
159 dma_addr_t per_address;
160 u32 watermark_level;
161 struct dma_chan chan;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200162 struct dma_async_tx_descriptor desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200163 enum dma_status status;
164 int dma_request;
165 struct scatterlist *sg_list;
Javier Martin359291a2012-03-22 14:54:06 +0100166 u32 ccr_from_device;
167 u32 ccr_to_device;
Javier Martinf606ab82012-03-22 14:54:14 +0100168 bool enabled_2d;
169 int slot_2d;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200170};
171
Shawn Guoe51d0f02012-09-15 21:11:28 +0800172enum imx_dma_type {
173 IMX1_DMA,
174 IMX21_DMA,
175 IMX27_DMA,
176};
177
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200178struct imxdma_engine {
179 struct device *dev;
Sascha Hauer1e070a62011-01-12 13:14:37 +0100180 struct device_dma_parameters dma_parms;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200181 struct dma_device dma_device;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100182 void __iomem *base;
Fabio Estevama2367db2012-07-03 15:33:29 -0300183 struct clk *dma_ahb;
184 struct clk *dma_ipg;
Javier Martinf606ab82012-03-22 14:54:14 +0100185 spinlock_t lock;
186 struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS];
Javier Martin6bd08122012-03-22 14:54:01 +0100187 struct imxdma_channel channel[IMX_DMA_CHANNELS];
Shawn Guoe51d0f02012-09-15 21:11:28 +0800188 enum imx_dma_type devtype;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200189};
190
Markus Pargmann290ad0f2013-05-26 11:53:20 +0200191struct imxdma_filter_data {
192 struct imxdma_engine *imxdma;
193 int request;
194};
195
Shawn Guoe51d0f02012-09-15 21:11:28 +0800196static struct platform_device_id imx_dma_devtype[] = {
197 {
198 .name = "imx1-dma",
199 .driver_data = IMX1_DMA,
200 }, {
201 .name = "imx21-dma",
202 .driver_data = IMX21_DMA,
203 }, {
204 .name = "imx27-dma",
205 .driver_data = IMX27_DMA,
206 }, {
207 /* sentinel */
208 }
209};
210MODULE_DEVICE_TABLE(platform, imx_dma_devtype);
211
Markus Pargmann290ad0f2013-05-26 11:53:20 +0200212static const struct of_device_id imx_dma_of_dev_id[] = {
213 {
214 .compatible = "fsl,imx1-dma",
215 .data = &imx_dma_devtype[IMX1_DMA],
216 }, {
217 .compatible = "fsl,imx21-dma",
218 .data = &imx_dma_devtype[IMX21_DMA],
219 }, {
220 .compatible = "fsl,imx27-dma",
221 .data = &imx_dma_devtype[IMX27_DMA],
222 }, {
223 /* sentinel */
224 }
225};
226MODULE_DEVICE_TABLE(of, imx_dma_of_dev_id);
227
Shawn Guoe51d0f02012-09-15 21:11:28 +0800228static inline int is_imx1_dma(struct imxdma_engine *imxdma)
229{
230 return imxdma->devtype == IMX1_DMA;
231}
232
233static inline int is_imx21_dma(struct imxdma_engine *imxdma)
234{
235 return imxdma->devtype == IMX21_DMA;
236}
237
238static inline int is_imx27_dma(struct imxdma_engine *imxdma)
239{
240 return imxdma->devtype == IMX27_DMA;
241}
242
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200243static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
244{
245 return container_of(chan, struct imxdma_channel, chan);
246}
247
Javier Martin9e15db72012-03-02 09:28:47 +0100248static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200249{
Javier Martin9e15db72012-03-02 09:28:47 +0100250 struct imxdma_desc *desc;
251
252 if (!list_empty(&imxdmac->ld_active)) {
253 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
254 node);
255 if (desc->type == IMXDMA_DESC_CYCLIC)
256 return true;
257 }
258 return false;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200259}
260
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200261
Javier Martincd5cf9d2012-03-22 14:54:12 +0100262
263static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
264 unsigned offset)
Javier Martin6bd08122012-03-22 14:54:01 +0100265{
Javier Martincd5cf9d2012-03-22 14:54:12 +0100266 __raw_writel(val, imxdma->base + offset);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200267}
268
Javier Martincd5cf9d2012-03-22 14:54:12 +0100269static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200270{
Javier Martincd5cf9d2012-03-22 14:54:12 +0100271 return __raw_readl(imxdma->base + offset);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200272}
273
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100274static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200275{
Shawn Guoe51d0f02012-09-15 21:11:28 +0800276 struct imxdma_engine *imxdma = imxdmac->imxdma;
277
278 if (is_imx27_dma(imxdma))
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100279 return imxdmac->hw_chaining;
Javier Martin6bd08122012-03-22 14:54:01 +0100280 else
281 return 0;
282}
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200283
Javier Martin6bd08122012-03-22 14:54:01 +0100284/*
285 * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
286 */
Javier Martina6cbb2d2012-03-22 14:54:11 +0100287static inline int imxdma_sg_next(struct imxdma_desc *d)
Javier Martin6bd08122012-03-22 14:54:01 +0100288{
Javier Martin2efc3442012-03-22 14:54:03 +0100289 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100290 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martina6cbb2d2012-03-22 14:54:11 +0100291 struct scatterlist *sg = d->sg;
Javier Martin6bd08122012-03-22 14:54:01 +0100292 unsigned long now;
293
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200294 now = min(d->len, sg_dma_len(sg));
Javier Martin6b0e2f52012-03-22 14:54:09 +0100295 if (d->len != IMX_DMA_LENGTH_LOOP)
296 d->len -= now;
Javier Martin6bd08122012-03-22 14:54:01 +0100297
Javier Martin2efc3442012-03-22 14:54:03 +0100298 if (d->direction == DMA_DEV_TO_MEM)
Javier Martincd5cf9d2012-03-22 14:54:12 +0100299 imx_dmav1_writel(imxdma, sg->dma_address,
300 DMA_DAR(imxdmac->channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100301 else
Javier Martincd5cf9d2012-03-22 14:54:12 +0100302 imx_dmav1_writel(imxdma, sg->dma_address,
303 DMA_SAR(imxdmac->channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100304
Javier Martincd5cf9d2012-03-22 14:54:12 +0100305 imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100306
Javier Martinf9b283a2012-03-22 14:54:13 +0100307 dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
308 "size 0x%08x\n", __func__, imxdmac->channel,
Javier Martincd5cf9d2012-03-22 14:54:12 +0100309 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
310 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
311 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
Javier Martin6bd08122012-03-22 14:54:01 +0100312
313 return now;
314}
315
Javier Martin2efc3442012-03-22 14:54:03 +0100316static void imxdma_enable_hw(struct imxdma_desc *d)
Javier Martin6bd08122012-03-22 14:54:01 +0100317{
Javier Martin2efc3442012-03-22 14:54:03 +0100318 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100319 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin6bd08122012-03-22 14:54:01 +0100320 int channel = imxdmac->channel;
321 unsigned long flags;
322
Javier Martinf9b283a2012-03-22 14:54:13 +0100323 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
Javier Martin6bd08122012-03-22 14:54:01 +0100324
Javier Martin6bd08122012-03-22 14:54:01 +0100325 local_irq_save(flags);
326
Javier Martincd5cf9d2012-03-22 14:54:12 +0100327 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
328 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
329 ~(1 << channel), DMA_DIMR);
330 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
331 CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100332
Shawn Guoe51d0f02012-09-15 21:11:28 +0800333 if (!is_imx1_dma(imxdma) &&
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100334 d->sg && imxdma_hw_chain(imxdmac)) {
Javier Martin833bc032012-03-22 14:54:07 +0100335 d->sg = sg_next(d->sg);
336 if (d->sg) {
Javier Martin6bd08122012-03-22 14:54:01 +0100337 u32 tmp;
Javier Martina6cbb2d2012-03-22 14:54:11 +0100338 imxdma_sg_next(d);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100339 tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
340 imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
341 DMA_CCR(channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100342 }
343 }
Javier Martin6bd08122012-03-22 14:54:01 +0100344
345 local_irq_restore(flags);
346}
347
348static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
349{
Javier Martincd5cf9d2012-03-22 14:54:12 +0100350 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin6bd08122012-03-22 14:54:01 +0100351 int channel = imxdmac->channel;
352 unsigned long flags;
353
Javier Martinf9b283a2012-03-22 14:54:13 +0100354 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
Javier Martin6bd08122012-03-22 14:54:01 +0100355
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100356 if (imxdma_hw_chain(imxdmac))
357 del_timer(&imxdmac->watchdog);
Javier Martin6bd08122012-03-22 14:54:01 +0100358
359 local_irq_save(flags);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100360 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
361 (1 << channel), DMA_DIMR);
362 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
363 ~CCR_CEN, DMA_CCR(channel));
364 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +0100365 local_irq_restore(flags);
366}
367
Javier Martin6bd08122012-03-22 14:54:01 +0100368static void imxdma_watchdog(unsigned long data)
369{
370 struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100371 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin6bd08122012-03-22 14:54:01 +0100372 int channel = imxdmac->channel;
373
Javier Martincd5cf9d2012-03-22 14:54:12 +0100374 imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100375
376 /* Tasklet watchdog error handler */
377 tasklet_schedule(&imxdmac->dma_tasklet);
Javier Martinf9b283a2012-03-22 14:54:13 +0100378 dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
379 imxdmac->channel);
Javier Martin6bd08122012-03-22 14:54:01 +0100380}
381
382static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
383{
384 struct imxdma_engine *imxdma = dev_id;
Javier Martin6bd08122012-03-22 14:54:01 +0100385 unsigned int err_mask;
386 int i, disr;
387 int errcode;
388
Javier Martincd5cf9d2012-03-22 14:54:12 +0100389 disr = imx_dmav1_readl(imxdma, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +0100390
Javier Martincd5cf9d2012-03-22 14:54:12 +0100391 err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
392 imx_dmav1_readl(imxdma, DMA_DRTOSR) |
393 imx_dmav1_readl(imxdma, DMA_DSESR) |
394 imx_dmav1_readl(imxdma, DMA_DBOSR);
Javier Martin6bd08122012-03-22 14:54:01 +0100395
396 if (!err_mask)
397 return IRQ_HANDLED;
398
Javier Martincd5cf9d2012-03-22 14:54:12 +0100399 imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +0100400
401 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
402 if (!(err_mask & (1 << i)))
403 continue;
Javier Martin6bd08122012-03-22 14:54:01 +0100404 errcode = 0;
405
Javier Martincd5cf9d2012-03-22 14:54:12 +0100406 if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
407 imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
Javier Martin6bd08122012-03-22 14:54:01 +0100408 errcode |= IMX_DMA_ERR_BURST;
409 }
Javier Martincd5cf9d2012-03-22 14:54:12 +0100410 if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
411 imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
Javier Martin6bd08122012-03-22 14:54:01 +0100412 errcode |= IMX_DMA_ERR_REQUEST;
413 }
Javier Martincd5cf9d2012-03-22 14:54:12 +0100414 if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
415 imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
Javier Martin6bd08122012-03-22 14:54:01 +0100416 errcode |= IMX_DMA_ERR_TRANSFER;
417 }
Javier Martincd5cf9d2012-03-22 14:54:12 +0100418 if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
419 imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
Javier Martin6bd08122012-03-22 14:54:01 +0100420 errcode |= IMX_DMA_ERR_BUFFER;
421 }
422 /* Tasklet error handler */
423 tasklet_schedule(&imxdma->channel[i].dma_tasklet);
424
Alexander Shiyan1d94fe02014-02-22 22:16:47 +0400425 dev_warn(imxdma->dev,
426 "DMA timeout on channel %d -%s%s%s%s\n", i,
427 errcode & IMX_DMA_ERR_BURST ? " burst" : "",
428 errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
429 errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
430 errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
Javier Martin6bd08122012-03-22 14:54:01 +0100431 }
432 return IRQ_HANDLED;
433}
434
435static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
436{
Javier Martincd5cf9d2012-03-22 14:54:12 +0100437 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin6bd08122012-03-22 14:54:01 +0100438 int chno = imxdmac->channel;
Javier Martin2efc3442012-03-22 14:54:03 +0100439 struct imxdma_desc *desc;
Michael Grzeschik5a276fa2013-09-17 15:56:07 +0200440 unsigned long flags;
Javier Martin6bd08122012-03-22 14:54:01 +0100441
Michael Grzeschik5a276fa2013-09-17 15:56:07 +0200442 spin_lock_irqsave(&imxdma->lock, flags);
Javier Martin833bc032012-03-22 14:54:07 +0100443 if (list_empty(&imxdmac->ld_active)) {
Michael Grzeschik5a276fa2013-09-17 15:56:07 +0200444 spin_unlock_irqrestore(&imxdma->lock, flags);
Javier Martin833bc032012-03-22 14:54:07 +0100445 goto out;
446 }
447
448 desc = list_first_entry(&imxdmac->ld_active,
449 struct imxdma_desc,
450 node);
Michael Grzeschik5a276fa2013-09-17 15:56:07 +0200451 spin_unlock_irqrestore(&imxdma->lock, flags);
Javier Martin833bc032012-03-22 14:54:07 +0100452
453 if (desc->sg) {
Javier Martin6bd08122012-03-22 14:54:01 +0100454 u32 tmp;
Javier Martin833bc032012-03-22 14:54:07 +0100455 desc->sg = sg_next(desc->sg);
Javier Martin6bd08122012-03-22 14:54:01 +0100456
Javier Martin833bc032012-03-22 14:54:07 +0100457 if (desc->sg) {
Javier Martina6cbb2d2012-03-22 14:54:11 +0100458 imxdma_sg_next(desc);
Javier Martin6bd08122012-03-22 14:54:01 +0100459
Javier Martincd5cf9d2012-03-22 14:54:12 +0100460 tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100461
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100462 if (imxdma_hw_chain(imxdmac)) {
Javier Martin6bd08122012-03-22 14:54:01 +0100463 /* FIXME: The timeout should probably be
464 * configurable
465 */
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100466 mod_timer(&imxdmac->watchdog,
Javier Martin6bd08122012-03-22 14:54:01 +0100467 jiffies + msecs_to_jiffies(500));
468
469 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100470 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100471 } else {
Javier Martincd5cf9d2012-03-22 14:54:12 +0100472 imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
473 DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100474 tmp |= CCR_CEN;
475 }
476
Javier Martincd5cf9d2012-03-22 14:54:12 +0100477 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100478
479 if (imxdma_chan_is_doing_cyclic(imxdmac))
480 /* Tasklet progression */
481 tasklet_schedule(&imxdmac->dma_tasklet);
482
483 return;
484 }
485
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100486 if (imxdma_hw_chain(imxdmac)) {
487 del_timer(&imxdmac->watchdog);
Javier Martin6bd08122012-03-22 14:54:01 +0100488 return;
489 }
490 }
491
Javier Martin2efc3442012-03-22 14:54:03 +0100492out:
Javier Martincd5cf9d2012-03-22 14:54:12 +0100493 imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100494 /* Tasklet irq */
Javier Martin9e15db72012-03-02 09:28:47 +0100495 tasklet_schedule(&imxdmac->dma_tasklet);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200496}
497
Javier Martin6bd08122012-03-22 14:54:01 +0100498static irqreturn_t dma_irq_handler(int irq, void *dev_id)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200499{
Javier Martin6bd08122012-03-22 14:54:01 +0100500 struct imxdma_engine *imxdma = dev_id;
Javier Martin6bd08122012-03-22 14:54:01 +0100501 int i, disr;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200502
Shawn Guoe51d0f02012-09-15 21:11:28 +0800503 if (!is_imx1_dma(imxdma))
Javier Martin6bd08122012-03-22 14:54:01 +0100504 imxdma_err_handler(irq, dev_id);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200505
Javier Martincd5cf9d2012-03-22 14:54:12 +0100506 disr = imx_dmav1_readl(imxdma, DMA_DISR);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200507
Javier Martinf9b283a2012-03-22 14:54:13 +0100508 dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
Javier Martin6bd08122012-03-22 14:54:01 +0100509
Javier Martincd5cf9d2012-03-22 14:54:12 +0100510 imx_dmav1_writel(imxdma, disr, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +0100511 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100512 if (disr & (1 << i))
Javier Martin6bd08122012-03-22 14:54:01 +0100513 dma_irq_handle_channel(&imxdma->channel[i]);
Javier Martin6bd08122012-03-22 14:54:01 +0100514 }
515
516 return IRQ_HANDLED;
Javier Martin9e15db72012-03-02 09:28:47 +0100517}
518
519static int imxdma_xfer_desc(struct imxdma_desc *d)
520{
521 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
Javier Martin3b4b6df2012-03-22 14:54:04 +0100522 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martinf606ab82012-03-22 14:54:14 +0100523 int slot = -1;
524 int i;
Javier Martin9e15db72012-03-02 09:28:47 +0100525
526 /* Configure and enable */
527 switch (d->type) {
Javier Martinf606ab82012-03-22 14:54:14 +0100528 case IMXDMA_DESC_INTERLEAVED:
529 /* Try to get a free 2D slot */
Javier Martinf606ab82012-03-22 14:54:14 +0100530 for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
531 if ((imxdma->slots_2d[i].count > 0) &&
532 ((imxdma->slots_2d[i].xsr != d->x) ||
533 (imxdma->slots_2d[i].ysr != d->y) ||
534 (imxdma->slots_2d[i].wsr != d->w)))
535 continue;
536 slot = i;
537 break;
538 }
Michael Grzeschik5a276fa2013-09-17 15:56:07 +0200539 if (slot < 0)
Javier Martinf606ab82012-03-22 14:54:14 +0100540 return -EBUSY;
541
542 imxdma->slots_2d[slot].xsr = d->x;
543 imxdma->slots_2d[slot].ysr = d->y;
544 imxdma->slots_2d[slot].wsr = d->w;
545 imxdma->slots_2d[slot].count++;
546
547 imxdmac->slot_2d = slot;
548 imxdmac->enabled_2d = true;
Javier Martinf606ab82012-03-22 14:54:14 +0100549
550 if (slot == IMX_DMA_2D_SLOT_A) {
551 d->config_mem &= ~CCR_MSEL_B;
552 d->config_port &= ~CCR_MSEL_B;
553 imx_dmav1_writel(imxdma, d->x, DMA_XSRA);
554 imx_dmav1_writel(imxdma, d->y, DMA_YSRA);
555 imx_dmav1_writel(imxdma, d->w, DMA_WSRA);
556 } else {
557 d->config_mem |= CCR_MSEL_B;
558 d->config_port |= CCR_MSEL_B;
559 imx_dmav1_writel(imxdma, d->x, DMA_XSRB);
560 imx_dmav1_writel(imxdma, d->y, DMA_YSRB);
561 imx_dmav1_writel(imxdma, d->w, DMA_WSRB);
562 }
563 /*
564 * We fall-through here intentionally, since a 2D transfer is
565 * similar to MEMCPY just adding the 2D slot configuration.
566 */
Javier Martin9e15db72012-03-02 09:28:47 +0100567 case IMXDMA_DESC_MEMCPY:
Javier Martincd5cf9d2012-03-22 14:54:12 +0100568 imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
569 imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
570 imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
Javier Martin3b4b6df2012-03-22 14:54:04 +0100571 DMA_CCR(imxdmac->channel));
572
Javier Martincd5cf9d2012-03-22 14:54:12 +0100573 imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
Javier Martin3b4b6df2012-03-22 14:54:04 +0100574
Russell Kingac806a12013-10-31 00:40:30 +0000575 dev_dbg(imxdma->dev,
576 "%s channel: %d dest=0x%08llx src=0x%08llx dma_length=%zu\n",
577 __func__, imxdmac->channel,
578 (unsigned long long)d->dest,
579 (unsigned long long)d->src, d->len);
Javier Martin3b4b6df2012-03-22 14:54:04 +0100580
581 break;
Javier Martin6bd08122012-03-22 14:54:01 +0100582 /* Cyclic transfer is the same as slave_sg with special sg configuration. */
Javier Martin9e15db72012-03-02 09:28:47 +0100583 case IMXDMA_DESC_CYCLIC:
Javier Martin9e15db72012-03-02 09:28:47 +0100584 case IMXDMA_DESC_SLAVE_SG:
Javier Martin359291a2012-03-22 14:54:06 +0100585 if (d->direction == DMA_DEV_TO_MEM) {
Javier Martincd5cf9d2012-03-22 14:54:12 +0100586 imx_dmav1_writel(imxdma, imxdmac->per_address,
Javier Martin359291a2012-03-22 14:54:06 +0100587 DMA_SAR(imxdmac->channel));
Javier Martincd5cf9d2012-03-22 14:54:12 +0100588 imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
Javier Martin359291a2012-03-22 14:54:06 +0100589 DMA_CCR(imxdmac->channel));
590
Russell Kingac806a12013-10-31 00:40:30 +0000591 dev_dbg(imxdma->dev,
592 "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (dev2mem)\n",
593 __func__, imxdmac->channel,
594 d->sg, d->sgcount, d->len,
595 (unsigned long long)imxdmac->per_address);
Javier Martin359291a2012-03-22 14:54:06 +0100596 } else if (d->direction == DMA_MEM_TO_DEV) {
Javier Martincd5cf9d2012-03-22 14:54:12 +0100597 imx_dmav1_writel(imxdma, imxdmac->per_address,
Javier Martin359291a2012-03-22 14:54:06 +0100598 DMA_DAR(imxdmac->channel));
Javier Martincd5cf9d2012-03-22 14:54:12 +0100599 imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
Javier Martin359291a2012-03-22 14:54:06 +0100600 DMA_CCR(imxdmac->channel));
601
Russell Kingac806a12013-10-31 00:40:30 +0000602 dev_dbg(imxdma->dev,
603 "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (mem2dev)\n",
604 __func__, imxdmac->channel,
605 d->sg, d->sgcount, d->len,
606 (unsigned long long)imxdmac->per_address);
Javier Martin359291a2012-03-22 14:54:06 +0100607 } else {
608 dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
609 __func__, imxdmac->channel);
610 return -EINVAL;
611 }
612
Javier Martina6cbb2d2012-03-22 14:54:11 +0100613 imxdma_sg_next(d);
Javier Martin359291a2012-03-22 14:54:06 +0100614
Javier Martin9e15db72012-03-02 09:28:47 +0100615 break;
616 default:
617 return -EINVAL;
618 }
Javier Martin2efc3442012-03-22 14:54:03 +0100619 imxdma_enable_hw(d);
Javier Martin9e15db72012-03-02 09:28:47 +0100620 return 0;
621}
622
623static void imxdma_tasklet(unsigned long data)
624{
625 struct imxdma_channel *imxdmac = (void *)data;
626 struct imxdma_engine *imxdma = imxdmac->imxdma;
627 struct imxdma_desc *desc;
Michael Grzeschik5a276fa2013-09-17 15:56:07 +0200628 unsigned long flags;
Javier Martin9e15db72012-03-02 09:28:47 +0100629
Michael Grzeschik5a276fa2013-09-17 15:56:07 +0200630 spin_lock_irqsave(&imxdma->lock, flags);
Javier Martin9e15db72012-03-02 09:28:47 +0100631
632 if (list_empty(&imxdmac->ld_active)) {
633 /* Someone might have called terminate all */
Michael Grzeschikfcaaba62013-09-17 15:56:08 +0200634 spin_unlock_irqrestore(&imxdma->lock, flags);
635 return;
Javier Martin9e15db72012-03-02 09:28:47 +0100636 }
637 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
638
Masanari Iidad73111c2012-08-04 23:37:53 +0900639 /* If we are dealing with a cyclic descriptor, keep it on ld_active
640 * and dont mark the descriptor as complete.
Vinod Koul60f29512012-04-20 15:28:07 +0530641 * Only in non-cyclic cases it would be marked as complete
642 */
Javier Martin9e15db72012-03-02 09:28:47 +0100643 if (imxdma_chan_is_doing_cyclic(imxdmac))
644 goto out;
Vinod Koul60f29512012-04-20 15:28:07 +0530645 else
646 dma_cookie_complete(&desc->desc);
Javier Martin9e15db72012-03-02 09:28:47 +0100647
Javier Martinf606ab82012-03-22 14:54:14 +0100648 /* Free 2D slot if it was an interleaved transfer */
649 if (imxdmac->enabled_2d) {
650 imxdma->slots_2d[imxdmac->slot_2d].count--;
651 imxdmac->enabled_2d = false;
652 }
653
Javier Martin9e15db72012-03-02 09:28:47 +0100654 list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
655
656 if (!list_empty(&imxdmac->ld_queue)) {
657 desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc,
658 node);
659 list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
660 if (imxdma_xfer_desc(desc) < 0)
661 dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
662 __func__, imxdmac->channel);
663 }
664out:
Michael Grzeschik5a276fa2013-09-17 15:56:07 +0200665 spin_unlock_irqrestore(&imxdma->lock, flags);
Michael Grzeschikfcaaba62013-09-17 15:56:08 +0200666
667 if (desc->desc.callback)
668 desc->desc.callback(desc->desc.callback_param);
669
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200670}
671
672static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
673 unsigned long arg)
674{
675 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
676 struct dma_slave_config *dmaengine_cfg = (void *)arg;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100677 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100678 unsigned long flags;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200679 unsigned int mode = 0;
680
681 switch (cmd) {
682 case DMA_TERMINATE_ALL:
Javier Martin6bd08122012-03-22 14:54:01 +0100683 imxdma_disable_hw(imxdmac);
Javier Martin9e15db72012-03-02 09:28:47 +0100684
Javier Martinf606ab82012-03-22 14:54:14 +0100685 spin_lock_irqsave(&imxdma->lock, flags);
Javier Martin9e15db72012-03-02 09:28:47 +0100686 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
687 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
Javier Martinf606ab82012-03-22 14:54:14 +0100688 spin_unlock_irqrestore(&imxdma->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200689 return 0;
690 case DMA_SLAVE_CONFIG:
Vinod Kouldb8196d2011-10-13 22:34:23 +0530691 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200692 imxdmac->per_address = dmaengine_cfg->src_addr;
693 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
694 imxdmac->word_size = dmaengine_cfg->src_addr_width;
695 } else {
696 imxdmac->per_address = dmaengine_cfg->dst_addr;
697 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
698 imxdmac->word_size = dmaengine_cfg->dst_addr_width;
699 }
700
701 switch (imxdmac->word_size) {
702 case DMA_SLAVE_BUSWIDTH_1_BYTE:
703 mode = IMX_DMA_MEMSIZE_8;
704 break;
705 case DMA_SLAVE_BUSWIDTH_2_BYTES:
706 mode = IMX_DMA_MEMSIZE_16;
707 break;
708 default:
709 case DMA_SLAVE_BUSWIDTH_4_BYTES:
710 mode = IMX_DMA_MEMSIZE_32;
711 break;
712 }
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200713
Javier Martinbef2a8d2012-10-30 15:58:50 +0000714 imxdmac->hw_chaining = 0;
715
Javier Martin359291a2012-03-22 14:54:06 +0100716 imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
Javier Martinbdc0c752012-03-22 14:54:05 +0100717 ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
718 CCR_REN;
Javier Martin359291a2012-03-22 14:54:06 +0100719 imxdmac->ccr_to_device =
Javier Martinbdc0c752012-03-22 14:54:05 +0100720 (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
721 ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100722 imx_dmav1_writel(imxdma, imxdmac->dma_request,
Javier Martinbdc0c752012-03-22 14:54:05 +0100723 DMA_RSSR(imxdmac->channel));
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200724
Javier Martin6bd08122012-03-22 14:54:01 +0100725 /* Set burst length */
Javier Martincd5cf9d2012-03-22 14:54:12 +0100726 imx_dmav1_writel(imxdma, imxdmac->watermark_level *
727 imxdmac->word_size, DMA_BLR(imxdmac->channel));
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200728
729 return 0;
730 default:
731 return -ENOSYS;
732 }
733
734 return -EINVAL;
735}
736
737static enum dma_status imxdma_tx_status(struct dma_chan *chan,
738 dma_cookie_t cookie,
739 struct dma_tx_state *txstate)
740{
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000741 return dma_cookie_status(chan, cookie, txstate);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200742}
743
744static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
745{
746 struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
Javier Martinf606ab82012-03-22 14:54:14 +0100747 struct imxdma_engine *imxdma = imxdmac->imxdma;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200748 dma_cookie_t cookie;
Javier Martin9e15db72012-03-02 09:28:47 +0100749 unsigned long flags;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200750
Javier Martinf606ab82012-03-22 14:54:14 +0100751 spin_lock_irqsave(&imxdma->lock, flags);
Javier Martin660cd0d2012-03-22 14:54:15 +0100752 list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000753 cookie = dma_cookie_assign(tx);
Javier Martinf606ab82012-03-22 14:54:14 +0100754 spin_unlock_irqrestore(&imxdma->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200755
756 return cookie;
757}
758
759static int imxdma_alloc_chan_resources(struct dma_chan *chan)
760{
761 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
762 struct imx_dma_data *data = chan->private;
763
Javier Martin6c05f092012-02-28 17:08:17 +0100764 if (data != NULL)
765 imxdmac->dma_request = data->dma_request;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200766
Javier Martin9e15db72012-03-02 09:28:47 +0100767 while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
768 struct imxdma_desc *desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200769
Javier Martin9e15db72012-03-02 09:28:47 +0100770 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
771 if (!desc)
772 break;
773 __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor));
774 dma_async_tx_descriptor_init(&desc->desc, chan);
775 desc->desc.tx_submit = imxdma_tx_submit;
776 /* txd.flags will be overwritten in prep funcs */
777 desc->desc.flags = DMA_CTRL_ACK;
Vinod Koul3ded1ad2013-10-16 14:06:24 +0530778 desc->status = DMA_COMPLETE;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200779
Javier Martin9e15db72012-03-02 09:28:47 +0100780 list_add_tail(&desc->node, &imxdmac->ld_free);
781 imxdmac->descs_allocated++;
782 }
783
784 if (!imxdmac->descs_allocated)
785 return -ENOMEM;
786
787 return imxdmac->descs_allocated;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200788}
789
790static void imxdma_free_chan_resources(struct dma_chan *chan)
791{
792 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
Javier Martinf606ab82012-03-22 14:54:14 +0100793 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100794 struct imxdma_desc *desc, *_desc;
795 unsigned long flags;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200796
Javier Martinf606ab82012-03-22 14:54:14 +0100797 spin_lock_irqsave(&imxdma->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200798
Javier Martin6bd08122012-03-22 14:54:01 +0100799 imxdma_disable_hw(imxdmac);
Javier Martin9e15db72012-03-02 09:28:47 +0100800 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
801 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
802
Javier Martinf606ab82012-03-22 14:54:14 +0100803 spin_unlock_irqrestore(&imxdma->lock, flags);
Javier Martin9e15db72012-03-02 09:28:47 +0100804
805 list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
806 kfree(desc);
807 imxdmac->descs_allocated--;
808 }
809 INIT_LIST_HEAD(&imxdmac->ld_free);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200810
Sachin Kamat06f8db42013-09-02 13:21:18 +0530811 kfree(imxdmac->sg_list);
812 imxdmac->sg_list = NULL;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200813}
814
815static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
816 struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +0530817 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500818 unsigned long flags, void *context)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200819{
820 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
821 struct scatterlist *sg;
Javier Martin9e15db72012-03-02 09:28:47 +0100822 int i, dma_length = 0;
823 struct imxdma_desc *desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200824
Javier Martin9e15db72012-03-02 09:28:47 +0100825 if (list_empty(&imxdmac->ld_free) ||
826 imxdma_chan_is_doing_cyclic(imxdmac))
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200827 return NULL;
828
Javier Martin9e15db72012-03-02 09:28:47 +0100829 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200830
831 for_each_sg(sgl, sg, sg_len, i) {
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200832 dma_length += sg_dma_len(sg);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200833 }
834
Sascha Hauerd07102a2011-01-12 14:13:23 +0100835 switch (imxdmac->word_size) {
836 case DMA_SLAVE_BUSWIDTH_4_BYTES:
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200837 if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3)
Sascha Hauerd07102a2011-01-12 14:13:23 +0100838 return NULL;
839 break;
840 case DMA_SLAVE_BUSWIDTH_2_BYTES:
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200841 if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1)
Sascha Hauerd07102a2011-01-12 14:13:23 +0100842 return NULL;
843 break;
844 case DMA_SLAVE_BUSWIDTH_1_BYTE:
845 break;
846 default:
847 return NULL;
848 }
849
Javier Martin9e15db72012-03-02 09:28:47 +0100850 desc->type = IMXDMA_DESC_SLAVE_SG;
851 desc->sg = sgl;
852 desc->sgcount = sg_len;
853 desc->len = dma_length;
Javier Martin2efc3442012-03-22 14:54:03 +0100854 desc->direction = direction;
Javier Martin9e15db72012-03-02 09:28:47 +0100855 if (direction == DMA_DEV_TO_MEM) {
Javier Martin9e15db72012-03-02 09:28:47 +0100856 desc->src = imxdmac->per_address;
857 } else {
Javier Martin9e15db72012-03-02 09:28:47 +0100858 desc->dest = imxdmac->per_address;
859 }
860 desc->desc.callback = NULL;
861 desc->desc.callback_param = NULL;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200862
Javier Martin9e15db72012-03-02 09:28:47 +0100863 return &desc->desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200864}
865
866static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
867 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500868 size_t period_len, enum dma_transfer_direction direction,
Laurent Pinchart31c1e5a2014-08-01 12:20:10 +0200869 unsigned long flags)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200870{
871 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
872 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100873 struct imxdma_desc *desc;
874 int i;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200875 unsigned int periods = buf_len / period_len;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200876
Russell Kingac806a12013-10-31 00:40:30 +0000877 dev_dbg(imxdma->dev, "%s channel: %d buf_len=%zu period_len=%zu\n",
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200878 __func__, imxdmac->channel, buf_len, period_len);
879
Javier Martin9e15db72012-03-02 09:28:47 +0100880 if (list_empty(&imxdmac->ld_free) ||
881 imxdma_chan_is_doing_cyclic(imxdmac))
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200882 return NULL;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200883
Javier Martin9e15db72012-03-02 09:28:47 +0100884 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200885
Syam Sidhardhan96a37132013-02-25 04:46:26 +0530886 kfree(imxdmac->sg_list);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200887
888 imxdmac->sg_list = kcalloc(periods + 1,
Michael Grzeschikedc530f2013-09-17 15:56:06 +0200889 sizeof(struct scatterlist), GFP_ATOMIC);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200890 if (!imxdmac->sg_list)
891 return NULL;
892
893 sg_init_table(imxdmac->sg_list, periods);
894
895 for (i = 0; i < periods; i++) {
896 imxdmac->sg_list[i].page_link = 0;
897 imxdmac->sg_list[i].offset = 0;
898 imxdmac->sg_list[i].dma_address = dma_addr;
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200899 sg_dma_len(&imxdmac->sg_list[i]) = period_len;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200900 dma_addr += period_len;
901 }
902
903 /* close the loop */
904 imxdmac->sg_list[periods].offset = 0;
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200905 sg_dma_len(&imxdmac->sg_list[periods]) = 0;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200906 imxdmac->sg_list[periods].page_link =
907 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
908
Javier Martin9e15db72012-03-02 09:28:47 +0100909 desc->type = IMXDMA_DESC_CYCLIC;
910 desc->sg = imxdmac->sg_list;
911 desc->sgcount = periods;
912 desc->len = IMX_DMA_LENGTH_LOOP;
Javier Martin2efc3442012-03-22 14:54:03 +0100913 desc->direction = direction;
Javier Martin9e15db72012-03-02 09:28:47 +0100914 if (direction == DMA_DEV_TO_MEM) {
Javier Martin9e15db72012-03-02 09:28:47 +0100915 desc->src = imxdmac->per_address;
916 } else {
Javier Martin9e15db72012-03-02 09:28:47 +0100917 desc->dest = imxdmac->per_address;
918 }
919 desc->desc.callback = NULL;
920 desc->desc.callback_param = NULL;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200921
Javier Martin9e15db72012-03-02 09:28:47 +0100922 return &desc->desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200923}
924
Javier Martin6c05f092012-02-28 17:08:17 +0100925static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
926 struct dma_chan *chan, dma_addr_t dest,
927 dma_addr_t src, size_t len, unsigned long flags)
928{
929 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
930 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100931 struct imxdma_desc *desc;
Javier Martin6c05f092012-02-28 17:08:17 +0100932
Russell Kingac806a12013-10-31 00:40:30 +0000933 dev_dbg(imxdma->dev, "%s channel: %d src=0x%llx dst=0x%llx len=%zu\n",
934 __func__, imxdmac->channel, (unsigned long long)src,
935 (unsigned long long)dest, len);
Javier Martin6c05f092012-02-28 17:08:17 +0100936
Javier Martin9e15db72012-03-02 09:28:47 +0100937 if (list_empty(&imxdmac->ld_free) ||
938 imxdma_chan_is_doing_cyclic(imxdmac))
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200939 return NULL;
940
Javier Martin9e15db72012-03-02 09:28:47 +0100941 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
Javier Martin6c05f092012-02-28 17:08:17 +0100942
Javier Martin9e15db72012-03-02 09:28:47 +0100943 desc->type = IMXDMA_DESC_MEMCPY;
944 desc->src = src;
945 desc->dest = dest;
946 desc->len = len;
Javier Martin2efc3442012-03-22 14:54:03 +0100947 desc->direction = DMA_MEM_TO_MEM;
Javier Martin9e15db72012-03-02 09:28:47 +0100948 desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
949 desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
950 desc->desc.callback = NULL;
951 desc->desc.callback_param = NULL;
952
953 return &desc->desc;
Javier Martin6c05f092012-02-28 17:08:17 +0100954}
955
Javier Martinf606ab82012-03-22 14:54:14 +0100956static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved(
957 struct dma_chan *chan, struct dma_interleaved_template *xt,
958 unsigned long flags)
959{
960 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
961 struct imxdma_engine *imxdma = imxdmac->imxdma;
962 struct imxdma_desc *desc;
963
Russell Kingac806a12013-10-31 00:40:30 +0000964 dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%llx dst_start=0x%llx\n"
965 " src_sgl=%s dst_sgl=%s numf=%zu frame_size=%zu\n", __func__,
966 imxdmac->channel, (unsigned long long)xt->src_start,
967 (unsigned long long) xt->dst_start,
Javier Martinf606ab82012-03-22 14:54:14 +0100968 xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
969 xt->numf, xt->frame_size);
970
971 if (list_empty(&imxdmac->ld_free) ||
972 imxdma_chan_is_doing_cyclic(imxdmac))
973 return NULL;
974
975 if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM)
976 return NULL;
977
978 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
979
980 desc->type = IMXDMA_DESC_INTERLEAVED;
981 desc->src = xt->src_start;
982 desc->dest = xt->dst_start;
983 desc->x = xt->sgl[0].size;
984 desc->y = xt->numf;
985 desc->w = xt->sgl[0].icg + desc->x;
986 desc->len = desc->x * desc->y;
987 desc->direction = DMA_MEM_TO_MEM;
988 desc->config_port = IMX_DMA_MEMSIZE_32;
989 desc->config_mem = IMX_DMA_MEMSIZE_32;
990 if (xt->src_sgl)
991 desc->config_mem |= IMX_DMA_TYPE_2D;
992 if (xt->dst_sgl)
993 desc->config_port |= IMX_DMA_TYPE_2D;
994 desc->desc.callback = NULL;
995 desc->desc.callback_param = NULL;
996
997 return &desc->desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200998}
999
1000static void imxdma_issue_pending(struct dma_chan *chan)
1001{
Sascha Hauer5b316872012-01-09 10:32:49 +01001002 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
Javier Martin9e15db72012-03-02 09:28:47 +01001003 struct imxdma_engine *imxdma = imxdmac->imxdma;
1004 struct imxdma_desc *desc;
1005 unsigned long flags;
Sascha Hauer5b316872012-01-09 10:32:49 +01001006
Javier Martinf606ab82012-03-22 14:54:14 +01001007 spin_lock_irqsave(&imxdma->lock, flags);
Javier Martin9e15db72012-03-02 09:28:47 +01001008 if (list_empty(&imxdmac->ld_active) &&
1009 !list_empty(&imxdmac->ld_queue)) {
1010 desc = list_first_entry(&imxdmac->ld_queue,
1011 struct imxdma_desc, node);
1012
1013 if (imxdma_xfer_desc(desc) < 0) {
1014 dev_warn(imxdma->dev,
1015 "%s: channel: %d couldn't issue DMA xfer\n",
1016 __func__, imxdmac->channel);
1017 } else {
1018 list_move_tail(imxdmac->ld_queue.next,
1019 &imxdmac->ld_active);
1020 }
1021 }
Javier Martinf606ab82012-03-22 14:54:14 +01001022 spin_unlock_irqrestore(&imxdma->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001023}
1024
Markus Pargmann290ad0f2013-05-26 11:53:20 +02001025static bool imxdma_filter_fn(struct dma_chan *chan, void *param)
1026{
1027 struct imxdma_filter_data *fdata = param;
1028 struct imxdma_channel *imxdma_chan = to_imxdma_chan(chan);
1029
1030 if (chan->device->dev != fdata->imxdma->dev)
1031 return false;
1032
1033 imxdma_chan->dma_request = fdata->request;
1034 chan->private = NULL;
1035
1036 return true;
1037}
1038
1039static struct dma_chan *imxdma_xlate(struct of_phandle_args *dma_spec,
1040 struct of_dma *ofdma)
1041{
1042 int count = dma_spec->args_count;
1043 struct imxdma_engine *imxdma = ofdma->of_dma_data;
1044 struct imxdma_filter_data fdata = {
1045 .imxdma = imxdma,
1046 };
1047
1048 if (count != 1)
1049 return NULL;
1050
1051 fdata.request = dma_spec->args[0];
1052
1053 return dma_request_channel(imxdma->dma_device.cap_mask,
1054 imxdma_filter_fn, &fdata);
1055}
1056
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001057static int __init imxdma_probe(struct platform_device *pdev)
Javier Martin6bd08122012-03-22 14:54:01 +01001058 {
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001059 struct imxdma_engine *imxdma;
Shawn Guo73930eb2012-09-15 15:57:00 +08001060 struct resource *res;
Markus Pargmann290ad0f2013-05-26 11:53:20 +02001061 const struct of_device_id *of_id;
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001062 int ret, i;
Shawn Guo73930eb2012-09-15 15:57:00 +08001063 int irq, irq_err;
Javier Martin6bd08122012-03-22 14:54:01 +01001064
Markus Pargmann290ad0f2013-05-26 11:53:20 +02001065 of_id = of_match_device(imx_dma_of_dev_id, &pdev->dev);
1066 if (of_id)
1067 pdev->id_entry = of_id->data;
1068
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001069 imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001070 if (!imxdma)
1071 return -ENOMEM;
1072
Markus Pargmann5c6b3e72013-05-26 11:53:21 +02001073 imxdma->dev = &pdev->dev;
Shawn Guoe51d0f02012-09-15 21:11:28 +08001074 imxdma->devtype = pdev->id_entry->driver_data;
1075
Shawn Guo73930eb2012-09-15 15:57:00 +08001076 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Thierry Reding73312052013-01-21 11:09:00 +01001077 imxdma->base = devm_ioremap_resource(&pdev->dev, res);
1078 if (IS_ERR(imxdma->base))
1079 return PTR_ERR(imxdma->base);
Shawn Guo73930eb2012-09-15 15:57:00 +08001080
1081 irq = platform_get_irq(pdev, 0);
1082 if (irq < 0)
1083 return irq;
Javier Martincd5cf9d2012-03-22 14:54:12 +01001084
Fabio Estevama2367db2012-07-03 15:33:29 -03001085 imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg");
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001086 if (IS_ERR(imxdma->dma_ipg))
1087 return PTR_ERR(imxdma->dma_ipg);
Fabio Estevama2367db2012-07-03 15:33:29 -03001088
1089 imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb");
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001090 if (IS_ERR(imxdma->dma_ahb))
1091 return PTR_ERR(imxdma->dma_ahb);
Fabio Estevama2367db2012-07-03 15:33:29 -03001092
1093 clk_prepare_enable(imxdma->dma_ipg);
1094 clk_prepare_enable(imxdma->dma_ahb);
Javier Martin6bd08122012-03-22 14:54:01 +01001095
1096 /* reset DMA module */
Javier Martincd5cf9d2012-03-22 14:54:12 +01001097 imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
Javier Martin6bd08122012-03-22 14:54:01 +01001098
Shawn Guoe51d0f02012-09-15 21:11:28 +08001099 if (is_imx1_dma(imxdma)) {
Shawn Guo73930eb2012-09-15 15:57:00 +08001100 ret = devm_request_irq(&pdev->dev, irq,
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001101 dma_irq_handler, 0, "DMA", imxdma);
Javier Martin6bd08122012-03-22 14:54:01 +01001102 if (ret) {
Javier Martinf9b283a2012-03-22 14:54:13 +01001103 dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001104 goto err;
Javier Martin6bd08122012-03-22 14:54:01 +01001105 }
1106
Shawn Guo73930eb2012-09-15 15:57:00 +08001107 irq_err = platform_get_irq(pdev, 1);
1108 if (irq_err < 0) {
1109 ret = irq_err;
1110 goto err;
1111 }
1112
1113 ret = devm_request_irq(&pdev->dev, irq_err,
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001114 imxdma_err_handler, 0, "DMA", imxdma);
Javier Martin6bd08122012-03-22 14:54:01 +01001115 if (ret) {
Javier Martinf9b283a2012-03-22 14:54:13 +01001116 dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001117 goto err;
Javier Martin6bd08122012-03-22 14:54:01 +01001118 }
1119 }
1120
1121 /* enable DMA module */
Javier Martincd5cf9d2012-03-22 14:54:12 +01001122 imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
Javier Martin6bd08122012-03-22 14:54:01 +01001123
1124 /* clear all interrupts */
Javier Martincd5cf9d2012-03-22 14:54:12 +01001125 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +01001126
1127 /* disable interrupts */
Javier Martincd5cf9d2012-03-22 14:54:12 +01001128 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001129
1130 INIT_LIST_HEAD(&imxdma->dma_device.channels);
1131
Sascha Hauerf8a356f2011-01-31 11:35:59 +01001132 dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
1133 dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
Javier Martin6c05f092012-02-28 17:08:17 +01001134 dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
Javier Martinf606ab82012-03-22 14:54:14 +01001135 dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask);
1136
1137 /* Initialize 2D global parameters */
1138 for (i = 0; i < IMX_DMA_2D_SLOTS; i++)
1139 imxdma->slots_2d[i].count = 0;
1140
1141 spin_lock_init(&imxdma->lock);
Sascha Hauerf8a356f2011-01-31 11:35:59 +01001142
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001143 /* Initialize channel parameters */
Javier Martin6bd08122012-03-22 14:54:01 +01001144 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001145 struct imxdma_channel *imxdmac = &imxdma->channel[i];
1146
Shawn Guoe51d0f02012-09-15 21:11:28 +08001147 if (!is_imx1_dma(imxdma)) {
Shawn Guo73930eb2012-09-15 15:57:00 +08001148 ret = devm_request_irq(&pdev->dev, irq + i,
Javier Martin6bd08122012-03-22 14:54:01 +01001149 dma_irq_handler, 0, "DMA", imxdma);
1150 if (ret) {
Javier Martinf9b283a2012-03-22 14:54:13 +01001151 dev_warn(imxdma->dev, "Can't register IRQ %d "
1152 "for DMA channel %d\n",
Shawn Guo73930eb2012-09-15 15:57:00 +08001153 irq + i, i);
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001154 goto err;
Javier Martin6bd08122012-03-22 14:54:01 +01001155 }
Javier Martin2d9c2fc2012-03-22 14:54:10 +01001156 init_timer(&imxdmac->watchdog);
1157 imxdmac->watchdog.function = &imxdma_watchdog;
1158 imxdmac->watchdog.data = (unsigned long)imxdmac;
Sascha Hauer8267f162010-10-20 08:37:19 +02001159 }
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001160
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001161 imxdmac->imxdma = imxdma;
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001162
Javier Martin9e15db72012-03-02 09:28:47 +01001163 INIT_LIST_HEAD(&imxdmac->ld_queue);
1164 INIT_LIST_HEAD(&imxdmac->ld_free);
1165 INIT_LIST_HEAD(&imxdmac->ld_active);
1166
1167 tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet,
1168 (unsigned long)imxdmac);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001169 imxdmac->chan.device = &imxdma->dma_device;
Russell King - ARM Linux8ac69542012-03-06 22:36:27 +00001170 dma_cookie_init(&imxdmac->chan);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001171 imxdmac->channel = i;
1172
1173 /* Add the channel to the DMAC list */
Javier Martin9e15db72012-03-02 09:28:47 +01001174 list_add_tail(&imxdmac->chan.device_node,
1175 &imxdma->dma_device.channels);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001176 }
1177
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001178 imxdma->dma_device.dev = &pdev->dev;
1179
1180 imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
1181 imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
1182 imxdma->dma_device.device_tx_status = imxdma_tx_status;
1183 imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
1184 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
Javier Martin6c05f092012-02-28 17:08:17 +01001185 imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
Javier Martinf606ab82012-03-22 14:54:14 +01001186 imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001187 imxdma->dma_device.device_control = imxdma_control;
1188 imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
1189
1190 platform_set_drvdata(pdev, imxdma);
1191
Javier Martin6c05f092012-02-28 17:08:17 +01001192 imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */
Sascha Hauer1e070a62011-01-12 13:14:37 +01001193 imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
1194 dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
1195
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001196 ret = dma_async_device_register(&imxdma->dma_device);
1197 if (ret) {
1198 dev_err(&pdev->dev, "unable to register\n");
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001199 goto err;
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001200 }
1201
Markus Pargmann290ad0f2013-05-26 11:53:20 +02001202 if (pdev->dev.of_node) {
1203 ret = of_dma_controller_register(pdev->dev.of_node,
1204 imxdma_xlate, imxdma);
1205 if (ret) {
1206 dev_err(&pdev->dev, "unable to register of_dma_controller\n");
1207 goto err_of_dma_controller;
1208 }
1209 }
1210
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001211 return 0;
1212
Markus Pargmann290ad0f2013-05-26 11:53:20 +02001213err_of_dma_controller:
1214 dma_async_device_unregister(&imxdma->dma_device);
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001215err:
Fabio Estevama2367db2012-07-03 15:33:29 -03001216 clk_disable_unprepare(imxdma->dma_ipg);
1217 clk_disable_unprepare(imxdma->dma_ahb);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001218 return ret;
1219}
1220
Maxin B. John1d1bbd32013-02-20 02:07:04 +02001221static int imxdma_remove(struct platform_device *pdev)
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001222{
1223 struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001224
1225 dma_async_device_unregister(&imxdma->dma_device);
1226
Markus Pargmann290ad0f2013-05-26 11:53:20 +02001227 if (pdev->dev.of_node)
1228 of_dma_controller_free(pdev->dev.of_node);
1229
Fabio Estevama2367db2012-07-03 15:33:29 -03001230 clk_disable_unprepare(imxdma->dma_ipg);
1231 clk_disable_unprepare(imxdma->dma_ahb);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001232
1233 return 0;
1234}
1235
1236static struct platform_driver imxdma_driver = {
1237 .driver = {
1238 .name = "imx-dma",
Alexander Shiyan4de9b3b2014-02-22 22:16:48 +04001239 .owner = THIS_MODULE,
Markus Pargmann290ad0f2013-05-26 11:53:20 +02001240 .of_match_table = imx_dma_of_dev_id,
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001241 },
Shawn Guoe51d0f02012-09-15 21:11:28 +08001242 .id_table = imx_dma_devtype,
Maxin B. John1d1bbd32013-02-20 02:07:04 +02001243 .remove = imxdma_remove,
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001244};
1245
1246static int __init imxdma_module_init(void)
1247{
1248 return platform_driver_probe(&imxdma_driver, imxdma_probe);
1249}
1250subsys_initcall(imxdma_module_init);
1251
1252MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1253MODULE_DESCRIPTION("i.MX dma driver");
1254MODULE_LICENSE("GPL");