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gerrit-public.fairphone.software / kernel / msm-4.9 / 324ddc702eb89fb4ec8ed0cb38b4563ba4804f88 / . / arch / arm / boot / dts / dove.dtsi
blob: 42eac1ff3cc82a02c5f52fddba478e76d83548d8 [file] [log] [blame]
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "marvell,dove";
5 model = "Marvell Armada 88AP510 SoC";
6
Sebastian Hesselbarth9139acd2012-11-19 10:39:55 +0100[diff] [blame]7 aliases {
8 gpio0 = &gpio0;
9 gpio1 = &gpio1;
10 gpio2 = &gpio2;
11 };
12
Sebastian Hesselbarth138ee962012-09-25 02:02:16 +0200[diff] [blame]13 soc@f1000000 {
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]14 compatible = "simple-bus";
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]15 #address-cells = <1>;
16 #size-cells = <1>;
Sebastian Hesselbarth138ee962012-09-25 02:02:16 +0200[diff] [blame]17 interrupt-parent = <&intc>;
18
19 ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */
20 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */
21 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */
22 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */
23 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */
24 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */
25 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
26 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]27
Sebastian Hesselbarthfd57c652012-09-25 02:02:14 +0200[diff] [blame]28 l2: l2-cache {
29 compatible = "marvell,tauros2-cache";
30 marvell,tauros2-cache-features = <0>;
31 };
32
Sebastian Hesselbarth138ee962012-09-25 02:02:16 +0200[diff] [blame]33 intc: interrupt-controller {
34 compatible = "marvell,orion-intc";
35 interrupt-controller;
36 #interrupt-cells = <1>;
37 reg = <0x20204 0x04>, <0x20214 0x04>;
38 };
39
Sebastian Hesselbarth5b03df92012-11-17 15:22:27 +0100[diff] [blame]40 core_clk: core-clocks@d0214 {
41 compatible = "marvell,dove-core-clock";
42 reg = <0xd0214 0x4>;
43 #clock-cells = <1>;
44 };
45
46 gate_clk: clock-gating-control@d0038 {
47 compatible = "marvell,dove-gating-clock";
48 reg = <0xd0038 0x4>;
49 clocks = <&core_clk 0>;
50 #clock-cells = <1>;
51 };
52
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]53 uart0: serial@12000 {
54 compatible = "ns16550a";
55 reg = <0x12000 0x100>;
56 reg-shift = <2>;
57 interrupts = <7>;
58 clock-frequency = <166666667>;
59 status = "disabled";
60 };
61
62 uart1: serial@12100 {
63 compatible = "ns16550a";
64 reg = <0x12100 0x100>;
65 reg-shift = <2>;
66 interrupts = <8>;
67 clock-frequency = <166666667>;
68 status = "disabled";
69 };
70
71 uart2: serial@12200 {
72 compatible = "ns16550a";
73 reg = <0x12000 0x100>;
74 reg-shift = <2>;
75 interrupts = <9>;
76 clock-frequency = <166666667>;
77 status = "disabled";
78 };
79
80 uart3: serial@12300 {
81 compatible = "ns16550a";
82 reg = <0x12100 0x100>;
83 reg-shift = <2>;
84 interrupts = <10>;
85 clock-frequency = <166666667>;
86 status = "disabled";
87 };
88
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]89 gpio0: gpio@d0400 {
90 compatible = "marvell,orion-gpio";
91 #gpio-cells = <2>;
92 gpio-controller;
93 reg = <0xd0400 0x20>;
Sebastian Hesselbarth9139acd2012-11-19 10:39:55 +0100[diff] [blame]94 ngpios = <32>;
95 interrupt-controller;
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]96 interrupts = <12>, <13>, <14>, <60>;
97 };
98
99 gpio1: gpio@d0420 {
100 compatible = "marvell,orion-gpio";
101 #gpio-cells = <2>;
102 gpio-controller;
103 reg = <0xd0420 0x20>;
Sebastian Hesselbarth9139acd2012-11-19 10:39:55 +0100[diff] [blame]104 ngpios = <32>;
105 interrupt-controller;
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]106 interrupts = <61>;
107 };
108
109 gpio2: gpio@e8400 {
110 compatible = "marvell,orion-gpio";
111 #gpio-cells = <2>;
112 gpio-controller;
113 reg = <0xe8400 0x0c>;
Sebastian Hesselbarth9139acd2012-11-19 10:39:55 +0100[diff] [blame]114 ngpios = <8>;
115 };
116
117 pinctrl: pinctrl@d0200 {
118 compatible = "marvell,dove-pinctrl";
119 reg = <0xd0200 0x10>;
Sebastian Hesselbarthdb7d77e2012-11-26 20:16:38 +0100[diff] [blame]120 clocks = <&gate_clk 22>;
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]121 };
122
123 spi0: spi@10600 {
124 compatible = "marvell,orion-spi";
125 #address-cells = <1>;
126 #size-cells = <0>;
127 cell-index = <0>;
128 interrupts = <6>;
129 reg = <0x10600 0x28>;
Sebastian Hesselbarth5b03df92012-11-17 15:22:27 +0100[diff] [blame]130 clocks = <&core_clk 0>;
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]131 status = "disabled";
132 };
133
134 spi1: spi@14600 {
135 compatible = "marvell,orion-spi";
136 #address-cells = <1>;
137 #size-cells = <0>;
138 cell-index = <1>;
139 interrupts = <5>;
140 reg = <0x14600 0x28>;
Sebastian Hesselbarth5b03df92012-11-17 15:22:27 +0100[diff] [blame]141 clocks = <&core_clk 0>;
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]142 status = "disabled";
143 };
144
145 i2c0: i2c@11000 {
146 compatible = "marvell,mv64xxx-i2c";
147 reg = <0x11000 0x20>;
148 #address-cells = <1>;
149 #size-cells = <0>;
150 interrupts = <11>;
151 clock-frequency = <400000>;
152 timeout-ms = <1000>;
Sebastian Hesselbarth5b03df92012-11-17 15:22:27 +0100[diff] [blame]153 clocks = <&core_clk 0>;
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]154 status = "disabled";
155 };
156
157 sdio0: sdio@92000 {
158 compatible = "marvell,dove-sdhci";
159 reg = <0x92000 0x100>;
160 interrupts = <35>, <37>;
Sebastian Hesselbarth5b03df92012-11-17 15:22:27 +0100[diff] [blame]161 clocks = <&gate_clk 8>;
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]162 status = "disabled";
163 };
164
165 sdio1: sdio@90000 {
166 compatible = "marvell,dove-sdhci";
167 reg = <0x90000 0x100>;
168 interrupts = <36>, <38>;
Sebastian Hesselbarth5b03df92012-11-17 15:22:27 +0100[diff] [blame]169 clocks = <&gate_clk 9>;
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]170 status = "disabled";
171 };
172
173 sata0: sata@a0000 {
174 compatible = "marvell,orion-sata";
175 reg = <0xa0000 0x2400>;
176 interrupts = <62>;
Sebastian Hesselbarth5b03df92012-11-17 15:22:27 +0100[diff] [blame]177 clocks = <&gate_clk 3>;
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]178 nr-ports = <1>;
179 status = "disabled";
180 };
Sebastian Hesselbartha4589262012-09-25 02:02:18 +0200[diff] [blame]181
182 crypto: crypto@30000 {
183 compatible = "marvell,orion-crypto";
184 reg = <0x30000 0x10000>,
185 <0xc8000000 0x800>;
186 reg-names = "regs", "sram";
187 interrupts = <31>;
Sebastian Hesselbarth5b03df92012-11-17 15:22:27 +0100[diff] [blame]188 clocks = <&gate_clk 15>;
Sebastian Hesselbartha4589262012-09-25 02:02:18 +0200[diff] [blame]189 status = "okay";
190 };
Sebastian Hesselbarth49f175b2012-11-19 09:37:24 +0100[diff] [blame]191
192 xor0: dma-engine@60800 {
193 compatible = "marvell,orion-xor";
194 reg = <0x60800 0x100
195 0x60a00 0x100>;
196 clocks = <&gate_clk 23>;
197 status = "okay";
198
199 channel0 {
200 interrupts = <39>;
201 dmacap,memcpy;
202 dmacap,xor;
203 };
204
205 channel1 {
206 interrupts = <40>;
207 dmacap,memset;
208 dmacap,memcpy;
209 dmacap,xor;
210 };
211 };
212
213 xor1: dma-engine@60900 {
214 compatible = "marvell,orion-xor";
215 reg = <0x60900 0x100
216 0x60b00 0x100>;
217 clocks = <&gate_clk 24>;
218 status = "okay";
219
220 channel0 {
221 interrupts = <42>;
222 dmacap,memcpy;
223 dmacap,xor;
224 };
225
226 channel1 {
227 interrupts = <43>;
228 dmacap,memset;
229 dmacap,memcpy;
230 dmacap,xor;
231 };
232 };
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]233 };
234};