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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Russell King4baa9922008-08-02 10:55:55 +01002 * arch/arm/include/asm/cacheflush.h
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 *
4 * Copyright (C) 1999-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef _ASMARM_CACHEFLUSH_H
11#define _ASMARM_CACHEFLUSH_H
12
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#include <linux/mm.h>
14
Linus Torvalds1da177e2005-04-16 15:20:36 -070015#include <asm/glue.h>
Russell Kingb8a9b662005-06-20 11:31:09 +010016#include <asm/shmparam.h>
Catalin Marinas376e1422008-11-06 13:23:08 +000017#include <asm/cachetype.h>
Catalin Marinas33f663f2010-03-24 16:46:52 +010018#include <asm/outercache.h>
Russell Kingb8a9b662005-06-20 11:31:09 +010019
20#define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
Linus Torvalds1da177e2005-04-16 15:20:36 -070021
22/*
23 * Cache Model
24 * ===========
25 */
26#undef _CACHE
27#undef MULTI_CACHE
28
Russell King6cc7cbe2006-09-27 18:00:35 +010029#if defined(CONFIG_CPU_CACHE_V3)
Linus Torvalds1da177e2005-04-16 15:20:36 -070030# ifdef _CACHE
31# define MULTI_CACHE 1
32# else
33# define _CACHE v3
34# endif
35#endif
36
Russell King6cc7cbe2006-09-27 18:00:35 +010037#if defined(CONFIG_CPU_CACHE_V4)
Linus Torvalds1da177e2005-04-16 15:20:36 -070038# ifdef _CACHE
39# define MULTI_CACHE 1
40# else
41# define _CACHE v4
42# endif
43#endif
44
45#if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
Abdoulaye Walsimou Gaye1c8e1702010-02-19 12:47:14 +010046 defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) || \
47 defined(CONFIG_CPU_ARM1026)
Linus Torvalds1da177e2005-04-16 15:20:36 -070048# define MULTI_CACHE 1
49#endif
50
Paulius Zaleckas28853ac2009-03-25 13:10:01 +020051#if defined(CONFIG_CPU_FA526)
52# ifdef _CACHE
53# define MULTI_CACHE 1
54# else
55# define _CACHE fa
56# endif
57#endif
58
Linus Torvalds1da177e2005-04-16 15:20:36 -070059#if defined(CONFIG_CPU_ARM926T)
60# ifdef _CACHE
61# define MULTI_CACHE 1
62# else
63# define _CACHE arm926
64# endif
65#endif
66
Hyok S. Choid60674e2006-09-26 17:38:18 +090067#if defined(CONFIG_CPU_ARM940T)
68# ifdef _CACHE
69# define MULTI_CACHE 1
70# else
71# define _CACHE arm940
72# endif
73#endif
74
Hyok S. Choif37f46e2006-09-26 17:38:32 +090075#if defined(CONFIG_CPU_ARM946E)
76# ifdef _CACHE
77# define MULTI_CACHE 1
78# else
79# define _CACHE arm946
80# endif
81#endif
82
Russell King6cc7cbe2006-09-27 18:00:35 +010083#if defined(CONFIG_CPU_CACHE_V4WB)
Linus Torvalds1da177e2005-04-16 15:20:36 -070084# ifdef _CACHE
85# define MULTI_CACHE 1
86# else
87# define _CACHE v4wb
88# endif
89#endif
90
91#if defined(CONFIG_CPU_XSCALE)
92# ifdef _CACHE
93# define MULTI_CACHE 1
94# else
95# define _CACHE xscale
96# endif
97#endif
98
Lennert Buytenhek23bdf862006-03-28 21:00:40 +010099#if defined(CONFIG_CPU_XSC3)
100# ifdef _CACHE
101# define MULTI_CACHE 1
102# else
103# define _CACHE xsc3
104# endif
105#endif
106
Eric Miao49cbe782009-01-20 14:15:18 +0800107#if defined(CONFIG_CPU_MOHAWK)
108# ifdef _CACHE
109# define MULTI_CACHE 1
110# else
111# define _CACHE mohawk
112# endif
113#endif
114
Assaf Hoffmane50d6402007-10-23 15:14:41 -0400115#if defined(CONFIG_CPU_FEROCEON)
Stanislav Samsonov836a8052008-06-03 11:24:40 +0300116# define MULTI_CACHE 1
Assaf Hoffmane50d6402007-10-23 15:14:41 -0400117#endif
118
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119#if defined(CONFIG_CPU_V6)
120//# ifdef _CACHE
121# define MULTI_CACHE 1
122//# else
123//# define _CACHE v6
124//# endif
125#endif
126
Catalin Marinasbbe88882007-05-08 22:27:46 +0100127#if defined(CONFIG_CPU_V7)
128//# ifdef _CACHE
129# define MULTI_CACHE 1
130//# else
131//# define _CACHE v7
132//# endif
133#endif
134
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135#if !defined(_CACHE) && !defined(MULTI_CACHE)
136#error Unknown cache maintainence model
137#endif
138
139/*
140 * This flag is used to indicate that the page pointed to by a pte
141 * is dirty and requires cleaning before returning it to the user.
142 */
143#define PG_dcache_dirty PG_arch_1
144
145/*
146 * MM Cache Management
147 * ===================
148 *
149 * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
150 * implement these methods.
151 *
152 * Start addresses are inclusive and end addresses are exclusive;
153 * start addresses should be rounded down, end addresses up.
154 *
155 * See Documentation/cachetlb.txt for more information.
156 * Please note that the implementation of these, and the required
157 * effects are cache-type (VIVT/VIPT/PIPT) specific.
158 *
Tony Lindgren20451242010-01-19 23:42:08 +0100159 * flush_kern_all()
Linus Torvalds1da177e2005-04-16 15:20:36 -0700160 *
161 * Unconditionally clean and invalidate the entire cache.
162 *
Tony Lindgren20451242010-01-19 23:42:08 +0100163 * flush_user_all()
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164 *
165 * Clean and invalidate all user space cache entries
166 * before a change of page tables.
167 *
Tony Lindgren20451242010-01-19 23:42:08 +0100168 * flush_user_range(start, end, flags)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700169 *
170 * Clean and invalidate a range of cache entries in the
171 * specified address space before a change of page tables.
172 * - start - user start address (inclusive, page aligned)
173 * - end - user end address (exclusive, page aligned)
174 * - flags - vma->vm_flags field
175 *
176 * coherent_kern_range(start, end)
177 *
178 * Ensure coherency between the Icache and the Dcache in the
179 * region described by start, end. If you have non-snooping
180 * Harvard caches, you need to implement this function.
181 * - start - virtual start address
182 * - end - virtual end address
183 *
Tony Lindgren20451242010-01-19 23:42:08 +0100184 * coherent_user_range(start, end)
185 *
186 * Ensure coherency between the Icache and the Dcache in the
187 * region described by start, end. If you have non-snooping
188 * Harvard caches, you need to implement this function.
189 * - start - virtual start address
190 * - end - virtual end address
191 *
192 * flush_kern_dcache_area(kaddr, size)
193 *
194 * Ensure that the data held in page is written back.
195 * - kaddr - page address
196 * - size - region size
197 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198 * DMA Cache Coherency
199 * ===================
200 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201 * dma_flush_range(start, end)
202 *
203 * Clean and invalidate the specified virtual address range.
204 * - start - virtual start address
205 * - end - virtual end address
206 */
207
208struct cpu_cache_fns {
209 void (*flush_kern_all)(void);
210 void (*flush_user_all)(void);
211 void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
212
213 void (*coherent_kern_range)(unsigned long, unsigned long);
214 void (*coherent_user_range)(unsigned long, unsigned long);
Russell King2c9b9c82009-11-26 12:56:21 +0000215 void (*flush_kern_dcache_area)(void *, size_t);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216
Russell Kinga9c91472009-11-26 16:19:58 +0000217 void (*dma_map_area)(const void *, size_t, int);
218 void (*dma_unmap_area)(const void *, size_t, int);
219
Russell King7ae5a762007-02-06 17:39:31 +0000220 void (*dma_flush_range)(const void *, const void *);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221};
222
223/*
224 * Select the calling method
225 */
226#ifdef MULTI_CACHE
227
228extern struct cpu_cache_fns cpu_cache;
229
230#define __cpuc_flush_kern_all cpu_cache.flush_kern_all
231#define __cpuc_flush_user_all cpu_cache.flush_user_all
232#define __cpuc_flush_user_range cpu_cache.flush_user_range
233#define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range
234#define __cpuc_coherent_user_range cpu_cache.coherent_user_range
Russell King2c9b9c82009-11-26 12:56:21 +0000235#define __cpuc_flush_dcache_area cpu_cache.flush_kern_dcache_area
Linus Torvalds1da177e2005-04-16 15:20:36 -0700236
237/*
238 * These are private to the dma-mapping API. Do not use directly.
239 * Their sole purpose is to ensure that data held in the cache
240 * is visible to DMA, or data written by DMA to system memory is
241 * visible to the CPU.
242 */
Russell Kinga9c91472009-11-26 16:19:58 +0000243#define dmac_map_area cpu_cache.dma_map_area
244#define dmac_unmap_area cpu_cache.dma_unmap_area
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245#define dmac_flush_range cpu_cache.dma_flush_range
246
247#else
248
249#define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
250#define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all)
251#define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
252#define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
253#define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
Russell King2c9b9c82009-11-26 12:56:21 +0000254#define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700255
256extern void __cpuc_flush_kern_all(void);
257extern void __cpuc_flush_user_all(void);
258extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
259extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
260extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
Russell King2c9b9c82009-11-26 12:56:21 +0000261extern void __cpuc_flush_dcache_area(void *, size_t);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262
263/*
264 * These are private to the dma-mapping API. Do not use directly.
265 * Their sole purpose is to ensure that data held in the cache
266 * is visible to DMA, or data written by DMA to system memory is
267 * visible to the CPU.
268 */
Russell Kinga9c91472009-11-26 16:19:58 +0000269#define dmac_map_area __glue(_CACHE,_dma_map_area)
270#define dmac_unmap_area __glue(_CACHE,_dma_unmap_area)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271#define dmac_flush_range __glue(_CACHE,_dma_flush_range)
272
Russell Kinga9c91472009-11-26 16:19:58 +0000273extern void dmac_map_area(const void *, size_t, int);
274extern void dmac_unmap_area(const void *, size_t, int);
Russell King7ae5a762007-02-06 17:39:31 +0000275extern void dmac_flush_range(const void *, const void *);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700276
277#endif
278
279/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280 * Copy user data from/to a page which is mapped into a different
281 * processes address space. Really, we want to allow our "user
282 * space" model to handle this.
283 */
Russell King2ef7f3d2009-11-05 13:29:36 +0000284extern void copy_to_user_page(struct vm_area_struct *, struct page *,
285 unsigned long, void *, const void *, unsigned long);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700286#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
287 do { \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288 memcpy(dst, src, len); \
289 } while (0)
290
291/*
292 * Convert calls to our calling convention.
293 */
294#define flush_cache_all() __cpuc_flush_kern_all()
Russell King2f0b1922009-10-25 10:40:02 +0000295
296static inline void vivt_flush_cache_mm(struct mm_struct *mm)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700297{
Rusty Russell56f8ba82009-09-24 09:34:49 -0600298 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299 __cpuc_flush_user_all();
300}
301
302static inline void
Russell King2f0b1922009-10-25 10:40:02 +0000303vivt_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304{
Rusty Russell56f8ba82009-09-24 09:34:49 -0600305 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700306 __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
307 vma->vm_flags);
308}
309
310static inline void
Russell King2f0b1922009-10-25 10:40:02 +0000311vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312{
Rusty Russell56f8ba82009-09-24 09:34:49 -0600313 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700314 unsigned long addr = user_addr & PAGE_MASK;
315 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
316 }
317}
George G. Davisa188ad22006-09-02 18:43:20 +0100318
Russell King2f0b1922009-10-25 10:40:02 +0000319#ifndef CONFIG_CPU_CACHE_VIPT
320#define flush_cache_mm(mm) \
321 vivt_flush_cache_mm(mm)
322#define flush_cache_range(vma,start,end) \
323 vivt_flush_cache_range(vma,start,end)
324#define flush_cache_page(vma,addr,pfn) \
325 vivt_flush_cache_page(vma,addr,pfn)
Russell Kingd7b6b352005-09-08 15:32:23 +0100326#else
327extern void flush_cache_mm(struct mm_struct *mm);
328extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
329extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
330#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700331
Ralf Baechleec8c0442006-12-12 17:14:57 +0000332#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
333
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334/*
335 * flush_cache_user_range is used when we want to ensure that the
336 * Harvard caches are synchronised for the user space address range.
337 * This is used for the ARM private sys_cacheflush system call.
338 */
339#define flush_cache_user_range(vma,start,end) \
340 __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
341
342/*
343 * Perform necessary cache operations to ensure that data previously
344 * stored within this range of addresses can be executed by the CPU.
345 */
346#define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e)
347
348/*
349 * Perform necessary cache operations to ensure that the TLB will
350 * see data written in the specified area.
351 */
352#define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size)
353
354/*
355 * flush_dcache_page is used when the kernel has written to the page
356 * cache page at virtual address page->virtual.
357 *
358 * If this page isn't mapped (ie, page_mapping == NULL), or it might
359 * have userspace mappings, then we _must_ always clean + invalidate
360 * the dcache entries associated with the kernel mapping.
361 *
362 * Otherwise we can defer the operation, and clean the cache when we are
363 * about to change to user space. This is the same method as used on SPARC64.
364 * See update_mmu_cache for the user space part.
365 */
Ilya Loginov2d4dc892009-11-26 09:16:19 +0100366#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367extern void flush_dcache_page(struct page *);
368
Catalin Marinas826cbda2008-06-13 10:28:36 +0100369static inline void __flush_icache_all(void)
370{
Russell Kingdf71dfd2009-10-24 22:36:36 +0100371#ifdef CONFIG_ARM_ERRATA_411920
372 extern void v6_icache_inval_all(void);
373 v6_icache_inval_all();
374#else
Catalin Marinas826cbda2008-06-13 10:28:36 +0100375 asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n"
376 :
377 : "r" (0));
Russell Kingdf71dfd2009-10-24 22:36:36 +0100378#endif
Catalin Marinas826cbda2008-06-13 10:28:36 +0100379}
James Bottomley252a9af2010-01-25 11:42:22 -0600380static inline void flush_kernel_vmap_range(void *addr, int size)
381{
382 if ((cache_is_vivt() || cache_is_vipt_aliasing()))
383 __cpuc_flush_dcache_area(addr, (size_t)size);
384}
385static inline void invalidate_kernel_vmap_range(void *addr, int size)
386{
387 if ((cache_is_vivt() || cache_is_vipt_aliasing()))
388 __cpuc_flush_dcache_area(addr, (size_t)size);
389}
Catalin Marinas826cbda2008-06-13 10:28:36 +0100390
Russell King6020dff2006-12-30 23:17:40 +0000391#define ARCH_HAS_FLUSH_ANON_PAGE
392static inline void flush_anon_page(struct vm_area_struct *vma,
393 struct page *page, unsigned long vmaddr)
394{
395 extern void __flush_anon_page(struct vm_area_struct *vma,
396 struct page *, unsigned long);
397 if (PageAnon(page))
398 __flush_anon_page(vma, page, vmaddr);
399}
400
Nicolas Pitre73be1592009-06-12 03:09:29 +0100401#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
402static inline void flush_kernel_dcache_page(struct page *page)
403{
404 /* highmem pages are always flushed upon kunmap already */
405 if ((cache_is_vivt() || cache_is_vipt_aliasing()) && !PageHighMem(page))
Russell King2c9b9c82009-11-26 12:56:21 +0000406 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
Nicolas Pitre73be1592009-06-12 03:09:29 +0100407}
408
Linus Torvalds1da177e2005-04-16 15:20:36 -0700409#define flush_dcache_mmap_lock(mapping) \
Nick Piggin19fd6232008-07-25 19:45:32 -0700410 spin_lock_irq(&(mapping)->tree_lock)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411#define flush_dcache_mmap_unlock(mapping) \
Nick Piggin19fd6232008-07-25 19:45:32 -0700412 spin_unlock_irq(&(mapping)->tree_lock)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413
414#define flush_icache_user_range(vma,page,addr,len) \
415 flush_dcache_page(page)
416
417/*
418 * We don't appear to need to do anything here. In fact, if we did, we'd
419 * duplicate cache flushing elsewhere performed by flush_dcache_page().
420 */
421#define flush_icache_page(vma,page) do { } while (0)
422
Catalin Marinas376e1422008-11-06 13:23:08 +0000423/*
424 * flush_cache_vmap() is used when creating mappings (eg, via vmap,
425 * vmalloc, ioremap etc) in kernel space for pages. On non-VIPT
426 * caches, since the direct-mappings of these pages may contain cached
427 * data, we need to do a full cache flush to ensure that writebacks
428 * don't corrupt data placed into these pages via the new mappings.
429 */
430static inline void flush_cache_vmap(unsigned long start, unsigned long end)
431{
432 if (!cache_is_vipt_nonaliasing())
433 flush_cache_all();
434 else
435 /*
436 * set_pte_at() called from vmap_pte_range() does not
437 * have a DSB after cleaning the cache line.
438 */
439 dsb();
440}
441
442static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
443{
444 if (!cache_is_vipt_nonaliasing())
445 flush_cache_all();
446}
447
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448#endif