blob: 940fc0ad6bc18da3502096aa47a20838a0ce5e36 [file] [log] [blame]
Alan Ott3731a332012-09-02 15:44:13 +00001/*
2 * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller
3 *
4 * Copyright (C) 2012 Alan Ott <alan@signal11.us>
5 * Signal 11 Software
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Alan Ott3731a332012-09-02 15:44:13 +000016 */
17
18#include <linux/spi/spi.h>
19#include <linux/interrupt.h>
20#include <linux/module.h>
Alexander Aringb0156792015-09-21 11:24:30 +020021#include <linux/regmap.h>
Alexander Aring4ca24ac2014-10-25 09:41:04 +020022#include <linux/ieee802154.h>
Alexander Aring5ad60d32014-10-25 09:41:02 +020023#include <net/cfg802154.h>
Alan Ott3731a332012-09-02 15:44:13 +000024#include <net/mac802154.h>
25
26/* MRF24J40 Short Address Registers */
Alexander Aringc9f883f2015-09-21 11:24:22 +020027#define REG_RXMCR 0x00 /* Receive MAC control */
28#define REG_PANIDL 0x01 /* PAN ID (low) */
29#define REG_PANIDH 0x02 /* PAN ID (high) */
30#define REG_SADRL 0x03 /* Short address (low) */
31#define REG_SADRH 0x04 /* Short address (high) */
32#define REG_EADR0 0x05 /* Long address (low) (high is EADR7) */
Alexander Aring554b4942015-09-21 11:24:29 +020033#define REG_EADR1 0x06
34#define REG_EADR2 0x07
35#define REG_EADR3 0x08
36#define REG_EADR4 0x09
37#define REG_EADR5 0x0A
38#define REG_EADR6 0x0B
39#define REG_EADR7 0x0C
40#define REG_RXFLUSH 0x0D
41#define REG_ORDER 0x10
Alexander Aringc9f883f2015-09-21 11:24:22 +020042#define REG_TXMCR 0x11 /* Transmit MAC control */
Alexander Aring554b4942015-09-21 11:24:29 +020043#define REG_ACKTMOUT 0x12
44#define REG_ESLOTG1 0x13
45#define REG_SYMTICKL 0x14
46#define REG_SYMTICKH 0x15
Alexander Aringc9f883f2015-09-21 11:24:22 +020047#define REG_PACON0 0x16 /* Power Amplifier Control */
48#define REG_PACON1 0x17 /* Power Amplifier Control */
49#define REG_PACON2 0x18 /* Power Amplifier Control */
Alexander Aring554b4942015-09-21 11:24:29 +020050#define REG_TXBCON0 0x1A
Alexander Aringc9f883f2015-09-21 11:24:22 +020051#define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */
Alexander Aring554b4942015-09-21 11:24:29 +020052#define REG_TXG1CON 0x1C
53#define REG_TXG2CON 0x1D
54#define REG_ESLOTG23 0x1E
55#define REG_ESLOTG45 0x1F
56#define REG_ESLOTG67 0x20
57#define REG_TXPEND 0x21
58#define REG_WAKECON 0x22
59#define REG_FROMOFFSET 0x23
Alexander Aringc9f883f2015-09-21 11:24:22 +020060#define REG_TXSTAT 0x24 /* TX MAC Status Register */
Alexander Aring554b4942015-09-21 11:24:29 +020061#define REG_TXBCON1 0x25
62#define REG_GATECLK 0x26
63#define REG_TXTIME 0x27
64#define REG_HSYMTMRL 0x28
65#define REG_HSYMTMRH 0x29
Alexander Aringc9f883f2015-09-21 11:24:22 +020066#define REG_SOFTRST 0x2A /* Soft Reset */
Alexander Aring554b4942015-09-21 11:24:29 +020067#define REG_SECCON0 0x2C
68#define REG_SECCON1 0x2D
Alexander Aringc9f883f2015-09-21 11:24:22 +020069#define REG_TXSTBL 0x2E /* TX Stabilization */
Alexander Aring554b4942015-09-21 11:24:29 +020070#define REG_RXSR 0x30
Alexander Aringc9f883f2015-09-21 11:24:22 +020071#define REG_INTSTAT 0x31 /* Interrupt Status */
72#define REG_INTCON 0x32 /* Interrupt Control */
73#define REG_GPIO 0x33 /* GPIO */
74#define REG_TRISGPIO 0x34 /* GPIO direction */
Alexander Aring554b4942015-09-21 11:24:29 +020075#define REG_SLPACK 0x35
Alexander Aringc9f883f2015-09-21 11:24:22 +020076#define REG_RFCTL 0x36 /* RF Control Mode Register */
Alexander Aring554b4942015-09-21 11:24:29 +020077#define REG_SECCR2 0x37
78#define REG_BBREG0 0x38
Alexander Aringc9f883f2015-09-21 11:24:22 +020079#define REG_BBREG1 0x39 /* Baseband Registers */
80#define REG_BBREG2 0x3A /* */
Alexander Aring554b4942015-09-21 11:24:29 +020081#define REG_BBREG3 0x3B
82#define REG_BBREG4 0x3C
Alexander Aringc9f883f2015-09-21 11:24:22 +020083#define REG_BBREG6 0x3E /* */
84#define REG_CCAEDTH 0x3F /* Energy Detection Threshold */
Alan Ott3731a332012-09-02 15:44:13 +000085
86/* MRF24J40 Long Address Registers */
Alexander Aringc9f883f2015-09-21 11:24:22 +020087#define REG_RFCON0 0x200 /* RF Control Registers */
88#define REG_RFCON1 0x201
89#define REG_RFCON2 0x202
90#define REG_RFCON3 0x203
91#define REG_RFCON5 0x205
92#define REG_RFCON6 0x206
93#define REG_RFCON7 0x207
94#define REG_RFCON8 0x208
Alexander Aring554b4942015-09-21 11:24:29 +020095#define REG_SLPCAL0 0x209
96#define REG_SLPCAL1 0x20A
97#define REG_SLPCAL2 0x20B
98#define REG_RFSTATE 0x20F
Alexander Aringc9f883f2015-09-21 11:24:22 +020099#define REG_RSSI 0x210
100#define REG_SLPCON0 0x211 /* Sleep Clock Control Registers */
101#define REG_SLPCON1 0x220
102#define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */
103#define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */
Alexander Aring554b4942015-09-21 11:24:29 +0200104#define REG_REMCNTL 0x224
105#define REG_REMCNTH 0x225
106#define REG_MAINCNT0 0x226
107#define REG_MAINCNT1 0x227
108#define REG_MAINCNT2 0x228
109#define REG_MAINCNT3 0x229
Alexander Aringc9f883f2015-09-21 11:24:22 +0200110#define REG_TESTMODE 0x22F /* Test mode */
Alexander Aring554b4942015-09-21 11:24:29 +0200111#define REG_ASSOEAR0 0x230
112#define REG_ASSOEAR1 0x231
113#define REG_ASSOEAR2 0x232
114#define REG_ASSOEAR3 0x233
115#define REG_ASSOEAR4 0x234
116#define REG_ASSOEAR5 0x235
117#define REG_ASSOEAR6 0x236
118#define REG_ASSOEAR7 0x237
119#define REG_ASSOSAR0 0x238
120#define REG_ASSOSAR1 0x239
121#define REG_UNONCE0 0x240
122#define REG_UNONCE1 0x241
123#define REG_UNONCE2 0x242
124#define REG_UNONCE3 0x243
125#define REG_UNONCE4 0x244
126#define REG_UNONCE5 0x245
127#define REG_UNONCE6 0x246
128#define REG_UNONCE7 0x247
129#define REG_UNONCE8 0x248
130#define REG_UNONCE9 0x249
131#define REG_UNONCE10 0x24A
132#define REG_UNONCE11 0x24B
133#define REG_UNONCE12 0x24C
Alexander Aringc9f883f2015-09-21 11:24:22 +0200134#define REG_RX_FIFO 0x300 /* Receive FIFO */
Alan Ott3731a332012-09-02 15:44:13 +0000135
136/* Device configuration: Only channels 11-26 on page 0 are supported. */
137#define MRF24J40_CHAN_MIN 11
138#define MRF24J40_CHAN_MAX 26
139#define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \
140 - ((u32)1 << MRF24J40_CHAN_MIN))
141
142#define TX_FIFO_SIZE 128 /* From datasheet */
143#define RX_FIFO_SIZE 144 /* From datasheet */
144#define SET_CHANNEL_DELAY_US 192 /* From datasheet */
145
Simon Vincentdb9e0ee2014-10-06 10:39:45 +0100146enum mrf24j40_modules { MRF24J40, MRF24J40MA, MRF24J40MC };
147
Alan Ott3731a332012-09-02 15:44:13 +0000148/* Device Private Data */
149struct mrf24j40 {
150 struct spi_device *spi;
Alexander Aring5a504392014-10-25 17:16:34 +0200151 struct ieee802154_hw *hw;
Alan Ott3731a332012-09-02 15:44:13 +0000152
Alexander Aringb0156792015-09-21 11:24:30 +0200153 struct regmap *regmap_short;
154 struct regmap *regmap_long;
Alexander Aring6844a0e2015-09-21 11:24:34 +0200155
156 /* for writing txfifo */
157 struct spi_message tx_msg;
158 u8 tx_hdr_buf[2];
159 struct spi_transfer tx_hdr_trx;
160 u8 tx_len_buf[2];
161 struct spi_transfer tx_len_trx;
162 struct spi_transfer tx_buf_trx;
163 struct sk_buff *tx_skb;
164
165 /* post transmit message to send frame out */
166 struct spi_message tx_post_msg;
167 u8 tx_post_buf[2];
168 struct spi_transfer tx_post_trx;
169
Alexander Aringc91a3012015-09-21 11:24:35 +0200170 /* for protect/unprotect/read length rxfifo */
171 struct spi_message rx_msg;
172 u8 rx_buf[3];
173 struct spi_transfer rx_trx;
174
175 /* receive handling */
176 struct spi_message rx_buf_msg;
177 u8 rx_addr_buf[2];
178 struct spi_transfer rx_addr_trx;
179 u8 rx_lqi_buf[2];
180 struct spi_transfer rx_lqi_trx;
181 u8 rx_fifo_buf[RX_FIFO_SIZE];
182 struct spi_transfer rx_fifo_buf_trx;
183
Alexander Aring37441612015-09-21 11:24:36 +0200184 /* isr handling for reading intstat */
185 struct spi_message irq_msg;
186 u8 irq_buf[2];
187 struct spi_transfer irq_trx;
Alan Ott3731a332012-09-02 15:44:13 +0000188};
189
Alexander Aringb0156792015-09-21 11:24:30 +0200190/* regmap information for short address register access */
191#define MRF24J40_SHORT_WRITE 0x01
192#define MRF24J40_SHORT_READ 0x00
193#define MRF24J40_SHORT_NUMREGS 0x3F
194
195/* regmap information for long address register access */
196#define MRF24J40_LONG_ACCESS 0x80
197#define MRF24J40_LONG_NUMREGS 0x38F
198
Alan Ott3731a332012-09-02 15:44:13 +0000199/* Read/Write SPI Commands for Short and Long Address registers. */
200#define MRF24J40_READSHORT(reg) ((reg) << 1)
201#define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1)
202#define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5)
203#define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4)
204
Alan Ottcf82dab2013-03-18 12:06:42 +0000205/* The datasheet indicates the theoretical maximum for SCK to be 10MHz */
206#define MAX_SPI_SPEED_HZ 10000000
Alan Ott3731a332012-09-02 15:44:13 +0000207
208#define printdev(X) (&X->spi->dev)
209
Alexander Aringb0156792015-09-21 11:24:30 +0200210static bool
211mrf24j40_short_reg_writeable(struct device *dev, unsigned int reg)
212{
213 switch (reg) {
214 case REG_RXMCR:
215 case REG_PANIDL:
216 case REG_PANIDH:
217 case REG_SADRL:
218 case REG_SADRH:
219 case REG_EADR0:
220 case REG_EADR1:
221 case REG_EADR2:
222 case REG_EADR3:
223 case REG_EADR4:
224 case REG_EADR5:
225 case REG_EADR6:
226 case REG_EADR7:
227 case REG_RXFLUSH:
228 case REG_ORDER:
229 case REG_TXMCR:
230 case REG_ACKTMOUT:
231 case REG_ESLOTG1:
232 case REG_SYMTICKL:
233 case REG_SYMTICKH:
234 case REG_PACON0:
235 case REG_PACON1:
236 case REG_PACON2:
237 case REG_TXBCON0:
238 case REG_TXNCON:
239 case REG_TXG1CON:
240 case REG_TXG2CON:
241 case REG_ESLOTG23:
242 case REG_ESLOTG45:
243 case REG_ESLOTG67:
244 case REG_TXPEND:
245 case REG_WAKECON:
246 case REG_FROMOFFSET:
247 case REG_TXBCON1:
248 case REG_GATECLK:
249 case REG_TXTIME:
250 case REG_HSYMTMRL:
251 case REG_HSYMTMRH:
252 case REG_SOFTRST:
253 case REG_SECCON0:
254 case REG_SECCON1:
255 case REG_TXSTBL:
256 case REG_RXSR:
257 case REG_INTCON:
258 case REG_TRISGPIO:
259 case REG_GPIO:
260 case REG_RFCTL:
261 case REG_SLPACK:
262 case REG_BBREG0:
263 case REG_BBREG1:
264 case REG_BBREG2:
265 case REG_BBREG3:
266 case REG_BBREG4:
267 case REG_BBREG6:
268 case REG_CCAEDTH:
269 return true;
270 default:
271 return false;
272 }
273}
274
275static bool
276mrf24j40_short_reg_readable(struct device *dev, unsigned int reg)
277{
278 bool rc;
279
280 /* all writeable are also readable */
281 rc = mrf24j40_short_reg_writeable(dev, reg);
282 if (rc)
283 return rc;
284
285 /* readonly regs */
286 switch (reg) {
287 case REG_TXSTAT:
288 case REG_INTSTAT:
289 return true;
290 default:
291 return false;
292 }
293}
294
295static bool
296mrf24j40_short_reg_volatile(struct device *dev, unsigned int reg)
297{
298 /* can be changed during runtime */
299 switch (reg) {
300 case REG_TXSTAT:
301 case REG_INTSTAT:
302 case REG_RXFLUSH:
303 case REG_TXNCON:
304 case REG_SOFTRST:
305 case REG_RFCTL:
306 case REG_TXBCON0:
307 case REG_TXG1CON:
308 case REG_TXG2CON:
309 case REG_TXBCON1:
310 case REG_SECCON0:
311 case REG_RXSR:
312 case REG_SLPACK:
313 case REG_SECCR2:
314 case REG_BBREG6:
315 /* use them in spi_async and regmap so it's volatile */
316 case REG_BBREG1:
317 return true;
318 default:
319 return false;
320 }
321}
322
323static bool
324mrf24j40_short_reg_precious(struct device *dev, unsigned int reg)
325{
326 /* don't clear irq line on read */
327 switch (reg) {
328 case REG_INTSTAT:
329 return true;
330 default:
331 return false;
332 }
333}
334
335static const struct regmap_config mrf24j40_short_regmap = {
336 .name = "mrf24j40_short",
337 .reg_bits = 7,
338 .val_bits = 8,
339 .pad_bits = 1,
340 .write_flag_mask = MRF24J40_SHORT_WRITE,
341 .read_flag_mask = MRF24J40_SHORT_READ,
342 .cache_type = REGCACHE_RBTREE,
343 .max_register = MRF24J40_SHORT_NUMREGS,
344 .writeable_reg = mrf24j40_short_reg_writeable,
345 .readable_reg = mrf24j40_short_reg_readable,
346 .volatile_reg = mrf24j40_short_reg_volatile,
347 .precious_reg = mrf24j40_short_reg_precious,
348};
349
350static bool
351mrf24j40_long_reg_writeable(struct device *dev, unsigned int reg)
352{
353 switch (reg) {
354 case REG_RFCON0:
355 case REG_RFCON1:
356 case REG_RFCON2:
357 case REG_RFCON3:
358 case REG_RFCON5:
359 case REG_RFCON6:
360 case REG_RFCON7:
361 case REG_RFCON8:
362 case REG_SLPCAL2:
363 case REG_SLPCON0:
364 case REG_SLPCON1:
365 case REG_WAKETIMEL:
366 case REG_WAKETIMEH:
367 case REG_REMCNTL:
368 case REG_REMCNTH:
369 case REG_MAINCNT0:
370 case REG_MAINCNT1:
371 case REG_MAINCNT2:
372 case REG_MAINCNT3:
373 case REG_TESTMODE:
374 case REG_ASSOEAR0:
375 case REG_ASSOEAR1:
376 case REG_ASSOEAR2:
377 case REG_ASSOEAR3:
378 case REG_ASSOEAR4:
379 case REG_ASSOEAR5:
380 case REG_ASSOEAR6:
381 case REG_ASSOEAR7:
382 case REG_ASSOSAR0:
383 case REG_ASSOSAR1:
384 case REG_UNONCE0:
385 case REG_UNONCE1:
386 case REG_UNONCE2:
387 case REG_UNONCE3:
388 case REG_UNONCE4:
389 case REG_UNONCE5:
390 case REG_UNONCE6:
391 case REG_UNONCE7:
392 case REG_UNONCE8:
393 case REG_UNONCE9:
394 case REG_UNONCE10:
395 case REG_UNONCE11:
396 case REG_UNONCE12:
397 return true;
398 default:
399 return false;
400 }
401}
402
403static bool
404mrf24j40_long_reg_readable(struct device *dev, unsigned int reg)
405{
406 bool rc;
407
408 /* all writeable are also readable */
409 rc = mrf24j40_long_reg_writeable(dev, reg);
410 if (rc)
411 return rc;
412
413 /* readonly regs */
414 switch (reg) {
415 case REG_SLPCAL0:
416 case REG_SLPCAL1:
417 case REG_RFSTATE:
418 case REG_RSSI:
419 return true;
420 default:
421 return false;
422 }
423}
424
425static bool
426mrf24j40_long_reg_volatile(struct device *dev, unsigned int reg)
427{
428 /* can be changed during runtime */
429 switch (reg) {
430 case REG_SLPCAL0:
431 case REG_SLPCAL1:
432 case REG_SLPCAL2:
433 case REG_RFSTATE:
434 case REG_RSSI:
435 case REG_MAINCNT3:
436 return true;
437 default:
438 return false;
439 }
440}
441
442static const struct regmap_config mrf24j40_long_regmap = {
443 .name = "mrf24j40_long",
444 .reg_bits = 11,
445 .val_bits = 8,
446 .pad_bits = 5,
447 .write_flag_mask = MRF24J40_LONG_ACCESS,
448 .read_flag_mask = MRF24J40_LONG_ACCESS,
449 .cache_type = REGCACHE_RBTREE,
450 .max_register = MRF24J40_LONG_NUMREGS,
451 .writeable_reg = mrf24j40_long_reg_writeable,
452 .readable_reg = mrf24j40_long_reg_readable,
453 .volatile_reg = mrf24j40_long_reg_volatile,
454};
455
456static int mrf24j40_long_regmap_write(void *context, const void *data,
457 size_t count)
458{
459 struct spi_device *spi = context;
460 u8 buf[3];
461
462 if (count > 3)
463 return -EINVAL;
464
465 /* regmap supports read/write mask only in frist byte
466 * long write access need to set the 12th bit, so we
467 * make special handling for write.
468 */
469 memcpy(buf, data, count);
470 buf[1] |= (1 << 4);
471
472 return spi_write(spi, buf, count);
473}
474
475static int
476mrf24j40_long_regmap_read(void *context, const void *reg, size_t reg_size,
477 void *val, size_t val_size)
478{
479 struct spi_device *spi = context;
480
481 return spi_write_then_read(spi, reg, reg_size, val, val_size);
482}
483
484static const struct regmap_bus mrf24j40_long_regmap_bus = {
485 .write = mrf24j40_long_regmap_write,
486 .read = mrf24j40_long_regmap_read,
487 .reg_format_endian_default = REGMAP_ENDIAN_BIG,
488 .val_format_endian_default = REGMAP_ENDIAN_BIG,
489};
490
Alexander Aring6844a0e2015-09-21 11:24:34 +0200491static void write_tx_buf_complete(void *context)
492{
493 struct mrf24j40 *devrec = context;
494 __le16 fc = ieee802154_get_fc_from_skb(devrec->tx_skb);
495 u8 val = 0x01;
496 int ret;
497
498 if (ieee802154_is_ackreq(fc))
499 val |= 0x04;
500
501 devrec->tx_post_msg.complete = NULL;
502 devrec->tx_post_buf[0] = MRF24J40_WRITESHORT(REG_TXNCON);
503 devrec->tx_post_buf[1] = val;
504
505 ret = spi_async(devrec->spi, &devrec->tx_post_msg);
506 if (ret)
507 dev_err(printdev(devrec), "SPI write Failed for transmit buf\n");
508}
509
Alan Ott3731a332012-09-02 15:44:13 +0000510/* This function relies on an undocumented write method. Once a write command
511 and address is set, as many bytes of data as desired can be clocked into
512 the device. The datasheet only shows setting one byte at a time. */
513static int write_tx_buf(struct mrf24j40 *devrec, u16 reg,
514 const u8 *data, size_t length)
515{
Alan Ott3731a332012-09-02 15:44:13 +0000516 u16 cmd;
Alexander Aring6844a0e2015-09-21 11:24:34 +0200517 int ret;
Alan Ott3731a332012-09-02 15:44:13 +0000518
519 /* Range check the length. 2 bytes are used for the length fields.*/
520 if (length > TX_FIFO_SIZE-2) {
521 dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n");
522 length = TX_FIFO_SIZE-2;
523 }
524
Alan Ott3731a332012-09-02 15:44:13 +0000525 cmd = MRF24J40_WRITELONG(reg);
Alexander Aring6844a0e2015-09-21 11:24:34 +0200526 devrec->tx_hdr_buf[0] = cmd >> 8 & 0xff;
527 devrec->tx_hdr_buf[1] = cmd & 0xff;
528 devrec->tx_len_buf[0] = 0x0; /* Header Length. Set to 0 for now. TODO */
529 devrec->tx_len_buf[1] = length; /* Total length */
530 devrec->tx_buf_trx.tx_buf = data;
531 devrec->tx_buf_trx.len = length;
Alan Ott3731a332012-09-02 15:44:13 +0000532
Alexander Aring6844a0e2015-09-21 11:24:34 +0200533 ret = spi_async(devrec->spi, &devrec->tx_msg);
Alan Ott3731a332012-09-02 15:44:13 +0000534 if (ret)
535 dev_err(printdev(devrec), "SPI write Failed for TX buf\n");
536
Alan Ott3731a332012-09-02 15:44:13 +0000537 return ret;
538}
539
Alexander Aring6844a0e2015-09-21 11:24:34 +0200540static int mrf24j40_tx(struct ieee802154_hw *hw, struct sk_buff *skb)
541{
542 struct mrf24j40 *devrec = hw->priv;
543
544 dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len);
545 devrec->tx_skb = skb;
546
547 return write_tx_buf(devrec, 0x000, skb->data, skb->len);
548}
549
Alexander Aring5a504392014-10-25 17:16:34 +0200550static int mrf24j40_ed(struct ieee802154_hw *hw, u8 *level)
Alan Ott3731a332012-09-02 15:44:13 +0000551{
552 /* TODO: */
Varka Bhadramca079ad2014-09-24 12:21:32 +0200553 pr_warn("mrf24j40: ed not implemented\n");
Alan Ott3731a332012-09-02 15:44:13 +0000554 *level = 0;
555 return 0;
556}
557
Alexander Aring5a504392014-10-25 17:16:34 +0200558static int mrf24j40_start(struct ieee802154_hw *hw)
Alan Ott3731a332012-09-02 15:44:13 +0000559{
Alexander Aring5a504392014-10-25 17:16:34 +0200560 struct mrf24j40 *devrec = hw->priv;
Alan Ott3731a332012-09-02 15:44:13 +0000561
562 dev_dbg(printdev(devrec), "start\n");
563
Alexander Aring42c71482015-09-21 11:24:31 +0200564 /* Clear TXNIE and RXIE. Enable interrupts */
565 return regmap_update_bits(devrec->regmap_short, REG_INTCON,
566 0x01 | 0x08, 0x00);
Alan Ott3731a332012-09-02 15:44:13 +0000567}
568
Alexander Aring5a504392014-10-25 17:16:34 +0200569static void mrf24j40_stop(struct ieee802154_hw *hw)
Alan Ott3731a332012-09-02 15:44:13 +0000570{
Alexander Aring5a504392014-10-25 17:16:34 +0200571 struct mrf24j40 *devrec = hw->priv;
Varka Bhadram529160d2014-09-24 12:21:30 +0200572
Alan Ott3731a332012-09-02 15:44:13 +0000573 dev_dbg(printdev(devrec), "stop\n");
574
Alexander Aring42c71482015-09-21 11:24:31 +0200575 /* Set TXNIE and RXIE. Disable Interrupts */
576 regmap_update_bits(devrec->regmap_short, REG_INTCON, 0x01 | 0x08,
577 0x01 | 0x08);
Alan Ott3731a332012-09-02 15:44:13 +0000578}
579
Alexander Aringe37d2ec2014-10-28 18:21:19 +0100580static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
Alan Ott3731a332012-09-02 15:44:13 +0000581{
Alexander Aring5a504392014-10-25 17:16:34 +0200582 struct mrf24j40 *devrec = hw->priv;
Alan Ott3731a332012-09-02 15:44:13 +0000583 u8 val;
584 int ret;
585
586 dev_dbg(printdev(devrec), "Set Channel %d\n", channel);
587
588 WARN_ON(page != 0);
589 WARN_ON(channel < MRF24J40_CHAN_MIN);
590 WARN_ON(channel > MRF24J40_CHAN_MAX);
591
592 /* Set Channel TODO */
593 val = (channel-11) << 4 | 0x03;
Alexander Aring42c71482015-09-21 11:24:31 +0200594 ret = regmap_update_bits(devrec->regmap_long, REG_RFCON0, 0xf0, val);
Alan Ott3731a332012-09-02 15:44:13 +0000595 if (ret)
596 return ret;
Alan Ott3731a332012-09-02 15:44:13 +0000597
Alexander Aring42c71482015-09-21 11:24:31 +0200598 /* RF Reset */
599 ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, 0x04, 0x04);
600 if (ret)
601 return ret;
Alan Ott3731a332012-09-02 15:44:13 +0000602
Alexander Aring42c71482015-09-21 11:24:31 +0200603 ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, 0x04, 0x00);
604 if (!ret)
605 udelay(SET_CHANNEL_DELAY_US); /* per datasheet */
606
607 return ret;
Alan Ott3731a332012-09-02 15:44:13 +0000608}
609
Alexander Aring5a504392014-10-25 17:16:34 +0200610static int mrf24j40_filter(struct ieee802154_hw *hw,
Alan Ott3731a332012-09-02 15:44:13 +0000611 struct ieee802154_hw_addr_filt *filt,
612 unsigned long changed)
613{
Alexander Aring5a504392014-10-25 17:16:34 +0200614 struct mrf24j40 *devrec = hw->priv;
Alan Ott3731a332012-09-02 15:44:13 +0000615
616 dev_dbg(printdev(devrec), "filter\n");
617
Alexander Aring57205c12014-10-25 05:25:09 +0200618 if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
Alan Ott3731a332012-09-02 15:44:13 +0000619 /* Short Addr */
620 u8 addrh, addrl;
Varka Bhadram529160d2014-09-24 12:21:30 +0200621
Phoebe Buckheisterb70ab2e2014-03-14 21:23:59 +0100622 addrh = le16_to_cpu(filt->short_addr) >> 8 & 0xff;
623 addrl = le16_to_cpu(filt->short_addr) & 0xff;
Alan Ott3731a332012-09-02 15:44:13 +0000624
Alexander Aring42c71482015-09-21 11:24:31 +0200625 regmap_write(devrec->regmap_short, REG_SADRH, addrh);
626 regmap_write(devrec->regmap_short, REG_SADRL, addrl);
Alan Ott3731a332012-09-02 15:44:13 +0000627 dev_dbg(printdev(devrec),
628 "Set short addr to %04hx\n", filt->short_addr);
629 }
630
Alexander Aring57205c12014-10-25 05:25:09 +0200631 if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
Alan Ott3731a332012-09-02 15:44:13 +0000632 /* Device Address */
Phoebe Buckheisterb70ab2e2014-03-14 21:23:59 +0100633 u8 i, addr[8];
634
635 memcpy(addr, &filt->ieee_addr, 8);
Alan Ott3731a332012-09-02 15:44:13 +0000636 for (i = 0; i < 8; i++)
Alexander Aring42c71482015-09-21 11:24:31 +0200637 regmap_write(devrec->regmap_short, REG_EADR0 + i,
638 addr[i]);
Alan Ott3731a332012-09-02 15:44:13 +0000639
640#ifdef DEBUG
Varka Bhadramca079ad2014-09-24 12:21:32 +0200641 pr_debug("Set long addr to: ");
Alan Ott3731a332012-09-02 15:44:13 +0000642 for (i = 0; i < 8; i++)
Varka Bhadramca079ad2014-09-24 12:21:32 +0200643 pr_debug("%02hhx ", addr[7 - i]);
644 pr_debug("\n");
Alan Ott3731a332012-09-02 15:44:13 +0000645#endif
646 }
647
Alexander Aring57205c12014-10-25 05:25:09 +0200648 if (changed & IEEE802154_AFILT_PANID_CHANGED) {
Alan Ott3731a332012-09-02 15:44:13 +0000649 /* PAN ID */
650 u8 panidl, panidh;
Varka Bhadram529160d2014-09-24 12:21:30 +0200651
Phoebe Buckheisterb70ab2e2014-03-14 21:23:59 +0100652 panidh = le16_to_cpu(filt->pan_id) >> 8 & 0xff;
653 panidl = le16_to_cpu(filt->pan_id) & 0xff;
Alexander Aring42c71482015-09-21 11:24:31 +0200654 regmap_write(devrec->regmap_short, REG_PANIDH, panidh);
655 regmap_write(devrec->regmap_short, REG_PANIDL, panidl);
Alan Ott3731a332012-09-02 15:44:13 +0000656
657 dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id);
658 }
659
Alexander Aring57205c12014-10-25 05:25:09 +0200660 if (changed & IEEE802154_AFILT_PANC_CHANGED) {
Alan Ott3731a332012-09-02 15:44:13 +0000661 /* Pan Coordinator */
662 u8 val;
663 int ret;
664
Alexander Aring42c71482015-09-21 11:24:31 +0200665 if (filt->pan_coord)
666 val = 0x8;
667 else
668 val = 0x0;
669 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x8,
670 val);
Alan Ott3731a332012-09-02 15:44:13 +0000671 if (ret)
672 return ret;
Alan Ott3731a332012-09-02 15:44:13 +0000673
674 /* REG_SLOTTED is maintained as default (unslotted/CSMA-CA).
675 * REG_ORDER is maintained as default (no beacon/superframe).
676 */
677
678 dev_dbg(printdev(devrec), "Set Pan Coord to %s\n",
Stefan Schmidtce261bc2014-12-12 12:45:33 +0100679 filt->pan_coord ? "on" : "off");
Alan Ott3731a332012-09-02 15:44:13 +0000680 }
681
682 return 0;
683}
684
Alexander Aringc91a3012015-09-21 11:24:35 +0200685static void mrf24j40_handle_rx_read_buf_unlock(struct mrf24j40 *devrec)
Alan Ott3731a332012-09-02 15:44:13 +0000686{
Alexander Aringc91a3012015-09-21 11:24:35 +0200687 int ret;
688
689 /* Turn back on reception of packets off the air. */
690 devrec->rx_msg.complete = NULL;
691 devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
692 devrec->rx_buf[1] = 0x00; /* CLR RXDECINV */
693 ret = spi_async(devrec->spi, &devrec->rx_msg);
694 if (ret)
695 dev_err(printdev(devrec), "failed to unlock rx buffer\n");
696}
697
698static void mrf24j40_handle_rx_read_buf_complete(void *context)
699{
700 struct mrf24j40 *devrec = context;
701 u8 len = devrec->rx_buf[2];
702 u8 rx_local_buf[RX_FIFO_SIZE];
Alan Ott3731a332012-09-02 15:44:13 +0000703 struct sk_buff *skb;
704
Alexander Aringc91a3012015-09-21 11:24:35 +0200705 memcpy(rx_local_buf, devrec->rx_fifo_buf, len);
706 mrf24j40_handle_rx_read_buf_unlock(devrec);
Alan Ott3731a332012-09-02 15:44:13 +0000707
Alexander Aringc91a3012015-09-21 11:24:35 +0200708 skb = dev_alloc_skb(IEEE802154_MTU);
Alan Ott3731a332012-09-02 15:44:13 +0000709 if (!skb) {
Alexander Aringc91a3012015-09-21 11:24:35 +0200710 dev_err(printdev(devrec), "failed to allocate skb\n");
711 return;
Alan Ott3731a332012-09-02 15:44:13 +0000712 }
713
Alexander Aringc91a3012015-09-21 11:24:35 +0200714 memcpy(skb_put(skb, len), rx_local_buf, len);
715 ieee802154_rx_irqsafe(devrec->hw, skb, 0);
716
717#ifdef DEBUG
718 print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ", DUMP_PREFIX_OFFSET, 16, 1,
719 rx_local_buf, len, 0);
720 pr_debug("mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n",
721 devrec->rx_lqi_buf[0], devrec->rx_lqi_buf[1]);
722#endif
723}
724
725static void mrf24j40_handle_rx_read_buf(void *context)
726{
727 struct mrf24j40 *devrec = context;
728 u16 cmd;
729 int ret;
730
731 /* if length is invalid read the full MTU */
732 if (!ieee802154_is_valid_psdu_len(devrec->rx_buf[2]))
733 devrec->rx_buf[2] = IEEE802154_MTU;
734
735 cmd = MRF24J40_READLONG(REG_RX_FIFO + 1);
736 devrec->rx_addr_buf[0] = cmd >> 8 & 0xff;
737 devrec->rx_addr_buf[1] = cmd & 0xff;
738 devrec->rx_fifo_buf_trx.len = devrec->rx_buf[2];
739 ret = spi_async(devrec->spi, &devrec->rx_buf_msg);
740 if (ret) {
741 dev_err(printdev(devrec), "failed to read rx buffer\n");
742 mrf24j40_handle_rx_read_buf_unlock(devrec);
Alan Ott3731a332012-09-02 15:44:13 +0000743 }
Alexander Aringc91a3012015-09-21 11:24:35 +0200744}
Alan Ott3731a332012-09-02 15:44:13 +0000745
Alexander Aringc91a3012015-09-21 11:24:35 +0200746static void mrf24j40_handle_rx_read_len(void *context)
747{
748 struct mrf24j40 *devrec = context;
749 u16 cmd;
750 int ret;
Alan Ott3731a332012-09-02 15:44:13 +0000751
Alexander Aringc91a3012015-09-21 11:24:35 +0200752 /* read the length of received frame */
753 devrec->rx_msg.complete = mrf24j40_handle_rx_read_buf;
754 devrec->rx_trx.len = 3;
755 cmd = MRF24J40_READLONG(REG_RX_FIFO);
756 devrec->rx_buf[0] = cmd >> 8 & 0xff;
757 devrec->rx_buf[1] = cmd & 0xff;
Alan Ott3731a332012-09-02 15:44:13 +0000758
Alexander Aringc91a3012015-09-21 11:24:35 +0200759 ret = spi_async(devrec->spi, &devrec->rx_msg);
760 if (ret) {
761 dev_err(printdev(devrec), "failed to read rx buffer length\n");
762 mrf24j40_handle_rx_read_buf_unlock(devrec);
763 }
764}
Alan Ott3731a332012-09-02 15:44:13 +0000765
Alexander Aringc91a3012015-09-21 11:24:35 +0200766static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
767{
768 /* Turn off reception of packets off the air. This prevents the
769 * device from overwriting the buffer while we're reading it.
770 */
771 devrec->rx_msg.complete = mrf24j40_handle_rx_read_len;
772 devrec->rx_trx.len = 2;
773 devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
774 devrec->rx_buf[1] = 0x04; /* SET RXDECINV */
775
776 return spi_async(devrec->spi, &devrec->rx_msg);
Alan Ott3731a332012-09-02 15:44:13 +0000777}
778
Alexander Aring16301862014-10-28 18:21:18 +0100779static const struct ieee802154_ops mrf24j40_ops = {
Alan Ott3731a332012-09-02 15:44:13 +0000780 .owner = THIS_MODULE,
Alexander Aring6844a0e2015-09-21 11:24:34 +0200781 .xmit_async = mrf24j40_tx,
Alan Ott3731a332012-09-02 15:44:13 +0000782 .ed = mrf24j40_ed,
783 .start = mrf24j40_start,
784 .stop = mrf24j40_stop,
785 .set_channel = mrf24j40_set_channel,
786 .set_hw_addr_filt = mrf24j40_filter,
787};
788
Alexander Aring37441612015-09-21 11:24:36 +0200789static void mrf24j40_intstat_complete(void *context)
Alan Ott3731a332012-09-02 15:44:13 +0000790{
Alexander Aring37441612015-09-21 11:24:36 +0200791 struct mrf24j40 *devrec = context;
792 u8 intstat = devrec->irq_buf[1];
Alan Ott3731a332012-09-02 15:44:13 +0000793
Alexander Aring37441612015-09-21 11:24:36 +0200794 enable_irq(devrec->spi->irq);
Alan Ott3731a332012-09-02 15:44:13 +0000795
796 /* Check for TX complete */
797 if (intstat & 0x1)
Alexander Aring6844a0e2015-09-21 11:24:34 +0200798 ieee802154_xmit_complete(devrec->hw, devrec->tx_skb, false);
Alan Ott3731a332012-09-02 15:44:13 +0000799
800 /* Check for Rx */
801 if (intstat & 0x8)
802 mrf24j40_handle_rx(devrec);
Alexander Aring37441612015-09-21 11:24:36 +0200803}
Alan Ott3731a332012-09-02 15:44:13 +0000804
Alexander Aring37441612015-09-21 11:24:36 +0200805static irqreturn_t mrf24j40_isr(int irq, void *data)
806{
807 struct mrf24j40 *devrec = data;
808 int ret;
809
810 disable_irq_nosync(irq);
811
812 devrec->irq_buf[0] = MRF24J40_READSHORT(REG_INTSTAT);
813 /* Read the interrupt status */
814 ret = spi_async(devrec->spi, &devrec->irq_msg);
815 if (ret) {
816 enable_irq(irq);
817 return IRQ_NONE;
818 }
819
Alan Ott4a4e1da2013-10-05 23:52:23 -0400820 return IRQ_HANDLED;
Alan Ott3731a332012-09-02 15:44:13 +0000821}
822
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530823static int mrf24j40_hw_init(struct mrf24j40 *devrec)
824{
825 int ret;
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530826
827 /* Initialize the device.
828 From datasheet section 3.2: Initialization. */
Alexander Aring42c71482015-09-21 11:24:31 +0200829 ret = regmap_write(devrec->regmap_short, REG_SOFTRST, 0x07);
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530830 if (ret)
831 goto err_ret;
832
Alexander Aring42c71482015-09-21 11:24:31 +0200833 ret = regmap_write(devrec->regmap_short, REG_PACON2, 0x98);
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530834 if (ret)
835 goto err_ret;
836
Alexander Aring42c71482015-09-21 11:24:31 +0200837 ret = regmap_write(devrec->regmap_short, REG_TXSTBL, 0x95);
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530838 if (ret)
839 goto err_ret;
840
Alexander Aring42c71482015-09-21 11:24:31 +0200841 ret = regmap_write(devrec->regmap_long, REG_RFCON0, 0x03);
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530842 if (ret)
843 goto err_ret;
844
Alexander Aring42c71482015-09-21 11:24:31 +0200845 ret = regmap_write(devrec->regmap_long, REG_RFCON1, 0x01);
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530846 if (ret)
847 goto err_ret;
848
Alexander Aring42c71482015-09-21 11:24:31 +0200849 ret = regmap_write(devrec->regmap_long, REG_RFCON2, 0x80);
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530850 if (ret)
851 goto err_ret;
852
Alexander Aring42c71482015-09-21 11:24:31 +0200853 ret = regmap_write(devrec->regmap_long, REG_RFCON6, 0x90);
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530854 if (ret)
855 goto err_ret;
856
Alexander Aring42c71482015-09-21 11:24:31 +0200857 ret = regmap_write(devrec->regmap_long, REG_RFCON7, 0x80);
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530858 if (ret)
859 goto err_ret;
860
Alexander Aring42c71482015-09-21 11:24:31 +0200861 ret = regmap_write(devrec->regmap_long, REG_RFCON8, 0x10);
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530862 if (ret)
863 goto err_ret;
864
Alexander Aring42c71482015-09-21 11:24:31 +0200865 ret = regmap_write(devrec->regmap_long, REG_SLPCON1, 0x21);
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530866 if (ret)
867 goto err_ret;
868
Alexander Aring42c71482015-09-21 11:24:31 +0200869 ret = regmap_write(devrec->regmap_short, REG_BBREG2, 0x80);
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530870 if (ret)
871 goto err_ret;
872
Alexander Aring42c71482015-09-21 11:24:31 +0200873 ret = regmap_write(devrec->regmap_short, REG_CCAEDTH, 0x60);
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530874 if (ret)
875 goto err_ret;
876
Alexander Aring42c71482015-09-21 11:24:31 +0200877 ret = regmap_write(devrec->regmap_short, REG_BBREG6, 0x40);
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530878 if (ret)
879 goto err_ret;
880
Alexander Aring42c71482015-09-21 11:24:31 +0200881 ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x04);
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530882 if (ret)
883 goto err_ret;
884
Alexander Aring42c71482015-09-21 11:24:31 +0200885 ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x0);
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530886 if (ret)
887 goto err_ret;
888
889 udelay(192);
890
891 /* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */
Alexander Aring42c71482015-09-21 11:24:31 +0200892 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x03, 0x00);
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530893 if (ret)
894 goto err_ret;
895
Simon Vincentdb9e0ee2014-10-06 10:39:45 +0100896 if (spi_get_device_id(devrec->spi)->driver_data == MRF24J40MC) {
897 /* Enable external amplifier.
898 * From MRF24J40MC datasheet section 1.3: Operation.
899 */
Alexander Aring42c71482015-09-21 11:24:31 +0200900 regmap_update_bits(devrec->regmap_long, REG_TESTMODE, 0x07,
901 0x07);
Simon Vincentdb9e0ee2014-10-06 10:39:45 +0100902
Alexander Aring42c71482015-09-21 11:24:31 +0200903 /* Set GPIO3 as output. */
904 regmap_update_bits(devrec->regmap_short, REG_TRISGPIO, 0x08,
905 0x08);
Simon Vincentdb9e0ee2014-10-06 10:39:45 +0100906
Alexander Aring42c71482015-09-21 11:24:31 +0200907 /* Set GPIO3 HIGH to enable U5 voltage regulator */
908 regmap_update_bits(devrec->regmap_short, REG_GPIO, 0x08, 0x08);
Simon Vincentdb9e0ee2014-10-06 10:39:45 +0100909
910 /* Reduce TX pwr to meet FCC requirements.
911 * From MRF24J40MC datasheet section 3.1.1
912 */
Alexander Aring42c71482015-09-21 11:24:31 +0200913 regmap_write(devrec->regmap_long, REG_RFCON3, 0x28);
Simon Vincentdb9e0ee2014-10-06 10:39:45 +0100914 }
915
Varka Bhadram3dac9a72014-06-16 09:12:31 +0530916 return 0;
917
918err_ret:
919 return ret;
920}
921
Alexander Aring6844a0e2015-09-21 11:24:34 +0200922static void
923mrf24j40_setup_tx_spi_messages(struct mrf24j40 *devrec)
924{
925 spi_message_init(&devrec->tx_msg);
926 devrec->tx_msg.context = devrec;
927 devrec->tx_msg.complete = write_tx_buf_complete;
928 devrec->tx_hdr_trx.len = 2;
929 devrec->tx_hdr_trx.tx_buf = devrec->tx_hdr_buf;
930 spi_message_add_tail(&devrec->tx_hdr_trx, &devrec->tx_msg);
931 devrec->tx_len_trx.len = 2;
932 devrec->tx_len_trx.tx_buf = devrec->tx_len_buf;
933 spi_message_add_tail(&devrec->tx_len_trx, &devrec->tx_msg);
934 spi_message_add_tail(&devrec->tx_buf_trx, &devrec->tx_msg);
935
936 spi_message_init(&devrec->tx_post_msg);
937 devrec->tx_post_msg.context = devrec;
938 devrec->tx_post_trx.len = 2;
939 devrec->tx_post_trx.tx_buf = devrec->tx_post_buf;
940 spi_message_add_tail(&devrec->tx_post_trx, &devrec->tx_post_msg);
941}
942
Alexander Aringc91a3012015-09-21 11:24:35 +0200943static void
944mrf24j40_setup_rx_spi_messages(struct mrf24j40 *devrec)
945{
946 spi_message_init(&devrec->rx_msg);
947 devrec->rx_msg.context = devrec;
948 devrec->rx_trx.len = 2;
949 devrec->rx_trx.tx_buf = devrec->rx_buf;
950 devrec->rx_trx.rx_buf = devrec->rx_buf;
951 spi_message_add_tail(&devrec->rx_trx, &devrec->rx_msg);
952
953 spi_message_init(&devrec->rx_buf_msg);
954 devrec->rx_buf_msg.context = devrec;
955 devrec->rx_buf_msg.complete = mrf24j40_handle_rx_read_buf_complete;
956 devrec->rx_addr_trx.len = 2;
957 devrec->rx_addr_trx.tx_buf = devrec->rx_addr_buf;
958 spi_message_add_tail(&devrec->rx_addr_trx, &devrec->rx_buf_msg);
959 devrec->rx_fifo_buf_trx.rx_buf = devrec->rx_fifo_buf;
960 spi_message_add_tail(&devrec->rx_fifo_buf_trx, &devrec->rx_buf_msg);
961 devrec->rx_lqi_trx.len = 2;
962 devrec->rx_lqi_trx.rx_buf = devrec->rx_lqi_buf;
963 spi_message_add_tail(&devrec->rx_lqi_trx, &devrec->rx_buf_msg);
964}
965
Alexander Aring37441612015-09-21 11:24:36 +0200966static void
967mrf24j40_setup_irq_spi_messages(struct mrf24j40 *devrec)
968{
969 spi_message_init(&devrec->irq_msg);
970 devrec->irq_msg.context = devrec;
971 devrec->irq_msg.complete = mrf24j40_intstat_complete;
972 devrec->irq_trx.len = 2;
973 devrec->irq_trx.tx_buf = devrec->irq_buf;
974 devrec->irq_trx.rx_buf = devrec->irq_buf;
975 spi_message_add_tail(&devrec->irq_trx, &devrec->irq_msg);
976}
977
Alexander Aring766928f2015-09-21 11:24:27 +0200978static void mrf24j40_phy_setup(struct mrf24j40 *devrec)
979{
Alexander Aringd344c912015-09-21 11:24:28 +0200980 ieee802154_random_extended_addr(&devrec->hw->phy->perm_extended_addr);
Alexander Aring766928f2015-09-21 11:24:27 +0200981 devrec->hw->phy->current_channel = 11;
982}
983
Bill Pembertonbb1f4602012-12-03 09:24:12 -0500984static int mrf24j40_probe(struct spi_device *spi)
Alan Ott3731a332012-09-02 15:44:13 +0000985{
986 int ret = -ENOMEM;
Alexander Aringb2cfdf32015-09-21 11:24:23 +0200987 struct ieee802154_hw *hw;
Alan Ott3731a332012-09-02 15:44:13 +0000988 struct mrf24j40 *devrec;
989
Varka Bhadramca079ad2014-09-24 12:21:32 +0200990 dev_info(&spi->dev, "probe(). IRQ: %d\n", spi->irq);
Alan Ott3731a332012-09-02 15:44:13 +0000991
Alexander Aringb2cfdf32015-09-21 11:24:23 +0200992 /* Register with the 802154 subsystem */
993
994 hw = ieee802154_alloc_hw(sizeof(*devrec), &mrf24j40_ops);
995 if (!hw)
Varka Bhadram0aaf43f2014-06-11 10:04:44 +0530996 goto err_ret;
Alexander Aringb2cfdf32015-09-21 11:24:23 +0200997
998 devrec = hw->priv;
999 devrec->spi = spi;
1000 spi_set_drvdata(spi, devrec);
1001 devrec->hw = hw;
1002 devrec->hw->parent = &spi->dev;
1003 devrec->hw->phy->supported.channels[0] = CHANNEL_MASK;
Alexander Aringab40ff72015-09-21 11:24:32 +02001004 devrec->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AFILT;
Alexander Aringb2cfdf32015-09-21 11:24:23 +02001005
Alexander Aring6844a0e2015-09-21 11:24:34 +02001006 mrf24j40_setup_tx_spi_messages(devrec);
Alexander Aringc91a3012015-09-21 11:24:35 +02001007 mrf24j40_setup_rx_spi_messages(devrec);
Alexander Aring37441612015-09-21 11:24:36 +02001008 mrf24j40_setup_irq_spi_messages(devrec);
Alexander Aring6844a0e2015-09-21 11:24:34 +02001009
Alexander Aringb0156792015-09-21 11:24:30 +02001010 devrec->regmap_short = devm_regmap_init_spi(spi,
1011 &mrf24j40_short_regmap);
1012 if (IS_ERR(devrec->regmap_short)) {
1013 ret = PTR_ERR(devrec->regmap_short);
1014 dev_err(&spi->dev, "Failed to allocate short register map: %d\n",
1015 ret);
1016 goto err_register_device;
1017 }
1018
1019 devrec->regmap_long = devm_regmap_init(&spi->dev,
1020 &mrf24j40_long_regmap_bus,
1021 spi, &mrf24j40_long_regmap);
1022 if (IS_ERR(devrec->regmap_long)) {
1023 ret = PTR_ERR(devrec->regmap_long);
1024 dev_err(&spi->dev, "Failed to allocate long register map: %d\n",
1025 ret);
1026 goto err_register_device;
1027 }
1028
Alexander Aring78aedb62015-09-21 11:24:25 +02001029 if (spi->max_speed_hz > MAX_SPI_SPEED_HZ) {
1030 dev_warn(&spi->dev, "spi clock above possible maximum: %d",
1031 MAX_SPI_SPEED_HZ);
1032 return -EINVAL;
1033 }
Alan Ott3731a332012-09-02 15:44:13 +00001034
Varka Bhadram3dac9a72014-06-16 09:12:31 +05301035 ret = mrf24j40_hw_init(devrec);
Alan Ott3731a332012-09-02 15:44:13 +00001036 if (ret)
Alexander Aringa339e182015-09-21 11:24:24 +02001037 goto err_register_device;
Alan Ott3731a332012-09-02 15:44:13 +00001038
Alexander Aring766928f2015-09-21 11:24:27 +02001039 mrf24j40_phy_setup(devrec);
1040
Alexander Aring37441612015-09-21 11:24:36 +02001041 ret = devm_request_irq(&spi->dev, spi->irq, mrf24j40_isr,
1042 IRQF_TRIGGER_LOW, dev_name(&spi->dev),
1043 devrec);
Alan Ott3731a332012-09-02 15:44:13 +00001044 if (ret) {
1045 dev_err(printdev(devrec), "Unable to get IRQ");
Alexander Aringa339e182015-09-21 11:24:24 +02001046 goto err_register_device;
Alan Ott3731a332012-09-02 15:44:13 +00001047 }
1048
Alexander Aringa339e182015-09-21 11:24:24 +02001049 dev_dbg(printdev(devrec), "registered mrf24j40\n");
1050 ret = ieee802154_register_hw(devrec->hw);
1051 if (ret)
1052 goto err_register_device;
1053
Alan Ott3731a332012-09-02 15:44:13 +00001054 return 0;
1055
Alan Ott3731a332012-09-02 15:44:13 +00001056err_register_device:
Alexander Aring5a504392014-10-25 17:16:34 +02001057 ieee802154_free_hw(devrec->hw);
Varka Bhadram0aaf43f2014-06-11 10:04:44 +05301058err_ret:
Alan Ott3731a332012-09-02 15:44:13 +00001059 return ret;
1060}
1061
Bill Pembertonbb1f4602012-12-03 09:24:12 -05001062static int mrf24j40_remove(struct spi_device *spi)
Alan Ott3731a332012-09-02 15:44:13 +00001063{
Jingoo Han4fa0a0e2013-04-05 20:34:18 +00001064 struct mrf24j40 *devrec = spi_get_drvdata(spi);
Alan Ott3731a332012-09-02 15:44:13 +00001065
1066 dev_dbg(printdev(devrec), "remove\n");
1067
Alexander Aring5a504392014-10-25 17:16:34 +02001068 ieee802154_unregister_hw(devrec->hw);
1069 ieee802154_free_hw(devrec->hw);
Alan Ott3731a332012-09-02 15:44:13 +00001070 /* TODO: Will ieee802154_free_device() wait until ->xmit() is
1071 * complete? */
1072
Alan Ott3731a332012-09-02 15:44:13 +00001073 return 0;
1074}
1075
Alexander Aring2e6fd642015-09-21 11:24:26 +02001076static const struct of_device_id mrf24j40_of_match[] = {
1077 { .compatible = "microchip,mrf24j40", .data = (void *)MRF24J40 },
1078 { .compatible = "microchip,mrf24j40ma", .data = (void *)MRF24J40MA },
1079 { .compatible = "microchip,mrf24j40mc", .data = (void *)MRF24J40MC },
1080 { },
1081};
1082MODULE_DEVICE_TABLE(of, mrf24j40_of_match);
1083
Alan Ott3731a332012-09-02 15:44:13 +00001084static const struct spi_device_id mrf24j40_ids[] = {
Simon Vincentdb9e0ee2014-10-06 10:39:45 +01001085 { "mrf24j40", MRF24J40 },
1086 { "mrf24j40ma", MRF24J40MA },
1087 { "mrf24j40mc", MRF24J40MC },
Alan Ott3731a332012-09-02 15:44:13 +00001088 { },
1089};
1090MODULE_DEVICE_TABLE(spi, mrf24j40_ids);
1091
1092static struct spi_driver mrf24j40_driver = {
1093 .driver = {
Alexander Aring2e6fd642015-09-21 11:24:26 +02001094 .of_match_table = of_match_ptr(mrf24j40_of_match),
Alan Ott3731a332012-09-02 15:44:13 +00001095 .name = "mrf24j40",
Alan Ott3731a332012-09-02 15:44:13 +00001096 .owner = THIS_MODULE,
1097 },
1098 .id_table = mrf24j40_ids,
1099 .probe = mrf24j40_probe,
Bill Pembertonbb1f4602012-12-03 09:24:12 -05001100 .remove = mrf24j40_remove,
Alan Ott3731a332012-09-02 15:44:13 +00001101};
1102
Wei Yongjun3d4a1312013-04-08 20:34:44 +00001103module_spi_driver(mrf24j40_driver);
Alan Ott3731a332012-09-02 15:44:13 +00001104
1105MODULE_LICENSE("GPL");
1106MODULE_AUTHOR("Alan Ott");
1107MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver");