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Mika Westerbergd16a5aa2014-03-20 22:04:23 +08001/*
2 * Intel Low Power Subsystem PWM controller driver
3 *
4 * Copyright (C) 2014, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Author: Chew Kean Ho <kean.ho.chew@intel.com>
7 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
8 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
Alan Cox093e00b2014-04-18 19:17:40 +08009 * Author: Alan Cox <alan@linux.intel.com>
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080010 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
Mika Westerberg37670672015-11-18 13:25:18 +020016#include <linux/delay.h>
Thierry Redinge0c86a32014-08-23 00:22:45 +020017#include <linux/io.h>
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080018#include <linux/kernel.h>
19#include <linux/module.h>
Qipeng Zhaf080be22015-10-26 12:58:27 +020020#include <linux/pm_runtime.h>
qipeng.zha883e4d02015-11-17 17:20:15 +080021#include <linux/time.h>
Alan Cox093e00b2014-04-18 19:17:40 +080022
Andy Shevchenkoc558e392014-08-19 19:17:35 +030023#include "pwm-lpss.h"
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080024
25#define PWM 0x00000000
26#define PWM_ENABLE BIT(31)
27#define PWM_SW_UPDATE BIT(30)
28#define PWM_BASE_UNIT_SHIFT 8
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080029#define PWM_ON_TIME_DIV_MASK 0x000000ff
30#define PWM_DIVISION_CORRECTION 0x2
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080031
Mika Westerberg4e11f5a2015-10-20 16:53:05 +030032/* Size of each PWM register space if multiple */
33#define PWM_SIZE 0x400
34
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080035struct pwm_lpss_chip {
36 struct pwm_chip chip;
37 void __iomem *regs;
qipeng.zha883e4d02015-11-17 17:20:15 +080038 const struct pwm_lpss_boardinfo *info;
Alan Cox093e00b2014-04-18 19:17:40 +080039};
40
Alan Cox093e00b2014-04-18 19:17:40 +080041/* BayTrail */
Andy Shevchenkoc558e392014-08-19 19:17:35 +030042const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
Mika Westerberg4e11f5a2015-10-20 16:53:05 +030043 .clk_rate = 25000000,
44 .npwm = 1,
qipeng.zha883e4d02015-11-17 17:20:15 +080045 .base_unit_bits = 16,
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080046};
Andy Shevchenkoc558e392014-08-19 19:17:35 +030047EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080048
Alan Cox373c5782014-08-19 17:18:29 +030049/* Braswell */
Andy Shevchenkoc558e392014-08-19 19:17:35 +030050const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
Mika Westerberg4e11f5a2015-10-20 16:53:05 +030051 .clk_rate = 19200000,
52 .npwm = 1,
qipeng.zha883e4d02015-11-17 17:20:15 +080053 .base_unit_bits = 16,
Alan Cox373c5782014-08-19 17:18:29 +030054};
Andy Shevchenkoc558e392014-08-19 19:17:35 +030055EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);
Alan Cox373c5782014-08-19 17:18:29 +030056
Mika Westerberg87219cb2015-10-20 16:53:06 +030057/* Broxton */
58const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = {
59 .clk_rate = 19200000,
60 .npwm = 4,
qipeng.zha883e4d02015-11-17 17:20:15 +080061 .base_unit_bits = 22,
Mika Westerberg87219cb2015-10-20 16:53:06 +030062};
63EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info);
64
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080065static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
66{
67 return container_of(chip, struct pwm_lpss_chip, chip);
68}
69
Mika Westerberg4e11f5a2015-10-20 16:53:05 +030070static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
71{
72 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
73
74 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
75}
76
77static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
78{
79 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
80
81 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
82}
83
Mika Westerberg37670672015-11-18 13:25:18 +020084static void pwm_lpss_update(struct pwm_device *pwm)
85{
86 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE);
87 /* Give it some time to propagate */
88 usleep_range(10, 50);
89}
90
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080091static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm,
92 int duty_ns, int period_ns)
93{
94 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
95 u8 on_time_div;
qipeng.zha883e4d02015-11-17 17:20:15 +080096 unsigned long c, base_unit_range;
97 unsigned long long base_unit, freq = NSEC_PER_SEC;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080098 u32 ctrl;
99
100 do_div(freq, period_ns);
101
qipeng.zha883e4d02015-11-17 17:20:15 +0800102 /*
103 * The equation is:
104 * base_unit = ((freq / c) * base_unit_range) + correction
105 */
106 base_unit_range = BIT(lpwm->info->base_unit_bits);
107 base_unit = freq * base_unit_range;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800108
qipeng.zha883e4d02015-11-17 17:20:15 +0800109 c = lpwm->info->clk_rate;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800110 if (!c)
111 return -EINVAL;
112
113 do_div(base_unit, c);
114 base_unit += PWM_DIVISION_CORRECTION;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800115
116 if (duty_ns <= 0)
117 duty_ns = 1;
118 on_time_div = 255 - (255 * duty_ns / period_ns);
119
Qipeng Zhaf080be22015-10-26 12:58:27 +0200120 pm_runtime_get_sync(chip->dev);
121
Mika Westerberg4e11f5a2015-10-20 16:53:05 +0300122 ctrl = pwm_lpss_read(pwm);
qipeng.zha883e4d02015-11-17 17:20:15 +0800123 ctrl &= ~PWM_ON_TIME_DIV_MASK;
124 ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT);
125 base_unit &= (base_unit_range - 1);
126 ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800127 ctrl |= on_time_div;
Mika Westerberg4e11f5a2015-10-20 16:53:05 +0300128 pwm_lpss_write(pwm, ctrl);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800129
Mika Westerberg37670672015-11-18 13:25:18 +0200130 /*
131 * If the PWM is already enabled we need to notify the hardware
132 * about the change by setting PWM_SW_UPDATE.
133 */
134 if (pwm_is_enabled(pwm))
135 pwm_lpss_update(pwm);
136
Qipeng Zhaf080be22015-10-26 12:58:27 +0200137 pm_runtime_put(chip->dev);
138
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800139 return 0;
140}
141
142static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm)
143{
Qipeng Zhaf080be22015-10-26 12:58:27 +0200144 pm_runtime_get_sync(chip->dev);
Mika Westerberg37670672015-11-18 13:25:18 +0200145
146 /*
147 * Hardware must first see PWM_SW_UPDATE before the PWM can be
148 * enabled.
149 */
150 pwm_lpss_update(pwm);
Mika Westerberg4e11f5a2015-10-20 16:53:05 +0300151 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800152 return 0;
153}
154
155static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm)
156{
Mika Westerberg4e11f5a2015-10-20 16:53:05 +0300157 pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
Qipeng Zhaf080be22015-10-26 12:58:27 +0200158 pm_runtime_put(chip->dev);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800159}
160
161static const struct pwm_ops pwm_lpss_ops = {
162 .config = pwm_lpss_config,
163 .enable = pwm_lpss_enable,
164 .disable = pwm_lpss_disable,
165 .owner = THIS_MODULE,
166};
167
Andy Shevchenkoc558e392014-08-19 19:17:35 +0300168struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
169 const struct pwm_lpss_boardinfo *info)
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800170{
171 struct pwm_lpss_chip *lpwm;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800172 int ret;
173
Alan Cox093e00b2014-04-18 19:17:40 +0800174 lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800175 if (!lpwm)
Alan Cox093e00b2014-04-18 19:17:40 +0800176 return ERR_PTR(-ENOMEM);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800177
Alan Cox093e00b2014-04-18 19:17:40 +0800178 lpwm->regs = devm_ioremap_resource(dev, r);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800179 if (IS_ERR(lpwm->regs))
Thierry Reding89c03392014-05-07 10:27:57 +0200180 return ERR_CAST(lpwm->regs);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800181
qipeng.zha883e4d02015-11-17 17:20:15 +0800182 lpwm->info = info;
Alan Cox093e00b2014-04-18 19:17:40 +0800183 lpwm->chip.dev = dev;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800184 lpwm->chip.ops = &pwm_lpss_ops;
185 lpwm->chip.base = -1;
Mika Westerberg4e11f5a2015-10-20 16:53:05 +0300186 lpwm->chip.npwm = info->npwm;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800187
188 ret = pwmchip_add(&lpwm->chip);
189 if (ret) {
Alan Cox093e00b2014-04-18 19:17:40 +0800190 dev_err(dev, "failed to add PWM chip: %d\n", ret);
191 return ERR_PTR(ret);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800192 }
193
Alan Cox093e00b2014-04-18 19:17:40 +0800194 return lpwm;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800195}
Andy Shevchenkoc558e392014-08-19 19:17:35 +0300196EXPORT_SYMBOL_GPL(pwm_lpss_probe);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800197
Andy Shevchenkoc558e392014-08-19 19:17:35 +0300198int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800199{
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800200 return pwmchip_remove(&lpwm->chip);
201}
Andy Shevchenkoc558e392014-08-19 19:17:35 +0300202EXPORT_SYMBOL_GPL(pwm_lpss_remove);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800203
204MODULE_DESCRIPTION("PWM driver for Intel LPSS");
205MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
206MODULE_LICENSE("GPL v2");