Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Carsten Langgaard, carstenl@mips.com |
| 3 | * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. |
| 4 | * |
| 5 | * This program is free software; you can distribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License (Version 2) as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 12 | * for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along |
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 16 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
| 17 | * |
| 18 | * Setting up the clock on the MIPS boards. |
| 19 | */ |
| 20 | |
| 21 | #include <linux/types.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | #include <linux/init.h> |
| 23 | #include <linux/kernel_stat.h> |
| 24 | #include <linux/sched.h> |
| 25 | #include <linux/spinlock.h> |
| 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/time.h> |
| 28 | #include <linux/timex.h> |
| 29 | #include <linux/mc146818rtc.h> |
| 30 | |
| 31 | #include <asm/mipsregs.h> |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 32 | #include <asm/mipsmtregs.h> |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 33 | #include <asm/hardirq.h> |
Ralf Baechle | d865bea | 2007-10-11 23:46:10 +0100 | [diff] [blame] | 34 | #include <asm/i8253.h> |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 35 | #include <asm/irq.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | #include <asm/div64.h> |
| 37 | #include <asm/cpu.h> |
| 38 | #include <asm/time.h> |
| 39 | #include <asm/mc146818-time.h> |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 40 | #include <asm/msc01_ic.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | |
| 42 | #include <asm/mips-boards/generic.h> |
| 43 | #include <asm/mips-boards/prom.h> |
Maciej W. Rozycki | fc095a9 | 2006-09-12 19:12:18 +0100 | [diff] [blame] | 44 | |
| 45 | #ifdef CONFIG_MIPS_ATLAS |
| 46 | #include <asm/mips-boards/atlasint.h> |
| 47 | #endif |
| 48 | #ifdef CONFIG_MIPS_MALTA |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 49 | #include <asm/mips-boards/maltaint.h> |
Maciej W. Rozycki | fc095a9 | 2006-09-12 19:12:18 +0100 | [diff] [blame] | 50 | #endif |
Atsushi Nemoto | f75f369 | 2007-01-08 01:27:40 +0900 | [diff] [blame] | 51 | #ifdef CONFIG_MIPS_SEAD |
| 52 | #include <asm/mips-boards/seadint.h> |
| 53 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | |
| 55 | unsigned long cpu_khz; |
| 56 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 57 | static int mips_cpu_timer_irq; |
Ralf Baechle | 3b1d4ed | 2007-06-20 22:27:10 +0100 | [diff] [blame] | 58 | extern int cp0_perfcount_irq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 60 | static void mips_timer_dispatch(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 61 | { |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 62 | do_IRQ(mips_cpu_timer_irq); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 63 | } |
| 64 | |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame] | 65 | static void mips_perf_dispatch(void) |
| 66 | { |
Ralf Baechle | 3b1d4ed | 2007-06-20 22:27:10 +0100 | [diff] [blame] | 67 | do_IRQ(cp0_perfcount_irq); |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame] | 68 | } |
| 69 | |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 70 | /* |
Ralf Baechle | 224dc50 | 2006-10-21 02:05:20 +0100 | [diff] [blame] | 71 | * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 72 | */ |
| 73 | static unsigned int __init estimate_cpu_frequency(void) |
| 74 | { |
| 75 | unsigned int prid = read_c0_prid() & 0xffff00; |
| 76 | unsigned int count; |
| 77 | |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 78 | #if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 79 | /* |
| 80 | * The SEAD board doesn't have a real time clock, so we can't |
| 81 | * really calculate the timer frequency |
| 82 | * For now we hardwire the SEAD board frequency to 12MHz. |
| 83 | */ |
Ralf Baechle | 42a3b4f | 2005-09-03 15:56:17 -0700 | [diff] [blame] | 84 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 85 | if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) || |
| 86 | (prid == (PRID_COMP_MIPS | PRID_IMP_25KF))) |
| 87 | count = 12000000; |
| 88 | else |
| 89 | count = 6000000; |
| 90 | #endif |
| 91 | #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) |
Ralf Baechle | e79f55a | 2006-10-31 19:53:15 +0000 | [diff] [blame] | 92 | unsigned long flags; |
Ralf Baechle | 70e46f4 | 2006-10-31 18:33:09 +0000 | [diff] [blame] | 93 | unsigned int start; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 94 | |
| 95 | local_irq_save(flags); |
| 96 | |
| 97 | /* Start counter exactly on falling edge of update flag */ |
| 98 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); |
| 99 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); |
| 100 | |
| 101 | /* Start r4k counter. */ |
Ralf Baechle | 70e46f4 | 2006-10-31 18:33:09 +0000 | [diff] [blame] | 102 | start = read_c0_count(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | |
| 104 | /* Read counter exactly on falling edge of update flag */ |
| 105 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); |
| 106 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); |
| 107 | |
Ralf Baechle | 70e46f4 | 2006-10-31 18:33:09 +0000 | [diff] [blame] | 108 | count = read_c0_count() - start; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 109 | |
| 110 | /* restore interrupts */ |
| 111 | local_irq_restore(flags); |
| 112 | #endif |
| 113 | |
| 114 | mips_hpt_frequency = count; |
| 115 | if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && |
| 116 | (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) |
| 117 | count *= 2; |
| 118 | |
| 119 | count += 5000; /* round */ |
| 120 | count -= count%10000; |
| 121 | |
| 122 | return count; |
| 123 | } |
| 124 | |
Ralf Baechle | 4b55048 | 2007-10-11 23:46:08 +0100 | [diff] [blame] | 125 | unsigned long read_persistent_clock(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 126 | { |
| 127 | return mc146818_get_cmos_time(); |
| 128 | } |
| 129 | |
Ralf Baechle | 91a2fcc | 2007-10-11 23:46:09 +0100 | [diff] [blame] | 130 | void __init plat_perf_setup(void) |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame] | 131 | { |
Ralf Baechle | 3b1d4ed | 2007-06-20 22:27:10 +0100 | [diff] [blame] | 132 | cp0_perfcount_irq = -1; |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame] | 133 | |
| 134 | #ifdef MSC01E_INT_BASE |
| 135 | if (cpu_has_veic) { |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 136 | set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch); |
Ralf Baechle | 3b1d4ed | 2007-06-20 22:27:10 +0100 | [diff] [blame] | 137 | cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame] | 138 | } else |
| 139 | #endif |
Ralf Baechle | 3b1d4ed | 2007-06-20 22:27:10 +0100 | [diff] [blame] | 140 | if (cp0_perfcount_irq >= 0) { |
| 141 | if (cpu_has_vint) |
| 142 | set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame] | 143 | #ifdef CONFIG_SMP |
Ralf Baechle | 3b1d4ed | 2007-06-20 22:27:10 +0100 | [diff] [blame] | 144 | set_irq_handler(cp0_perfcount_irq, handle_percpu_irq); |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame] | 145 | #endif |
| 146 | } |
| 147 | } |
| 148 | |
Ralf Baechle | 234fcd1 | 2008-03-08 09:56:28 +0000 | [diff] [blame] | 149 | unsigned int __cpuinit get_c0_compare_int(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 150 | { |
Chris Dearman | 7b4f4ec | 2007-05-24 22:46:25 +0100 | [diff] [blame] | 151 | #ifdef MSC01E_INT_BASE |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 152 | if (cpu_has_veic) { |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 153 | set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 154 | mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; |
Ralf Baechle | 38760d4 | 2007-10-29 14:23:43 +0000 | [diff] [blame] | 155 | } else |
Chris Dearman | 7b4f4ec | 2007-05-24 22:46:25 +0100 | [diff] [blame] | 156 | #endif |
| 157 | { |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame] | 158 | if (cpu_has_vint) |
Ralf Baechle | 3b1d4ed | 2007-06-20 22:27:10 +0100 | [diff] [blame] | 159 | set_vi_handler(cp0_compare_irq, mips_timer_dispatch); |
| 160 | mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame] | 161 | } |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 162 | |
Ralf Baechle | 38760d4 | 2007-10-29 14:23:43 +0000 | [diff] [blame] | 163 | return mips_cpu_timer_irq; |
| 164 | } |
| 165 | |
| 166 | void __init plat_time_init(void) |
| 167 | { |
| 168 | unsigned int est_freq; |
| 169 | |
| 170 | /* Set Data mode - binary. */ |
| 171 | CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); |
| 172 | |
| 173 | est_freq = estimate_cpu_frequency(); |
| 174 | |
| 175 | printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, |
| 176 | (est_freq%1000000)*100/1000000); |
| 177 | |
| 178 | cpu_khz = est_freq / 1000; |
| 179 | |
| 180 | mips_scroll_message(); |
| 181 | #ifdef CONFIG_I8253 /* Only Malta has a PIT */ |
| 182 | setup_pit_timer(); |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 183 | #endif |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame] | 184 | |
Ralf Baechle | 91a2fcc | 2007-10-11 23:46:09 +0100 | [diff] [blame] | 185 | plat_perf_setup(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 186 | } |