Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Pierre Ossman | 70f1048 | 2007-07-11 20:04:50 +0200 | [diff] [blame] | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 5 | * Copyright (C) 2010 ST-Ericsson SA |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | #include <linux/module.h> |
| 12 | #include <linux/moduleparam.h> |
| 13 | #include <linux/init.h> |
| 14 | #include <linux/ioport.h> |
| 15 | #include <linux/device.h> |
| 16 | #include <linux/interrupt.h> |
Russell King | 613b152 | 2011-01-30 21:06:53 +0000 | [diff] [blame] | 17 | #include <linux/kernel.h> |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 18 | #include <linux/slab.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 19 | #include <linux/delay.h> |
| 20 | #include <linux/err.h> |
| 21 | #include <linux/highmem.h> |
Nicolas Pitre | 019a5f5 | 2007-10-11 01:06:03 -0400 | [diff] [blame] | 22 | #include <linux/log2.h> |
Ulf Hansson | 70be208 | 2013-01-07 15:35:06 +0100 | [diff] [blame] | 23 | #include <linux/mmc/pm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | #include <linux/mmc/host.h> |
Linus Walleij | 3417780 | 2010-10-19 12:43:58 +0100 | [diff] [blame] | 25 | #include <linux/mmc/card.h> |
Russell King | a62c80e | 2006-01-07 13:52:45 +0000 | [diff] [blame] | 26 | #include <linux/amba/bus.h> |
Russell King | f8ce254 | 2006-01-07 16:15:52 +0000 | [diff] [blame] | 27 | #include <linux/clk.h> |
Jens Axboe | bd6dee6 | 2007-10-24 09:01:09 +0200 | [diff] [blame] | 28 | #include <linux/scatterlist.h> |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 29 | #include <linux/gpio.h> |
Lee Jones | 9a59701 | 2012-04-12 16:51:13 +0100 | [diff] [blame] | 30 | #include <linux/of_gpio.h> |
Linus Walleij | 34e84f3 | 2009-09-22 14:41:40 +0100 | [diff] [blame] | 31 | #include <linux/regulator/consumer.h> |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 32 | #include <linux/dmaengine.h> |
| 33 | #include <linux/dma-mapping.h> |
| 34 | #include <linux/amba/mmci.h> |
Russell King | 1c3be36 | 2011-08-14 09:17:05 +0100 | [diff] [blame] | 35 | #include <linux/pm_runtime.h> |
Viresh Kumar | 258aea7 | 2012-02-01 16:12:19 +0530 | [diff] [blame] | 36 | #include <linux/types.h> |
Linus Walleij | a9a8378 | 2012-10-29 14:39:30 +0100 | [diff] [blame] | 37 | #include <linux/pinctrl/consumer.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | |
Russell King | 7b09cda | 2005-07-01 12:02:59 +0100 | [diff] [blame] | 39 | #include <asm/div64.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | #include <asm/io.h> |
Russell King | c6b8fda | 2005-10-28 14:05:16 +0100 | [diff] [blame] | 41 | #include <asm/sizes.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | |
| 43 | #include "mmci.h" |
| 44 | |
| 45 | #define DRIVER_NAME "mmci-pl18x" |
| 46 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | static unsigned int fmax = 515633; |
| 48 | |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 49 | /** |
| 50 | * struct variant_data - MMCI variant-specific quirks |
| 51 | * @clkreg: default value for MCICLOCK register |
Rabin Vincent | 4380c14 | 2010-07-21 12:55:18 +0100 | [diff] [blame] | 52 | * @clkreg_enable: enable value for MMCICLOCK register |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 53 | * @datalength_bits: number of bits in the MMCIDATALENGTH register |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 54 | * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY |
| 55 | * is asserted (likewise for RX) |
| 56 | * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY |
| 57 | * is asserted (likewise for RX) |
Linus Walleij | 3417780 | 2010-10-19 12:43:58 +0100 | [diff] [blame] | 58 | * @sdio: variant supports SDIO |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 59 | * @st_clkdiv: true if using a ST-specific clock divider algorithm |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 60 | * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 61 | * @pwrreg_powerup: power up value for MMCIPOWER register |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 62 | * @signal_direction: input/out direction of bus signals can be indicated |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 63 | * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 64 | */ |
| 65 | struct variant_data { |
| 66 | unsigned int clkreg; |
Rabin Vincent | 4380c14 | 2010-07-21 12:55:18 +0100 | [diff] [blame] | 67 | unsigned int clkreg_enable; |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 68 | unsigned int datalength_bits; |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 69 | unsigned int fifosize; |
| 70 | unsigned int fifohalfsize; |
Linus Walleij | 3417780 | 2010-10-19 12:43:58 +0100 | [diff] [blame] | 71 | bool sdio; |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 72 | bool st_clkdiv; |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 73 | bool blksz_datactrl16; |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 74 | u32 pwrreg_powerup; |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 75 | bool signal_direction; |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 76 | bool pwrreg_clkgate; |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 77 | }; |
| 78 | |
| 79 | static struct variant_data variant_arm = { |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 80 | .fifosize = 16 * 4, |
| 81 | .fifohalfsize = 8 * 4, |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 82 | .datalength_bits = 16, |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 83 | .pwrreg_powerup = MCI_PWR_UP, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 84 | }; |
| 85 | |
Pawel Moll | 768fbc1 | 2011-03-11 17:18:07 +0000 | [diff] [blame] | 86 | static struct variant_data variant_arm_extended_fifo = { |
| 87 | .fifosize = 128 * 4, |
| 88 | .fifohalfsize = 64 * 4, |
| 89 | .datalength_bits = 16, |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 90 | .pwrreg_powerup = MCI_PWR_UP, |
Pawel Moll | 768fbc1 | 2011-03-11 17:18:07 +0000 | [diff] [blame] | 91 | }; |
| 92 | |
Pawel Moll | 3a37298 | 2013-01-24 14:12:45 +0100 | [diff] [blame^] | 93 | static struct variant_data variant_arm_extended_fifo_hwfc = { |
| 94 | .fifosize = 128 * 4, |
| 95 | .fifohalfsize = 64 * 4, |
| 96 | .clkreg_enable = MCI_ARM_HWFCEN, |
| 97 | .datalength_bits = 16, |
| 98 | .pwrreg_powerup = MCI_PWR_UP, |
| 99 | }; |
| 100 | |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 101 | static struct variant_data variant_u300 = { |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 102 | .fifosize = 16 * 4, |
| 103 | .fifohalfsize = 8 * 4, |
Linus Walleij | 49ac215 | 2011-03-04 14:54:16 +0100 | [diff] [blame] | 104 | .clkreg_enable = MCI_ST_U300_HWFCEN, |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 105 | .datalength_bits = 16, |
Linus Walleij | 3417780 | 2010-10-19 12:43:58 +0100 | [diff] [blame] | 106 | .sdio = true, |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 107 | .pwrreg_powerup = MCI_PWR_ON, |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 108 | .signal_direction = true, |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 109 | .pwrreg_clkgate = true, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 110 | }; |
| 111 | |
Linus Walleij | 34fd421 | 2012-04-10 17:43:59 +0100 | [diff] [blame] | 112 | static struct variant_data variant_nomadik = { |
| 113 | .fifosize = 16 * 4, |
| 114 | .fifohalfsize = 8 * 4, |
| 115 | .clkreg = MCI_CLK_ENABLE, |
| 116 | .datalength_bits = 24, |
| 117 | .sdio = true, |
| 118 | .st_clkdiv = true, |
| 119 | .pwrreg_powerup = MCI_PWR_ON, |
| 120 | .signal_direction = true, |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 121 | .pwrreg_clkgate = true, |
Linus Walleij | 34fd421 | 2012-04-10 17:43:59 +0100 | [diff] [blame] | 122 | }; |
| 123 | |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 124 | static struct variant_data variant_ux500 = { |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 125 | .fifosize = 30 * 4, |
| 126 | .fifohalfsize = 8 * 4, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 127 | .clkreg = MCI_CLK_ENABLE, |
Linus Walleij | 49ac215 | 2011-03-04 14:54:16 +0100 | [diff] [blame] | 128 | .clkreg_enable = MCI_ST_UX500_HWFCEN, |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 129 | .datalength_bits = 24, |
Linus Walleij | 3417780 | 2010-10-19 12:43:58 +0100 | [diff] [blame] | 130 | .sdio = true, |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 131 | .st_clkdiv = true, |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 132 | .pwrreg_powerup = MCI_PWR_ON, |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 133 | .signal_direction = true, |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 134 | .pwrreg_clkgate = true, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 135 | }; |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 136 | |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 137 | static struct variant_data variant_ux500v2 = { |
| 138 | .fifosize = 30 * 4, |
| 139 | .fifohalfsize = 8 * 4, |
| 140 | .clkreg = MCI_CLK_ENABLE, |
| 141 | .clkreg_enable = MCI_ST_UX500_HWFCEN, |
| 142 | .datalength_bits = 24, |
| 143 | .sdio = true, |
| 144 | .st_clkdiv = true, |
| 145 | .blksz_datactrl16 = true, |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 146 | .pwrreg_powerup = MCI_PWR_ON, |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 147 | .signal_direction = true, |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 148 | .pwrreg_clkgate = true, |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 149 | }; |
| 150 | |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 151 | /* |
| 152 | * This must be called with host->lock held |
| 153 | */ |
Ulf Hansson | 7437cfa | 2012-01-18 09:17:27 +0100 | [diff] [blame] | 154 | static void mmci_write_clkreg(struct mmci_host *host, u32 clk) |
| 155 | { |
| 156 | if (host->clk_reg != clk) { |
| 157 | host->clk_reg = clk; |
| 158 | writel(clk, host->base + MMCICLOCK); |
| 159 | } |
| 160 | } |
| 161 | |
| 162 | /* |
| 163 | * This must be called with host->lock held |
| 164 | */ |
| 165 | static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) |
| 166 | { |
| 167 | if (host->pwr_reg != pwr) { |
| 168 | host->pwr_reg = pwr; |
| 169 | writel(pwr, host->base + MMCIPOWER); |
| 170 | } |
| 171 | } |
| 172 | |
| 173 | /* |
| 174 | * This must be called with host->lock held |
| 175 | */ |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 176 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) |
| 177 | { |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 178 | struct variant_data *variant = host->variant; |
| 179 | u32 clk = variant->clkreg; |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 180 | |
| 181 | if (desired) { |
| 182 | if (desired >= host->mclk) { |
Linus Walleij | 991a86e | 2010-12-10 09:35:53 +0100 | [diff] [blame] | 183 | clk = MCI_CLK_BYPASS; |
Linus Walleij | 399bc48 | 2011-04-01 07:59:17 +0100 | [diff] [blame] | 184 | if (variant->st_clkdiv) |
| 185 | clk |= MCI_ST_UX500_NEG_EDGE; |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 186 | host->cclk = host->mclk; |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 187 | } else if (variant->st_clkdiv) { |
| 188 | /* |
| 189 | * DB8500 TRM says f = mclk / (clkdiv + 2) |
| 190 | * => clkdiv = (mclk / f) - 2 |
| 191 | * Round the divider up so we don't exceed the max |
| 192 | * frequency |
| 193 | */ |
| 194 | clk = DIV_ROUND_UP(host->mclk, desired) - 2; |
| 195 | if (clk >= 256) |
| 196 | clk = 255; |
| 197 | host->cclk = host->mclk / (clk + 2); |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 198 | } else { |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 199 | /* |
| 200 | * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) |
| 201 | * => clkdiv = mclk / (2 * f) - 1 |
| 202 | */ |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 203 | clk = host->mclk / (2 * desired) - 1; |
| 204 | if (clk >= 256) |
| 205 | clk = 255; |
| 206 | host->cclk = host->mclk / (2 * (clk + 1)); |
| 207 | } |
Rabin Vincent | 4380c14 | 2010-07-21 12:55:18 +0100 | [diff] [blame] | 208 | |
| 209 | clk |= variant->clkreg_enable; |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 210 | clk |= MCI_CLK_ENABLE; |
| 211 | /* This hasn't proven to be worthwhile */ |
| 212 | /* clk |= MCI_CLK_PWRSAVE; */ |
| 213 | } |
| 214 | |
Linus Walleij | 9e6c82c | 2009-09-14 12:57:11 +0100 | [diff] [blame] | 215 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
Linus Walleij | 771dc15 | 2010-04-08 07:38:52 +0100 | [diff] [blame] | 216 | clk |= MCI_4BIT_BUS; |
| 217 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) |
| 218 | clk |= MCI_ST_8BIT_BUS; |
Linus Walleij | 9e6c82c | 2009-09-14 12:57:11 +0100 | [diff] [blame] | 219 | |
Ulf Hansson | 6dbb6ee | 2013-01-07 15:30:44 +0100 | [diff] [blame] | 220 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) |
| 221 | clk |= MCI_ST_UX500_NEG_EDGE; |
| 222 | |
Ulf Hansson | 7437cfa | 2012-01-18 09:17:27 +0100 | [diff] [blame] | 223 | mmci_write_clkreg(host, clk); |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 224 | } |
| 225 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 226 | static void |
| 227 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) |
| 228 | { |
| 229 | writel(0, host->base + MMCICOMMAND); |
| 230 | |
Russell King | e47c222 | 2007-01-08 16:42:51 +0000 | [diff] [blame] | 231 | BUG_ON(host->data); |
| 232 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 233 | host->mrq = NULL; |
| 234 | host->cmd = NULL; |
| 235 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 236 | mmc_request_done(host->mmc, mrq); |
Ulf Hansson | 2cd976c | 2011-12-13 17:01:11 +0100 | [diff] [blame] | 237 | |
| 238 | pm_runtime_mark_last_busy(mmc_dev(host->mmc)); |
| 239 | pm_runtime_put_autosuspend(mmc_dev(host->mmc)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 240 | } |
| 241 | |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 242 | static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) |
| 243 | { |
| 244 | void __iomem *base = host->base; |
| 245 | |
| 246 | if (host->singleirq) { |
| 247 | unsigned int mask0 = readl(base + MMCIMASK0); |
| 248 | |
| 249 | mask0 &= ~MCI_IRQ1MASK; |
| 250 | mask0 |= mask; |
| 251 | |
| 252 | writel(mask0, base + MMCIMASK0); |
| 253 | } |
| 254 | |
| 255 | writel(mask, base + MMCIMASK1); |
| 256 | } |
| 257 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 258 | static void mmci_stop_data(struct mmci_host *host) |
| 259 | { |
| 260 | writel(0, host->base + MMCIDATACTRL); |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 261 | mmci_set_mask1(host, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 262 | host->data = NULL; |
| 263 | } |
| 264 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 265 | static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
| 266 | { |
| 267 | unsigned int flags = SG_MITER_ATOMIC; |
| 268 | |
| 269 | if (data->flags & MMC_DATA_READ) |
| 270 | flags |= SG_MITER_TO_SG; |
| 271 | else |
| 272 | flags |= SG_MITER_FROM_SG; |
| 273 | |
| 274 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); |
| 275 | } |
| 276 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 277 | /* |
| 278 | * All the DMA operation mode stuff goes inside this ifdef. |
| 279 | * This assumes that you have a generic DMA device interface, |
| 280 | * no custom DMA interfaces are supported. |
| 281 | */ |
| 282 | #ifdef CONFIG_DMA_ENGINE |
Bill Pemberton | c3be1ef | 2012-11-19 13:23:06 -0500 | [diff] [blame] | 283 | static void mmci_dma_setup(struct mmci_host *host) |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 284 | { |
| 285 | struct mmci_platform_data *plat = host->plat; |
| 286 | const char *rxname, *txname; |
| 287 | dma_cap_mask_t mask; |
| 288 | |
| 289 | if (!plat || !plat->dma_filter) { |
| 290 | dev_info(mmc_dev(host->mmc), "no DMA platform data\n"); |
| 291 | return; |
| 292 | } |
| 293 | |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 294 | /* initialize pre request cookie */ |
| 295 | host->next_data.cookie = 1; |
| 296 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 297 | /* Try to acquire a generic DMA engine slave channel */ |
| 298 | dma_cap_zero(mask); |
| 299 | dma_cap_set(DMA_SLAVE, mask); |
| 300 | |
| 301 | /* |
| 302 | * If only an RX channel is specified, the driver will |
| 303 | * attempt to use it bidirectionally, however if it is |
| 304 | * is specified but cannot be located, DMA will be disabled. |
| 305 | */ |
| 306 | if (plat->dma_rx_param) { |
| 307 | host->dma_rx_channel = dma_request_channel(mask, |
| 308 | plat->dma_filter, |
| 309 | plat->dma_rx_param); |
| 310 | /* E.g if no DMA hardware is present */ |
| 311 | if (!host->dma_rx_channel) |
| 312 | dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); |
| 313 | } |
| 314 | |
| 315 | if (plat->dma_tx_param) { |
| 316 | host->dma_tx_channel = dma_request_channel(mask, |
| 317 | plat->dma_filter, |
| 318 | plat->dma_tx_param); |
| 319 | if (!host->dma_tx_channel) |
| 320 | dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); |
| 321 | } else { |
| 322 | host->dma_tx_channel = host->dma_rx_channel; |
| 323 | } |
| 324 | |
| 325 | if (host->dma_rx_channel) |
| 326 | rxname = dma_chan_name(host->dma_rx_channel); |
| 327 | else |
| 328 | rxname = "none"; |
| 329 | |
| 330 | if (host->dma_tx_channel) |
| 331 | txname = dma_chan_name(host->dma_tx_channel); |
| 332 | else |
| 333 | txname = "none"; |
| 334 | |
| 335 | dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", |
| 336 | rxname, txname); |
| 337 | |
| 338 | /* |
| 339 | * Limit the maximum segment size in any SG entry according to |
| 340 | * the parameters of the DMA engine device. |
| 341 | */ |
| 342 | if (host->dma_tx_channel) { |
| 343 | struct device *dev = host->dma_tx_channel->device->dev; |
| 344 | unsigned int max_seg_size = dma_get_max_seg_size(dev); |
| 345 | |
| 346 | if (max_seg_size < host->mmc->max_seg_size) |
| 347 | host->mmc->max_seg_size = max_seg_size; |
| 348 | } |
| 349 | if (host->dma_rx_channel) { |
| 350 | struct device *dev = host->dma_rx_channel->device->dev; |
| 351 | unsigned int max_seg_size = dma_get_max_seg_size(dev); |
| 352 | |
| 353 | if (max_seg_size < host->mmc->max_seg_size) |
| 354 | host->mmc->max_seg_size = max_seg_size; |
| 355 | } |
| 356 | } |
| 357 | |
| 358 | /* |
Bill Pemberton | 6e0ee71 | 2012-11-19 13:26:03 -0500 | [diff] [blame] | 359 | * This is used in or so inline it |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 360 | * so it can be discarded. |
| 361 | */ |
| 362 | static inline void mmci_dma_release(struct mmci_host *host) |
| 363 | { |
| 364 | struct mmci_platform_data *plat = host->plat; |
| 365 | |
| 366 | if (host->dma_rx_channel) |
| 367 | dma_release_channel(host->dma_rx_channel); |
| 368 | if (host->dma_tx_channel && plat->dma_tx_param) |
| 369 | dma_release_channel(host->dma_tx_channel); |
| 370 | host->dma_rx_channel = host->dma_tx_channel = NULL; |
| 371 | } |
| 372 | |
| 373 | static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) |
| 374 | { |
| 375 | struct dma_chan *chan = host->dma_current; |
| 376 | enum dma_data_direction dir; |
| 377 | u32 status; |
| 378 | int i; |
| 379 | |
| 380 | /* Wait up to 1ms for the DMA to complete */ |
| 381 | for (i = 0; ; i++) { |
| 382 | status = readl(host->base + MMCISTATUS); |
| 383 | if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) |
| 384 | break; |
| 385 | udelay(10); |
| 386 | } |
| 387 | |
| 388 | /* |
| 389 | * Check to see whether we still have some data left in the FIFO - |
| 390 | * this catches DMA controllers which are unable to monitor the |
| 391 | * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- |
| 392 | * contiguous buffers. On TX, we'll get a FIFO underrun error. |
| 393 | */ |
| 394 | if (status & MCI_RXDATAAVLBLMASK) { |
| 395 | dmaengine_terminate_all(chan); |
| 396 | if (!data->error) |
| 397 | data->error = -EIO; |
| 398 | } |
| 399 | |
| 400 | if (data->flags & MMC_DATA_WRITE) { |
| 401 | dir = DMA_TO_DEVICE; |
| 402 | } else { |
| 403 | dir = DMA_FROM_DEVICE; |
| 404 | } |
| 405 | |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 406 | if (!data->host_cookie) |
| 407 | dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 408 | |
| 409 | /* |
| 410 | * Use of DMA with scatter-gather is impossible. |
| 411 | * Give up with DMA and switch back to PIO mode. |
| 412 | */ |
| 413 | if (status & MCI_RXDATAAVLBLMASK) { |
| 414 | dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); |
| 415 | mmci_dma_release(host); |
| 416 | } |
| 417 | } |
| 418 | |
| 419 | static void mmci_dma_data_error(struct mmci_host *host) |
| 420 | { |
| 421 | dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); |
| 422 | dmaengine_terminate_all(host->dma_current); |
| 423 | } |
| 424 | |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 425 | static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, |
| 426 | struct mmci_host_next *next) |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 427 | { |
| 428 | struct variant_data *variant = host->variant; |
| 429 | struct dma_slave_config conf = { |
| 430 | .src_addr = host->phybase + MMCIFIFO, |
| 431 | .dst_addr = host->phybase + MMCIFIFO, |
| 432 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, |
| 433 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, |
| 434 | .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ |
| 435 | .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ |
Viresh Kumar | 258aea7 | 2012-02-01 16:12:19 +0530 | [diff] [blame] | 436 | .device_fc = false, |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 437 | }; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 438 | struct dma_chan *chan; |
| 439 | struct dma_device *device; |
| 440 | struct dma_async_tx_descriptor *desc; |
Vinod Koul | 05f5799 | 2011-10-14 10:45:11 +0530 | [diff] [blame] | 441 | enum dma_data_direction buffer_dirn; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 442 | int nr_sg; |
| 443 | |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 444 | /* Check if next job is already prepared */ |
| 445 | if (data->host_cookie && !next && |
| 446 | host->dma_current && host->dma_desc_current) |
| 447 | return 0; |
| 448 | |
| 449 | if (!next) { |
| 450 | host->dma_current = NULL; |
| 451 | host->dma_desc_current = NULL; |
| 452 | } |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 453 | |
| 454 | if (data->flags & MMC_DATA_READ) { |
Vinod Koul | 05f5799 | 2011-10-14 10:45:11 +0530 | [diff] [blame] | 455 | conf.direction = DMA_DEV_TO_MEM; |
| 456 | buffer_dirn = DMA_FROM_DEVICE; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 457 | chan = host->dma_rx_channel; |
| 458 | } else { |
Vinod Koul | 05f5799 | 2011-10-14 10:45:11 +0530 | [diff] [blame] | 459 | conf.direction = DMA_MEM_TO_DEV; |
| 460 | buffer_dirn = DMA_TO_DEVICE; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 461 | chan = host->dma_tx_channel; |
| 462 | } |
| 463 | |
| 464 | /* If there's no DMA channel, fall back to PIO */ |
| 465 | if (!chan) |
| 466 | return -EINVAL; |
| 467 | |
| 468 | /* If less than or equal to the fifo size, don't bother with DMA */ |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 469 | if (data->blksz * data->blocks <= variant->fifosize) |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 470 | return -EINVAL; |
| 471 | |
| 472 | device = chan->device; |
Vinod Koul | 05f5799 | 2011-10-14 10:45:11 +0530 | [diff] [blame] | 473 | nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 474 | if (nr_sg == 0) |
| 475 | return -EINVAL; |
| 476 | |
| 477 | dmaengine_slave_config(chan, &conf); |
Alexandre Bounine | 1605282 | 2012-03-08 16:11:18 -0500 | [diff] [blame] | 478 | desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 479 | conf.direction, DMA_CTRL_ACK); |
| 480 | if (!desc) |
| 481 | goto unmap_exit; |
| 482 | |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 483 | if (next) { |
| 484 | next->dma_chan = chan; |
| 485 | next->dma_desc = desc; |
| 486 | } else { |
| 487 | host->dma_current = chan; |
| 488 | host->dma_desc_current = desc; |
| 489 | } |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 490 | |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 491 | return 0; |
| 492 | |
| 493 | unmap_exit: |
| 494 | if (!next) |
| 495 | dmaengine_terminate_all(chan); |
Vinod Koul | 05f5799 | 2011-10-14 10:45:11 +0530 | [diff] [blame] | 496 | dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 497 | return -ENOMEM; |
| 498 | } |
| 499 | |
| 500 | static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) |
| 501 | { |
| 502 | int ret; |
| 503 | struct mmc_data *data = host->data; |
| 504 | |
| 505 | ret = mmci_dma_prep_data(host, host->data, NULL); |
| 506 | if (ret) |
| 507 | return ret; |
| 508 | |
| 509 | /* Okay, go for it. */ |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 510 | dev_vdbg(mmc_dev(host->mmc), |
| 511 | "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", |
| 512 | data->sg_len, data->blksz, data->blocks, data->flags); |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 513 | dmaengine_submit(host->dma_desc_current); |
| 514 | dma_async_issue_pending(host->dma_current); |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 515 | |
| 516 | datactrl |= MCI_DPSM_DMAENABLE; |
| 517 | |
| 518 | /* Trigger the DMA transfer */ |
| 519 | writel(datactrl, host->base + MMCIDATACTRL); |
| 520 | |
| 521 | /* |
| 522 | * Let the MMCI say when the data is ended and it's time |
| 523 | * to fire next DMA request. When that happens, MMCI will |
| 524 | * call mmci_data_end() |
| 525 | */ |
| 526 | writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, |
| 527 | host->base + MMCIMASK0); |
| 528 | return 0; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 529 | } |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 530 | |
| 531 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
| 532 | { |
| 533 | struct mmci_host_next *next = &host->next_data; |
| 534 | |
| 535 | if (data->host_cookie && data->host_cookie != next->cookie) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 536 | pr_warning("[%s] invalid cookie: data->host_cookie %d" |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 537 | " host->next_data.cookie %d\n", |
| 538 | __func__, data->host_cookie, host->next_data.cookie); |
| 539 | data->host_cookie = 0; |
| 540 | } |
| 541 | |
| 542 | if (!data->host_cookie) |
| 543 | return; |
| 544 | |
| 545 | host->dma_desc_current = next->dma_desc; |
| 546 | host->dma_current = next->dma_chan; |
| 547 | |
| 548 | next->dma_desc = NULL; |
| 549 | next->dma_chan = NULL; |
| 550 | } |
| 551 | |
| 552 | static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, |
| 553 | bool is_first_req) |
| 554 | { |
| 555 | struct mmci_host *host = mmc_priv(mmc); |
| 556 | struct mmc_data *data = mrq->data; |
| 557 | struct mmci_host_next *nd = &host->next_data; |
| 558 | |
| 559 | if (!data) |
| 560 | return; |
| 561 | |
| 562 | if (data->host_cookie) { |
| 563 | data->host_cookie = 0; |
| 564 | return; |
| 565 | } |
| 566 | |
| 567 | /* if config for dma */ |
| 568 | if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) || |
| 569 | ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) { |
| 570 | if (mmci_dma_prep_data(host, data, nd)) |
| 571 | data->host_cookie = 0; |
| 572 | else |
| 573 | data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; |
| 574 | } |
| 575 | } |
| 576 | |
| 577 | static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, |
| 578 | int err) |
| 579 | { |
| 580 | struct mmci_host *host = mmc_priv(mmc); |
| 581 | struct mmc_data *data = mrq->data; |
| 582 | struct dma_chan *chan; |
| 583 | enum dma_data_direction dir; |
| 584 | |
| 585 | if (!data) |
| 586 | return; |
| 587 | |
| 588 | if (data->flags & MMC_DATA_READ) { |
| 589 | dir = DMA_FROM_DEVICE; |
| 590 | chan = host->dma_rx_channel; |
| 591 | } else { |
| 592 | dir = DMA_TO_DEVICE; |
| 593 | chan = host->dma_tx_channel; |
| 594 | } |
| 595 | |
| 596 | |
| 597 | /* if config for dma */ |
| 598 | if (chan) { |
| 599 | if (err) |
| 600 | dmaengine_terminate_all(chan); |
Per Forlin | 8e3336b | 2011-08-29 15:35:59 +0200 | [diff] [blame] | 601 | if (data->host_cookie) |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 602 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, |
| 603 | data->sg_len, dir); |
| 604 | mrq->data->host_cookie = 0; |
| 605 | } |
| 606 | } |
| 607 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 608 | #else |
| 609 | /* Blank functions if the DMA engine is not available */ |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 610 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
| 611 | { |
| 612 | } |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 613 | static inline void mmci_dma_setup(struct mmci_host *host) |
| 614 | { |
| 615 | } |
| 616 | |
| 617 | static inline void mmci_dma_release(struct mmci_host *host) |
| 618 | { |
| 619 | } |
| 620 | |
| 621 | static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) |
| 622 | { |
| 623 | } |
| 624 | |
| 625 | static inline void mmci_dma_data_error(struct mmci_host *host) |
| 626 | { |
| 627 | } |
| 628 | |
| 629 | static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) |
| 630 | { |
| 631 | return -ENOSYS; |
| 632 | } |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 633 | |
| 634 | #define mmci_pre_request NULL |
| 635 | #define mmci_post_request NULL |
| 636 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 637 | #endif |
| 638 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 639 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) |
| 640 | { |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 641 | struct variant_data *variant = host->variant; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 642 | unsigned int datactrl, timeout, irqmask; |
Russell King | 7b09cda | 2005-07-01 12:02:59 +0100 | [diff] [blame] | 643 | unsigned long long clks; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 644 | void __iomem *base; |
Russell King | 3bc87f2 | 2006-08-27 13:51:28 +0100 | [diff] [blame] | 645 | int blksz_bits; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 646 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 647 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
| 648 | data->blksz, data->blocks, data->flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 649 | |
| 650 | host->data = data; |
Rabin Vincent | 528320d | 2010-07-21 12:49:49 +0100 | [diff] [blame] | 651 | host->size = data->blksz * data->blocks; |
Russell King | 51d4375 | 2011-01-27 10:56:52 +0000 | [diff] [blame] | 652 | data->bytes_xfered = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 653 | |
Russell King | 7b09cda | 2005-07-01 12:02:59 +0100 | [diff] [blame] | 654 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
| 655 | do_div(clks, 1000000000UL); |
| 656 | |
| 657 | timeout = data->timeout_clks + (unsigned int)clks; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 658 | |
| 659 | base = host->base; |
| 660 | writel(timeout, base + MMCIDATATIMER); |
| 661 | writel(host->size, base + MMCIDATALENGTH); |
| 662 | |
Russell King | 3bc87f2 | 2006-08-27 13:51:28 +0100 | [diff] [blame] | 663 | blksz_bits = ffs(data->blksz) - 1; |
| 664 | BUG_ON(1 << blksz_bits != data->blksz); |
| 665 | |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 666 | if (variant->blksz_datactrl16) |
| 667 | datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); |
| 668 | else |
| 669 | datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 670 | |
| 671 | if (data->flags & MMC_DATA_READ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 672 | datactrl |= MCI_DPSM_DIRECTION; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 673 | |
Ulf Hansson | 7258db7 | 2011-12-13 17:05:28 +0100 | [diff] [blame] | 674 | /* The ST Micro variants has a special bit to enable SDIO */ |
| 675 | if (variant->sdio && host->mmc->card) |
Ulf Hansson | 06c1a12 | 2012-10-12 14:01:50 +0100 | [diff] [blame] | 676 | if (mmc_card_sdio(host->mmc->card)) { |
| 677 | /* |
| 678 | * The ST Micro variants has a special bit |
| 679 | * to enable SDIO. |
| 680 | */ |
| 681 | u32 clk; |
| 682 | |
Ulf Hansson | 7258db7 | 2011-12-13 17:05:28 +0100 | [diff] [blame] | 683 | datactrl |= MCI_ST_DPSM_SDIOEN; |
| 684 | |
Ulf Hansson | 06c1a12 | 2012-10-12 14:01:50 +0100 | [diff] [blame] | 685 | /* |
Ulf Hansson | 70ac093 | 2012-10-12 14:07:36 +0100 | [diff] [blame] | 686 | * The ST Micro variant for SDIO small write transfers |
| 687 | * needs to have clock H/W flow control disabled, |
| 688 | * otherwise the transfer will not start. The threshold |
| 689 | * depends on the rate of MCLK. |
Ulf Hansson | 06c1a12 | 2012-10-12 14:01:50 +0100 | [diff] [blame] | 690 | */ |
Ulf Hansson | 70ac093 | 2012-10-12 14:07:36 +0100 | [diff] [blame] | 691 | if (data->flags & MMC_DATA_WRITE && |
| 692 | (host->size < 8 || |
| 693 | (host->size <= 8 && host->mclk > 50000000))) |
Ulf Hansson | 06c1a12 | 2012-10-12 14:01:50 +0100 | [diff] [blame] | 694 | clk = host->clk_reg & ~variant->clkreg_enable; |
| 695 | else |
| 696 | clk = host->clk_reg | variant->clkreg_enable; |
| 697 | |
| 698 | mmci_write_clkreg(host, clk); |
| 699 | } |
| 700 | |
Ulf Hansson | 6dbb6ee | 2013-01-07 15:30:44 +0100 | [diff] [blame] | 701 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) |
| 702 | datactrl |= MCI_ST_DPSM_DDRMODE; |
| 703 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 704 | /* |
| 705 | * Attempt to use DMA operation mode, if this |
| 706 | * should fail, fall back to PIO mode |
| 707 | */ |
| 708 | if (!mmci_dma_start_data(host, datactrl)) |
| 709 | return; |
| 710 | |
| 711 | /* IRQ mode, map the SG list for CPU reading/writing */ |
| 712 | mmci_init_sg(host, data); |
| 713 | |
| 714 | if (data->flags & MMC_DATA_READ) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 715 | irqmask = MCI_RXFIFOHALFFULLMASK; |
Russell King | 0425a14 | 2006-02-16 16:48:31 +0000 | [diff] [blame] | 716 | |
| 717 | /* |
Russell King | c4d877c | 2011-01-27 09:50:13 +0000 | [diff] [blame] | 718 | * If we have less than the fifo 'half-full' threshold to |
| 719 | * transfer, trigger a PIO interrupt as soon as any data |
| 720 | * is available. |
Russell King | 0425a14 | 2006-02-16 16:48:31 +0000 | [diff] [blame] | 721 | */ |
Russell King | c4d877c | 2011-01-27 09:50:13 +0000 | [diff] [blame] | 722 | if (host->size < variant->fifohalfsize) |
Russell King | 0425a14 | 2006-02-16 16:48:31 +0000 | [diff] [blame] | 723 | irqmask |= MCI_RXDATAAVLBLMASK; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 724 | } else { |
| 725 | /* |
| 726 | * We don't actually need to include "FIFO empty" here |
| 727 | * since its implicit in "FIFO half empty". |
| 728 | */ |
| 729 | irqmask = MCI_TXFIFOHALFEMPTYMASK; |
| 730 | } |
| 731 | |
| 732 | writel(datactrl, base + MMCIDATACTRL); |
| 733 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 734 | mmci_set_mask1(host, irqmask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 735 | } |
| 736 | |
| 737 | static void |
| 738 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) |
| 739 | { |
| 740 | void __iomem *base = host->base; |
| 741 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 742 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 743 | cmd->opcode, cmd->arg, cmd->flags); |
| 744 | |
| 745 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { |
| 746 | writel(0, base + MMCICOMMAND); |
| 747 | udelay(1); |
| 748 | } |
| 749 | |
| 750 | c |= cmd->opcode | MCI_CPSM_ENABLE; |
Russell King | e922517 | 2006-02-02 12:23:12 +0000 | [diff] [blame] | 751 | if (cmd->flags & MMC_RSP_PRESENT) { |
| 752 | if (cmd->flags & MMC_RSP_136) |
| 753 | c |= MCI_CPSM_LONGRSP; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 754 | c |= MCI_CPSM_RESPONSE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 755 | } |
| 756 | if (/*interrupt*/0) |
| 757 | c |= MCI_CPSM_INTERRUPT; |
| 758 | |
| 759 | host->cmd = cmd; |
| 760 | |
| 761 | writel(cmd->arg, base + MMCIARGUMENT); |
| 762 | writel(c, base + MMCICOMMAND); |
| 763 | } |
| 764 | |
| 765 | static void |
| 766 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, |
| 767 | unsigned int status) |
| 768 | { |
Linus Walleij | f20f8f2 | 2010-10-19 13:41:24 +0100 | [diff] [blame] | 769 | /* First check for errors */ |
Ulf Hansson | b63038d | 2011-12-13 16:51:04 +0100 | [diff] [blame] | 770 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| |
| 771 | MCI_TXUNDERRUN|MCI_RXOVERRUN)) { |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 772 | u32 remain, success; |
Linus Walleij | f20f8f2 | 2010-10-19 13:41:24 +0100 | [diff] [blame] | 773 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 774 | /* Terminate the DMA transfer */ |
| 775 | if (dma_inprogress(host)) |
| 776 | mmci_dma_data_error(host); |
| 777 | |
Russell King | c8afc9d | 2011-02-04 09:19:46 +0000 | [diff] [blame] | 778 | /* |
| 779 | * Calculate how far we are into the transfer. Note that |
| 780 | * the data counter gives the number of bytes transferred |
| 781 | * on the MMC bus, not on the host side. On reads, this |
| 782 | * can be as much as a FIFO-worth of data ahead. This |
| 783 | * matters for FIFO overruns only. |
| 784 | */ |
Linus Walleij | f5a106d | 2011-01-27 17:44:34 +0100 | [diff] [blame] | 785 | remain = readl(host->base + MMCIDATACNT); |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 786 | success = data->blksz * data->blocks - remain; |
| 787 | |
Russell King | c8afc9d | 2011-02-04 09:19:46 +0000 | [diff] [blame] | 788 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", |
| 789 | status, success); |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 790 | if (status & MCI_DATACRCFAIL) { |
| 791 | /* Last block was not successful */ |
Russell King | c8afc9d | 2011-02-04 09:19:46 +0000 | [diff] [blame] | 792 | success -= 1; |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 793 | data->error = -EILSEQ; |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 794 | } else if (status & MCI_DATATIMEOUT) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 795 | data->error = -ETIMEDOUT; |
Linus Walleij | 757df74 | 2011-06-30 15:10:21 +0100 | [diff] [blame] | 796 | } else if (status & MCI_STARTBITERR) { |
| 797 | data->error = -ECOMM; |
Russell King | c8afc9d | 2011-02-04 09:19:46 +0000 | [diff] [blame] | 798 | } else if (status & MCI_TXUNDERRUN) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 799 | data->error = -EIO; |
Russell King | c8afc9d | 2011-02-04 09:19:46 +0000 | [diff] [blame] | 800 | } else if (status & MCI_RXOVERRUN) { |
| 801 | if (success > host->variant->fifosize) |
| 802 | success -= host->variant->fifosize; |
| 803 | else |
| 804 | success = 0; |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 805 | data->error = -EIO; |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 806 | } |
Russell King | 51d4375 | 2011-01-27 10:56:52 +0000 | [diff] [blame] | 807 | data->bytes_xfered = round_down(success, data->blksz); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 808 | } |
Linus Walleij | f20f8f2 | 2010-10-19 13:41:24 +0100 | [diff] [blame] | 809 | |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 810 | if (status & MCI_DATABLOCKEND) |
| 811 | dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); |
Linus Walleij | f20f8f2 | 2010-10-19 13:41:24 +0100 | [diff] [blame] | 812 | |
Russell King | ccff9b5 | 2011-01-30 21:03:50 +0000 | [diff] [blame] | 813 | if (status & MCI_DATAEND || data->error) { |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 814 | if (dma_inprogress(host)) |
| 815 | mmci_dma_unmap(host, data); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 816 | mmci_stop_data(host); |
| 817 | |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 818 | if (!data->error) |
| 819 | /* The error clause is handled above, success! */ |
Russell King | 51d4375 | 2011-01-27 10:56:52 +0000 | [diff] [blame] | 820 | data->bytes_xfered = data->blksz * data->blocks; |
Linus Walleij | f20f8f2 | 2010-10-19 13:41:24 +0100 | [diff] [blame] | 821 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 822 | if (!data->stop) { |
| 823 | mmci_request_end(host, data->mrq); |
| 824 | } else { |
| 825 | mmci_start_command(host, data->stop, 0); |
| 826 | } |
| 827 | } |
| 828 | } |
| 829 | |
| 830 | static void |
| 831 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, |
| 832 | unsigned int status) |
| 833 | { |
| 834 | void __iomem *base = host->base; |
| 835 | |
| 836 | host->cmd = NULL; |
| 837 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 838 | if (status & MCI_CMDTIMEOUT) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 839 | cmd->error = -ETIMEDOUT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 840 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 841 | cmd->error = -EILSEQ; |
Russell King - ARM Linux | 9047b43 | 2011-01-11 16:35:56 +0000 | [diff] [blame] | 842 | } else { |
| 843 | cmd->resp[0] = readl(base + MMCIRESPONSE0); |
| 844 | cmd->resp[1] = readl(base + MMCIRESPONSE1); |
| 845 | cmd->resp[2] = readl(base + MMCIRESPONSE2); |
| 846 | cmd->resp[3] = readl(base + MMCIRESPONSE3); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 847 | } |
| 848 | |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 849 | if (!cmd->data || cmd->error) { |
Ulf Hansson | 3b6e3c7 | 2011-12-13 16:58:43 +0100 | [diff] [blame] | 850 | if (host->data) { |
| 851 | /* Terminate the DMA transfer */ |
| 852 | if (dma_inprogress(host)) |
| 853 | mmci_dma_data_error(host); |
Russell King | e47c222 | 2007-01-08 16:42:51 +0000 | [diff] [blame] | 854 | mmci_stop_data(host); |
Ulf Hansson | 3b6e3c7 | 2011-12-13 16:58:43 +0100 | [diff] [blame] | 855 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 856 | mmci_request_end(host, cmd->mrq); |
| 857 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { |
| 858 | mmci_start_data(host, cmd->data); |
| 859 | } |
| 860 | } |
| 861 | |
| 862 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) |
| 863 | { |
| 864 | void __iomem *base = host->base; |
| 865 | char *ptr = buffer; |
| 866 | u32 status; |
Linus Walleij | 26eed9a | 2008-04-26 23:39:44 +0100 | [diff] [blame] | 867 | int host_remain = host->size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 868 | |
| 869 | do { |
Linus Walleij | 26eed9a | 2008-04-26 23:39:44 +0100 | [diff] [blame] | 870 | int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 871 | |
| 872 | if (count > remain) |
| 873 | count = remain; |
| 874 | |
| 875 | if (count <= 0) |
| 876 | break; |
| 877 | |
Ulf Hansson | 393e5e2 | 2011-12-13 17:08:04 +0100 | [diff] [blame] | 878 | /* |
| 879 | * SDIO especially may want to send something that is |
| 880 | * not divisible by 4 (as opposed to card sectors |
| 881 | * etc). Therefore make sure to always read the last bytes |
| 882 | * while only doing full 32-bit reads towards the FIFO. |
| 883 | */ |
| 884 | if (unlikely(count & 0x3)) { |
| 885 | if (count < 4) { |
| 886 | unsigned char buf[4]; |
Davide Ciminaghi | 4b85da0 | 2012-12-10 14:47:21 +0100 | [diff] [blame] | 887 | ioread32_rep(base + MMCIFIFO, buf, 1); |
Ulf Hansson | 393e5e2 | 2011-12-13 17:08:04 +0100 | [diff] [blame] | 888 | memcpy(ptr, buf, count); |
| 889 | } else { |
Davide Ciminaghi | 4b85da0 | 2012-12-10 14:47:21 +0100 | [diff] [blame] | 890 | ioread32_rep(base + MMCIFIFO, ptr, count >> 2); |
Ulf Hansson | 393e5e2 | 2011-12-13 17:08:04 +0100 | [diff] [blame] | 891 | count &= ~0x3; |
| 892 | } |
| 893 | } else { |
Davide Ciminaghi | 4b85da0 | 2012-12-10 14:47:21 +0100 | [diff] [blame] | 894 | ioread32_rep(base + MMCIFIFO, ptr, count >> 2); |
Ulf Hansson | 393e5e2 | 2011-12-13 17:08:04 +0100 | [diff] [blame] | 895 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 896 | |
| 897 | ptr += count; |
| 898 | remain -= count; |
Linus Walleij | 26eed9a | 2008-04-26 23:39:44 +0100 | [diff] [blame] | 899 | host_remain -= count; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 900 | |
| 901 | if (remain == 0) |
| 902 | break; |
| 903 | |
| 904 | status = readl(base + MMCISTATUS); |
| 905 | } while (status & MCI_RXDATAAVLBL); |
| 906 | |
| 907 | return ptr - buffer; |
| 908 | } |
| 909 | |
| 910 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) |
| 911 | { |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 912 | struct variant_data *variant = host->variant; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 913 | void __iomem *base = host->base; |
| 914 | char *ptr = buffer; |
| 915 | |
| 916 | do { |
| 917 | unsigned int count, maxcnt; |
| 918 | |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 919 | maxcnt = status & MCI_TXFIFOEMPTY ? |
| 920 | variant->fifosize : variant->fifohalfsize; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 921 | count = min(remain, maxcnt); |
| 922 | |
Linus Walleij | 3417780 | 2010-10-19 12:43:58 +0100 | [diff] [blame] | 923 | /* |
Linus Walleij | 3417780 | 2010-10-19 12:43:58 +0100 | [diff] [blame] | 924 | * SDIO especially may want to send something that is |
| 925 | * not divisible by 4 (as opposed to card sectors |
| 926 | * etc), and the FIFO only accept full 32-bit writes. |
| 927 | * So compensate by adding +3 on the count, a single |
| 928 | * byte become a 32bit write, 7 bytes will be two |
| 929 | * 32bit writes etc. |
| 930 | */ |
Davide Ciminaghi | 4b85da0 | 2012-12-10 14:47:21 +0100 | [diff] [blame] | 931 | iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 932 | |
| 933 | ptr += count; |
| 934 | remain -= count; |
| 935 | |
| 936 | if (remain == 0) |
| 937 | break; |
| 938 | |
| 939 | status = readl(base + MMCISTATUS); |
| 940 | } while (status & MCI_TXFIFOHALFEMPTY); |
| 941 | |
| 942 | return ptr - buffer; |
| 943 | } |
| 944 | |
| 945 | /* |
| 946 | * PIO data transfer IRQ handler. |
| 947 | */ |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 948 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 949 | { |
| 950 | struct mmci_host *host = dev_id; |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 951 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 952 | struct variant_data *variant = host->variant; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 953 | void __iomem *base = host->base; |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 954 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 955 | u32 status; |
| 956 | |
| 957 | status = readl(base + MMCISTATUS); |
| 958 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 959 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 960 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 961 | local_irq_save(flags); |
| 962 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 963 | do { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 964 | unsigned int remain, len; |
| 965 | char *buffer; |
| 966 | |
| 967 | /* |
| 968 | * For write, we only need to test the half-empty flag |
| 969 | * here - if the FIFO is completely empty, then by |
| 970 | * definition it is more than half empty. |
| 971 | * |
| 972 | * For read, check for data available. |
| 973 | */ |
| 974 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) |
| 975 | break; |
| 976 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 977 | if (!sg_miter_next(sg_miter)) |
| 978 | break; |
| 979 | |
| 980 | buffer = sg_miter->addr; |
| 981 | remain = sg_miter->length; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 982 | |
| 983 | len = 0; |
| 984 | if (status & MCI_RXACTIVE) |
| 985 | len = mmci_pio_read(host, buffer, remain); |
| 986 | if (status & MCI_TXACTIVE) |
| 987 | len = mmci_pio_write(host, buffer, remain, status); |
| 988 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 989 | sg_miter->consumed = len; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 990 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 991 | host->size -= len; |
| 992 | remain -= len; |
| 993 | |
| 994 | if (remain) |
| 995 | break; |
| 996 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 997 | status = readl(base + MMCISTATUS); |
| 998 | } while (1); |
| 999 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 1000 | sg_miter_stop(sg_miter); |
| 1001 | |
| 1002 | local_irq_restore(flags); |
| 1003 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1004 | /* |
Russell King | c4d877c | 2011-01-27 09:50:13 +0000 | [diff] [blame] | 1005 | * If we have less than the fifo 'half-full' threshold to transfer, |
| 1006 | * trigger a PIO interrupt as soon as any data is available. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1007 | */ |
Russell King | c4d877c | 2011-01-27 09:50:13 +0000 | [diff] [blame] | 1008 | if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1009 | mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1010 | |
| 1011 | /* |
| 1012 | * If we run out of data, disable the data IRQs; this |
| 1013 | * prevents a race where the FIFO becomes empty before |
| 1014 | * the chip itself has disabled the data path, and |
| 1015 | * stops us racing with our data end IRQ. |
| 1016 | */ |
| 1017 | if (host->size == 0) { |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1018 | mmci_set_mask1(host, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1019 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); |
| 1020 | } |
| 1021 | |
| 1022 | return IRQ_HANDLED; |
| 1023 | } |
| 1024 | |
| 1025 | /* |
| 1026 | * Handle completion of command and data transfers. |
| 1027 | */ |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1028 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1029 | { |
| 1030 | struct mmci_host *host = dev_id; |
| 1031 | u32 status; |
| 1032 | int ret = 0; |
| 1033 | |
| 1034 | spin_lock(&host->lock); |
| 1035 | |
| 1036 | do { |
| 1037 | struct mmc_command *cmd; |
| 1038 | struct mmc_data *data; |
| 1039 | |
| 1040 | status = readl(host->base + MMCISTATUS); |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1041 | |
| 1042 | if (host->singleirq) { |
| 1043 | if (status & readl(host->base + MMCIMASK1)) |
| 1044 | mmci_pio_irq(irq, dev_id); |
| 1045 | |
| 1046 | status &= ~MCI_IRQ1MASK; |
| 1047 | } |
| 1048 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1049 | status &= readl(host->base + MMCIMASK0); |
| 1050 | writel(status, host->base + MMCICLEAR); |
| 1051 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 1052 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1053 | |
| 1054 | data = host->data; |
Ulf Hansson | b63038d | 2011-12-13 16:51:04 +0100 | [diff] [blame] | 1055 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| |
| 1056 | MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| |
| 1057 | MCI_DATABLOCKEND) && data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1058 | mmci_data_irq(host, data, status); |
| 1059 | |
| 1060 | cmd = host->cmd; |
| 1061 | if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) |
| 1062 | mmci_cmd_irq(host, cmd, status); |
| 1063 | |
| 1064 | ret = 1; |
| 1065 | } while (status); |
| 1066 | |
| 1067 | spin_unlock(&host->lock); |
| 1068 | |
| 1069 | return IRQ_RETVAL(ret); |
| 1070 | } |
| 1071 | |
| 1072 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) |
| 1073 | { |
| 1074 | struct mmci_host *host = mmc_priv(mmc); |
Linus Walleij | 9e94302 | 2008-10-24 21:17:50 +0100 | [diff] [blame] | 1075 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1076 | |
| 1077 | WARN_ON(host->mrq != NULL); |
| 1078 | |
Nicolas Pitre | 019a5f5 | 2007-10-11 01:06:03 -0400 | [diff] [blame] | 1079 | if (mrq->data && !is_power_of_2(mrq->data->blksz)) { |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 1080 | dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", |
| 1081 | mrq->data->blksz); |
Pierre Ossman | 255d01a | 2007-07-24 20:38:53 +0200 | [diff] [blame] | 1082 | mrq->cmd->error = -EINVAL; |
| 1083 | mmc_request_done(mmc, mrq); |
| 1084 | return; |
| 1085 | } |
| 1086 | |
Russell King | 1c3be36 | 2011-08-14 09:17:05 +0100 | [diff] [blame] | 1087 | pm_runtime_get_sync(mmc_dev(mmc)); |
| 1088 | |
Linus Walleij | 9e94302 | 2008-10-24 21:17:50 +0100 | [diff] [blame] | 1089 | spin_lock_irqsave(&host->lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1090 | |
| 1091 | host->mrq = mrq; |
| 1092 | |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 1093 | if (mrq->data) |
| 1094 | mmci_get_next_data(host, mrq->data); |
| 1095 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1096 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) |
| 1097 | mmci_start_data(host, mrq->data); |
| 1098 | |
| 1099 | mmci_start_command(host, mrq->cmd, 0); |
| 1100 | |
Linus Walleij | 9e94302 | 2008-10-24 21:17:50 +0100 | [diff] [blame] | 1101 | spin_unlock_irqrestore(&host->lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1102 | } |
| 1103 | |
| 1104 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
| 1105 | { |
| 1106 | struct mmci_host *host = mmc_priv(mmc); |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 1107 | struct variant_data *variant = host->variant; |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 1108 | u32 pwr = 0; |
| 1109 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1110 | |
Ulf Hansson | 2cd976c | 2011-12-13 17:01:11 +0100 | [diff] [blame] | 1111 | pm_runtime_get_sync(mmc_dev(mmc)); |
| 1112 | |
Ulf Hansson | bc52181 | 2011-12-13 16:57:55 +0100 | [diff] [blame] | 1113 | if (host->plat->ios_handler && |
| 1114 | host->plat->ios_handler(mmc_dev(mmc), ios)) |
| 1115 | dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); |
| 1116 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1117 | switch (ios->power_mode) { |
| 1118 | case MMC_POWER_OFF: |
Ulf Hansson | 599c1d5 | 2013-01-07 16:22:50 +0100 | [diff] [blame] | 1119 | if (!IS_ERR(mmc->supply.vmmc)) |
| 1120 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1121 | break; |
| 1122 | case MMC_POWER_UP: |
Ulf Hansson | 599c1d5 | 2013-01-07 16:22:50 +0100 | [diff] [blame] | 1123 | if (!IS_ERR(mmc->supply.vmmc)) |
| 1124 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); |
| 1125 | |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 1126 | /* |
| 1127 | * The ST Micro variant doesn't have the PL180s MCI_PWR_UP |
| 1128 | * and instead uses MCI_PWR_ON so apply whatever value is |
| 1129 | * configured in the variant data. |
| 1130 | */ |
| 1131 | pwr |= variant->pwrreg_powerup; |
| 1132 | |
| 1133 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1134 | case MMC_POWER_ON: |
| 1135 | pwr |= MCI_PWR_ON; |
| 1136 | break; |
| 1137 | } |
| 1138 | |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 1139 | if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { |
| 1140 | /* |
| 1141 | * The ST Micro variant has some additional bits |
| 1142 | * indicating signal direction for the signals in |
| 1143 | * the SD/MMC bus and feedback-clock usage. |
| 1144 | */ |
| 1145 | pwr |= host->plat->sigdir; |
| 1146 | |
| 1147 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
| 1148 | pwr &= ~MCI_ST_DATA74DIREN; |
| 1149 | else if (ios->bus_width == MMC_BUS_WIDTH_1) |
| 1150 | pwr &= (~MCI_ST_DATA74DIREN & |
| 1151 | ~MCI_ST_DATA31DIREN & |
| 1152 | ~MCI_ST_DATA2DIREN); |
| 1153 | } |
| 1154 | |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 1155 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { |
Linus Walleij | f17a1f0 | 2009-08-04 01:01:02 +0100 | [diff] [blame] | 1156 | if (host->hw_designer != AMBA_VENDOR_ST) |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 1157 | pwr |= MCI_ROD; |
| 1158 | else { |
| 1159 | /* |
| 1160 | * The ST Micro variant use the ROD bit for something |
| 1161 | * else and only has OD (Open Drain). |
| 1162 | */ |
| 1163 | pwr |= MCI_OD; |
| 1164 | } |
| 1165 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1166 | |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 1167 | /* |
| 1168 | * If clock = 0 and the variant requires the MMCIPOWER to be used for |
| 1169 | * gating the clock, the MCI_PWR_ON bit is cleared. |
| 1170 | */ |
| 1171 | if (!ios->clock && variant->pwrreg_clkgate) |
| 1172 | pwr &= ~MCI_PWR_ON; |
| 1173 | |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 1174 | spin_lock_irqsave(&host->lock, flags); |
| 1175 | |
| 1176 | mmci_set_clkreg(host, ios->clock); |
Ulf Hansson | 7437cfa | 2012-01-18 09:17:27 +0100 | [diff] [blame] | 1177 | mmci_write_pwrreg(host, pwr); |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 1178 | |
| 1179 | spin_unlock_irqrestore(&host->lock, flags); |
Ulf Hansson | 2cd976c | 2011-12-13 17:01:11 +0100 | [diff] [blame] | 1180 | |
Ulf Hansson | 2cd976c | 2011-12-13 17:01:11 +0100 | [diff] [blame] | 1181 | pm_runtime_mark_last_busy(mmc_dev(mmc)); |
| 1182 | pm_runtime_put_autosuspend(mmc_dev(mmc)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1183 | } |
| 1184 | |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1185 | static int mmci_get_ro(struct mmc_host *mmc) |
| 1186 | { |
| 1187 | struct mmci_host *host = mmc_priv(mmc); |
| 1188 | |
| 1189 | if (host->gpio_wp == -ENOSYS) |
| 1190 | return -ENOSYS; |
| 1191 | |
Linus Walleij | 18a06301 | 2010-09-12 12:56:44 +0100 | [diff] [blame] | 1192 | return gpio_get_value_cansleep(host->gpio_wp); |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1193 | } |
| 1194 | |
| 1195 | static int mmci_get_cd(struct mmc_host *mmc) |
| 1196 | { |
| 1197 | struct mmci_host *host = mmc_priv(mmc); |
Rabin Vincent | 2971944 | 2010-08-09 12:54:43 +0100 | [diff] [blame] | 1198 | struct mmci_platform_data *plat = host->plat; |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1199 | unsigned int status; |
| 1200 | |
Rabin Vincent | 4b8caec | 2010-08-09 12:56:40 +0100 | [diff] [blame] | 1201 | if (host->gpio_cd == -ENOSYS) { |
| 1202 | if (!plat->status) |
| 1203 | return 1; /* Assume always present */ |
| 1204 | |
Rabin Vincent | 2971944 | 2010-08-09 12:54:43 +0100 | [diff] [blame] | 1205 | status = plat->status(mmc_dev(host->mmc)); |
Rabin Vincent | 4b8caec | 2010-08-09 12:56:40 +0100 | [diff] [blame] | 1206 | } else |
Linus Walleij | 18a06301 | 2010-09-12 12:56:44 +0100 | [diff] [blame] | 1207 | status = !!gpio_get_value_cansleep(host->gpio_cd) |
| 1208 | ^ plat->cd_invert; |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1209 | |
Russell King | 74bc809 | 2010-07-29 15:58:59 +0100 | [diff] [blame] | 1210 | /* |
| 1211 | * Use positive logic throughout - status is zero for no card, |
| 1212 | * non-zero for card inserted. |
| 1213 | */ |
| 1214 | return status; |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1215 | } |
| 1216 | |
Rabin Vincent | 148b8b3 | 2010-08-09 12:55:48 +0100 | [diff] [blame] | 1217 | static irqreturn_t mmci_cd_irq(int irq, void *dev_id) |
| 1218 | { |
| 1219 | struct mmci_host *host = dev_id; |
| 1220 | |
| 1221 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); |
| 1222 | |
| 1223 | return IRQ_HANDLED; |
| 1224 | } |
| 1225 | |
David Brownell | ab7aefd | 2006-11-12 17:55:30 -0800 | [diff] [blame] | 1226 | static const struct mmc_host_ops mmci_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1227 | .request = mmci_request, |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 1228 | .pre_req = mmci_pre_request, |
| 1229 | .post_req = mmci_post_request, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1230 | .set_ios = mmci_set_ios, |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1231 | .get_ro = mmci_get_ro, |
| 1232 | .get_cd = mmci_get_cd, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1233 | }; |
| 1234 | |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1235 | #ifdef CONFIG_OF |
| 1236 | static void mmci_dt_populate_generic_pdata(struct device_node *np, |
| 1237 | struct mmci_platform_data *pdata) |
| 1238 | { |
| 1239 | int bus_width = 0; |
| 1240 | |
Lee Jones | 9a59701 | 2012-04-12 16:51:13 +0100 | [diff] [blame] | 1241 | pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); |
Lee Jones | 9a59701 | 2012-04-12 16:51:13 +0100 | [diff] [blame] | 1242 | pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0); |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1243 | |
| 1244 | if (of_get_property(np, "cd-inverted", NULL)) |
| 1245 | pdata->cd_invert = true; |
| 1246 | else |
| 1247 | pdata->cd_invert = false; |
| 1248 | |
| 1249 | of_property_read_u32(np, "max-frequency", &pdata->f_max); |
| 1250 | if (!pdata->f_max) |
| 1251 | pr_warn("%s has no 'max-frequency' property\n", np->full_name); |
| 1252 | |
| 1253 | if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) |
| 1254 | pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED; |
| 1255 | if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) |
| 1256 | pdata->capabilities |= MMC_CAP_SD_HIGHSPEED; |
| 1257 | |
| 1258 | of_property_read_u32(np, "bus-width", &bus_width); |
| 1259 | switch (bus_width) { |
| 1260 | case 0 : |
| 1261 | /* No bus-width supplied. */ |
| 1262 | break; |
| 1263 | case 4 : |
| 1264 | pdata->capabilities |= MMC_CAP_4_BIT_DATA; |
| 1265 | break; |
| 1266 | case 8 : |
| 1267 | pdata->capabilities |= MMC_CAP_8_BIT_DATA; |
| 1268 | break; |
| 1269 | default : |
| 1270 | pr_warn("%s: Unsupported bus width\n", np->full_name); |
| 1271 | } |
| 1272 | } |
Lee Jones | c0a120a | 2012-05-08 13:59:38 +0100 | [diff] [blame] | 1273 | #else |
| 1274 | static void mmci_dt_populate_generic_pdata(struct device_node *np, |
| 1275 | struct mmci_platform_data *pdata) |
| 1276 | { |
| 1277 | return; |
| 1278 | } |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1279 | #endif |
| 1280 | |
Bill Pemberton | c3be1ef | 2012-11-19 13:23:06 -0500 | [diff] [blame] | 1281 | static int mmci_probe(struct amba_device *dev, |
Russell King | aa25afa | 2011-02-19 15:55:00 +0000 | [diff] [blame] | 1282 | const struct amba_id *id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1283 | { |
Linus Walleij | 6ef297f | 2009-09-22 14:29:36 +0100 | [diff] [blame] | 1284 | struct mmci_platform_data *plat = dev->dev.platform_data; |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1285 | struct device_node *np = dev->dev.of_node; |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1286 | struct variant_data *variant = id->data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1287 | struct mmci_host *host; |
| 1288 | struct mmc_host *mmc; |
| 1289 | int ret; |
| 1290 | |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1291 | /* Must have platform data or Device Tree. */ |
| 1292 | if (!plat && !np) { |
| 1293 | dev_err(&dev->dev, "No plat data or DT found\n"); |
| 1294 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1295 | } |
| 1296 | |
Lee Jones | b9b5291 | 2012-06-12 10:49:51 +0100 | [diff] [blame] | 1297 | if (!plat) { |
| 1298 | plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); |
| 1299 | if (!plat) |
| 1300 | return -ENOMEM; |
| 1301 | } |
| 1302 | |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1303 | if (np) |
| 1304 | mmci_dt_populate_generic_pdata(np, plat); |
| 1305 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1306 | ret = amba_request_regions(dev, DRIVER_NAME); |
| 1307 | if (ret) |
| 1308 | goto out; |
| 1309 | |
| 1310 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); |
| 1311 | if (!mmc) { |
| 1312 | ret = -ENOMEM; |
| 1313 | goto rel_regions; |
| 1314 | } |
| 1315 | |
| 1316 | host = mmc_priv(mmc); |
Rabin Vincent | 4ea580f | 2009-04-17 08:44:19 +0530 | [diff] [blame] | 1317 | host->mmc = mmc; |
Russell King | 012b7d3 | 2009-07-09 15:13:56 +0100 | [diff] [blame] | 1318 | |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1319 | host->gpio_wp = -ENOSYS; |
| 1320 | host->gpio_cd = -ENOSYS; |
Rabin Vincent | 148b8b3 | 2010-08-09 12:55:48 +0100 | [diff] [blame] | 1321 | host->gpio_cd_irq = -1; |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1322 | |
Russell King | 012b7d3 | 2009-07-09 15:13:56 +0100 | [diff] [blame] | 1323 | host->hw_designer = amba_manf(dev); |
| 1324 | host->hw_revision = amba_rev(dev); |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 1325 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
| 1326 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); |
Russell King | 012b7d3 | 2009-07-09 15:13:56 +0100 | [diff] [blame] | 1327 | |
Russell King | ee569c4 | 2008-11-30 17:38:14 +0000 | [diff] [blame] | 1328 | host->clk = clk_get(&dev->dev, NULL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1329 | if (IS_ERR(host->clk)) { |
| 1330 | ret = PTR_ERR(host->clk); |
| 1331 | host->clk = NULL; |
| 1332 | goto host_free; |
| 1333 | } |
| 1334 | |
Julia Lawall | ac94093 | 2012-08-26 16:00:59 +0000 | [diff] [blame] | 1335 | ret = clk_prepare_enable(host->clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1336 | if (ret) |
Russell King | a8d3584 | 2006-01-03 18:41:37 +0000 | [diff] [blame] | 1337 | goto clk_free; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1338 | |
| 1339 | host->plat = plat; |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1340 | host->variant = variant; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1341 | host->mclk = clk_get_rate(host->clk); |
Linus Walleij | c8df9a5 | 2008-04-29 09:34:07 +0100 | [diff] [blame] | 1342 | /* |
| 1343 | * According to the spec, mclk is max 100 MHz, |
| 1344 | * so we try to adjust the clock down to this, |
| 1345 | * (if possible). |
| 1346 | */ |
| 1347 | if (host->mclk > 100000000) { |
| 1348 | ret = clk_set_rate(host->clk, 100000000); |
| 1349 | if (ret < 0) |
| 1350 | goto clk_disable; |
| 1351 | host->mclk = clk_get_rate(host->clk); |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 1352 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
| 1353 | host->mclk); |
Linus Walleij | c8df9a5 | 2008-04-29 09:34:07 +0100 | [diff] [blame] | 1354 | } |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 1355 | host->phybase = dev->res.start; |
Linus Walleij | dc890c2 | 2009-06-07 23:27:31 +0100 | [diff] [blame] | 1356 | host->base = ioremap(dev->res.start, resource_size(&dev->res)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1357 | if (!host->base) { |
| 1358 | ret = -ENOMEM; |
| 1359 | goto clk_disable; |
| 1360 | } |
| 1361 | |
| 1362 | mmc->ops = &mmci_ops; |
Linus Walleij | 7f294e4 | 2011-07-08 09:57:15 +0100 | [diff] [blame] | 1363 | /* |
| 1364 | * The ARM and ST versions of the block have slightly different |
| 1365 | * clock divider equations which means that the minimum divider |
| 1366 | * differs too. |
| 1367 | */ |
| 1368 | if (variant->st_clkdiv) |
| 1369 | mmc->f_min = DIV_ROUND_UP(host->mclk, 257); |
| 1370 | else |
| 1371 | mmc->f_min = DIV_ROUND_UP(host->mclk, 512); |
Linus Walleij | 808d97c | 2010-04-08 07:39:38 +0100 | [diff] [blame] | 1372 | /* |
| 1373 | * If the platform data supplies a maximum operating |
| 1374 | * frequency, this takes precedence. Else, we fall back |
| 1375 | * to using the module parameter, which has a (low) |
| 1376 | * default value in case it is not specified. Either |
| 1377 | * value must not exceed the clock rate into the block, |
| 1378 | * of course. |
| 1379 | */ |
| 1380 | if (plat->f_max) |
| 1381 | mmc->f_max = min(host->mclk, plat->f_max); |
| 1382 | else |
| 1383 | mmc->f_max = min(host->mclk, fmax); |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 1384 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
| 1385 | |
Linus Walleij | a9a8378 | 2012-10-29 14:39:30 +0100 | [diff] [blame] | 1386 | host->pinctrl = devm_pinctrl_get(&dev->dev); |
| 1387 | if (IS_ERR(host->pinctrl)) { |
| 1388 | ret = PTR_ERR(host->pinctrl); |
| 1389 | goto clk_disable; |
| 1390 | } |
| 1391 | |
| 1392 | host->pins_default = pinctrl_lookup_state(host->pinctrl, |
| 1393 | PINCTRL_STATE_DEFAULT); |
| 1394 | |
| 1395 | /* enable pins to be muxed in and configured */ |
| 1396 | if (!IS_ERR(host->pins_default)) { |
| 1397 | ret = pinctrl_select_state(host->pinctrl, host->pins_default); |
| 1398 | if (ret) |
| 1399 | dev_warn(&dev->dev, "could not set default pins\n"); |
| 1400 | } else |
| 1401 | dev_warn(&dev->dev, "could not get default pinstate\n"); |
| 1402 | |
Ulf Hansson | 599c1d5 | 2013-01-07 16:22:50 +0100 | [diff] [blame] | 1403 | /* Get regulators and the supported OCR mask */ |
| 1404 | mmc_regulator_get_supply(mmc); |
| 1405 | if (!mmc->ocr_avail) |
Linus Walleij | 34e84f3 | 2009-09-22 14:41:40 +0100 | [diff] [blame] | 1406 | mmc->ocr_avail = plat->ocr_mask; |
Ulf Hansson | 599c1d5 | 2013-01-07 16:22:50 +0100 | [diff] [blame] | 1407 | else if (plat->ocr_mask) |
| 1408 | dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); |
| 1409 | |
Linus Walleij | 9e6c82c | 2009-09-14 12:57:11 +0100 | [diff] [blame] | 1410 | mmc->caps = plat->capabilities; |
Per Forlin | 5a09262 | 2011-11-14 12:02:28 +0100 | [diff] [blame] | 1411 | mmc->caps2 = plat->capabilities2; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1412 | |
Ulf Hansson | 70be208 | 2013-01-07 15:35:06 +0100 | [diff] [blame] | 1413 | /* We support these PM capabilities. */ |
| 1414 | mmc->pm_caps = MMC_PM_KEEP_POWER; |
| 1415 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1416 | /* |
| 1417 | * We can do SGIO |
| 1418 | */ |
Martin K. Petersen | a36274e | 2010-09-10 01:33:59 -0400 | [diff] [blame] | 1419 | mmc->max_segs = NR_SG; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1420 | |
| 1421 | /* |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 1422 | * Since only a certain number of bits are valid in the data length |
| 1423 | * register, we must ensure that we don't exceed 2^num-1 bytes in a |
| 1424 | * single request. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1425 | */ |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 1426 | mmc->max_req_size = (1 << variant->datalength_bits) - 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1427 | |
| 1428 | /* |
| 1429 | * Set the maximum segment size. Since we aren't doing DMA |
| 1430 | * (yet) we are only limited by the data length register. |
| 1431 | */ |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 1432 | mmc->max_seg_size = mmc->max_req_size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1433 | |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 1434 | /* |
| 1435 | * Block size can be up to 2048 bytes, but must be a power of two. |
| 1436 | */ |
Will Deacon | 8f7f6b7 | 2012-02-24 11:25:21 +0000 | [diff] [blame] | 1437 | mmc->max_blk_size = 1 << 11; |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 1438 | |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 1439 | /* |
Will Deacon | 8f7f6b7 | 2012-02-24 11:25:21 +0000 | [diff] [blame] | 1440 | * Limit the number of blocks transferred so that we don't overflow |
| 1441 | * the maximum request size. |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 1442 | */ |
Will Deacon | 8f7f6b7 | 2012-02-24 11:25:21 +0000 | [diff] [blame] | 1443 | mmc->max_blk_count = mmc->max_req_size >> 11; |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 1444 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1445 | spin_lock_init(&host->lock); |
| 1446 | |
| 1447 | writel(0, host->base + MMCIMASK0); |
| 1448 | writel(0, host->base + MMCIMASK1); |
| 1449 | writel(0xfff, host->base + MMCICLEAR); |
| 1450 | |
Roland Stigge | 2805b9a | 2012-06-17 21:14:27 +0100 | [diff] [blame] | 1451 | if (plat->gpio_cd == -EPROBE_DEFER) { |
| 1452 | ret = -EPROBE_DEFER; |
| 1453 | goto err_gpio_cd; |
| 1454 | } |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1455 | if (gpio_is_valid(plat->gpio_cd)) { |
| 1456 | ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); |
| 1457 | if (ret == 0) |
| 1458 | ret = gpio_direction_input(plat->gpio_cd); |
| 1459 | if (ret == 0) |
| 1460 | host->gpio_cd = plat->gpio_cd; |
| 1461 | else if (ret != -ENOSYS) |
| 1462 | goto err_gpio_cd; |
Rabin Vincent | 148b8b3 | 2010-08-09 12:55:48 +0100 | [diff] [blame] | 1463 | |
Linus Walleij | 17ee083 | 2011-05-05 17:23:10 +0100 | [diff] [blame] | 1464 | /* |
| 1465 | * A gpio pin that will detect cards when inserted and removed |
| 1466 | * will most likely want to trigger on the edges if it is |
| 1467 | * 0 when ejected and 1 when inserted (or mutatis mutandis |
| 1468 | * for the inverted case) so we request triggers on both |
| 1469 | * edges. |
| 1470 | */ |
Rabin Vincent | 148b8b3 | 2010-08-09 12:55:48 +0100 | [diff] [blame] | 1471 | ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), |
Linus Walleij | 17ee083 | 2011-05-05 17:23:10 +0100 | [diff] [blame] | 1472 | mmci_cd_irq, |
| 1473 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, |
| 1474 | DRIVER_NAME " (cd)", host); |
Rabin Vincent | 148b8b3 | 2010-08-09 12:55:48 +0100 | [diff] [blame] | 1475 | if (ret >= 0) |
| 1476 | host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1477 | } |
Roland Stigge | 2805b9a | 2012-06-17 21:14:27 +0100 | [diff] [blame] | 1478 | if (plat->gpio_wp == -EPROBE_DEFER) { |
| 1479 | ret = -EPROBE_DEFER; |
| 1480 | goto err_gpio_wp; |
| 1481 | } |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1482 | if (gpio_is_valid(plat->gpio_wp)) { |
| 1483 | ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); |
| 1484 | if (ret == 0) |
| 1485 | ret = gpio_direction_input(plat->gpio_wp); |
| 1486 | if (ret == 0) |
| 1487 | host->gpio_wp = plat->gpio_wp; |
| 1488 | else if (ret != -ENOSYS) |
| 1489 | goto err_gpio_wp; |
| 1490 | } |
| 1491 | |
Rabin Vincent | 4b8caec | 2010-08-09 12:56:40 +0100 | [diff] [blame] | 1492 | if ((host->plat->status || host->gpio_cd != -ENOSYS) |
| 1493 | && host->gpio_cd_irq < 0) |
Rabin Vincent | 148b8b3 | 2010-08-09 12:55:48 +0100 | [diff] [blame] | 1494 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
| 1495 | |
Thomas Gleixner | dace145 | 2006-07-01 19:29:38 -0700 | [diff] [blame] | 1496 | ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1497 | if (ret) |
| 1498 | goto unmap; |
| 1499 | |
Russell King | dfb8518 | 2012-05-03 11:33:15 +0100 | [diff] [blame] | 1500 | if (!dev->irq[1]) |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1501 | host->singleirq = true; |
| 1502 | else { |
| 1503 | ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, |
| 1504 | DRIVER_NAME " (pio)", host); |
| 1505 | if (ret) |
| 1506 | goto irq0_free; |
| 1507 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1508 | |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 1509 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1510 | |
| 1511 | amba_set_drvdata(dev, mmc); |
| 1512 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 1513 | dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", |
| 1514 | mmc_hostname(mmc), amba_part(dev), amba_manf(dev), |
| 1515 | amba_rev(dev), (unsigned long long)dev->res.start, |
| 1516 | dev->irq[0], dev->irq[1]); |
| 1517 | |
| 1518 | mmci_dma_setup(host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1519 | |
Ulf Hansson | 2cd976c | 2011-12-13 17:01:11 +0100 | [diff] [blame] | 1520 | pm_runtime_set_autosuspend_delay(&dev->dev, 50); |
| 1521 | pm_runtime_use_autosuspend(&dev->dev); |
Russell King | 1c3be36 | 2011-08-14 09:17:05 +0100 | [diff] [blame] | 1522 | pm_runtime_put(&dev->dev); |
| 1523 | |
Russell King | 8c11a94 | 2010-12-28 19:40:40 +0000 | [diff] [blame] | 1524 | mmc_add_host(mmc); |
| 1525 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1526 | return 0; |
| 1527 | |
| 1528 | irq0_free: |
| 1529 | free_irq(dev->irq[0], host); |
| 1530 | unmap: |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1531 | if (host->gpio_wp != -ENOSYS) |
| 1532 | gpio_free(host->gpio_wp); |
| 1533 | err_gpio_wp: |
Rabin Vincent | 148b8b3 | 2010-08-09 12:55:48 +0100 | [diff] [blame] | 1534 | if (host->gpio_cd_irq >= 0) |
| 1535 | free_irq(host->gpio_cd_irq, host); |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1536 | if (host->gpio_cd != -ENOSYS) |
| 1537 | gpio_free(host->gpio_cd); |
| 1538 | err_gpio_cd: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1539 | iounmap(host->base); |
| 1540 | clk_disable: |
Julia Lawall | ac94093 | 2012-08-26 16:00:59 +0000 | [diff] [blame] | 1541 | clk_disable_unprepare(host->clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1542 | clk_free: |
| 1543 | clk_put(host->clk); |
| 1544 | host_free: |
| 1545 | mmc_free_host(mmc); |
| 1546 | rel_regions: |
| 1547 | amba_release_regions(dev); |
| 1548 | out: |
| 1549 | return ret; |
| 1550 | } |
| 1551 | |
Bill Pemberton | 6e0ee71 | 2012-11-19 13:26:03 -0500 | [diff] [blame] | 1552 | static int mmci_remove(struct amba_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1553 | { |
| 1554 | struct mmc_host *mmc = amba_get_drvdata(dev); |
| 1555 | |
| 1556 | amba_set_drvdata(dev, NULL); |
| 1557 | |
| 1558 | if (mmc) { |
| 1559 | struct mmci_host *host = mmc_priv(mmc); |
| 1560 | |
Russell King | 1c3be36 | 2011-08-14 09:17:05 +0100 | [diff] [blame] | 1561 | /* |
| 1562 | * Undo pm_runtime_put() in probe. We use the _sync |
| 1563 | * version here so that we can access the primecell. |
| 1564 | */ |
| 1565 | pm_runtime_get_sync(&dev->dev); |
| 1566 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1567 | mmc_remove_host(mmc); |
| 1568 | |
| 1569 | writel(0, host->base + MMCIMASK0); |
| 1570 | writel(0, host->base + MMCIMASK1); |
| 1571 | |
| 1572 | writel(0, host->base + MMCICOMMAND); |
| 1573 | writel(0, host->base + MMCIDATACTRL); |
| 1574 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 1575 | mmci_dma_release(host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1576 | free_irq(dev->irq[0], host); |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1577 | if (!host->singleirq) |
| 1578 | free_irq(dev->irq[1], host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1579 | |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1580 | if (host->gpio_wp != -ENOSYS) |
| 1581 | gpio_free(host->gpio_wp); |
Rabin Vincent | 148b8b3 | 2010-08-09 12:55:48 +0100 | [diff] [blame] | 1582 | if (host->gpio_cd_irq >= 0) |
| 1583 | free_irq(host->gpio_cd_irq, host); |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1584 | if (host->gpio_cd != -ENOSYS) |
| 1585 | gpio_free(host->gpio_cd); |
| 1586 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1587 | iounmap(host->base); |
Julia Lawall | ac94093 | 2012-08-26 16:00:59 +0000 | [diff] [blame] | 1588 | clk_disable_unprepare(host->clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1589 | clk_put(host->clk); |
| 1590 | |
| 1591 | mmc_free_host(mmc); |
| 1592 | |
| 1593 | amba_release_regions(dev); |
| 1594 | } |
| 1595 | |
| 1596 | return 0; |
| 1597 | } |
| 1598 | |
Ulf Hansson | 48fa700 | 2011-12-13 16:59:34 +0100 | [diff] [blame] | 1599 | #ifdef CONFIG_SUSPEND |
| 1600 | static int mmci_suspend(struct device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1601 | { |
Ulf Hansson | 48fa700 | 2011-12-13 16:59:34 +0100 | [diff] [blame] | 1602 | struct amba_device *adev = to_amba_device(dev); |
| 1603 | struct mmc_host *mmc = amba_get_drvdata(adev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1604 | int ret = 0; |
| 1605 | |
| 1606 | if (mmc) { |
| 1607 | struct mmci_host *host = mmc_priv(mmc); |
| 1608 | |
Matt Fleming | 1a13f8f | 2010-05-26 14:42:08 -0700 | [diff] [blame] | 1609 | ret = mmc_suspend_host(mmc); |
Ulf Hansson | 2cd976c | 2011-12-13 17:01:11 +0100 | [diff] [blame] | 1610 | if (ret == 0) { |
| 1611 | pm_runtime_get_sync(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1612 | writel(0, host->base + MMCIMASK0); |
Ulf Hansson | 2cd976c | 2011-12-13 17:01:11 +0100 | [diff] [blame] | 1613 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1614 | } |
| 1615 | |
| 1616 | return ret; |
| 1617 | } |
| 1618 | |
Ulf Hansson | 48fa700 | 2011-12-13 16:59:34 +0100 | [diff] [blame] | 1619 | static int mmci_resume(struct device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1620 | { |
Ulf Hansson | 48fa700 | 2011-12-13 16:59:34 +0100 | [diff] [blame] | 1621 | struct amba_device *adev = to_amba_device(dev); |
| 1622 | struct mmc_host *mmc = amba_get_drvdata(adev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1623 | int ret = 0; |
| 1624 | |
| 1625 | if (mmc) { |
| 1626 | struct mmci_host *host = mmc_priv(mmc); |
| 1627 | |
| 1628 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); |
Ulf Hansson | 2cd976c | 2011-12-13 17:01:11 +0100 | [diff] [blame] | 1629 | pm_runtime_put(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1630 | |
| 1631 | ret = mmc_resume_host(mmc); |
| 1632 | } |
| 1633 | |
| 1634 | return ret; |
| 1635 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1636 | #endif |
| 1637 | |
Ulf Hansson | 8259293 | 2013-01-09 11:15:26 +0100 | [diff] [blame] | 1638 | #ifdef CONFIG_PM_RUNTIME |
| 1639 | static int mmci_runtime_suspend(struct device *dev) |
| 1640 | { |
| 1641 | struct amba_device *adev = to_amba_device(dev); |
| 1642 | struct mmc_host *mmc = amba_get_drvdata(adev); |
| 1643 | |
| 1644 | if (mmc) { |
| 1645 | struct mmci_host *host = mmc_priv(mmc); |
| 1646 | clk_disable_unprepare(host->clk); |
| 1647 | } |
| 1648 | |
| 1649 | return 0; |
| 1650 | } |
| 1651 | |
| 1652 | static int mmci_runtime_resume(struct device *dev) |
| 1653 | { |
| 1654 | struct amba_device *adev = to_amba_device(dev); |
| 1655 | struct mmc_host *mmc = amba_get_drvdata(adev); |
| 1656 | |
| 1657 | if (mmc) { |
| 1658 | struct mmci_host *host = mmc_priv(mmc); |
| 1659 | clk_prepare_enable(host->clk); |
| 1660 | } |
| 1661 | |
| 1662 | return 0; |
| 1663 | } |
| 1664 | #endif |
| 1665 | |
Ulf Hansson | 48fa700 | 2011-12-13 16:59:34 +0100 | [diff] [blame] | 1666 | static const struct dev_pm_ops mmci_dev_pm_ops = { |
| 1667 | SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume) |
Ulf Hansson | 8259293 | 2013-01-09 11:15:26 +0100 | [diff] [blame] | 1668 | SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) |
Ulf Hansson | 48fa700 | 2011-12-13 16:59:34 +0100 | [diff] [blame] | 1669 | }; |
| 1670 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1671 | static struct amba_id mmci_ids[] = { |
| 1672 | { |
| 1673 | .id = 0x00041180, |
Pawel Moll | 768fbc1 | 2011-03-11 17:18:07 +0000 | [diff] [blame] | 1674 | .mask = 0xff0fffff, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1675 | .data = &variant_arm, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1676 | }, |
| 1677 | { |
Pawel Moll | 768fbc1 | 2011-03-11 17:18:07 +0000 | [diff] [blame] | 1678 | .id = 0x01041180, |
| 1679 | .mask = 0xff0fffff, |
| 1680 | .data = &variant_arm_extended_fifo, |
| 1681 | }, |
| 1682 | { |
Pawel Moll | 3a37298 | 2013-01-24 14:12:45 +0100 | [diff] [blame^] | 1683 | .id = 0x02041180, |
| 1684 | .mask = 0xff0fffff, |
| 1685 | .data = &variant_arm_extended_fifo_hwfc, |
| 1686 | }, |
| 1687 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1688 | .id = 0x00041181, |
| 1689 | .mask = 0x000fffff, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1690 | .data = &variant_arm, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1691 | }, |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 1692 | /* ST Micro variants */ |
| 1693 | { |
| 1694 | .id = 0x00180180, |
| 1695 | .mask = 0x00ffffff, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1696 | .data = &variant_u300, |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 1697 | }, |
| 1698 | { |
Linus Walleij | 34fd421 | 2012-04-10 17:43:59 +0100 | [diff] [blame] | 1699 | .id = 0x10180180, |
| 1700 | .mask = 0xf0ffffff, |
| 1701 | .data = &variant_nomadik, |
| 1702 | }, |
| 1703 | { |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 1704 | .id = 0x00280180, |
| 1705 | .mask = 0x00ffffff, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1706 | .data = &variant_u300, |
| 1707 | }, |
| 1708 | { |
| 1709 | .id = 0x00480180, |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 1710 | .mask = 0xf0ffffff, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1711 | .data = &variant_ux500, |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 1712 | }, |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 1713 | { |
| 1714 | .id = 0x10480180, |
| 1715 | .mask = 0xf0ffffff, |
| 1716 | .data = &variant_ux500v2, |
| 1717 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1718 | { 0, 0 }, |
| 1719 | }; |
| 1720 | |
Dave Martin | 9f99835 | 2011-10-05 15:15:21 +0100 | [diff] [blame] | 1721 | MODULE_DEVICE_TABLE(amba, mmci_ids); |
| 1722 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1723 | static struct amba_driver mmci_driver = { |
| 1724 | .drv = { |
| 1725 | .name = DRIVER_NAME, |
Ulf Hansson | 48fa700 | 2011-12-13 16:59:34 +0100 | [diff] [blame] | 1726 | .pm = &mmci_dev_pm_ops, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1727 | }, |
| 1728 | .probe = mmci_probe, |
Bill Pemberton | 0433c14 | 2012-11-19 13:20:26 -0500 | [diff] [blame] | 1729 | .remove = mmci_remove, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1730 | .id_table = mmci_ids, |
| 1731 | }; |
| 1732 | |
viresh kumar | 9e5ed09 | 2012-03-15 10:40:38 +0100 | [diff] [blame] | 1733 | module_amba_driver(mmci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1734 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1735 | module_param(fmax, uint, 0444); |
| 1736 | |
| 1737 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); |
| 1738 | MODULE_LICENSE("GPL"); |