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Bard Liao07cf7cba2014-06-20 14:41:13 +08001/*
2 * rt286.c -- RT286 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
Bard Liao6c67cde2014-11-06 09:59:59 +080020#include <linux/dmi.h>
Bard Liao07cf7cba2014-06-20 14:41:13 +080021#include <linux/acpi.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29#include <sound/jack.h>
30#include <linux/workqueue.h>
31#include <sound/rt286.h>
32#include <sound/hda_verbs.h>
33
34#include "rt286.h"
35
36#define RT286_VENDOR_ID 0x10ec0286
Bard Liao3ab888d2015-02-09 14:19:45 +080037#define RT288_VENDOR_ID 0x10ec0288
Bard Liao07cf7cba2014-06-20 14:41:13 +080038
39struct rt286_priv {
40 struct regmap *regmap;
Bard Liao6879db72014-10-31 14:52:16 +080041 struct snd_soc_codec *codec;
Bard Liao07cf7cba2014-06-20 14:41:13 +080042 struct rt286_platform_data pdata;
43 struct i2c_client *i2c;
44 struct snd_soc_jack *jack;
45 struct delayed_work jack_detect_work;
46 int sys_clk;
Bard Liao6879db72014-10-31 14:52:16 +080047 int clk_id;
Bard Liao07cf7cba2014-06-20 14:41:13 +080048 struct reg_default *index_cache;
49};
50
51static struct reg_default rt286_index_def[] = {
52 { 0x01, 0xaaaa },
53 { 0x02, 0x8aaa },
54 { 0x03, 0x0002 },
55 { 0x04, 0xaf01 },
56 { 0x08, 0x000d },
57 { 0x09, 0xd810 },
Bard Liaob7a29762014-09-26 11:06:39 +080058 { 0x0a, 0x0120 },
Bard Liao07cf7cba2014-06-20 14:41:13 +080059 { 0x0b, 0x0000 },
Bard Liaobc6c4e42014-07-07 19:15:30 +080060 { 0x0d, 0x2800 },
Bard Liao07cf7cba2014-06-20 14:41:13 +080061 { 0x0f, 0x0000 },
62 { 0x19, 0x0a17 },
63 { 0x20, 0x0020 },
64 { 0x33, 0x0208 },
65 { 0x49, 0x0004 },
66 { 0x4f, 0x50e9 },
Bard Liaob7a29762014-09-26 11:06:39 +080067 { 0x50, 0x2000 },
Bard Liao07cf7cba2014-06-20 14:41:13 +080068 { 0x63, 0x2902 },
Bard Liaobc6c4e42014-07-07 19:15:30 +080069 { 0x67, 0x1111 },
70 { 0x68, 0x1016 },
71 { 0x69, 0x273f },
Bard Liao07cf7cba2014-06-20 14:41:13 +080072};
73#define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def)
74
75static const struct reg_default rt286_reg[] = {
76 { 0x00170500, 0x00000400 },
77 { 0x00220000, 0x00000031 },
78 { 0x00239000, 0x0000007f },
79 { 0x0023a000, 0x0000007f },
80 { 0x00270500, 0x00000400 },
81 { 0x00370500, 0x00000400 },
82 { 0x00870500, 0x00000400 },
83 { 0x00920000, 0x00000031 },
84 { 0x00935000, 0x000000c3 },
85 { 0x00936000, 0x000000c3 },
86 { 0x00970500, 0x00000400 },
87 { 0x00b37000, 0x00000097 },
88 { 0x00b37200, 0x00000097 },
89 { 0x00b37300, 0x00000097 },
90 { 0x00c37000, 0x00000000 },
91 { 0x00c37100, 0x00000080 },
92 { 0x01270500, 0x00000400 },
93 { 0x01370500, 0x00000400 },
94 { 0x01371f00, 0x411111f0 },
95 { 0x01439000, 0x00000080 },
96 { 0x0143a000, 0x00000080 },
97 { 0x01470700, 0x00000000 },
98 { 0x01470500, 0x00000400 },
99 { 0x01470c00, 0x00000000 },
100 { 0x01470100, 0x00000000 },
101 { 0x01837000, 0x00000000 },
102 { 0x01870500, 0x00000400 },
103 { 0x02050000, 0x00000000 },
104 { 0x02139000, 0x00000080 },
105 { 0x0213a000, 0x00000080 },
106 { 0x02170100, 0x00000000 },
107 { 0x02170500, 0x00000400 },
108 { 0x02170700, 0x00000000 },
109 { 0x02270100, 0x00000000 },
110 { 0x02370100, 0x00000000 },
Bard Liao07cf7cba2014-06-20 14:41:13 +0800111 { 0x01870700, 0x00000020 },
112 { 0x00830000, 0x000000c3 },
113 { 0x00930000, 0x000000c3 },
114 { 0x01270700, 0x00000000 },
115};
116
117static bool rt286_volatile_register(struct device *dev, unsigned int reg)
118{
119 switch (reg) {
120 case 0 ... 0xff:
121 case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
122 case RT286_GET_HP_SENSE:
123 case RT286_GET_MIC1_SENSE:
124 case RT286_PROC_COEF:
125 return true;
126 default:
127 return false;
128 }
129
130
131}
132
133static bool rt286_readable_register(struct device *dev, unsigned int reg)
134{
135 switch (reg) {
136 case 0 ... 0xff:
137 case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
138 case RT286_GET_HP_SENSE:
139 case RT286_GET_MIC1_SENSE:
140 case RT286_SET_AUDIO_POWER:
141 case RT286_SET_HPO_POWER:
142 case RT286_SET_SPK_POWER:
143 case RT286_SET_DMIC1_POWER:
144 case RT286_SPK_MUX:
145 case RT286_HPO_MUX:
146 case RT286_ADC0_MUX:
147 case RT286_ADC1_MUX:
148 case RT286_SET_MIC1:
149 case RT286_SET_PIN_HPO:
150 case RT286_SET_PIN_SPK:
151 case RT286_SET_PIN_DMIC1:
152 case RT286_SPK_EAPD:
153 case RT286_SET_AMP_GAIN_HPO:
154 case RT286_SET_DMIC2_DEFAULT:
155 case RT286_DACL_GAIN:
156 case RT286_DACR_GAIN:
157 case RT286_ADCL_GAIN:
158 case RT286_ADCR_GAIN:
159 case RT286_MIC_GAIN:
160 case RT286_SPOL_GAIN:
161 case RT286_SPOR_GAIN:
162 case RT286_HPOL_GAIN:
163 case RT286_HPOR_GAIN:
164 case RT286_F_DAC_SWITCH:
165 case RT286_F_RECMIX_SWITCH:
166 case RT286_REC_MIC_SWITCH:
167 case RT286_REC_I2S_SWITCH:
168 case RT286_REC_LINE_SWITCH:
169 case RT286_REC_BEEP_SWITCH:
170 case RT286_DAC_FORMAT:
171 case RT286_ADC_FORMAT:
172 case RT286_COEF_INDEX:
173 case RT286_PROC_COEF:
174 case RT286_SET_AMP_GAIN_ADC_IN1:
175 case RT286_SET_AMP_GAIN_ADC_IN2:
176 case RT286_SET_POWER(RT286_DAC_OUT1):
177 case RT286_SET_POWER(RT286_DAC_OUT2):
178 case RT286_SET_POWER(RT286_ADC_IN1):
179 case RT286_SET_POWER(RT286_ADC_IN2):
180 case RT286_SET_POWER(RT286_DMIC2):
181 case RT286_SET_POWER(RT286_MIC1):
182 return true;
183 default:
184 return false;
185 }
186}
187
188static int rt286_hw_write(void *context, unsigned int reg, unsigned int value)
189{
190 struct i2c_client *client = context;
191 struct rt286_priv *rt286 = i2c_get_clientdata(client);
192 u8 data[4];
193 int ret, i;
194
Bard Liaof8c101b2014-11-06 10:00:00 +0800195 /* handle index registers */
Bard Liao07cf7cba2014-06-20 14:41:13 +0800196 if (reg <= 0xff) {
197 rt286_hw_write(client, RT286_COEF_INDEX, reg);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800198 for (i = 0; i < INDEX_CACHE_SIZE; i++) {
199 if (reg == rt286->index_cache[i].reg) {
200 rt286->index_cache[i].def = value;
201 break;
202 }
203
204 }
Bard Liao66d627d2014-09-26 11:06:40 +0800205 reg = RT286_PROC_COEF;
Bard Liao07cf7cba2014-06-20 14:41:13 +0800206 }
207
208 data[0] = (reg >> 24) & 0xff;
209 data[1] = (reg >> 16) & 0xff;
210 /*
211 * 4 bit VID: reg should be 0
212 * 12 bit VID: value should be 0
213 * So we use an OR operator to handle it rather than use if condition.
214 */
215 data[2] = ((reg >> 8) & 0xff) | ((value >> 8) & 0xff);
216 data[3] = value & 0xff;
217
218 ret = i2c_master_send(client, data, 4);
219
220 if (ret == 4)
221 return 0;
222 else
223 pr_err("ret=%d\n", ret);
224 if (ret < 0)
225 return ret;
226 else
227 return -EIO;
228}
229
230static int rt286_hw_read(void *context, unsigned int reg, unsigned int *value)
231{
232 struct i2c_client *client = context;
233 struct i2c_msg xfer[2];
234 int ret;
235 __be32 be_reg;
236 unsigned int index, vid, buf = 0x0;
237
Bard Liaof8c101b2014-11-06 10:00:00 +0800238 /* handle index registers */
Bard Liao07cf7cba2014-06-20 14:41:13 +0800239 if (reg <= 0xff) {
240 rt286_hw_write(client, RT286_COEF_INDEX, reg);
241 reg = RT286_PROC_COEF;
242 }
243
244 reg = reg | 0x80000;
245 vid = (reg >> 8) & 0xfff;
246
247 if (AC_VERB_GET_AMP_GAIN_MUTE == (vid & 0xf00)) {
248 index = (reg >> 8) & 0xf;
249 reg = (reg & ~0xf0f) | index;
250 }
251 be_reg = cpu_to_be32(reg);
252
253 /* Write register */
254 xfer[0].addr = client->addr;
255 xfer[0].flags = 0;
256 xfer[0].len = 4;
257 xfer[0].buf = (u8 *)&be_reg;
258
259 /* Read data */
260 xfer[1].addr = client->addr;
261 xfer[1].flags = I2C_M_RD;
262 xfer[1].len = 4;
263 xfer[1].buf = (u8 *)&buf;
264
265 ret = i2c_transfer(client->adapter, xfer, 2);
266 if (ret < 0)
267 return ret;
268 else if (ret != 2)
269 return -EIO;
270
271 *value = be32_to_cpu(buf);
272
273 return 0;
274}
275
Thierry Reding81f3dfe2014-10-02 09:27:03 +0200276#ifdef CONFIG_PM
Bard Liao07cf7cba2014-06-20 14:41:13 +0800277static void rt286_index_sync(struct snd_soc_codec *codec)
278{
279 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
280 int i;
281
282 for (i = 0; i < INDEX_CACHE_SIZE; i++) {
283 snd_soc_write(codec, rt286->index_cache[i].reg,
284 rt286->index_cache[i].def);
285 }
286}
Thierry Reding81f3dfe2014-10-02 09:27:03 +0200287#endif
Bard Liao07cf7cba2014-06-20 14:41:13 +0800288
289static int rt286_support_power_controls[] = {
290 RT286_DAC_OUT1,
291 RT286_DAC_OUT2,
292 RT286_ADC_IN1,
293 RT286_ADC_IN2,
294 RT286_MIC1,
295 RT286_DMIC1,
296 RT286_DMIC2,
297 RT286_SPK_OUT,
298 RT286_HP_OUT,
299};
300#define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls)
301
Bard Liao90f601e2014-07-29 13:50:57 +0800302static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic)
Bard Liao07cf7cba2014-06-20 14:41:13 +0800303{
Bard Liao07cf7cba2014-06-20 14:41:13 +0800304 unsigned int val, buf;
Bard Liao07cf7cba2014-06-20 14:41:13 +0800305
306 *hp = false;
307 *mic = false;
308
309 if (rt286->pdata.cbj_en) {
Bard Liao90f601e2014-07-29 13:50:57 +0800310 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800311 *hp = buf & 0x80000000;
312 if (*hp) {
313 /* power on HV,VERF */
Bard Liao90f601e2014-07-29 13:50:57 +0800314 regmap_update_bits(rt286->regmap,
Bard Liao6879db72014-10-31 14:52:16 +0800315 RT286_DC_GAIN, 0x200, 0x200);
316
317 snd_soc_dapm_force_enable_pin(&rt286->codec->dapm,
318 "HV");
319 snd_soc_dapm_force_enable_pin(&rt286->codec->dapm,
320 "VREF");
Bard Liao07cf7cba2014-06-20 14:41:13 +0800321 /* power LDO1 */
Bard Liao6879db72014-10-31 14:52:16 +0800322 snd_soc_dapm_force_enable_pin(&rt286->codec->dapm,
323 "LDO1");
324 snd_soc_dapm_sync(&rt286->codec->dapm);
325
Bard Liao90f601e2014-07-29 13:50:57 +0800326 regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24);
Bard Liao6879db72014-10-31 14:52:16 +0800327 msleep(50);
328
329 regmap_update_bits(rt286->regmap,
330 RT286_CBJ_CTRL1, 0xfcc0, 0xd400);
331 msleep(300);
Bard Liao90f601e2014-07-29 13:50:57 +0800332 regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800333
Bard Liao6879db72014-10-31 14:52:16 +0800334 if (0x0070 == (val & 0x0070)) {
335 *mic = true;
336 } else {
337 regmap_update_bits(rt286->regmap,
338 RT286_CBJ_CTRL1, 0xfcc0, 0xe400);
339 msleep(300);
Bard Liao90f601e2014-07-29 13:50:57 +0800340 regmap_read(rt286->regmap,
341 RT286_CBJ_CTRL2, &val);
Bard Liao6879db72014-10-31 14:52:16 +0800342 if (0x0070 == (val & 0x0070))
343 *mic = true;
344 else
345 *mic = false;
Bard Liao07cf7cba2014-06-20 14:41:13 +0800346 }
Bard Liao90f601e2014-07-29 13:50:57 +0800347 regmap_update_bits(rt286->regmap,
Bard Liao6879db72014-10-31 14:52:16 +0800348 RT286_DC_GAIN, 0x200, 0x0);
349
Bard Liao07cf7cba2014-06-20 14:41:13 +0800350 } else {
Bard Liao07cf7cba2014-06-20 14:41:13 +0800351 *mic = false;
Bard Liao6879db72014-10-31 14:52:16 +0800352 regmap_write(rt286->regmap, RT286_SET_MIC1, 0x20);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800353 }
354 } else {
Bard Liao90f601e2014-07-29 13:50:57 +0800355 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800356 *hp = buf & 0x80000000;
Bard Liao90f601e2014-07-29 13:50:57 +0800357 regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800358 *mic = buf & 0x80000000;
359 }
360
Bard Liao6879db72014-10-31 14:52:16 +0800361 snd_soc_dapm_disable_pin(&rt286->codec->dapm, "HV");
362 snd_soc_dapm_disable_pin(&rt286->codec->dapm, "VREF");
363 if (!*hp)
364 snd_soc_dapm_disable_pin(&rt286->codec->dapm, "LDO1");
365 snd_soc_dapm_sync(&rt286->codec->dapm);
366
Bard Liao07cf7cba2014-06-20 14:41:13 +0800367 return 0;
368}
369
370static void rt286_jack_detect_work(struct work_struct *work)
371{
372 struct rt286_priv *rt286 =
373 container_of(work, struct rt286_priv, jack_detect_work.work);
374 int status = 0;
375 bool hp = false;
376 bool mic = false;
377
Bard Liao90f601e2014-07-29 13:50:57 +0800378 rt286_jack_detect(rt286, &hp, &mic);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800379
380 if (hp == true)
381 status |= SND_JACK_HEADPHONE;
382
383 if (mic == true)
384 status |= SND_JACK_MICROPHONE;
385
386 snd_soc_jack_report(rt286->jack, status,
387 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
388}
389
390int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
391{
392 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
393
394 rt286->jack = jack;
395
396 /* Send an initial empty report */
397 snd_soc_jack_report(rt286->jack, 0,
398 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
399
400 return 0;
401}
402EXPORT_SYMBOL_GPL(rt286_mic_detect);
403
Bard Liao6879db72014-10-31 14:52:16 +0800404static int is_mclk_mode(struct snd_soc_dapm_widget *source,
405 struct snd_soc_dapm_widget *sink)
406{
407 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(source->codec);
408
409 if (rt286->clk_id == RT286_SCLK_S_MCLK)
410 return 1;
411 else
412 return 0;
413}
414
Bard Liao07cf7cba2014-06-20 14:41:13 +0800415static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
416static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
417
418static const struct snd_kcontrol_new rt286_snd_controls[] = {
419 SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN,
420 RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
Bard Liao54d96a42015-01-23 14:51:09 +0800421 SOC_DOUBLE_R("ADC0 Capture Switch", RT286_ADCL_GAIN,
422 RT286_ADCR_GAIN, 7, 1, 1),
Bard Liao07cf7cba2014-06-20 14:41:13 +0800423 SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN,
424 RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
425 SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN,
426 0, 0x3, 0, mic_vol_tlv),
427 SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN,
428 RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1),
429};
430
431/* Digital Mixer */
432static const struct snd_kcontrol_new rt286_front_mix[] = {
433 SOC_DAPM_SINGLE("DAC Switch", RT286_F_DAC_SWITCH,
434 RT286_MUTE_SFT, 1, 1),
435 SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH,
436 RT286_MUTE_SFT, 1, 1),
437};
438
439/* Analog Input Mixer */
440static const struct snd_kcontrol_new rt286_rec_mix[] = {
441 SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH,
442 RT286_MUTE_SFT, 1, 1),
443 SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH,
444 RT286_MUTE_SFT, 1, 1),
445 SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH,
446 RT286_MUTE_SFT, 1, 1),
447 SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH,
448 RT286_MUTE_SFT, 1, 1),
449};
450
451static const struct snd_kcontrol_new spo_enable_control =
452 SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK,
453 RT286_SET_PIN_SFT, 1, 0);
454
455static const struct snd_kcontrol_new hpol_enable_control =
456 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN,
457 RT286_MUTE_SFT, 1, 1);
458
459static const struct snd_kcontrol_new hpor_enable_control =
460 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN,
461 RT286_MUTE_SFT, 1, 1);
462
463/* ADC0 source */
464static const char * const rt286_adc_src[] = {
465 "Mic", "RECMIX", "Dmic"
466};
467
468static const int rt286_adc_values[] = {
469 0, 4, 5,
470};
471
472static SOC_VALUE_ENUM_SINGLE_DECL(
473 rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT,
474 RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
475
476static const struct snd_kcontrol_new rt286_adc0_mux =
477 SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum);
478
479static SOC_VALUE_ENUM_SINGLE_DECL(
480 rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT,
481 RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
482
483static const struct snd_kcontrol_new rt286_adc1_mux =
484 SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum);
485
486static const char * const rt286_dac_src[] = {
487 "Front", "Surround"
488};
489/* HP-OUT source */
490static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX,
491 0, rt286_dac_src);
492
493static const struct snd_kcontrol_new rt286_hpo_mux =
494SOC_DAPM_ENUM("HPO source", rt286_hpo_enum);
495
496/* SPK-OUT source */
497static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX,
498 0, rt286_dac_src);
499
500static const struct snd_kcontrol_new rt286_spo_mux =
501SOC_DAPM_ENUM("SPO source", rt286_spo_enum);
502
503static int rt286_spk_event(struct snd_soc_dapm_widget *w,
504 struct snd_kcontrol *kcontrol, int event)
505{
506 struct snd_soc_codec *codec = w->codec;
507
508 switch (event) {
509 case SND_SOC_DAPM_POST_PMU:
510 snd_soc_write(codec,
511 RT286_SPK_EAPD, RT286_SET_EAPD_HIGH);
512 break;
513 case SND_SOC_DAPM_PRE_PMD:
514 snd_soc_write(codec,
515 RT286_SPK_EAPD, RT286_SET_EAPD_LOW);
516 break;
517
518 default:
519 return 0;
520 }
521
522 return 0;
523}
524
525static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w,
526 struct snd_kcontrol *kcontrol, int event)
527{
528 struct snd_soc_codec *codec = w->codec;
529
530 switch (event) {
531 case SND_SOC_DAPM_POST_PMU:
532 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0x20);
533 break;
534 case SND_SOC_DAPM_PRE_PMD:
535 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0);
536 break;
537 default:
538 return 0;
539 }
540
541 return 0;
542}
543
Bard Liao6879db72014-10-31 14:52:16 +0800544static int rt286_vref_event(struct snd_soc_dapm_widget *w,
545 struct snd_kcontrol *kcontrol, int event)
546{
547 struct snd_soc_codec *codec = w->codec;
548
549 switch (event) {
550 case SND_SOC_DAPM_PRE_PMU:
551 snd_soc_update_bits(codec,
552 RT286_CBJ_CTRL1, 0x0400, 0x0000);
553 mdelay(50);
554 break;
555 default:
556 return 0;
557 }
558
559 return 0;
560}
561
562static int rt286_ldo2_event(struct snd_soc_dapm_widget *w,
563 struct snd_kcontrol *kcontrol, int event)
564{
565 struct snd_soc_codec *codec = w->codec;
566
567 switch (event) {
568 case SND_SOC_DAPM_POST_PMU:
569 snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x08);
570 break;
571 case SND_SOC_DAPM_PRE_PMD:
572 snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x30);
573 break;
574 default:
575 return 0;
576 }
577
578 return 0;
579}
580
581static int rt286_mic1_event(struct snd_soc_dapm_widget *w,
582 struct snd_kcontrol *kcontrol, int event)
583{
584 struct snd_soc_codec *codec = w->codec;
585
586 switch (event) {
587 case SND_SOC_DAPM_PRE_PMU:
588 snd_soc_update_bits(codec,
589 RT286_A_BIAS_CTRL3, 0xc000, 0x8000);
590 snd_soc_update_bits(codec,
591 RT286_A_BIAS_CTRL2, 0xc000, 0x8000);
592 break;
593 case SND_SOC_DAPM_POST_PMD:
594 snd_soc_update_bits(codec,
595 RT286_A_BIAS_CTRL3, 0xc000, 0x0000);
596 snd_soc_update_bits(codec,
597 RT286_A_BIAS_CTRL2, 0xc000, 0x0000);
598 break;
599 default:
600 return 0;
601 }
602
603 return 0;
604}
605
Bard Liao07cf7cba2014-06-20 14:41:13 +0800606static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = {
Bard Liao6879db72014-10-31 14:52:16 +0800607 SND_SOC_DAPM_SUPPLY_S("HV", 1, RT286_POWER_CTRL1,
608 12, 1, NULL, 0),
609 SND_SOC_DAPM_SUPPLY("VREF", RT286_POWER_CTRL1,
610 0, 1, rt286_vref_event, SND_SOC_DAPM_PRE_PMU),
611 SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT286_POWER_CTRL2,
612 2, 0, NULL, 0),
613 SND_SOC_DAPM_SUPPLY_S("LDO2", 2, RT286_POWER_CTRL1,
614 13, 1, rt286_ldo2_event, SND_SOC_DAPM_PRE_PMD |
615 SND_SOC_DAPM_POST_PMU),
616 SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1,
617 5, 0, NULL, 0),
618 SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
619 0, 0, rt286_mic1_event, SND_SOC_DAPM_PRE_PMU |
620 SND_SOC_DAPM_POST_PMD),
621
Bard Liao07cf7cba2014-06-20 14:41:13 +0800622 /* Input Lines */
623 SND_SOC_DAPM_INPUT("DMIC1 Pin"),
624 SND_SOC_DAPM_INPUT("DMIC2 Pin"),
625 SND_SOC_DAPM_INPUT("MIC1"),
626 SND_SOC_DAPM_INPUT("LINE1"),
627 SND_SOC_DAPM_INPUT("Beep"),
628
629 /* DMIC */
630 SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1,
631 NULL, 0, rt286_set_dmic1_event,
632 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
633 SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1,
634 NULL, 0),
635 SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
636 0, 0, NULL, 0),
637
638 /* REC Mixer */
639 SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
640 rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)),
641
642 /* ADCs */
643 SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
644 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
645
646 /* ADC Mux */
Bard Liao54d96a42015-01-23 14:51:09 +0800647 SND_SOC_DAPM_MUX("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1,
648 &rt286_adc0_mux),
649 SND_SOC_DAPM_MUX("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1,
650 &rt286_adc1_mux),
Bard Liao07cf7cba2014-06-20 14:41:13 +0800651
652 /* Audio Interface */
653 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
654 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
655 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
656 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
657
658 /* Output Side */
659 /* DACs */
660 SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
661 SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
662
663 /* Output Mux */
664 SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux),
665 SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux),
666
667 SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO,
668 RT286_SET_PIN_SFT, 0, NULL, 0),
669
670 /* Output Mixer */
671 SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1,
672 rt286_front_mix, ARRAY_SIZE(rt286_front_mix)),
673 SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1,
674 NULL, 0),
675
676 /* Output Pga */
677 SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
678 &spo_enable_control, rt286_spk_event,
679 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
680 SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
681 &hpol_enable_control),
682 SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
683 &hpor_enable_control),
684
685 /* Output Lines */
686 SND_SOC_DAPM_OUTPUT("SPOL"),
687 SND_SOC_DAPM_OUTPUT("SPOR"),
688 SND_SOC_DAPM_OUTPUT("HPO Pin"),
689 SND_SOC_DAPM_OUTPUT("SPDIF"),
690};
691
692static const struct snd_soc_dapm_route rt286_dapm_routes[] = {
Bard Liao6879db72014-10-31 14:52:16 +0800693 {"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
694 {"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
695 {"Front", NULL, "MCLK MODE", is_mclk_mode},
696 {"Surround", NULL, "MCLK MODE", is_mclk_mode},
697
698 {"HP Power", NULL, "LDO1"},
699 {"HP Power", NULL, "LDO2"},
700
701 {"MIC1", NULL, "LDO1"},
702 {"MIC1", NULL, "LDO2"},
703 {"MIC1", NULL, "HV"},
704 {"MIC1", NULL, "VREF"},
705 {"MIC1", NULL, "MIC1 Input Buffer"},
706
707 {"SPO", NULL, "LDO1"},
708 {"SPO", NULL, "LDO2"},
709 {"SPO", NULL, "HV"},
710 {"SPO", NULL, "VREF"},
711
Bard Liao07cf7cba2014-06-20 14:41:13 +0800712 {"DMIC1", NULL, "DMIC1 Pin"},
713 {"DMIC2", NULL, "DMIC2 Pin"},
714 {"DMIC1", NULL, "DMIC Receiver"},
715 {"DMIC2", NULL, "DMIC Receiver"},
716
717 {"RECMIX", "Beep Switch", "Beep"},
718 {"RECMIX", "Line1 Switch", "LINE1"},
719 {"RECMIX", "Mic1 Switch", "MIC1"},
720
721 {"ADC 0 Mux", "Dmic", "DMIC1"},
722 {"ADC 0 Mux", "RECMIX", "RECMIX"},
723 {"ADC 0 Mux", "Mic", "MIC1"},
724 {"ADC 1 Mux", "Dmic", "DMIC2"},
725 {"ADC 1 Mux", "RECMIX", "RECMIX"},
726 {"ADC 1 Mux", "Mic", "MIC1"},
727
728 {"ADC 0", NULL, "ADC 0 Mux"},
729 {"ADC 1", NULL, "ADC 1 Mux"},
730
731 {"AIF1TX", NULL, "ADC 0"},
732 {"AIF2TX", NULL, "ADC 1"},
733
734 {"DAC 0", NULL, "AIF1RX"},
735 {"DAC 1", NULL, "AIF2RX"},
736
737 {"Front", "DAC Switch", "DAC 0"},
738 {"Front", "RECMIX Switch", "RECMIX"},
739
740 {"Surround", NULL, "DAC 1"},
741
742 {"SPK Mux", "Front", "Front"},
743 {"SPK Mux", "Surround", "Surround"},
744
745 {"HPO Mux", "Front", "Front"},
746 {"HPO Mux", "Surround", "Surround"},
747
748 {"SPO", "Switch", "SPK Mux"},
749 {"HPO L", "Switch", "HPO Mux"},
750 {"HPO R", "Switch", "HPO Mux"},
751 {"HPO L", NULL, "HP Power"},
752 {"HPO R", NULL, "HP Power"},
753
754 {"SPOL", NULL, "SPO"},
755 {"SPOR", NULL, "SPO"},
756 {"HPO Pin", NULL, "HPO L"},
757 {"HPO Pin", NULL, "HPO R"},
758};
759
760static int rt286_hw_params(struct snd_pcm_substream *substream,
761 struct snd_pcm_hw_params *params,
762 struct snd_soc_dai *dai)
763{
764 struct snd_soc_codec *codec = dai->codec;
765 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
766 unsigned int val = 0;
767 int d_len_code;
768
769 switch (params_rate(params)) {
770 /* bit 14 0:48K 1:44.1K */
771 case 44100:
772 val |= 0x4000;
773 break;
774 case 48000:
775 break;
776 default:
777 dev_err(codec->dev, "Unsupported sample rate %d\n",
778 params_rate(params));
779 return -EINVAL;
780 }
781 switch (rt286->sys_clk) {
782 case 12288000:
783 case 24576000:
784 if (params_rate(params) != 48000) {
785 dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
786 params_rate(params), rt286->sys_clk);
787 return -EINVAL;
788 }
789 break;
790 case 11289600:
791 case 22579200:
792 if (params_rate(params) != 44100) {
793 dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
794 params_rate(params), rt286->sys_clk);
795 return -EINVAL;
796 }
797 break;
798 }
799
800 if (params_channels(params) <= 16) {
801 /* bit 3:0 Number of Channel */
802 val |= (params_channels(params) - 1);
803 } else {
804 dev_err(codec->dev, "Unsupported channels %d\n",
805 params_channels(params));
806 return -EINVAL;
807 }
808
809 d_len_code = 0;
810 switch (params_width(params)) {
811 /* bit 6:4 Bits per Sample */
812 case 16:
813 d_len_code = 0;
814 val |= (0x1 << 4);
815 break;
816 case 32:
817 d_len_code = 2;
818 val |= (0x4 << 4);
819 break;
820 case 20:
821 d_len_code = 1;
822 val |= (0x2 << 4);
823 break;
824 case 24:
825 d_len_code = 2;
826 val |= (0x3 << 4);
827 break;
828 case 8:
829 d_len_code = 3;
830 break;
831 default:
832 return -EINVAL;
833 }
834
835 snd_soc_update_bits(codec,
836 RT286_I2S_CTRL1, 0x0018, d_len_code << 3);
837 dev_dbg(codec->dev, "format val = 0x%x\n", val);
838
Bard Liao45437fa2015-01-15 10:49:25 +0800839 snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x407f, val);
840 snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x407f, val);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800841
842 return 0;
843}
844
845static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
846{
847 struct snd_soc_codec *codec = dai->codec;
848
849 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
850 case SND_SOC_DAIFMT_CBM_CFM:
851 snd_soc_update_bits(codec,
852 RT286_I2S_CTRL1, 0x800, 0x800);
853 break;
854 case SND_SOC_DAIFMT_CBS_CFS:
855 snd_soc_update_bits(codec,
856 RT286_I2S_CTRL1, 0x800, 0x0);
857 break;
858 default:
859 return -EINVAL;
860 }
861
862 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
863 case SND_SOC_DAIFMT_I2S:
864 snd_soc_update_bits(codec,
865 RT286_I2S_CTRL1, 0x300, 0x0);
866 break;
867 case SND_SOC_DAIFMT_LEFT_J:
868 snd_soc_update_bits(codec,
869 RT286_I2S_CTRL1, 0x300, 0x1 << 8);
870 break;
871 case SND_SOC_DAIFMT_DSP_A:
872 snd_soc_update_bits(codec,
873 RT286_I2S_CTRL1, 0x300, 0x2 << 8);
874 break;
875 case SND_SOC_DAIFMT_DSP_B:
876 snd_soc_update_bits(codec,
877 RT286_I2S_CTRL1, 0x300, 0x3 << 8);
878 break;
879 default:
880 return -EINVAL;
881 }
882 /* bit 15 Stream Type 0:PCM 1:Non-PCM */
883 snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x8000, 0);
884 snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x8000, 0);
885
886 return 0;
887}
888
889static int rt286_set_dai_sysclk(struct snd_soc_dai *dai,
890 int clk_id, unsigned int freq, int dir)
891{
892 struct snd_soc_codec *codec = dai->codec;
893 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
894
895 dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq);
896
897 if (RT286_SCLK_S_MCLK == clk_id) {
898 snd_soc_update_bits(codec,
899 RT286_I2S_CTRL2, 0x0100, 0x0);
900 snd_soc_update_bits(codec,
901 RT286_PLL_CTRL1, 0x20, 0x20);
902 } else {
903 snd_soc_update_bits(codec,
904 RT286_I2S_CTRL2, 0x0100, 0x0100);
905 snd_soc_update_bits(codec,
906 RT286_PLL_CTRL, 0x4, 0x4);
907 snd_soc_update_bits(codec,
908 RT286_PLL_CTRL1, 0x20, 0x0);
909 }
910
911 switch (freq) {
912 case 19200000:
913 if (RT286_SCLK_S_MCLK == clk_id) {
914 dev_err(codec->dev, "Should not use MCLK\n");
915 return -EINVAL;
916 }
917 snd_soc_update_bits(codec,
918 RT286_I2S_CTRL2, 0x40, 0x40);
919 break;
920 case 24000000:
921 if (RT286_SCLK_S_MCLK == clk_id) {
922 dev_err(codec->dev, "Should not use MCLK\n");
923 return -EINVAL;
924 }
925 snd_soc_update_bits(codec,
926 RT286_I2S_CTRL2, 0x40, 0x0);
927 break;
928 case 12288000:
929 case 11289600:
930 snd_soc_update_bits(codec,
931 RT286_I2S_CTRL2, 0x8, 0x0);
932 snd_soc_update_bits(codec,
933 RT286_CLK_DIV, 0xfc1e, 0x0004);
934 break;
935 case 24576000:
936 case 22579200:
937 snd_soc_update_bits(codec,
938 RT286_I2S_CTRL2, 0x8, 0x8);
939 snd_soc_update_bits(codec,
940 RT286_CLK_DIV, 0xfc1e, 0x5406);
941 break;
942 default:
943 dev_err(codec->dev, "Unsupported system clock\n");
944 return -EINVAL;
945 }
946
947 rt286->sys_clk = freq;
Bard Liao6879db72014-10-31 14:52:16 +0800948 rt286->clk_id = clk_id;
Bard Liao07cf7cba2014-06-20 14:41:13 +0800949
950 return 0;
951}
952
953static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
954{
955 struct snd_soc_codec *codec = dai->codec;
956
957 dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
958 if (50 == ratio)
959 snd_soc_update_bits(codec,
960 RT286_I2S_CTRL1, 0x1000, 0x1000);
961 else
962 snd_soc_update_bits(codec,
963 RT286_I2S_CTRL1, 0x1000, 0x0);
964
965
966 return 0;
967}
968
969static int rt286_set_bias_level(struct snd_soc_codec *codec,
970 enum snd_soc_bias_level level)
971{
972 switch (level) {
973 case SND_SOC_BIAS_PREPARE:
Bard Liaobc6c4e42014-07-07 19:15:30 +0800974 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
Bard Liao07cf7cba2014-06-20 14:41:13 +0800975 snd_soc_write(codec,
976 RT286_SET_AUDIO_POWER, AC_PWRST_D0);
Bard Liaobc6c4e42014-07-07 19:15:30 +0800977 snd_soc_update_bits(codec,
978 RT286_DC_GAIN, 0x200, 0x200);
979 }
980 break;
981
982 case SND_SOC_BIAS_ON:
983 mdelay(10);
Bard Liao6879db72014-10-31 14:52:16 +0800984 snd_soc_update_bits(codec,
985 RT286_CBJ_CTRL1, 0x0400, 0x0400);
986 snd_soc_update_bits(codec,
987 RT286_DC_GAIN, 0x200, 0x0);
988
Bard Liao07cf7cba2014-06-20 14:41:13 +0800989 break;
990
991 case SND_SOC_BIAS_STANDBY:
992 snd_soc_write(codec,
993 RT286_SET_AUDIO_POWER, AC_PWRST_D3);
Bard Liaobc6c4e42014-07-07 19:15:30 +0800994 snd_soc_update_bits(codec,
Bard Liao6879db72014-10-31 14:52:16 +0800995 RT286_CBJ_CTRL1, 0x0400, 0x0000);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800996 break;
997
998 default:
999 break;
1000 }
1001 codec->dapm.bias_level = level;
1002
1003 return 0;
1004}
1005
1006static irqreturn_t rt286_irq(int irq, void *data)
1007{
1008 struct rt286_priv *rt286 = data;
1009 bool hp = false;
1010 bool mic = false;
1011 int status = 0;
1012
Bard Liao90f601e2014-07-29 13:50:57 +08001013 rt286_jack_detect(rt286, &hp, &mic);
Bard Liao07cf7cba2014-06-20 14:41:13 +08001014
1015 /* Clear IRQ */
Bard Liao90f601e2014-07-29 13:50:57 +08001016 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1);
Bard Liao07cf7cba2014-06-20 14:41:13 +08001017
1018 if (hp == true)
1019 status |= SND_JACK_HEADPHONE;
1020
1021 if (mic == true)
1022 status |= SND_JACK_MICROPHONE;
1023
1024 snd_soc_jack_report(rt286->jack, status,
1025 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
1026
1027 pm_wakeup_event(&rt286->i2c->dev, 300);
1028
1029 return IRQ_HANDLED;
1030}
1031
1032static int rt286_probe(struct snd_soc_codec *codec)
1033{
1034 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
Bard Liao07cf7cba2014-06-20 14:41:13 +08001035
Bard Liao6879db72014-10-31 14:52:16 +08001036 rt286->codec = codec;
Bard Liao07cf7cba2014-06-20 14:41:13 +08001037 codec->dapm.bias_level = SND_SOC_BIAS_OFF;
Bard Liao90f601e2014-07-29 13:50:57 +08001038
1039 if (rt286->i2c->irq) {
1040 regmap_update_bits(rt286->regmap,
1041 RT286_IRQ_CTRL, 0x2, 0x2);
1042
1043 INIT_DELAYED_WORK(&rt286->jack_detect_work,
1044 rt286_jack_detect_work);
1045 schedule_delayed_work(&rt286->jack_detect_work,
1046 msecs_to_jiffies(1250));
1047 }
Bard Liao07cf7cba2014-06-20 14:41:13 +08001048
Bard Liao07cf7cba2014-06-20 14:41:13 +08001049 return 0;
1050}
1051
1052static int rt286_remove(struct snd_soc_codec *codec)
1053{
1054 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1055
1056 cancel_delayed_work_sync(&rt286->jack_detect_work);
1057
1058 return 0;
1059}
1060
1061#ifdef CONFIG_PM
1062static int rt286_suspend(struct snd_soc_codec *codec)
1063{
1064 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1065
1066 regcache_cache_only(rt286->regmap, true);
1067 regcache_mark_dirty(rt286->regmap);
1068
1069 return 0;
1070}
1071
1072static int rt286_resume(struct snd_soc_codec *codec)
1073{
1074 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1075
1076 regcache_cache_only(rt286->regmap, false);
1077 rt286_index_sync(codec);
1078 regcache_sync(rt286->regmap);
1079
1080 return 0;
1081}
1082#else
1083#define rt286_suspend NULL
1084#define rt286_resume NULL
1085#endif
1086
1087#define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1088#define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1089 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1090
1091static const struct snd_soc_dai_ops rt286_aif_dai_ops = {
1092 .hw_params = rt286_hw_params,
1093 .set_fmt = rt286_set_dai_fmt,
1094 .set_sysclk = rt286_set_dai_sysclk,
1095 .set_bclk_ratio = rt286_set_bclk_ratio,
1096};
1097
1098static struct snd_soc_dai_driver rt286_dai[] = {
1099 {
1100 .name = "rt286-aif1",
1101 .id = RT286_AIF1,
1102 .playback = {
1103 .stream_name = "AIF1 Playback",
1104 .channels_min = 1,
1105 .channels_max = 2,
1106 .rates = RT286_STEREO_RATES,
1107 .formats = RT286_FORMATS,
1108 },
1109 .capture = {
1110 .stream_name = "AIF1 Capture",
1111 .channels_min = 1,
1112 .channels_max = 2,
1113 .rates = RT286_STEREO_RATES,
1114 .formats = RT286_FORMATS,
1115 },
1116 .ops = &rt286_aif_dai_ops,
1117 .symmetric_rates = 1,
1118 },
1119 {
1120 .name = "rt286-aif2",
1121 .id = RT286_AIF2,
1122 .playback = {
1123 .stream_name = "AIF2 Playback",
1124 .channels_min = 1,
1125 .channels_max = 2,
1126 .rates = RT286_STEREO_RATES,
1127 .formats = RT286_FORMATS,
1128 },
1129 .capture = {
1130 .stream_name = "AIF2 Capture",
1131 .channels_min = 1,
1132 .channels_max = 2,
1133 .rates = RT286_STEREO_RATES,
1134 .formats = RT286_FORMATS,
1135 },
1136 .ops = &rt286_aif_dai_ops,
1137 .symmetric_rates = 1,
1138 },
1139
1140};
1141
1142static struct snd_soc_codec_driver soc_codec_dev_rt286 = {
1143 .probe = rt286_probe,
1144 .remove = rt286_remove,
1145 .suspend = rt286_suspend,
1146 .resume = rt286_resume,
1147 .set_bias_level = rt286_set_bias_level,
1148 .idle_bias_off = true,
1149 .controls = rt286_snd_controls,
1150 .num_controls = ARRAY_SIZE(rt286_snd_controls),
1151 .dapm_widgets = rt286_dapm_widgets,
1152 .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets),
1153 .dapm_routes = rt286_dapm_routes,
1154 .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes),
1155};
1156
1157static const struct regmap_config rt286_regmap = {
1158 .reg_bits = 32,
1159 .val_bits = 32,
1160 .max_register = 0x02370100,
1161 .volatile_reg = rt286_volatile_register,
1162 .readable_reg = rt286_readable_register,
1163 .reg_write = rt286_hw_write,
1164 .reg_read = rt286_hw_read,
1165 .cache_type = REGCACHE_RBTREE,
1166 .reg_defaults = rt286_reg,
1167 .num_reg_defaults = ARRAY_SIZE(rt286_reg),
1168};
1169
1170static const struct i2c_device_id rt286_i2c_id[] = {
1171 {"rt286", 0},
Bard Liao3ab888d2015-02-09 14:19:45 +08001172 {"rt288", 0},
Bard Liao07cf7cba2014-06-20 14:41:13 +08001173 {}
1174};
1175MODULE_DEVICE_TABLE(i2c, rt286_i2c_id);
1176
1177static const struct acpi_device_id rt286_acpi_match[] = {
1178 { "INT343A", 0 },
1179 {},
1180};
1181MODULE_DEVICE_TABLE(acpi, rt286_acpi_match);
1182
Sudip Mukherjeea5a267c2014-11-18 17:42:54 +05301183static struct dmi_system_id force_combo_jack_table[] = {
Bard Liao6c67cde2014-11-06 09:59:59 +08001184 {
1185 .ident = "Intel Wilson Beach",
1186 .matches = {
1187 DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS")
1188 }
1189 },
1190 { }
1191};
1192
Bard Liao2cc3f232015-02-05 16:40:34 +08001193static struct dmi_system_id dmi_dell_dino[] = {
1194 {
1195 .ident = "Dell Dino",
1196 .matches = {
1197 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1198 DMI_MATCH(DMI_BOARD_NAME, "0144P8")
1199 }
1200 },
1201 { }
1202};
1203
Bard Liao07cf7cba2014-06-20 14:41:13 +08001204static int rt286_i2c_probe(struct i2c_client *i2c,
1205 const struct i2c_device_id *id)
1206{
1207 struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev);
1208 struct rt286_priv *rt286;
Bard Liao61a414c2014-07-07 16:48:38 +08001209 int i, ret;
Bard Liao07cf7cba2014-06-20 14:41:13 +08001210
1211 rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286),
1212 GFP_KERNEL);
1213 if (NULL == rt286)
1214 return -ENOMEM;
1215
1216 rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap);
1217 if (IS_ERR(rt286->regmap)) {
1218 ret = PTR_ERR(rt286->regmap);
1219 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1220 ret);
1221 return ret;
1222 }
1223
Bard Liao4b21768a2014-07-07 16:48:37 +08001224 regmap_read(rt286->regmap,
1225 RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &ret);
Bard Liao3ab888d2015-02-09 14:19:45 +08001226 if (ret != RT286_VENDOR_ID && ret != RT288_VENDOR_ID) {
Bard Liao4b21768a2014-07-07 16:48:37 +08001227 dev_err(&i2c->dev,
1228 "Device with ID register %x is not rt286\n", ret);
1229 return -ENODEV;
1230 }
1231
Bard Liao07cf7cba2014-06-20 14:41:13 +08001232 rt286->index_cache = rt286_index_def;
1233 rt286->i2c = i2c;
1234 i2c_set_clientdata(i2c, rt286);
1235
1236 if (pdata)
1237 rt286->pdata = *pdata;
1238
Bard Liao2cc3f232015-02-05 16:40:34 +08001239 if (dmi_check_system(force_combo_jack_table) ||
1240 dmi_check_system(dmi_dell_dino))
Bard Liao6c67cde2014-11-06 09:59:59 +08001241 rt286->pdata.cbj_en = true;
1242
Bard Liao61a414c2014-07-07 16:48:38 +08001243 regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3);
1244
1245 for (i = 0; i < RT286_POWER_REG_LEN; i++)
1246 regmap_write(rt286->regmap,
1247 RT286_SET_POWER(rt286_support_power_controls[i]),
1248 AC_PWRST_D1);
1249
1250 if (!rt286->pdata.cbj_en) {
1251 regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000);
1252 regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816);
Bard Liao61a414c2014-07-07 16:48:38 +08001253 regmap_update_bits(rt286->regmap,
1254 RT286_CBJ_CTRL1, 0xf000, 0xb000);
1255 } else {
1256 regmap_update_bits(rt286->regmap,
1257 RT286_CBJ_CTRL1, 0xf000, 0x5000);
1258 }
1259
1260 mdelay(10);
1261
1262 if (!rt286->pdata.gpio2_en)
1263 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x4000);
1264 else
1265 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0);
1266
1267 mdelay(10);
1268
Bard Liao6879db72014-10-31 14:52:16 +08001269 regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000);
Bard Liaof8c101b2014-11-06 10:00:00 +08001270 /* Power down LDO, VREF */
Bard Liao6879db72014-10-31 14:52:16 +08001271 regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0xc, 0x0);
1272 regmap_update_bits(rt286->regmap, RT286_POWER_CTRL1, 0x1001, 0x1001);
Bard Liao61a414c2014-07-07 16:48:38 +08001273
Bard Liaof8c101b2014-11-06 10:00:00 +08001274 /* Set depop parameter */
Bard Liaobc6c4e42014-07-07 19:15:30 +08001275 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a);
1276 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737);
1277 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
1278
Bard Liao2cc3f232015-02-05 16:40:34 +08001279 if (dmi_check_system(dmi_dell_dino)) {
1280 regmap_update_bits(rt286->regmap,
1281 RT286_SET_GPIO_MASK, 0x40, 0x40);
1282 regmap_update_bits(rt286->regmap,
1283 RT286_SET_GPIO_DIRECTION, 0x40, 0x40);
1284 regmap_update_bits(rt286->regmap,
1285 RT286_SET_GPIO_DATA, 0x40, 0x40);
1286 regmap_update_bits(rt286->regmap,
1287 RT286_GPIO_CTRL, 0xc, 0x8);
1288 }
1289
Bard Liao61a414c2014-07-07 16:48:38 +08001290 if (rt286->i2c->irq) {
Bard Liao61a414c2014-07-07 16:48:38 +08001291 ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq,
1292 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286);
1293 if (ret != 0) {
1294 dev_err(&i2c->dev,
1295 "Failed to reguest IRQ: %d\n", ret);
1296 return ret;
1297 }
1298 }
1299
Bard Liao07cf7cba2014-06-20 14:41:13 +08001300 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt286,
1301 rt286_dai, ARRAY_SIZE(rt286_dai));
1302
1303 return ret;
1304}
1305
1306static int rt286_i2c_remove(struct i2c_client *i2c)
1307{
1308 struct rt286_priv *rt286 = i2c_get_clientdata(i2c);
1309
1310 if (i2c->irq)
1311 free_irq(i2c->irq, rt286);
1312 snd_soc_unregister_codec(&i2c->dev);
1313
1314 return 0;
1315}
1316
1317
Bard Liao23c4fd52014-07-14 10:18:04 +08001318static struct i2c_driver rt286_i2c_driver = {
Bard Liao07cf7cba2014-06-20 14:41:13 +08001319 .driver = {
1320 .name = "rt286",
1321 .owner = THIS_MODULE,
1322 .acpi_match_table = ACPI_PTR(rt286_acpi_match),
1323 },
1324 .probe = rt286_i2c_probe,
1325 .remove = rt286_i2c_remove,
1326 .id_table = rt286_i2c_id,
1327};
1328
1329module_i2c_driver(rt286_i2c_driver);
1330
1331MODULE_DESCRIPTION("ASoC RT286 driver");
1332MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1333MODULE_LICENSE("GPL");