Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-pxa/gpio.c |
| 3 | * |
| 4 | * Generic PXA GPIO handling |
| 5 | * |
| 6 | * Author: Nicolas Pitre |
| 7 | * Created: Jun 15, 2001 |
| 8 | * Copyright: MontaVista Software Inc. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
| 14 | |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/module.h> |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 17 | #include <linux/irq.h> |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 18 | #include <linux/sysdev.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 19 | #include <linux/io.h> |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 20 | |
Eric Miao | da065a0 | 2009-01-06 18:29:01 +0800 | [diff] [blame] | 21 | #include <mach/gpio.h> |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 22 | |
Eric Miao | 3b8e285 | 2009-01-07 11:30:49 +0800 | [diff] [blame^] | 23 | int pxa_last_gpio; |
| 24 | |
Eric Miao | da065a0 | 2009-01-06 18:29:01 +0800 | [diff] [blame] | 25 | #define GPIO0_BASE (GPIO_REGS_VIRT + 0x0000) |
| 26 | #define GPIO1_BASE (GPIO_REGS_VIRT + 0x0004) |
| 27 | #define GPIO2_BASE (GPIO_REGS_VIRT + 0x0008) |
| 28 | #define GPIO3_BASE (GPIO_REGS_VIRT + 0x0100) |
Eric Miao | f1647e4 | 2008-11-28 14:54:39 +0800 | [diff] [blame] | 29 | |
| 30 | #define GPLR_OFFSET 0x00 |
| 31 | #define GPDR_OFFSET 0x0C |
| 32 | #define GPSR_OFFSET 0x18 |
| 33 | #define GPCR_OFFSET 0x24 |
| 34 | #define GRER_OFFSET 0x30 |
| 35 | #define GFER_OFFSET 0x3C |
| 36 | #define GEDR_OFFSET 0x48 |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 37 | |
| 38 | struct pxa_gpio_chip { |
| 39 | struct gpio_chip chip; |
| 40 | void __iomem *regbase; |
| 41 | }; |
| 42 | |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 43 | static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
| 44 | { |
| 45 | unsigned long flags; |
| 46 | u32 mask = 1 << offset; |
| 47 | u32 value; |
| 48 | struct pxa_gpio_chip *pxa; |
| 49 | void __iomem *gpdr; |
| 50 | |
| 51 | pxa = container_of(chip, struct pxa_gpio_chip, chip); |
| 52 | gpdr = pxa->regbase + GPDR_OFFSET; |
| 53 | local_irq_save(flags); |
| 54 | value = __raw_readl(gpdr); |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame] | 55 | if (__gpio_is_inverted(chip->base + offset)) |
| 56 | value |= mask; |
| 57 | else |
| 58 | value &= ~mask; |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 59 | __raw_writel(value, gpdr); |
| 60 | local_irq_restore(flags); |
| 61 | |
| 62 | return 0; |
| 63 | } |
| 64 | |
| 65 | static int pxa_gpio_direction_output(struct gpio_chip *chip, |
| 66 | unsigned offset, int value) |
| 67 | { |
| 68 | unsigned long flags; |
| 69 | u32 mask = 1 << offset; |
| 70 | u32 tmp; |
| 71 | struct pxa_gpio_chip *pxa; |
| 72 | void __iomem *gpdr; |
| 73 | |
| 74 | pxa = container_of(chip, struct pxa_gpio_chip, chip); |
| 75 | __raw_writel(mask, |
| 76 | pxa->regbase + (value ? GPSR_OFFSET : GPCR_OFFSET)); |
| 77 | gpdr = pxa->regbase + GPDR_OFFSET; |
| 78 | local_irq_save(flags); |
| 79 | tmp = __raw_readl(gpdr); |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame] | 80 | if (__gpio_is_inverted(chip->base + offset)) |
| 81 | tmp &= ~mask; |
| 82 | else |
| 83 | tmp |= mask; |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 84 | __raw_writel(tmp, gpdr); |
| 85 | local_irq_restore(flags); |
| 86 | |
| 87 | return 0; |
| 88 | } |
| 89 | |
| 90 | /* |
| 91 | * Return GPIO level |
| 92 | */ |
| 93 | static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 94 | { |
| 95 | u32 mask = 1 << offset; |
| 96 | struct pxa_gpio_chip *pxa; |
| 97 | |
| 98 | pxa = container_of(chip, struct pxa_gpio_chip, chip); |
| 99 | return __raw_readl(pxa->regbase + GPLR_OFFSET) & mask; |
| 100 | } |
| 101 | |
| 102 | /* |
| 103 | * Set output GPIO level |
| 104 | */ |
| 105 | static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 106 | { |
| 107 | u32 mask = 1 << offset; |
| 108 | struct pxa_gpio_chip *pxa; |
| 109 | |
| 110 | pxa = container_of(chip, struct pxa_gpio_chip, chip); |
| 111 | |
| 112 | if (value) |
| 113 | __raw_writel(mask, pxa->regbase + GPSR_OFFSET); |
| 114 | else |
| 115 | __raw_writel(mask, pxa->regbase + GPCR_OFFSET); |
| 116 | } |
| 117 | |
eric miao | 0e037bb | 2008-03-03 13:20:20 +0800 | [diff] [blame] | 118 | #define GPIO_CHIP(_n) \ |
| 119 | [_n] = { \ |
| 120 | .regbase = GPIO##_n##_BASE, \ |
| 121 | .chip = { \ |
| 122 | .label = "gpio-" #_n, \ |
| 123 | .direction_input = pxa_gpio_direction_input, \ |
| 124 | .direction_output = pxa_gpio_direction_output, \ |
| 125 | .get = pxa_gpio_get, \ |
| 126 | .set = pxa_gpio_set, \ |
| 127 | .base = (_n) * 32, \ |
| 128 | .ngpio = 32, \ |
| 129 | }, \ |
| 130 | } |
| 131 | |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 132 | static struct pxa_gpio_chip pxa_gpio_chip[] = { |
eric miao | 0e037bb | 2008-03-03 13:20:20 +0800 | [diff] [blame] | 133 | GPIO_CHIP(0), |
| 134 | GPIO_CHIP(1), |
| 135 | GPIO_CHIP(2), |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 136 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) |
eric miao | 0e037bb | 2008-03-03 13:20:20 +0800 | [diff] [blame] | 137 | GPIO_CHIP(3), |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 138 | #endif |
| 139 | }; |
| 140 | |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 141 | static void __init pxa_init_gpio_chip(int gpio_nr) |
| 142 | { |
| 143 | int i, gpio; |
| 144 | |
| 145 | /* add a GPIO chip for each register bank. |
| 146 | * the last PXA25x register only contains 21 GPIOs |
| 147 | */ |
| 148 | for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) { |
| 149 | if (gpio + 32 > gpio_nr) |
| 150 | pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio; |
| 151 | gpiochip_add(&pxa_gpio_chip[i].chip); |
| 152 | } |
| 153 | } |
| 154 | |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 155 | /* |
| 156 | * PXA GPIO edge detection for IRQs: |
| 157 | * IRQs are generated on Falling-Edge, Rising-Edge, or both. |
| 158 | * Use this instead of directly setting GRER/GFER. |
| 159 | */ |
| 160 | |
Dmitry Baryshkov | d8a42fc | 2008-04-19 10:42:18 +0100 | [diff] [blame] | 161 | static unsigned long GPIO_IRQ_rising_edge[4]; |
| 162 | static unsigned long GPIO_IRQ_falling_edge[4]; |
| 163 | static unsigned long GPIO_IRQ_mask[4]; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 164 | |
| 165 | static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) |
| 166 | { |
| 167 | int gpio, idx; |
| 168 | |
| 169 | gpio = IRQ_TO_GPIO(irq); |
| 170 | idx = gpio >> 5; |
| 171 | |
| 172 | if (type == IRQ_TYPE_PROBE) { |
| 173 | /* Don't mess with enabled GPIOs using preconfigured edges or |
| 174 | * GPIOs set to alternate function or to output during probe |
| 175 | */ |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame] | 176 | if ((GPIO_IRQ_rising_edge[idx] & GPIO_bit(gpio)) || |
| 177 | (GPIO_IRQ_falling_edge[idx] & GPIO_bit(gpio))) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 178 | return 0; |
eric miao | 689c04a | 2008-03-04 17:18:38 +0800 | [diff] [blame] | 179 | |
| 180 | if (__gpio_is_occupied(gpio)) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 181 | return 0; |
eric miao | 689c04a | 2008-03-04 17:18:38 +0800 | [diff] [blame] | 182 | |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 183 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
| 184 | } |
| 185 | |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame] | 186 | if (__gpio_is_inverted(gpio)) |
| 187 | GPDR(gpio) |= GPIO_bit(gpio); |
| 188 | else |
| 189 | GPDR(gpio) &= ~GPIO_bit(gpio); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 190 | |
| 191 | if (type & IRQ_TYPE_EDGE_RISING) |
| 192 | __set_bit(gpio, GPIO_IRQ_rising_edge); |
| 193 | else |
| 194 | __clear_bit(gpio, GPIO_IRQ_rising_edge); |
| 195 | |
| 196 | if (type & IRQ_TYPE_EDGE_FALLING) |
| 197 | __set_bit(gpio, GPIO_IRQ_falling_edge); |
| 198 | else |
| 199 | __clear_bit(gpio, GPIO_IRQ_falling_edge); |
| 200 | |
| 201 | GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; |
| 202 | GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; |
| 203 | |
| 204 | pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio, |
| 205 | ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), |
| 206 | ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); |
| 207 | return 0; |
| 208 | } |
| 209 | |
| 210 | /* |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 211 | * Demux handler for GPIO>=2 edge detect interrupts |
| 212 | */ |
| 213 | |
| 214 | #define GEDR_BITS (sizeof(gedr) * BITS_PER_BYTE) |
| 215 | |
| 216 | static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) |
| 217 | { |
| 218 | int loop, bit, n; |
| 219 | unsigned long gedr[4]; |
| 220 | |
| 221 | do { |
| 222 | gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3; |
| 223 | gedr[1] = GEDR1 & GPIO_IRQ_mask[1]; |
| 224 | gedr[2] = GEDR2 & GPIO_IRQ_mask[2]; |
| 225 | gedr[3] = GEDR3 & GPIO_IRQ_mask[3]; |
| 226 | |
| 227 | GEDR0 = gedr[0]; GEDR1 = gedr[1]; |
| 228 | GEDR2 = gedr[2]; GEDR3 = gedr[3]; |
| 229 | |
| 230 | loop = 0; |
| 231 | bit = find_first_bit(gedr, GEDR_BITS); |
| 232 | while (bit < GEDR_BITS) { |
| 233 | loop = 1; |
| 234 | |
| 235 | n = PXA_GPIO_IRQ_BASE + bit; |
Dmitry Baryshkov | d8aa025 | 2008-10-09 13:36:24 +0100 | [diff] [blame] | 236 | generic_handle_irq(n); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 237 | |
| 238 | bit = find_next_bit(gedr, GEDR_BITS, bit + 1); |
| 239 | } |
| 240 | } while (loop); |
| 241 | } |
| 242 | |
| 243 | static void pxa_ack_muxed_gpio(unsigned int irq) |
| 244 | { |
| 245 | int gpio = irq - IRQ_GPIO(2) + 2; |
| 246 | GEDR(gpio) = GPIO_bit(gpio); |
| 247 | } |
| 248 | |
| 249 | static void pxa_mask_muxed_gpio(unsigned int irq) |
| 250 | { |
| 251 | int gpio = irq - IRQ_GPIO(2) + 2; |
| 252 | __clear_bit(gpio, GPIO_IRQ_mask); |
| 253 | GRER(gpio) &= ~GPIO_bit(gpio); |
| 254 | GFER(gpio) &= ~GPIO_bit(gpio); |
| 255 | } |
| 256 | |
| 257 | static void pxa_unmask_muxed_gpio(unsigned int irq) |
| 258 | { |
| 259 | int gpio = irq - IRQ_GPIO(2) + 2; |
| 260 | int idx = gpio >> 5; |
| 261 | __set_bit(gpio, GPIO_IRQ_mask); |
| 262 | GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; |
| 263 | GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; |
| 264 | } |
| 265 | |
| 266 | static struct irq_chip pxa_muxed_gpio_chip = { |
| 267 | .name = "GPIO", |
| 268 | .ack = pxa_ack_muxed_gpio, |
| 269 | .mask = pxa_mask_muxed_gpio, |
| 270 | .unmask = pxa_unmask_muxed_gpio, |
| 271 | .set_type = pxa_gpio_irq_type, |
| 272 | }; |
| 273 | |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 274 | void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 275 | { |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 276 | int irq, i; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 277 | |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 278 | pxa_last_gpio = end; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 279 | |
| 280 | /* clear all GPIO edge detects */ |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 281 | for (i = start; i <= end; i += 32) { |
| 282 | GFER(i) &= ~GPIO_IRQ_mask[i]; |
| 283 | GRER(i) &= ~GPIO_IRQ_mask[i]; |
| 284 | GEDR(i) = GPIO_IRQ_mask[i]; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 285 | } |
| 286 | |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 287 | for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) { |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 288 | set_irq_chip(irq, &pxa_muxed_gpio_chip); |
| 289 | set_irq_handler(irq, handle_edge_irq); |
| 290 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
| 291 | } |
| 292 | |
| 293 | /* Install handler for GPIO>=2 edge detect interrupts */ |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 294 | set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler); |
eric miao | b9e25ac | 2008-03-04 14:19:58 +0800 | [diff] [blame] | 295 | pxa_muxed_gpio_chip.set_wake = fn; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 296 | |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 297 | /* Initialize GPIO chips */ |
| 298 | pxa_init_gpio_chip(end + 1); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 299 | } |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 300 | |
| 301 | #ifdef CONFIG_PM |
| 302 | |
| 303 | static unsigned long saved_gplr[4]; |
| 304 | static unsigned long saved_gpdr[4]; |
| 305 | static unsigned long saved_grer[4]; |
| 306 | static unsigned long saved_gfer[4]; |
| 307 | |
| 308 | static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state) |
| 309 | { |
| 310 | int i, gpio; |
| 311 | |
| 312 | for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) { |
| 313 | saved_gplr[i] = GPLR(gpio); |
| 314 | saved_gpdr[i] = GPDR(gpio); |
| 315 | saved_grer[i] = GRER(gpio); |
| 316 | saved_gfer[i] = GFER(gpio); |
| 317 | |
| 318 | /* Clear GPIO transition detect bits */ |
| 319 | GEDR(gpio) = GEDR(gpio); |
| 320 | } |
| 321 | return 0; |
| 322 | } |
| 323 | |
| 324 | static int pxa_gpio_resume(struct sys_device *dev) |
| 325 | { |
| 326 | int i, gpio; |
| 327 | |
| 328 | for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) { |
| 329 | /* restore level with set/clear */ |
| 330 | GPSR(gpio) = saved_gplr[i]; |
| 331 | GPCR(gpio) = ~saved_gplr[i]; |
| 332 | |
| 333 | GRER(gpio) = saved_grer[i]; |
| 334 | GFER(gpio) = saved_gfer[i]; |
| 335 | GPDR(gpio) = saved_gpdr[i]; |
| 336 | } |
| 337 | return 0; |
| 338 | } |
| 339 | #else |
| 340 | #define pxa_gpio_suspend NULL |
| 341 | #define pxa_gpio_resume NULL |
| 342 | #endif |
| 343 | |
| 344 | struct sysdev_class pxa_gpio_sysclass = { |
| 345 | .name = "gpio", |
| 346 | .suspend = pxa_gpio_suspend, |
| 347 | .resume = pxa_gpio_resume, |
| 348 | }; |
| 349 | |
| 350 | static int __init pxa_gpio_init(void) |
| 351 | { |
| 352 | return sysdev_class_register(&pxa_gpio_sysclass); |
| 353 | } |
| 354 | |
| 355 | core_initcall(pxa_gpio_init); |