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Linus Torvalds1da177e2005-04-16 15:20:36 -07001comment "Processor Type"
2
Linus Torvalds1da177e2005-04-16 15:20:36 -07003# Select CPU types depending on the architecture selected. This selects
4# which CPUs we support in the kernel image, and the compiler instruction
5# optimiser behaviour.
6
Hyok S. Choi07e0da72006-09-26 17:37:36 +09007# ARM7TDMI
8config CPU_ARM7TDMI
Arnd Bergmannc32b7652015-05-26 15:40:16 +01009 bool
Russell King6b237a32006-09-27 17:44:39 +010010 depends on !MMU
Hyok S. Choi07e0da72006-09-26 17:37:36 +090011 select CPU_32v4T
12 select CPU_ABRT_LV4T
13 select CPU_CACHE_V4
Russell Kingb1b3f492012-10-06 17:12:25 +010014 select CPU_PABRT_LEGACY
Hyok S. Choi07e0da72006-09-26 17:37:36 +090015 help
16 A 32-bit RISC microprocessor based on the ARM7 processor core
17 which has no memory control unit and cache.
18
19 Say Y if you want support for the ARM7TDMI processor.
20 Otherwise, say N.
21
Linus Torvalds1da177e2005-04-16 15:20:36 -070022# ARM720T
23config CPU_ARM720T
Linus Walleijdc680b92014-11-10 18:52:31 +010024 bool "Support ARM720T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
Lennert Buytenhek260e98e2006-08-28 12:51:20 +010025 select CPU_32v4T
Linus Torvalds1da177e2005-04-16 15:20:36 -070026 select CPU_ABRT_LV4T
27 select CPU_CACHE_V4
28 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +010029 select CPU_COPY_V4WT if MMU
Russell Kingb1b3f492012-10-06 17:12:25 +010030 select CPU_CP15_MMU
31 select CPU_PABRT_LEGACY
Hyok S. Choif9c21a62006-06-21 22:26:29 +010032 select CPU_TLB_V4WT if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -070033 help
34 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
35 MMU built around an ARM7TDMI core.
36
37 Say Y if you want support for the ARM720T processor.
38 Otherwise, say N.
39
Hyok S. Choib731c312006-09-26 17:37:50 +090040# ARM740T
41config CPU_ARM740T
Linus Walleijdc680b92014-11-10 18:52:31 +010042 bool "Support ARM740T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
Russell King6b237a32006-09-27 17:44:39 +010043 depends on !MMU
Hyok S. Choib731c312006-09-26 17:37:50 +090044 select CPU_32v4T
45 select CPU_ABRT_LV4T
Will Deacon82d9b0d2013-01-15 12:07:40 +000046 select CPU_CACHE_V4
Hyok S. Choib731c312006-09-26 17:37:50 +090047 select CPU_CP15_MPU
Russell Kingb1b3f492012-10-06 17:12:25 +010048 select CPU_PABRT_LEGACY
Hyok S. Choib731c312006-09-26 17:37:50 +090049 help
50 A 32-bit RISC processor with 8KB cache or 4KB variants,
51 write buffer and MPU(Protection Unit) built around
52 an ARM7TDMI core.
53
54 Say Y if you want support for the ARM740T processor.
55 Otherwise, say N.
56
Hyok S. Choi43f5f012006-09-26 17:38:05 +090057# ARM9TDMI
58config CPU_ARM9TDMI
Arnd Bergmannc32b7652015-05-26 15:40:16 +010059 bool
Russell King6b237a32006-09-27 17:44:39 +010060 depends on !MMU
Hyok S. Choi43f5f012006-09-26 17:38:05 +090061 select CPU_32v4T
Hyok S. Choi0f45d7f2006-09-28 21:46:16 +090062 select CPU_ABRT_NOMMU
Hyok S. Choi43f5f012006-09-26 17:38:05 +090063 select CPU_CACHE_V4
Russell Kingb1b3f492012-10-06 17:12:25 +010064 select CPU_PABRT_LEGACY
Hyok S. Choi43f5f012006-09-26 17:38:05 +090065 help
66 A 32-bit RISC microprocessor based on the ARM9 processor core
67 which has no memory control unit and cache.
68
69 Say Y if you want support for the ARM9TDMI processor.
70 Otherwise, say N.
71
Linus Torvalds1da177e2005-04-16 15:20:36 -070072# ARM920T
73config CPU_ARM920T
Linus Walleijdc680b92014-11-10 18:52:31 +010074 bool "Support ARM920T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
Lennert Buytenhek260e98e2006-08-28 12:51:20 +010075 select CPU_32v4T
Linus Torvalds1da177e2005-04-16 15:20:36 -070076 select CPU_ABRT_EV4T
77 select CPU_CACHE_V4WT
78 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +010079 select CPU_COPY_V4WB if MMU
Russell Kingb1b3f492012-10-06 17:12:25 +010080 select CPU_CP15_MMU
81 select CPU_PABRT_LEGACY
Hyok S. Choif9c21a62006-06-21 22:26:29 +010082 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -070083 help
84 The ARM920T is licensed to be produced by numerous vendors,
Hartley Sweetenc768e6762009-10-21 02:27:01 +010085 and is used in the Cirrus EP93xx and the Samsung S3C2410.
Linus Torvalds1da177e2005-04-16 15:20:36 -070086
87 Say Y if you want support for the ARM920T processor.
88 Otherwise, say N.
89
90# ARM922T
91config CPU_ARM922T
Linus Walleijdc680b92014-11-10 18:52:31 +010092 bool "Support ARM922T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
Lennert Buytenhek260e98e2006-08-28 12:51:20 +010093 select CPU_32v4T
Linus Torvalds1da177e2005-04-16 15:20:36 -070094 select CPU_ABRT_EV4T
95 select CPU_CACHE_V4WT
96 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +010097 select CPU_COPY_V4WB if MMU
Russell Kingb1b3f492012-10-06 17:12:25 +010098 select CPU_CP15_MMU
99 select CPU_PABRT_LEGACY
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100100 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101 help
102 The ARM922T is a version of the ARM920T, but with smaller
103 instruction and data caches. It is used in Altera's
Andrew Victorc53c9cf2007-05-11 21:01:28 +0100104 Excalibur XA device family and Micrel's KS8695 Centaur.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105
106 Say Y if you want support for the ARM922T processor.
107 Otherwise, say N.
108
109# ARM925T
110config CPU_ARM925T
Tony Lindgrenb288f752005-07-10 19:58:08 +0100111 bool "Support ARM925T processor" if ARCH_OMAP1
Lennert Buytenhek260e98e2006-08-28 12:51:20 +0100112 select CPU_32v4T
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113 select CPU_ABRT_EV4T
114 select CPU_CACHE_V4WT
115 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100116 select CPU_COPY_V4WB if MMU
Russell Kingb1b3f492012-10-06 17:12:25 +0100117 select CPU_CP15_MMU
118 select CPU_PABRT_LEGACY
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100119 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120 help
121 The ARM925T is a mix between the ARM920T and ARM926T, but with
122 different instruction and data caches. It is used in TI's OMAP
123 device family.
124
125 Say Y if you want support for the ARM925T processor.
126 Otherwise, say N.
127
128# ARM926T
129config CPU_ARM926T
Linus Walleijdc680b92014-11-10 18:52:31 +0100130 bool "Support ARM926T processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V5) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131 select CPU_32v5
132 select CPU_ABRT_EV5TJ
133 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100134 select CPU_COPY_V4WB if MMU
Russell Kingb1b3f492012-10-06 17:12:25 +0100135 select CPU_CP15_MMU
136 select CPU_PABRT_LEGACY
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100137 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138 help
139 This is a variant of the ARM920. It has slightly different
140 instruction sequences for cache and TLB operations. Curiously,
141 there is no documentation on it at the ARM corporate website.
142
143 Say Y if you want support for the ARM926T processor.
144 Otherwise, say N.
145
Paulius Zaleckas28853ac2009-03-25 13:10:01 +0200146# FA526
147config CPU_FA526
148 bool
149 select CPU_32v4
150 select CPU_ABRT_EV4
Paulius Zaleckas28853ac2009-03-25 13:10:01 +0200151 select CPU_CACHE_FA
Russell Kingb1b3f492012-10-06 17:12:25 +0100152 select CPU_CACHE_VIVT
Paulius Zaleckas28853ac2009-03-25 13:10:01 +0200153 select CPU_COPY_FA if MMU
Russell Kingb1b3f492012-10-06 17:12:25 +0100154 select CPU_CP15_MMU
155 select CPU_PABRT_LEGACY
Paulius Zaleckas28853ac2009-03-25 13:10:01 +0200156 select CPU_TLB_FA if MMU
157 help
158 The FA526 is a version of the ARMv4 compatible processor with
159 Branch Target Buffer, Unified TLB and cache line size 16.
160
161 Say Y if you want support for the FA526 processor.
162 Otherwise, say N.
163
Hyok S. Choid60674e2006-09-26 17:38:18 +0900164# ARM940T
165config CPU_ARM940T
Linus Walleijdc680b92014-11-10 18:52:31 +0100166 bool "Support ARM940T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
Russell King6b237a32006-09-27 17:44:39 +0100167 depends on !MMU
Hyok S. Choid60674e2006-09-26 17:38:18 +0900168 select CPU_32v4T
Hyok S. Choi0f45d7f2006-09-28 21:46:16 +0900169 select CPU_ABRT_NOMMU
Hyok S. Choid60674e2006-09-26 17:38:18 +0900170 select CPU_CACHE_VIVT
171 select CPU_CP15_MPU
Russell Kingb1b3f492012-10-06 17:12:25 +0100172 select CPU_PABRT_LEGACY
Hyok S. Choid60674e2006-09-26 17:38:18 +0900173 help
174 ARM940T is a member of the ARM9TDMI family of general-
Matt LaPlante3cb2fcc2006-11-30 05:22:59 +0100175 purpose microprocessors with MPU and separate 4KB
Hyok S. Choid60674e2006-09-26 17:38:18 +0900176 instruction and 4KB data cases, each with a 4-word line
177 length.
178
179 Say Y if you want support for the ARM940T processor.
180 Otherwise, say N.
181
Hyok S. Choif37f46e2006-09-26 17:38:32 +0900182# ARM946E-S
183config CPU_ARM946E
Linus Walleijdc680b92014-11-10 18:52:31 +0100184 bool "Support ARM946E-S processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
Russell King6b237a32006-09-27 17:44:39 +0100185 depends on !MMU
Hyok S. Choif37f46e2006-09-26 17:38:32 +0900186 select CPU_32v5
Hyok S. Choi0f45d7f2006-09-28 21:46:16 +0900187 select CPU_ABRT_NOMMU
Hyok S. Choif37f46e2006-09-26 17:38:32 +0900188 select CPU_CACHE_VIVT
189 select CPU_CP15_MPU
Russell Kingb1b3f492012-10-06 17:12:25 +0100190 select CPU_PABRT_LEGACY
Hyok S. Choif37f46e2006-09-26 17:38:32 +0900191 help
192 ARM946E-S is a member of the ARM9E-S family of high-
193 performance, 32-bit system-on-chip processor solutions.
194 The TCM and ARMv5TE 32-bit instruction set is supported.
195
196 Say Y if you want support for the ARM946E-S processor.
197 Otherwise, say N.
198
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199# ARM1020 - needs validating
200config CPU_ARM1020
Linus Walleijdc680b92014-11-10 18:52:31 +0100201 bool "Support ARM1020T (rev 0) processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202 select CPU_32v5
203 select CPU_ABRT_EV4T
204 select CPU_CACHE_V4WT
205 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100206 select CPU_COPY_V4WB if MMU
Russell Kingb1b3f492012-10-06 17:12:25 +0100207 select CPU_CP15_MMU
208 select CPU_PABRT_LEGACY
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100209 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700210 help
211 The ARM1020 is the 32K cached version of the ARM10 processor,
212 with an addition of a floating-point unit.
213
214 Say Y if you want support for the ARM1020 processor.
215 Otherwise, say N.
216
217# ARM1020E - needs validating
218config CPU_ARM1020E
Linus Walleijdc680b92014-11-10 18:52:31 +0100219 bool "Support ARM1020E processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
Russell Kingb1b3f492012-10-06 17:12:25 +0100220 depends on n
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221 select CPU_32v5
222 select CPU_ABRT_EV4T
223 select CPU_CACHE_V4WT
224 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100225 select CPU_COPY_V4WB if MMU
Russell Kingb1b3f492012-10-06 17:12:25 +0100226 select CPU_CP15_MMU
227 select CPU_PABRT_LEGACY
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100228 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229
230# ARM1022E
231config CPU_ARM1022
Linus Walleijdc680b92014-11-10 18:52:31 +0100232 bool "Support ARM1022E processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233 select CPU_32v5
234 select CPU_ABRT_EV4T
235 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100236 select CPU_COPY_V4WB if MMU # can probably do better
Russell Kingb1b3f492012-10-06 17:12:25 +0100237 select CPU_CP15_MMU
238 select CPU_PABRT_LEGACY
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100239 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240 help
241 The ARM1022E is an implementation of the ARMv5TE architecture
242 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
243 embedded trace macrocell, and a floating-point unit.
244
245 Say Y if you want support for the ARM1022E processor.
246 Otherwise, say N.
247
248# ARM1026EJ-S
249config CPU_ARM1026
Linus Walleijdc680b92014-11-10 18:52:31 +0100250 bool "Support ARM1026EJ-S processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251 select CPU_32v5
252 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
253 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100254 select CPU_COPY_V4WB if MMU # can probably do better
Russell Kingb1b3f492012-10-06 17:12:25 +0100255 select CPU_CP15_MMU
256 select CPU_PABRT_LEGACY
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100257 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258 help
259 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
260 based upon the ARM10 integer core.
261
262 Say Y if you want support for the ARM1026EJ-S processor.
263 Otherwise, say N.
264
265# SA110
266config CPU_SA110
Arnd Bergmannfa04e202014-02-26 17:39:12 +0100267 bool
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268 select CPU_32v3 if ARCH_RPC
269 select CPU_32v4 if !ARCH_RPC
270 select CPU_ABRT_EV4
271 select CPU_CACHE_V4WB
272 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100273 select CPU_COPY_V4WB if MMU
Russell Kingb1b3f492012-10-06 17:12:25 +0100274 select CPU_CP15_MMU
275 select CPU_PABRT_LEGACY
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100276 select CPU_TLB_V4WB if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700277 help
278 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
279 is available at five speeds ranging from 100 MHz to 233 MHz.
280 More information is available at
281 <http://developer.intel.com/design/strong/sa110.htm>.
282
283 Say Y if you want support for the SA-110 processor.
284 Otherwise, say N.
285
286# SA1100
287config CPU_SA1100
288 bool
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289 select CPU_32v4
290 select CPU_ABRT_EV4
291 select CPU_CACHE_V4WB
292 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900293 select CPU_CP15_MMU
Russell Kingb1b3f492012-10-06 17:12:25 +0100294 select CPU_PABRT_LEGACY
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100295 select CPU_TLB_V4WB if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700296
297# XScale
298config CPU_XSCALE
299 bool
Linus Torvalds1da177e2005-04-16 15:20:36 -0700300 select CPU_32v5
301 select CPU_ABRT_EV5T
302 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900303 select CPU_CP15_MMU
Russell Kingb1b3f492012-10-06 17:12:25 +0100304 select CPU_PABRT_LEGACY
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100305 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700306
Lennert Buytenhek23bdf862006-03-28 21:00:40 +0100307# XScale Core Version 3
308config CPU_XSC3
309 bool
Lennert Buytenhek23bdf862006-03-28 21:00:40 +0100310 select CPU_32v5
311 select CPU_ABRT_EV5T
312 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900313 select CPU_CP15_MMU
Russell Kingb1b3f492012-10-06 17:12:25 +0100314 select CPU_PABRT_LEGACY
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100315 select CPU_TLB_V4WBI if MMU
Lennert Buytenhek23bdf862006-03-28 21:00:40 +0100316 select IO_36
317
Eric Miao49cbe782009-01-20 14:15:18 +0800318# Marvell PJ1 (Mohawk)
319config CPU_MOHAWK
320 bool
321 select CPU_32v5
322 select CPU_ABRT_EV5T
Eric Miao49cbe782009-01-20 14:15:18 +0800323 select CPU_CACHE_VIVT
Eric Miao49cbe782009-01-20 14:15:18 +0800324 select CPU_COPY_V4WB if MMU
Russell Kingb1b3f492012-10-06 17:12:25 +0100325 select CPU_CP15_MMU
326 select CPU_PABRT_LEGACY
327 select CPU_TLB_V4WBI if MMU
Eric Miao49cbe782009-01-20 14:15:18 +0800328
Assaf Hoffmane50d6402007-10-23 15:14:41 -0400329# Feroceon
330config CPU_FEROCEON
331 bool
Assaf Hoffmane50d6402007-10-23 15:14:41 -0400332 select CPU_32v5
333 select CPU_ABRT_EV5T
334 select CPU_CACHE_VIVT
Lennert Buytenhek0ed15072008-04-24 01:31:45 -0400335 select CPU_COPY_FEROCEON if MMU
Russell Kingb1b3f492012-10-06 17:12:25 +0100336 select CPU_CP15_MMU
337 select CPU_PABRT_LEGACY
Lennert Buytenhek99c6dc12008-06-22 22:45:04 +0200338 select CPU_TLB_FEROCEON if MMU
Assaf Hoffmane50d6402007-10-23 15:14:41 -0400339
Tzachi Perelsteind910a0a2007-11-06 10:35:40 +0200340config CPU_FEROCEON_OLD_ID
341 bool "Accept early Feroceon cores with an ARM926 ID"
342 depends on CPU_FEROCEON && !CPU_ARM926T
343 default y
344 help
345 This enables the usage of some old Feroceon cores
346 for which the CPU ID is equal to the ARM926 ID.
347 Relevant for Feroceon-1850 and early Feroceon-2850.
348
Haojian Zhuanga4553352010-11-24 11:54:19 +0800349# Marvell PJ4
350config CPU_PJ4
351 bool
Haojian Zhuanga4553352010-11-24 11:54:19 +0800352 select ARM_THUMBEE
Russell Kingb1b3f492012-10-06 17:12:25 +0100353 select CPU_V7
Haojian Zhuanga4553352010-11-24 11:54:19 +0800354
Gregory CLEMENTde490192012-10-03 11:58:07 +0200355config CPU_PJ4B
356 bool
357 select CPU_V7
358
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359# ARMv6
360config CPU_V6
Linus Walleijdc680b92014-11-10 18:52:31 +0100361 bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362 select CPU_32v6
363 select CPU_ABRT_EV6
364 select CPU_CACHE_V6
365 select CPU_CACHE_VIPT
Russell Kingb1b3f492012-10-06 17:12:25 +0100366 select CPU_COPY_V6 if MMU
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900367 select CPU_CP15_MMU
Catalin Marinas7b4c9652007-07-20 11:42:57 +0100368 select CPU_HAS_ASID if MMU
Russell Kingb1b3f492012-10-06 17:12:25 +0100369 select CPU_PABRT_V6
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100370 select CPU_TLB_V6 if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700371
Russell King4a5f79e2005-11-03 15:48:21 +0000372# ARMv6k
Russell Kinge399b1a2011-01-17 15:08:32 +0000373config CPU_V6K
Linus Walleijdc680b92014-11-10 18:52:31 +0100374 bool "Support ARM V6K processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
Russell Kinge399b1a2011-01-17 15:08:32 +0000375 select CPU_32v6
Russell King60799c62011-01-15 16:25:04 +0000376 select CPU_32v6K
Russell Kinge399b1a2011-01-17 15:08:32 +0000377 select CPU_ABRT_EV6
Russell Kinge399b1a2011-01-17 15:08:32 +0000378 select CPU_CACHE_V6
379 select CPU_CACHE_VIPT
Russell Kingb1b3f492012-10-06 17:12:25 +0100380 select CPU_COPY_V6 if MMU
Russell Kinge399b1a2011-01-17 15:08:32 +0000381 select CPU_CP15_MMU
382 select CPU_HAS_ASID if MMU
Russell Kingb1b3f492012-10-06 17:12:25 +0100383 select CPU_PABRT_V6
Russell Kinge399b1a2011-01-17 15:08:32 +0000384 select CPU_TLB_V6 if MMU
Russell King4a5f79e2005-11-03 15:48:21 +0000385
Catalin Marinas23688e92007-05-08 22:45:26 +0100386# ARMv7
387config CPU_V7
Linus Walleijdc680b92014-11-10 18:52:31 +0100388 bool "Support ARM V7 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V7) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
Russell King15490ef2011-02-09 16:33:46 +0000389 select CPU_32v6K
Catalin Marinas23688e92007-05-08 22:45:26 +0100390 select CPU_32v7
391 select CPU_ABRT_EV7
392 select CPU_CACHE_V7
393 select CPU_CACHE_VIPT
Russell Kingb1b3f492012-10-06 17:12:25 +0100394 select CPU_COPY_V6 if MMU
Jonathan Austin66567612012-07-12 14:38:46 +0100395 select CPU_CP15_MMU if MMU
396 select CPU_CP15_MPU if !MMU
Catalin Marinas2eb8c822007-07-20 11:43:02 +0100397 select CPU_HAS_ASID if MMU
Russell Kingb1b3f492012-10-06 17:12:25 +0100398 select CPU_PABRT_V7
Catalin Marinas2ccdd1e2007-05-18 11:25:31 +0100399 select CPU_TLB_V7 if MMU
Catalin Marinas23688e92007-05-08 22:45:26 +0100400
Uwe Kleine-König4477ca42013-03-21 21:02:37 +0100401# ARMv7M
402config CPU_V7M
403 bool
404 select CPU_32v7M
405 select CPU_ABRT_NOMMU
406 select CPU_CACHE_NOP
407 select CPU_PABRT_LEGACY
408 select CPU_THUMBONLY
409
Uwe Kleine-Königbc7dea02011-12-09 20:52:10 +0100410config CPU_THUMBONLY
411 bool
412 # There are no CPUs available with MMU that don't implement an ARM ISA:
413 depends on !MMU
414 help
415 Select this if your CPU doesn't support the 32 bit ARM instructions.
416
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417# Figure out what processor architecture version we should be using.
418# This defines the compiler instruction set which depends on the machine type.
419config CPU_32v3
420 bool
Russell King8762df42011-01-17 15:53:56 +0000421 select CPU_USE_DOMAINS if MMU
Russell Kingb1b3f492012-10-06 17:12:25 +0100422 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
Russell Kingf6f91b02013-07-23 18:37:00 +0100423 select NEED_KUSER_HELPERS
Russell King51aaf812014-04-22 22:26:27 +0100424 select TLS_REG_EMUL if SMP || !MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425
426config CPU_32v4
427 bool
Russell King8762df42011-01-17 15:53:56 +0000428 select CPU_USE_DOMAINS if MMU
Russell Kingb1b3f492012-10-06 17:12:25 +0100429 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
Russell Kingf6f91b02013-07-23 18:37:00 +0100430 select NEED_KUSER_HELPERS
Russell King51aaf812014-04-22 22:26:27 +0100431 select TLS_REG_EMUL if SMP || !MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700432
Lennert Buytenhek260e98e2006-08-28 12:51:20 +0100433config CPU_32v4T
434 bool
Russell King8762df42011-01-17 15:53:56 +0000435 select CPU_USE_DOMAINS if MMU
Russell Kingb1b3f492012-10-06 17:12:25 +0100436 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
Russell Kingf6f91b02013-07-23 18:37:00 +0100437 select NEED_KUSER_HELPERS
Russell King51aaf812014-04-22 22:26:27 +0100438 select TLS_REG_EMUL if SMP || !MMU
Lennert Buytenhek260e98e2006-08-28 12:51:20 +0100439
Linus Torvalds1da177e2005-04-16 15:20:36 -0700440config CPU_32v5
441 bool
Russell King8762df42011-01-17 15:53:56 +0000442 select CPU_USE_DOMAINS if MMU
Russell Kingb1b3f492012-10-06 17:12:25 +0100443 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
Russell Kingf6f91b02013-07-23 18:37:00 +0100444 select NEED_KUSER_HELPERS
Russell King51aaf812014-04-22 22:26:27 +0100445 select TLS_REG_EMUL if SMP || !MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446
447config CPU_32v6
448 bool
Russell Kingb1b3f492012-10-06 17:12:25 +0100449 select TLS_REG_EMUL if !CPU_32v6K && !MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450
Russell Kinge399b1a2011-01-17 15:08:32 +0000451config CPU_32v6K
Russell King60799c62011-01-15 16:25:04 +0000452 bool
Linus Torvalds1da177e2005-04-16 15:20:36 -0700453
Catalin Marinas23688e92007-05-08 22:45:26 +0100454config CPU_32v7
455 bool
456
Uwe Kleine-König4477ca42013-03-21 21:02:37 +0100457config CPU_32v7M
458 bool
459
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460# The abort model
Hyok S. Choi0f45d7f2006-09-28 21:46:16 +0900461config CPU_ABRT_NOMMU
462 bool
463
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464config CPU_ABRT_EV4
465 bool
466
467config CPU_ABRT_EV4T
468 bool
469
470config CPU_ABRT_LV4T
471 bool
472
473config CPU_ABRT_EV5T
474 bool
475
476config CPU_ABRT_EV5TJ
477 bool
478
479config CPU_ABRT_EV6
480 bool
481
Catalin Marinas23688e92007-05-08 22:45:26 +0100482config CPU_ABRT_EV7
483 bool
484
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100485config CPU_PABRT_LEGACY
Paul Brook48d79272008-04-18 22:43:07 +0100486 bool
487
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100488config CPU_PABRT_V6
489 bool
490
491config CPU_PABRT_V7
Paul Brook48d79272008-04-18 22:43:07 +0100492 bool
493
Linus Torvalds1da177e2005-04-16 15:20:36 -0700494# The cache model
Linus Torvalds1da177e2005-04-16 15:20:36 -0700495config CPU_CACHE_V4
496 bool
497
498config CPU_CACHE_V4WT
499 bool
500
501config CPU_CACHE_V4WB
502 bool
503
504config CPU_CACHE_V6
505 bool
506
Catalin Marinas23688e92007-05-08 22:45:26 +0100507config CPU_CACHE_V7
508 bool
509
Uwe Kleine-König4477ca42013-03-21 21:02:37 +0100510config CPU_CACHE_NOP
511 bool
512
Linus Torvalds1da177e2005-04-16 15:20:36 -0700513config CPU_CACHE_VIVT
514 bool
515
516config CPU_CACHE_VIPT
517 bool
518
Paulius Zaleckas28853ac2009-03-25 13:10:01 +0200519config CPU_CACHE_FA
520 bool
521
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100522if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700523# The copy-page model
Linus Torvalds1da177e2005-04-16 15:20:36 -0700524config CPU_COPY_V4WT
525 bool
526
527config CPU_COPY_V4WB
528 bool
529
Lennert Buytenhek0ed15072008-04-24 01:31:45 -0400530config CPU_COPY_FEROCEON
531 bool
532
Paulius Zaleckas28853ac2009-03-25 13:10:01 +0200533config CPU_COPY_FA
534 bool
535
Linus Torvalds1da177e2005-04-16 15:20:36 -0700536config CPU_COPY_V6
537 bool
538
539# This selects the TLB model
Linus Torvalds1da177e2005-04-16 15:20:36 -0700540config CPU_TLB_V4WT
541 bool
542 help
543 ARM Architecture Version 4 TLB with writethrough cache.
544
545config CPU_TLB_V4WB
546 bool
547 help
548 ARM Architecture Version 4 TLB with writeback cache.
549
550config CPU_TLB_V4WBI
551 bool
552 help
553 ARM Architecture Version 4 TLB with writeback cache and invalidate
554 instruction cache entry.
555
Lennert Buytenhek99c6dc12008-06-22 22:45:04 +0200556config CPU_TLB_FEROCEON
557 bool
558 help
559 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
560
Paulius Zaleckas28853ac2009-03-25 13:10:01 +0200561config CPU_TLB_FA
562 bool
563 help
564 Faraday ARM FA526 architecture, unified TLB with writeback cache
565 and invalidate instruction cache entry. Branch target buffer is
566 also supported.
567
Linus Torvalds1da177e2005-04-16 15:20:36 -0700568config CPU_TLB_V6
569 bool
570
Catalin Marinas2ccdd1e2007-05-18 11:25:31 +0100571config CPU_TLB_V7
572 bool
573
Dave Estese220ba62009-08-11 17:58:49 -0400574config VERIFY_PERMISSION_FAULT
575 bool
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100576endif
577
Russell King516793c2007-05-17 10:19:23 +0100578config CPU_HAS_ASID
579 bool
580 help
581 This indicates whether the CPU has the ASID register; used to
582 tag TLB and possibly cache entries.
583
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900584config CPU_CP15
585 bool
586 help
587 Processor has the CP15 register.
588
589config CPU_CP15_MMU
590 bool
591 select CPU_CP15
592 help
593 Processor has the CP15 register, which has MMU related registers.
594
595config CPU_CP15_MPU
596 bool
597 select CPU_CP15
598 help
599 Processor has the CP15 register, which has MPU related registers.
600
Catalin Marinas247055a2010-09-13 16:03:21 +0100601config CPU_USE_DOMAINS
602 bool
Catalin Marinas247055a2010-09-13 16:03:21 +0100603 help
604 This option enables or disables the use of domain switching
605 via the set_fs() function.
606
Maxime Coquelin stm326b1814c2015-04-10 09:46:46 +0100607config CPU_V7M_NUM_IRQ
608 int "Number of external interrupts connected to the NVIC"
609 depends on CPU_V7M
610 default 90 if ARCH_STM32
611 default 38 if ARCH_EFM32
Stefan Agner45b0fa02015-05-20 00:16:46 +0100612 default 112 if SOC_VF610
Maxime Coquelin stm326b1814c2015-04-10 09:46:46 +0100613 default 240
614 help
615 This option indicates the number of interrupts connected to the NVIC.
616 The value can be larger than the real number of interrupts supported
617 by the system, but must not be lower.
618 The default value is 240, corresponding to the maximum number of
619 interrupts supported by the NVIC on Cortex-M family.
620
621 If unsure, keep default value.
622
Lennert Buytenhek23bdf862006-03-28 21:00:40 +0100623#
624# CPU supports 36-bit I/O
625#
626config IO_36
627 bool
628
Linus Torvalds1da177e2005-04-16 15:20:36 -0700629comment "Processor Features"
630
Catalin Marinas497b7e92011-11-22 17:30:32 +0000631config ARM_LPAE
632 bool "Support for the Large Physical Address Extension"
Catalin Marinas08a183f2012-02-14 16:33:27 +0100633 depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
634 !CPU_32v4 && !CPU_32v3
Catalin Marinas497b7e92011-11-22 17:30:32 +0000635 help
636 Say Y if you have an ARMv7 processor supporting the LPAE page
637 table format and you would like to access memory beyond the
638 4GB limit. The resulting kernel image will not run on
639 processors without the LPA extension.
640
641 If unsure, say N.
642
Russell Kingd8dc7fb2015-04-04 16:58:38 +0100643config ARM_PV_FIXUP
644 def_bool y
645 depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE
646
Catalin Marinas497b7e92011-11-22 17:30:32 +0000647config ARCH_PHYS_ADDR_T_64BIT
648 def_bool ARM_LPAE
649
650config ARCH_DMA_ADDR_T_64BIT
651 bool
652
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653config ARM_THUMB
Uwe Kleine-Königbc7dea02011-12-09 20:52:10 +0100654 bool "Support Thumb user binaries" if !CPU_THUMBONLY
Uwe Kleine-König4477ca42013-03-21 21:02:37 +0100655 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \
656 CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \
657 CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
658 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \
659 CPU_V7 || CPU_FEROCEON || CPU_V7M
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660 default y
661 help
662 Say Y if you want to include kernel support for running user space
663 Thumb binaries.
664
665 The Thumb instruction set is a compressed form of the standard ARM
666 instruction set resulting in smaller binaries at the expense of
667 slightly less efficient code.
668
669 If you don't know what this all is, saying Y is a safe choice.
670
Catalin Marinasd7f864b2008-04-18 22:43:06 +0100671config ARM_THUMBEE
672 bool "Enable ThumbEE CPU extension"
673 depends on CPU_V7
674 help
675 Say Y here if you have a CPU with the ThumbEE extension and code to
676 make use of it. Say N for code that can run on CPUs without ThumbEE.
677
Dave Martin5b6728d2012-02-17 16:54:28 +0000678config ARM_VIRT_EXT
Will Deacon651134b2013-01-09 14:29:33 +0000679 bool
680 depends on MMU
681 default y if CPU_V7
Dave Martin5b6728d2012-02-17 16:54:28 +0000682 help
683 Enable the kernel to make use of the ARM Virtualization
684 Extensions to install hypervisors without run-time firmware
685 assistance.
686
687 A compliant bootloader is required in order to make maximum
688 use of this feature. Refer to Documentation/arm/Booting for
689 details.
690
Leif Lindholm64d2dc32010-09-16 18:00:47 +0100691config SWP_EMULATE
Russell Kinga11dd732014-07-04 14:44:36 +0100692 bool "Emulate SWP/SWPB instructions" if !SMP
Will Deaconb6ccb982014-02-07 19:12:27 +0100693 depends on CPU_V7
Leif Lindholm64d2dc32010-09-16 18:00:47 +0100694 default y if SMP
Russell Kingb1b3f492012-10-06 17:12:25 +0100695 select HAVE_PROC_CPU if PROC_FS
Leif Lindholm64d2dc32010-09-16 18:00:47 +0100696 help
697 ARMv6 architecture deprecates use of the SWP/SWPB instructions.
698 ARMv7 multiprocessing extensions introduce the ability to disable
699 these instructions, triggering an undefined instruction exception
700 when executed. Say Y here to enable software emulation of these
701 instructions for userspace (not kernel) using LDREX/STREX.
702 Also creates /proc/cpu/swp_emulation for statistics.
703
704 In some older versions of glibc [<=2.8] SWP is used during futex
705 trylock() operations with the assumption that the code will not
706 be preempted. This invalid assumption may be more likely to fail
707 with SWP emulation enabled, leading to deadlock of the user
708 application.
709
710 NOTE: when accessing uncached shared regions, LDREX/STREX rely
711 on an external transaction monitoring block called a global
712 monitor to maintain update atomicity. If your system does not
713 implement a global monitor, this option can cause programs that
714 perform SWP operations to uncached memory to deadlock.
715
716 If unsure, say Y.
717
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718config CPU_BIG_ENDIAN
719 bool "Build big-endian kernel"
720 depends on ARCH_SUPPORTS_BIG_ENDIAN
721 help
722 Say Y if you plan on running a kernel in big-endian mode.
723 Note that your board must be properly built and your board
724 port must properly enable any big-endian related features
725 of your chipset/board/processor.
726
Catalin Marinas26584852009-05-30 14:00:18 +0100727config CPU_ENDIAN_BE8
728 bool
729 depends on CPU_BIG_ENDIAN
Russell Kinge399b1a2011-01-17 15:08:32 +0000730 default CPU_V6 || CPU_V6K || CPU_V7
Catalin Marinas26584852009-05-30 14:00:18 +0100731 help
732 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
733
734config CPU_ENDIAN_BE32
735 bool
736 depends on CPU_BIG_ENDIAN
737 default !CPU_ENDIAN_BE8
738 help
739 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
740
Hyok S. Choi6afd6fa2006-09-28 21:46:34 +0900741config CPU_HIGH_VECTOR
Robert P. J. Day6340aa62007-02-17 19:05:24 +0100742 depends on !MMU && CPU_CP15 && !CPU_ARM740T
Hyok S. Choi6afd6fa2006-09-28 21:46:34 +0900743 bool "Select the High exception vector"
Hyok S. Choi6afd6fa2006-09-28 21:46:34 +0900744 help
745 Say Y here to select high exception vector(0xFFFF0000~).
Will Deacon9b7333a2012-04-12 17:12:37 +0100746 The exception vector can vary depending on the platform
Hyok S. Choi6afd6fa2006-09-28 21:46:34 +0900747 design in nommu mode. If your platform needs to select
748 high exception vector, say Y.
749 Otherwise or if you are unsure, say N, and the low exception
750 vector (0x00000000~) will be used.
751
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752config CPU_ICACHE_DISABLE
Hyok S. Choif12d0d72006-09-26 17:36:37 +0900753 bool "Disable I-Cache (I-bit)"
Russell King357c9c12012-05-04 12:04:26 +0100754 depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700755 help
756 Say Y here to disable the processor instruction cache. Unless
757 you have a reason not to or are unsure, say N.
758
759config CPU_DCACHE_DISABLE
Hyok S. Choif12d0d72006-09-26 17:36:37 +0900760 bool "Disable D-Cache (C-bit)"
Florian Fainellie1e2f6e2015-01-09 19:34:43 +0100761 depends on CPU_CP15 && !SMP
Linus Torvalds1da177e2005-04-16 15:20:36 -0700762 help
763 Say Y here to disable the processor data cache. Unless
764 you have a reason not to or are unsure, say N.
765
Hyok S. Choif37f46e2006-09-26 17:38:32 +0900766config CPU_DCACHE_SIZE
767 hex
768 depends on CPU_ARM740T || CPU_ARM946E
769 default 0x00001000 if CPU_ARM740T
770 default 0x00002000 # default size for ARM946E-S
771 help
772 Some cores are synthesizable to have various sized cache. For
773 ARM946E-S case, it can vary from 0KB to 1MB.
774 To support such cache operations, it is efficient to know the size
775 before compile time.
776 If your SoC is configured to have a different size, define the value
777 here with proper conditions.
778
Linus Torvalds1da177e2005-04-16 15:20:36 -0700779config CPU_DCACHE_WRITETHROUGH
780 bool "Force write through D-cache"
Paulius Zaleckas28853ac2009-03-25 13:10:01 +0200781 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
Linus Torvalds1da177e2005-04-16 15:20:36 -0700782 default y if CPU_ARM925T
783 help
784 Say Y here to use the data cache in writethrough mode. Unless you
785 specifically require this or are unsure, say N.
786
787config CPU_CACHE_ROUND_ROBIN
788 bool "Round robin I and D cache replacement algorithm"
Hyok S. Choif37f46e2006-09-26 17:38:32 +0900789 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790 help
791 Say Y here to use the predictable round-robin cache replacement
792 policy. Unless you specifically require this or are unsure, say N.
793
794config CPU_BPREDICT_DISABLE
795 bool "Disable branch prediction"
Russell Kinge399b1a2011-01-17 15:08:32 +0000796 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
Linus Torvalds1da177e2005-04-16 15:20:36 -0700797 help
798 Say Y here to disable branch prediction. If unsure, say N.
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100799
Nicolas Pitre4b0e07a2005-05-05 23:24:45 +0100800config TLS_REG_EMUL
801 bool
Russell Kingf6f91b02013-07-23 18:37:00 +0100802 select NEED_KUSER_HELPERS
Nicolas Pitre4b0e07a2005-05-05 23:24:45 +0100803 help
Nicolas Pitre70489c82005-05-12 19:27:12 +0100804 An SMP system using a pre-ARMv6 processor (there are apparently
805 a few prototypes like that in existence) and therefore access to
806 that required register must be emulated.
Nicolas Pitre4b0e07a2005-05-05 23:24:45 +0100807
Nicolas Pitredcef1f62005-06-08 19:00:47 +0100808config NEEDS_SYSCALL_FOR_CMPXCHG
809 bool
Russell Kingf6f91b02013-07-23 18:37:00 +0100810 select NEED_KUSER_HELPERS
Nicolas Pitredcef1f62005-06-08 19:00:47 +0100811 help
812 SMP on a pre-ARMv6 processor? Well OK then.
813 Forget about fast user space cmpxchg support.
814 It is just not possible.
815
Russell Kingf6f91b02013-07-23 18:37:00 +0100816config NEED_KUSER_HELPERS
817 bool
818
819config KUSER_HELPERS
820 bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
Nathan Lynch08b964f2014-11-10 23:46:27 +0100821 depends on MMU
Russell Kingf6f91b02013-07-23 18:37:00 +0100822 default y
823 help
824 Warning: disabling this option may break user programs.
825
826 Provide kuser helpers in the vector page. The kernel provides
827 helper code to userspace in read only form at a fixed location
828 in the high vector page to allow userspace to be independent of
829 the CPU type fitted to the system. This permits binaries to be
830 run on ARMv4 through to ARMv7 without modification.
831
Nicolas Pitreac124502013-08-14 22:36:32 +0100832 See Documentation/arm/kernel_user_helpers.txt for details.
833
Russell Kingf6f91b02013-07-23 18:37:00 +0100834 However, the fixed address nature of these helpers can be used
835 by ROP (return orientated programming) authors when creating
836 exploits.
837
838 If all of the binaries and libraries which run on your platform
839 are built specifically for your platform, and make no use of
Nicolas Pitreac124502013-08-14 22:36:32 +0100840 these helpers, then you can turn this option off to hinder
841 such exploits. However, in that case, if a binary or library
842 relying on those helpers is run, it will receive a SIGILL signal,
843 which will terminate the program.
Russell Kingf6f91b02013-07-23 18:37:00 +0100844
845 Say N here only if you are absolutely certain that you do not
846 need these helpers; otherwise, the safe option is to say Y.
847
Nathan Lynche5b61de2015-03-25 19:16:05 +0100848config VDSO
849 bool "Enable VDSO for acceleration of some system calls"
Nathan Lynch5d380002015-04-17 21:51:38 +0100850 depends on AEABI && MMU && CPU_V7
Nathan Lynche5b61de2015-03-25 19:16:05 +0100851 default y if ARM_ARCH_TIMER
852 select GENERIC_TIME_VSYSCALL
853 help
854 Place in the process address space an ELF shared object
855 providing fast implementations of gettimeofday and
856 clock_gettime. Systems that implement the ARM architected
857 timer will receive maximum benefit.
858
859 You must have glibc 2.22 or later for programs to seamlessly
860 take advantage of this.
861
Catalin Marinasad642d92010-06-21 15:10:07 +0100862config DMA_CACHE_RWFO
863 bool "Enable read/write for ownership DMA cache maintenance"
Russell King3bc28c82011-01-18 13:30:33 +0000864 depends on CPU_V6K && SMP
Catalin Marinasad642d92010-06-21 15:10:07 +0100865 default y
866 help
867 The Snoop Control Unit on ARM11MPCore does not detect the
868 cache maintenance operations and the dma_{map,unmap}_area()
869 functions may leave stale cache entries on other CPUs. By
870 enabling this option, Read or Write For Ownership in the ARMv6
871 DMA cache maintenance functions is performed. These LDR/STR
872 instructions change the cache line state to shared or modified
873 so that the cache operation has the desired effect.
874
875 Note that the workaround is only valid on processors that do
876 not perform speculative loads into the D-cache. For such
877 processors, if cache maintenance operations are not broadcast
878 in hardware, other workarounds are needed (e.g. cache
879 maintenance broadcasting in software via FIQ).
880
Catalin Marinas953233d2007-02-05 14:48:08 +0100881config OUTER_CACHE
882 bool
Catalin Marinas382266a2007-02-05 14:48:19 +0100883
Catalin Marinas319f5512010-03-24 16:47:53 +0100884config OUTER_CACHE_SYNC
885 bool
886 help
887 The outer cache has a outer_cache_fns.sync function pointer
888 that can be used to drain the write buffer of the outer cache.
889
Lennert Buytenhek99c6dc12008-06-22 22:45:04 +0200890config CACHE_FEROCEON_L2
891 bool "Enable the Feroceon L2 cache controller"
Andrew Lunnba364fc2014-07-10 23:36:21 +0200892 depends on ARCH_MV78XX0 || ARCH_MVEBU
Lennert Buytenhek99c6dc12008-06-22 22:45:04 +0200893 default y
Catalin Marinas382266a2007-02-05 14:48:19 +0100894 select OUTER_CACHE
Lennert Buytenhek99c6dc12008-06-22 22:45:04 +0200895 help
896 This option enables the Feroceon L2 cache controller.
897
Ronen Shitrit4360bb42008-09-23 15:28:10 +0300898config CACHE_FEROCEON_L2_WRITETHROUGH
899 bool "Force Feroceon L2 cache write through"
900 depends on CACHE_FEROCEON_L2
Ronen Shitrit4360bb42008-09-23 15:28:10 +0300901 help
902 Say Y here to use the Feroceon L2 cache in writethrough mode.
903 Unless you specifically require this, say N for writeback mode.
904
Dave Martince5ea9f2011-11-29 15:56:19 +0000905config MIGHT_HAVE_CACHE_L2X0
906 bool
907 help
908 This option should be selected by machines which have a L2x0
909 or PL310 cache controller, but where its use is optional.
910
911 The only effect of this option is to make CACHE_L2X0 and
912 related options available to the user for configuration.
913
914 Boards or SoCs which always require the cache controller
915 support to be present should select CACHE_L2X0 directly
916 instead of this option, thus preventing the user from
917 inadvertently configuring a broken kernel.
918
Linus Torvalds1da177e2005-04-16 15:20:36 -0700919config CACHE_L2X0
Dave Martince5ea9f2011-11-29 15:56:19 +0000920 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
921 default MIGHT_HAVE_CACHE_L2X0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700922 select OUTER_CACHE
Catalin Marinas23107c52010-03-24 16:48:53 +0100923 select OUTER_CACHE_SYNC
Catalin Marinasba927952008-04-18 22:43:17 +0100924 help
925 This option enables the L2x0 PrimeCell.
Eric Miao905a09d2008-06-06 16:34:03 +0800926
Russell Kinga641f3a2014-06-19 10:19:10 +0100927if CACHE_L2X0
928
Russell Kingc0fe18b2014-03-16 12:12:11 +0000929config PL310_ERRATA_588369
930 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
Russell Kingc0fe18b2014-03-16 12:12:11 +0000931 help
932 The PL310 L2 cache controller implements three types of Clean &
933 Invalidate maintenance operations: by Physical Address
934 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
935 They are architecturally defined to behave as the execution of a
936 clean operation followed immediately by an invalidate operation,
937 both performing to the same memory location. This functionality
Shawn Guo80d3cb92014-07-08 02:59:42 +0100938 is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
939 as clean lines are not invalidated as a result of these operations.
Russell Kingc0fe18b2014-03-16 12:12:11 +0000940
941config PL310_ERRATA_727915
942 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
Russell Kingc0fe18b2014-03-16 12:12:11 +0000943 help
944 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
945 operation (offset 0x7FC). This operation runs in background so that
946 PL310 can handle normal accesses while it is in progress. Under very
947 rare circumstances, due to this erratum, write data can be lost when
948 PL310 treats a cacheable write transaction during a Clean &
Shawn Guo80d3cb92014-07-08 02:59:42 +0100949 Invalidate by Way operation. Revisions prior to r3p1 are affected by
950 this errata (fixed in r3p1).
Russell Kingc0fe18b2014-03-16 12:12:11 +0000951
952config PL310_ERRATA_753970
953 bool "PL310 errata: cache sync operation may be faulty"
Russell Kingc0fe18b2014-03-16 12:12:11 +0000954 help
955 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
956
957 Under some condition the effect of cache sync operation on
958 the store buffer still remains when the operation completes.
959 This means that the store buffer is always asked to drain and
960 this prevents it from merging any further writes. The workaround
961 is to replace the normal offset of cache sync operation (0x730)
962 by another offset targeting an unmapped PL310 register 0x740.
963 This has the same effect as the cache sync operation: store buffer
964 drain and waiting for all buffers empty.
965
966config PL310_ERRATA_769419
967 bool "PL310 errata: no automatic Store Buffer drain"
Russell Kingc0fe18b2014-03-16 12:12:11 +0000968 help
969 On revisions of the PL310 prior to r3p2, the Store Buffer does
970 not automatically drain. This can cause normal, non-cacheable
971 writes to be retained when the memory system is idle, leading
972 to suboptimal I/O performance for drivers using coherent DMA.
973 This option adds a write barrier to the cpu_idle loop so that,
974 on systems with an outer cache, the store buffer is drained
975 explicitly.
976
Russell Kinga641f3a2014-06-19 10:19:10 +0100977endif
978
Lennert Buytenhek573a6522009-11-24 19:33:52 +0200979config CACHE_TAUROS2
980 bool "Enable the Tauros2 L2 cache controller"
Haojian Zhuang3f408fa2010-11-24 11:54:21 +0800981 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
Lennert Buytenhek573a6522009-11-24 19:33:52 +0200982 default y
983 select OUTER_CACHE
984 help
985 This option enables the Tauros2 L2 cache controller (as
986 found on PJ1/PJ4).
987
Eric Miao905a09d2008-06-06 16:34:03 +0800988config CACHE_XSC3L2
989 bool "Enable the L2 cache on XScale3"
990 depends on CPU_XSC3
991 default y
992 select OUTER_CACHE
993 help
994 This option enables the L2 cache on XScale3.
Kirill A. Shutemov910a17e2009-09-15 10:23:53 +0100995
Russell King5637a122011-02-14 15:55:45 +0000996config ARM_L1_CACHE_SHIFT_6
997 bool
Will Deacona092f2b2012-01-20 12:01:10 +0100998 default y if CPU_V7
Russell King5637a122011-02-14 15:55:45 +0000999 help
1000 Setting ARM L1 cache line size to 64 Bytes.
1001
Kirill A. Shutemov910a17e2009-09-15 10:23:53 +01001002config ARM_L1_CACHE_SHIFT
1003 int
Kukjin Kimd6d502f2010-02-22 00:02:59 +01001004 default 6 if ARM_L1_CACHE_SHIFT_6
Kirill A. Shutemov910a17e2009-09-15 10:23:53 +01001005 default 5
Russell King47ab0de2010-05-15 11:02:43 +01001006
1007config ARM_DMA_MEM_BUFFERABLE
Russell Kinge399b1a2011-01-17 15:08:32 +00001008 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
Catalin Marinas42c4daf2010-07-01 13:22:48 +01001009 depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
1010 MACH_REALVIEW_PB11MP)
Russell Kinge399b1a2011-01-17 15:08:32 +00001011 default y if CPU_V6 || CPU_V6K || CPU_V7
Russell King47ab0de2010-05-15 11:02:43 +01001012 help
1013 Historically, the kernel has used strongly ordered mappings to
1014 provide DMA coherent memory. With the advent of ARMv7, mapping
1015 memory with differing types results in unpredictable behaviour,
1016 so on these CPUs, this option is forced on.
1017
1018 Multiple mappings with differing attributes is also unpredictable
1019 on ARMv6 CPUs, but since they do not have aggressive speculative
1020 prefetch, no harm appears to occur.
1021
1022 However, drivers may be missing the necessary barriers for ARMv6,
1023 and therefore turning this on may result in unpredictable driver
1024 behaviour. Therefore, we offer this as an option.
1025
1026 You are recommended say 'Y' here and debug any affected drivers.
Russell Kingac1d4262010-05-17 17:24:04 +01001027
Catalin Marinase7c56502010-03-24 16:49:54 +01001028config ARCH_HAS_BARRIERS
1029 bool
1030 help
1031 This option allows the use of custom mandatory barriers
1032 included via the mach/barriers.h file.
Ben Dooksd10d2d42013-02-01 09:41:37 +00001033
1034config ARCH_SUPPORTS_BIG_ENDIAN
1035 bool
1036 help
1037 This option specifies the architecture can support big endian
1038 operation.
Kees Cook1e6b4812014-04-03 17:28:11 -07001039
1040config ARM_KERNMEM_PERMS
1041 bool "Restrict kernel memory permissions"
Arnd Bergmannfba28902015-01-28 17:58:33 +01001042 depends on MMU
Kees Cook1e6b4812014-04-03 17:28:11 -07001043 help
1044 If this is set, kernel memory other than kernel text (and rodata)
1045 will be made non-executable. The tradeoff is that each region is
1046 padded to section-size (1MiB) boundaries (because their permissions
1047 are different and splitting the 1M pages into 4K ones causes TLB
1048 performance problems), wasting memory.
Kees Cook80d6b0c2014-04-03 13:29:50 -07001049
1050config DEBUG_RODATA
1051 bool "Make kernel text and rodata read-only"
1052 depends on ARM_KERNMEM_PERMS
1053 default y
1054 help
1055 If this is set, kernel text and rodata will be made read-only. This
1056 is to help catch accidental or malicious attempts to change the
1057 kernel's executable code. Additionally splits rodata from kernel
1058 text so it can be made explicitly non-executable. This creates
1059 another section-size padded region, so it can waste more memory
1060 space while gaining the read-only protections.