Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | comment "Processor Type" |
| 2 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | # Select CPU types depending on the architecture selected. This selects |
| 4 | # which CPUs we support in the kernel image, and the compiler instruction |
| 5 | # optimiser behaviour. |
| 6 | |
Hyok S. Choi | 07e0da7 | 2006-09-26 17:37:36 +0900 | [diff] [blame] | 7 | # ARM7TDMI |
| 8 | config CPU_ARM7TDMI |
Arnd Bergmann | c32b765 | 2015-05-26 15:40:16 +0100 | [diff] [blame] | 9 | bool |
Russell King | 6b237a3 | 2006-09-27 17:44:39 +0100 | [diff] [blame] | 10 | depends on !MMU |
Hyok S. Choi | 07e0da7 | 2006-09-26 17:37:36 +0900 | [diff] [blame] | 11 | select CPU_32v4T |
| 12 | select CPU_ABRT_LV4T |
| 13 | select CPU_CACHE_V4 |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 14 | select CPU_PABRT_LEGACY |
Hyok S. Choi | 07e0da7 | 2006-09-26 17:37:36 +0900 | [diff] [blame] | 15 | help |
| 16 | A 32-bit RISC microprocessor based on the ARM7 processor core |
| 17 | which has no memory control unit and cache. |
| 18 | |
| 19 | Say Y if you want support for the ARM7TDMI processor. |
| 20 | Otherwise, say N. |
| 21 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | # ARM720T |
| 23 | config CPU_ARM720T |
Linus Walleij | dc680b9 | 2014-11-10 18:52:31 +0100 | [diff] [blame] | 24 | bool "Support ARM720T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR) |
Lennert Buytenhek | 260e98e | 2006-08-28 12:51:20 +0100 | [diff] [blame] | 25 | select CPU_32v4T |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 26 | select CPU_ABRT_LV4T |
| 27 | select CPU_CACHE_V4 |
| 28 | select CPU_CACHE_VIVT |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 29 | select CPU_COPY_V4WT if MMU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 30 | select CPU_CP15_MMU |
| 31 | select CPU_PABRT_LEGACY |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 32 | select CPU_TLB_V4WT if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 33 | help |
| 34 | A 32-bit RISC processor with 8kByte Cache, Write Buffer and |
| 35 | MMU built around an ARM7TDMI core. |
| 36 | |
| 37 | Say Y if you want support for the ARM720T processor. |
| 38 | Otherwise, say N. |
| 39 | |
Hyok S. Choi | b731c31 | 2006-09-26 17:37:50 +0900 | [diff] [blame] | 40 | # ARM740T |
| 41 | config CPU_ARM740T |
Linus Walleij | dc680b9 | 2014-11-10 18:52:31 +0100 | [diff] [blame] | 42 | bool "Support ARM740T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR) |
Russell King | 6b237a3 | 2006-09-27 17:44:39 +0100 | [diff] [blame] | 43 | depends on !MMU |
Hyok S. Choi | b731c31 | 2006-09-26 17:37:50 +0900 | [diff] [blame] | 44 | select CPU_32v4T |
| 45 | select CPU_ABRT_LV4T |
Will Deacon | 82d9b0d | 2013-01-15 12:07:40 +0000 | [diff] [blame] | 46 | select CPU_CACHE_V4 |
Hyok S. Choi | b731c31 | 2006-09-26 17:37:50 +0900 | [diff] [blame] | 47 | select CPU_CP15_MPU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 48 | select CPU_PABRT_LEGACY |
Hyok S. Choi | b731c31 | 2006-09-26 17:37:50 +0900 | [diff] [blame] | 49 | help |
| 50 | A 32-bit RISC processor with 8KB cache or 4KB variants, |
| 51 | write buffer and MPU(Protection Unit) built around |
| 52 | an ARM7TDMI core. |
| 53 | |
| 54 | Say Y if you want support for the ARM740T processor. |
| 55 | Otherwise, say N. |
| 56 | |
Hyok S. Choi | 43f5f01 | 2006-09-26 17:38:05 +0900 | [diff] [blame] | 57 | # ARM9TDMI |
| 58 | config CPU_ARM9TDMI |
Arnd Bergmann | c32b765 | 2015-05-26 15:40:16 +0100 | [diff] [blame] | 59 | bool |
Russell King | 6b237a3 | 2006-09-27 17:44:39 +0100 | [diff] [blame] | 60 | depends on !MMU |
Hyok S. Choi | 43f5f01 | 2006-09-26 17:38:05 +0900 | [diff] [blame] | 61 | select CPU_32v4T |
Hyok S. Choi | 0f45d7f | 2006-09-28 21:46:16 +0900 | [diff] [blame] | 62 | select CPU_ABRT_NOMMU |
Hyok S. Choi | 43f5f01 | 2006-09-26 17:38:05 +0900 | [diff] [blame] | 63 | select CPU_CACHE_V4 |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 64 | select CPU_PABRT_LEGACY |
Hyok S. Choi | 43f5f01 | 2006-09-26 17:38:05 +0900 | [diff] [blame] | 65 | help |
| 66 | A 32-bit RISC microprocessor based on the ARM9 processor core |
| 67 | which has no memory control unit and cache. |
| 68 | |
| 69 | Say Y if you want support for the ARM9TDMI processor. |
| 70 | Otherwise, say N. |
| 71 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 72 | # ARM920T |
| 73 | config CPU_ARM920T |
Linus Walleij | dc680b9 | 2014-11-10 18:52:31 +0100 | [diff] [blame] | 74 | bool "Support ARM920T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR) |
Lennert Buytenhek | 260e98e | 2006-08-28 12:51:20 +0100 | [diff] [blame] | 75 | select CPU_32v4T |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 76 | select CPU_ABRT_EV4T |
| 77 | select CPU_CACHE_V4WT |
| 78 | select CPU_CACHE_VIVT |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 79 | select CPU_COPY_V4WB if MMU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 80 | select CPU_CP15_MMU |
| 81 | select CPU_PABRT_LEGACY |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 82 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | help |
| 84 | The ARM920T is licensed to be produced by numerous vendors, |
Hartley Sweeten | c768e676 | 2009-10-21 02:27:01 +0100 | [diff] [blame] | 85 | and is used in the Cirrus EP93xx and the Samsung S3C2410. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 86 | |
| 87 | Say Y if you want support for the ARM920T processor. |
| 88 | Otherwise, say N. |
| 89 | |
| 90 | # ARM922T |
| 91 | config CPU_ARM922T |
Linus Walleij | dc680b9 | 2014-11-10 18:52:31 +0100 | [diff] [blame] | 92 | bool "Support ARM922T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR) |
Lennert Buytenhek | 260e98e | 2006-08-28 12:51:20 +0100 | [diff] [blame] | 93 | select CPU_32v4T |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 94 | select CPU_ABRT_EV4T |
| 95 | select CPU_CACHE_V4WT |
| 96 | select CPU_CACHE_VIVT |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 97 | select CPU_COPY_V4WB if MMU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 98 | select CPU_CP15_MMU |
| 99 | select CPU_PABRT_LEGACY |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 100 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 101 | help |
| 102 | The ARM922T is a version of the ARM920T, but with smaller |
| 103 | instruction and data caches. It is used in Altera's |
Andrew Victor | c53c9cf | 2007-05-11 21:01:28 +0100 | [diff] [blame] | 104 | Excalibur XA device family and Micrel's KS8695 Centaur. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 105 | |
| 106 | Say Y if you want support for the ARM922T processor. |
| 107 | Otherwise, say N. |
| 108 | |
| 109 | # ARM925T |
| 110 | config CPU_ARM925T |
Tony Lindgren | b288f75 | 2005-07-10 19:58:08 +0100 | [diff] [blame] | 111 | bool "Support ARM925T processor" if ARCH_OMAP1 |
Lennert Buytenhek | 260e98e | 2006-08-28 12:51:20 +0100 | [diff] [blame] | 112 | select CPU_32v4T |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 113 | select CPU_ABRT_EV4T |
| 114 | select CPU_CACHE_V4WT |
| 115 | select CPU_CACHE_VIVT |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 116 | select CPU_COPY_V4WB if MMU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 117 | select CPU_CP15_MMU |
| 118 | select CPU_PABRT_LEGACY |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 119 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 120 | help |
| 121 | The ARM925T is a mix between the ARM920T and ARM926T, but with |
| 122 | different instruction and data caches. It is used in TI's OMAP |
| 123 | device family. |
| 124 | |
| 125 | Say Y if you want support for the ARM925T processor. |
| 126 | Otherwise, say N. |
| 127 | |
| 128 | # ARM926T |
| 129 | config CPU_ARM926T |
Linus Walleij | dc680b9 | 2014-11-10 18:52:31 +0100 | [diff] [blame] | 130 | bool "Support ARM926T processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V5) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 131 | select CPU_32v5 |
| 132 | select CPU_ABRT_EV5TJ |
| 133 | select CPU_CACHE_VIVT |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 134 | select CPU_COPY_V4WB if MMU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 135 | select CPU_CP15_MMU |
| 136 | select CPU_PABRT_LEGACY |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 137 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 138 | help |
| 139 | This is a variant of the ARM920. It has slightly different |
| 140 | instruction sequences for cache and TLB operations. Curiously, |
| 141 | there is no documentation on it at the ARM corporate website. |
| 142 | |
| 143 | Say Y if you want support for the ARM926T processor. |
| 144 | Otherwise, say N. |
| 145 | |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 146 | # FA526 |
| 147 | config CPU_FA526 |
| 148 | bool |
| 149 | select CPU_32v4 |
| 150 | select CPU_ABRT_EV4 |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 151 | select CPU_CACHE_FA |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 152 | select CPU_CACHE_VIVT |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 153 | select CPU_COPY_FA if MMU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 154 | select CPU_CP15_MMU |
| 155 | select CPU_PABRT_LEGACY |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 156 | select CPU_TLB_FA if MMU |
| 157 | help |
| 158 | The FA526 is a version of the ARMv4 compatible processor with |
| 159 | Branch Target Buffer, Unified TLB and cache line size 16. |
| 160 | |
| 161 | Say Y if you want support for the FA526 processor. |
| 162 | Otherwise, say N. |
| 163 | |
Hyok S. Choi | d60674e | 2006-09-26 17:38:18 +0900 | [diff] [blame] | 164 | # ARM940T |
| 165 | config CPU_ARM940T |
Linus Walleij | dc680b9 | 2014-11-10 18:52:31 +0100 | [diff] [blame] | 166 | bool "Support ARM940T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR) |
Russell King | 6b237a3 | 2006-09-27 17:44:39 +0100 | [diff] [blame] | 167 | depends on !MMU |
Hyok S. Choi | d60674e | 2006-09-26 17:38:18 +0900 | [diff] [blame] | 168 | select CPU_32v4T |
Hyok S. Choi | 0f45d7f | 2006-09-28 21:46:16 +0900 | [diff] [blame] | 169 | select CPU_ABRT_NOMMU |
Hyok S. Choi | d60674e | 2006-09-26 17:38:18 +0900 | [diff] [blame] | 170 | select CPU_CACHE_VIVT |
| 171 | select CPU_CP15_MPU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 172 | select CPU_PABRT_LEGACY |
Hyok S. Choi | d60674e | 2006-09-26 17:38:18 +0900 | [diff] [blame] | 173 | help |
| 174 | ARM940T is a member of the ARM9TDMI family of general- |
Matt LaPlante | 3cb2fcc | 2006-11-30 05:22:59 +0100 | [diff] [blame] | 175 | purpose microprocessors with MPU and separate 4KB |
Hyok S. Choi | d60674e | 2006-09-26 17:38:18 +0900 | [diff] [blame] | 176 | instruction and 4KB data cases, each with a 4-word line |
| 177 | length. |
| 178 | |
| 179 | Say Y if you want support for the ARM940T processor. |
| 180 | Otherwise, say N. |
| 181 | |
Hyok S. Choi | f37f46e | 2006-09-26 17:38:32 +0900 | [diff] [blame] | 182 | # ARM946E-S |
| 183 | config CPU_ARM946E |
Linus Walleij | dc680b9 | 2014-11-10 18:52:31 +0100 | [diff] [blame] | 184 | bool "Support ARM946E-S processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR) |
Russell King | 6b237a3 | 2006-09-27 17:44:39 +0100 | [diff] [blame] | 185 | depends on !MMU |
Hyok S. Choi | f37f46e | 2006-09-26 17:38:32 +0900 | [diff] [blame] | 186 | select CPU_32v5 |
Hyok S. Choi | 0f45d7f | 2006-09-28 21:46:16 +0900 | [diff] [blame] | 187 | select CPU_ABRT_NOMMU |
Hyok S. Choi | f37f46e | 2006-09-26 17:38:32 +0900 | [diff] [blame] | 188 | select CPU_CACHE_VIVT |
| 189 | select CPU_CP15_MPU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 190 | select CPU_PABRT_LEGACY |
Hyok S. Choi | f37f46e | 2006-09-26 17:38:32 +0900 | [diff] [blame] | 191 | help |
| 192 | ARM946E-S is a member of the ARM9E-S family of high- |
| 193 | performance, 32-bit system-on-chip processor solutions. |
| 194 | The TCM and ARMv5TE 32-bit instruction set is supported. |
| 195 | |
| 196 | Say Y if you want support for the ARM946E-S processor. |
| 197 | Otherwise, say N. |
| 198 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 199 | # ARM1020 - needs validating |
| 200 | config CPU_ARM1020 |
Linus Walleij | dc680b9 | 2014-11-10 18:52:31 +0100 | [diff] [blame] | 201 | bool "Support ARM1020T (rev 0) processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 202 | select CPU_32v5 |
| 203 | select CPU_ABRT_EV4T |
| 204 | select CPU_CACHE_V4WT |
| 205 | select CPU_CACHE_VIVT |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 206 | select CPU_COPY_V4WB if MMU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 207 | select CPU_CP15_MMU |
| 208 | select CPU_PABRT_LEGACY |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 209 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 210 | help |
| 211 | The ARM1020 is the 32K cached version of the ARM10 processor, |
| 212 | with an addition of a floating-point unit. |
| 213 | |
| 214 | Say Y if you want support for the ARM1020 processor. |
| 215 | Otherwise, say N. |
| 216 | |
| 217 | # ARM1020E - needs validating |
| 218 | config CPU_ARM1020E |
Linus Walleij | dc680b9 | 2014-11-10 18:52:31 +0100 | [diff] [blame] | 219 | bool "Support ARM1020E processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR) |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 220 | depends on n |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 221 | select CPU_32v5 |
| 222 | select CPU_ABRT_EV4T |
| 223 | select CPU_CACHE_V4WT |
| 224 | select CPU_CACHE_VIVT |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 225 | select CPU_COPY_V4WB if MMU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 226 | select CPU_CP15_MMU |
| 227 | select CPU_PABRT_LEGACY |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 228 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 229 | |
| 230 | # ARM1022E |
| 231 | config CPU_ARM1022 |
Linus Walleij | dc680b9 | 2014-11-10 18:52:31 +0100 | [diff] [blame] | 232 | bool "Support ARM1022E processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 233 | select CPU_32v5 |
| 234 | select CPU_ABRT_EV4T |
| 235 | select CPU_CACHE_VIVT |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 236 | select CPU_COPY_V4WB if MMU # can probably do better |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 237 | select CPU_CP15_MMU |
| 238 | select CPU_PABRT_LEGACY |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 239 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 240 | help |
| 241 | The ARM1022E is an implementation of the ARMv5TE architecture |
| 242 | based upon the ARM10 integer core with a 16KiB L1 Harvard cache, |
| 243 | embedded trace macrocell, and a floating-point unit. |
| 244 | |
| 245 | Say Y if you want support for the ARM1022E processor. |
| 246 | Otherwise, say N. |
| 247 | |
| 248 | # ARM1026EJ-S |
| 249 | config CPU_ARM1026 |
Linus Walleij | dc680b9 | 2014-11-10 18:52:31 +0100 | [diff] [blame] | 250 | bool "Support ARM1026EJ-S processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 251 | select CPU_32v5 |
| 252 | select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 |
| 253 | select CPU_CACHE_VIVT |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 254 | select CPU_COPY_V4WB if MMU # can probably do better |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 255 | select CPU_CP15_MMU |
| 256 | select CPU_PABRT_LEGACY |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 257 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 258 | help |
| 259 | The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture |
| 260 | based upon the ARM10 integer core. |
| 261 | |
| 262 | Say Y if you want support for the ARM1026EJ-S processor. |
| 263 | Otherwise, say N. |
| 264 | |
| 265 | # SA110 |
| 266 | config CPU_SA110 |
Arnd Bergmann | fa04e20 | 2014-02-26 17:39:12 +0100 | [diff] [blame] | 267 | bool |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 268 | select CPU_32v3 if ARCH_RPC |
| 269 | select CPU_32v4 if !ARCH_RPC |
| 270 | select CPU_ABRT_EV4 |
| 271 | select CPU_CACHE_V4WB |
| 272 | select CPU_CACHE_VIVT |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 273 | select CPU_COPY_V4WB if MMU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 274 | select CPU_CP15_MMU |
| 275 | select CPU_PABRT_LEGACY |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 276 | select CPU_TLB_V4WB if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 277 | help |
| 278 | The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and |
| 279 | is available at five speeds ranging from 100 MHz to 233 MHz. |
| 280 | More information is available at |
| 281 | <http://developer.intel.com/design/strong/sa110.htm>. |
| 282 | |
| 283 | Say Y if you want support for the SA-110 processor. |
| 284 | Otherwise, say N. |
| 285 | |
| 286 | # SA1100 |
| 287 | config CPU_SA1100 |
| 288 | bool |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 289 | select CPU_32v4 |
| 290 | select CPU_ABRT_EV4 |
| 291 | select CPU_CACHE_V4WB |
| 292 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 293 | select CPU_CP15_MMU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 294 | select CPU_PABRT_LEGACY |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 295 | select CPU_TLB_V4WB if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 296 | |
| 297 | # XScale |
| 298 | config CPU_XSCALE |
| 299 | bool |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 300 | select CPU_32v5 |
| 301 | select CPU_ABRT_EV5T |
| 302 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 303 | select CPU_CP15_MMU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 304 | select CPU_PABRT_LEGACY |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 305 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 306 | |
Lennert Buytenhek | 23bdf86 | 2006-03-28 21:00:40 +0100 | [diff] [blame] | 307 | # XScale Core Version 3 |
| 308 | config CPU_XSC3 |
| 309 | bool |
Lennert Buytenhek | 23bdf86 | 2006-03-28 21:00:40 +0100 | [diff] [blame] | 310 | select CPU_32v5 |
| 311 | select CPU_ABRT_EV5T |
| 312 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 313 | select CPU_CP15_MMU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 314 | select CPU_PABRT_LEGACY |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 315 | select CPU_TLB_V4WBI if MMU |
Lennert Buytenhek | 23bdf86 | 2006-03-28 21:00:40 +0100 | [diff] [blame] | 316 | select IO_36 |
| 317 | |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 318 | # Marvell PJ1 (Mohawk) |
| 319 | config CPU_MOHAWK |
| 320 | bool |
| 321 | select CPU_32v5 |
| 322 | select CPU_ABRT_EV5T |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 323 | select CPU_CACHE_VIVT |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 324 | select CPU_COPY_V4WB if MMU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 325 | select CPU_CP15_MMU |
| 326 | select CPU_PABRT_LEGACY |
| 327 | select CPU_TLB_V4WBI if MMU |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 328 | |
Assaf Hoffman | e50d640 | 2007-10-23 15:14:41 -0400 | [diff] [blame] | 329 | # Feroceon |
| 330 | config CPU_FEROCEON |
| 331 | bool |
Assaf Hoffman | e50d640 | 2007-10-23 15:14:41 -0400 | [diff] [blame] | 332 | select CPU_32v5 |
| 333 | select CPU_ABRT_EV5T |
| 334 | select CPU_CACHE_VIVT |
Lennert Buytenhek | 0ed1507 | 2008-04-24 01:31:45 -0400 | [diff] [blame] | 335 | select CPU_COPY_FEROCEON if MMU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 336 | select CPU_CP15_MMU |
| 337 | select CPU_PABRT_LEGACY |
Lennert Buytenhek | 99c6dc1 | 2008-06-22 22:45:04 +0200 | [diff] [blame] | 338 | select CPU_TLB_FEROCEON if MMU |
Assaf Hoffman | e50d640 | 2007-10-23 15:14:41 -0400 | [diff] [blame] | 339 | |
Tzachi Perelstein | d910a0a | 2007-11-06 10:35:40 +0200 | [diff] [blame] | 340 | config CPU_FEROCEON_OLD_ID |
| 341 | bool "Accept early Feroceon cores with an ARM926 ID" |
| 342 | depends on CPU_FEROCEON && !CPU_ARM926T |
| 343 | default y |
| 344 | help |
| 345 | This enables the usage of some old Feroceon cores |
| 346 | for which the CPU ID is equal to the ARM926 ID. |
| 347 | Relevant for Feroceon-1850 and early Feroceon-2850. |
| 348 | |
Haojian Zhuang | a455335 | 2010-11-24 11:54:19 +0800 | [diff] [blame] | 349 | # Marvell PJ4 |
| 350 | config CPU_PJ4 |
| 351 | bool |
Haojian Zhuang | a455335 | 2010-11-24 11:54:19 +0800 | [diff] [blame] | 352 | select ARM_THUMBEE |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 353 | select CPU_V7 |
Haojian Zhuang | a455335 | 2010-11-24 11:54:19 +0800 | [diff] [blame] | 354 | |
Gregory CLEMENT | de49019 | 2012-10-03 11:58:07 +0200 | [diff] [blame] | 355 | config CPU_PJ4B |
| 356 | bool |
| 357 | select CPU_V7 |
| 358 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 359 | # ARMv6 |
| 360 | config CPU_V6 |
Linus Walleij | dc680b9 | 2014-11-10 18:52:31 +0100 | [diff] [blame] | 361 | bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 362 | select CPU_32v6 |
| 363 | select CPU_ABRT_EV6 |
| 364 | select CPU_CACHE_V6 |
| 365 | select CPU_CACHE_VIPT |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 366 | select CPU_COPY_V6 if MMU |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 367 | select CPU_CP15_MMU |
Catalin Marinas | 7b4c965 | 2007-07-20 11:42:57 +0100 | [diff] [blame] | 368 | select CPU_HAS_ASID if MMU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 369 | select CPU_PABRT_V6 |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 370 | select CPU_TLB_V6 if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 371 | |
Russell King | 4a5f79e | 2005-11-03 15:48:21 +0000 | [diff] [blame] | 372 | # ARMv6k |
Russell King | e399b1a | 2011-01-17 15:08:32 +0000 | [diff] [blame] | 373 | config CPU_V6K |
Linus Walleij | dc680b9 | 2014-11-10 18:52:31 +0100 | [diff] [blame] | 374 | bool "Support ARM V6K processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX) |
Russell King | e399b1a | 2011-01-17 15:08:32 +0000 | [diff] [blame] | 375 | select CPU_32v6 |
Russell King | 60799c6 | 2011-01-15 16:25:04 +0000 | [diff] [blame] | 376 | select CPU_32v6K |
Russell King | e399b1a | 2011-01-17 15:08:32 +0000 | [diff] [blame] | 377 | select CPU_ABRT_EV6 |
Russell King | e399b1a | 2011-01-17 15:08:32 +0000 | [diff] [blame] | 378 | select CPU_CACHE_V6 |
| 379 | select CPU_CACHE_VIPT |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 380 | select CPU_COPY_V6 if MMU |
Russell King | e399b1a | 2011-01-17 15:08:32 +0000 | [diff] [blame] | 381 | select CPU_CP15_MMU |
| 382 | select CPU_HAS_ASID if MMU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 383 | select CPU_PABRT_V6 |
Russell King | e399b1a | 2011-01-17 15:08:32 +0000 | [diff] [blame] | 384 | select CPU_TLB_V6 if MMU |
Russell King | 4a5f79e | 2005-11-03 15:48:21 +0000 | [diff] [blame] | 385 | |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 386 | # ARMv7 |
| 387 | config CPU_V7 |
Linus Walleij | dc680b9 | 2014-11-10 18:52:31 +0100 | [diff] [blame] | 388 | bool "Support ARM V7 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V7) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX) |
Russell King | 15490ef | 2011-02-09 16:33:46 +0000 | [diff] [blame] | 389 | select CPU_32v6K |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 390 | select CPU_32v7 |
| 391 | select CPU_ABRT_EV7 |
| 392 | select CPU_CACHE_V7 |
| 393 | select CPU_CACHE_VIPT |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 394 | select CPU_COPY_V6 if MMU |
Jonathan Austin | 6656761 | 2012-07-12 14:38:46 +0100 | [diff] [blame] | 395 | select CPU_CP15_MMU if MMU |
| 396 | select CPU_CP15_MPU if !MMU |
Catalin Marinas | 2eb8c82 | 2007-07-20 11:43:02 +0100 | [diff] [blame] | 397 | select CPU_HAS_ASID if MMU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 398 | select CPU_PABRT_V7 |
Catalin Marinas | 2ccdd1e | 2007-05-18 11:25:31 +0100 | [diff] [blame] | 399 | select CPU_TLB_V7 if MMU |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 400 | |
Uwe Kleine-König | 4477ca4 | 2013-03-21 21:02:37 +0100 | [diff] [blame] | 401 | # ARMv7M |
| 402 | config CPU_V7M |
| 403 | bool |
| 404 | select CPU_32v7M |
| 405 | select CPU_ABRT_NOMMU |
| 406 | select CPU_CACHE_NOP |
| 407 | select CPU_PABRT_LEGACY |
| 408 | select CPU_THUMBONLY |
| 409 | |
Uwe Kleine-König | bc7dea0 | 2011-12-09 20:52:10 +0100 | [diff] [blame] | 410 | config CPU_THUMBONLY |
| 411 | bool |
| 412 | # There are no CPUs available with MMU that don't implement an ARM ISA: |
| 413 | depends on !MMU |
| 414 | help |
| 415 | Select this if your CPU doesn't support the 32 bit ARM instructions. |
| 416 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 417 | # Figure out what processor architecture version we should be using. |
| 418 | # This defines the compiler instruction set which depends on the machine type. |
| 419 | config CPU_32v3 |
| 420 | bool |
Russell King | 8762df4 | 2011-01-17 15:53:56 +0000 | [diff] [blame] | 421 | select CPU_USE_DOMAINS if MMU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 422 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
Russell King | f6f91b0 | 2013-07-23 18:37:00 +0100 | [diff] [blame] | 423 | select NEED_KUSER_HELPERS |
Russell King | 51aaf81 | 2014-04-22 22:26:27 +0100 | [diff] [blame] | 424 | select TLS_REG_EMUL if SMP || !MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 425 | |
| 426 | config CPU_32v4 |
| 427 | bool |
Russell King | 8762df4 | 2011-01-17 15:53:56 +0000 | [diff] [blame] | 428 | select CPU_USE_DOMAINS if MMU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 429 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
Russell King | f6f91b0 | 2013-07-23 18:37:00 +0100 | [diff] [blame] | 430 | select NEED_KUSER_HELPERS |
Russell King | 51aaf81 | 2014-04-22 22:26:27 +0100 | [diff] [blame] | 431 | select TLS_REG_EMUL if SMP || !MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 432 | |
Lennert Buytenhek | 260e98e | 2006-08-28 12:51:20 +0100 | [diff] [blame] | 433 | config CPU_32v4T |
| 434 | bool |
Russell King | 8762df4 | 2011-01-17 15:53:56 +0000 | [diff] [blame] | 435 | select CPU_USE_DOMAINS if MMU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 436 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
Russell King | f6f91b0 | 2013-07-23 18:37:00 +0100 | [diff] [blame] | 437 | select NEED_KUSER_HELPERS |
Russell King | 51aaf81 | 2014-04-22 22:26:27 +0100 | [diff] [blame] | 438 | select TLS_REG_EMUL if SMP || !MMU |
Lennert Buytenhek | 260e98e | 2006-08-28 12:51:20 +0100 | [diff] [blame] | 439 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 440 | config CPU_32v5 |
| 441 | bool |
Russell King | 8762df4 | 2011-01-17 15:53:56 +0000 | [diff] [blame] | 442 | select CPU_USE_DOMAINS if MMU |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 443 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
Russell King | f6f91b0 | 2013-07-23 18:37:00 +0100 | [diff] [blame] | 444 | select NEED_KUSER_HELPERS |
Russell King | 51aaf81 | 2014-04-22 22:26:27 +0100 | [diff] [blame] | 445 | select TLS_REG_EMUL if SMP || !MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 446 | |
| 447 | config CPU_32v6 |
| 448 | bool |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 449 | select TLS_REG_EMUL if !CPU_32v6K && !MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 450 | |
Russell King | e399b1a | 2011-01-17 15:08:32 +0000 | [diff] [blame] | 451 | config CPU_32v6K |
Russell King | 60799c6 | 2011-01-15 16:25:04 +0000 | [diff] [blame] | 452 | bool |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 453 | |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 454 | config CPU_32v7 |
| 455 | bool |
| 456 | |
Uwe Kleine-König | 4477ca4 | 2013-03-21 21:02:37 +0100 | [diff] [blame] | 457 | config CPU_32v7M |
| 458 | bool |
| 459 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 460 | # The abort model |
Hyok S. Choi | 0f45d7f | 2006-09-28 21:46:16 +0900 | [diff] [blame] | 461 | config CPU_ABRT_NOMMU |
| 462 | bool |
| 463 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 464 | config CPU_ABRT_EV4 |
| 465 | bool |
| 466 | |
| 467 | config CPU_ABRT_EV4T |
| 468 | bool |
| 469 | |
| 470 | config CPU_ABRT_LV4T |
| 471 | bool |
| 472 | |
| 473 | config CPU_ABRT_EV5T |
| 474 | bool |
| 475 | |
| 476 | config CPU_ABRT_EV5TJ |
| 477 | bool |
| 478 | |
| 479 | config CPU_ABRT_EV6 |
| 480 | bool |
| 481 | |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 482 | config CPU_ABRT_EV7 |
| 483 | bool |
| 484 | |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 485 | config CPU_PABRT_LEGACY |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 486 | bool |
| 487 | |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 488 | config CPU_PABRT_V6 |
| 489 | bool |
| 490 | |
| 491 | config CPU_PABRT_V7 |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 492 | bool |
| 493 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 494 | # The cache model |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 495 | config CPU_CACHE_V4 |
| 496 | bool |
| 497 | |
| 498 | config CPU_CACHE_V4WT |
| 499 | bool |
| 500 | |
| 501 | config CPU_CACHE_V4WB |
| 502 | bool |
| 503 | |
| 504 | config CPU_CACHE_V6 |
| 505 | bool |
| 506 | |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 507 | config CPU_CACHE_V7 |
| 508 | bool |
| 509 | |
Uwe Kleine-König | 4477ca4 | 2013-03-21 21:02:37 +0100 | [diff] [blame] | 510 | config CPU_CACHE_NOP |
| 511 | bool |
| 512 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 513 | config CPU_CACHE_VIVT |
| 514 | bool |
| 515 | |
| 516 | config CPU_CACHE_VIPT |
| 517 | bool |
| 518 | |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 519 | config CPU_CACHE_FA |
| 520 | bool |
| 521 | |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 522 | if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 523 | # The copy-page model |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 524 | config CPU_COPY_V4WT |
| 525 | bool |
| 526 | |
| 527 | config CPU_COPY_V4WB |
| 528 | bool |
| 529 | |
Lennert Buytenhek | 0ed1507 | 2008-04-24 01:31:45 -0400 | [diff] [blame] | 530 | config CPU_COPY_FEROCEON |
| 531 | bool |
| 532 | |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 533 | config CPU_COPY_FA |
| 534 | bool |
| 535 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 536 | config CPU_COPY_V6 |
| 537 | bool |
| 538 | |
| 539 | # This selects the TLB model |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 540 | config CPU_TLB_V4WT |
| 541 | bool |
| 542 | help |
| 543 | ARM Architecture Version 4 TLB with writethrough cache. |
| 544 | |
| 545 | config CPU_TLB_V4WB |
| 546 | bool |
| 547 | help |
| 548 | ARM Architecture Version 4 TLB with writeback cache. |
| 549 | |
| 550 | config CPU_TLB_V4WBI |
| 551 | bool |
| 552 | help |
| 553 | ARM Architecture Version 4 TLB with writeback cache and invalidate |
| 554 | instruction cache entry. |
| 555 | |
Lennert Buytenhek | 99c6dc1 | 2008-06-22 22:45:04 +0200 | [diff] [blame] | 556 | config CPU_TLB_FEROCEON |
| 557 | bool |
| 558 | help |
| 559 | Feroceon TLB (v4wbi with non-outer-cachable page table walks). |
| 560 | |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 561 | config CPU_TLB_FA |
| 562 | bool |
| 563 | help |
| 564 | Faraday ARM FA526 architecture, unified TLB with writeback cache |
| 565 | and invalidate instruction cache entry. Branch target buffer is |
| 566 | also supported. |
| 567 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 568 | config CPU_TLB_V6 |
| 569 | bool |
| 570 | |
Catalin Marinas | 2ccdd1e | 2007-05-18 11:25:31 +0100 | [diff] [blame] | 571 | config CPU_TLB_V7 |
| 572 | bool |
| 573 | |
Dave Estes | e220ba6 | 2009-08-11 17:58:49 -0400 | [diff] [blame] | 574 | config VERIFY_PERMISSION_FAULT |
| 575 | bool |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 576 | endif |
| 577 | |
Russell King | 516793c | 2007-05-17 10:19:23 +0100 | [diff] [blame] | 578 | config CPU_HAS_ASID |
| 579 | bool |
| 580 | help |
| 581 | This indicates whether the CPU has the ASID register; used to |
| 582 | tag TLB and possibly cache entries. |
| 583 | |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 584 | config CPU_CP15 |
| 585 | bool |
| 586 | help |
| 587 | Processor has the CP15 register. |
| 588 | |
| 589 | config CPU_CP15_MMU |
| 590 | bool |
| 591 | select CPU_CP15 |
| 592 | help |
| 593 | Processor has the CP15 register, which has MMU related registers. |
| 594 | |
| 595 | config CPU_CP15_MPU |
| 596 | bool |
| 597 | select CPU_CP15 |
| 598 | help |
| 599 | Processor has the CP15 register, which has MPU related registers. |
| 600 | |
Catalin Marinas | 247055a | 2010-09-13 16:03:21 +0100 | [diff] [blame] | 601 | config CPU_USE_DOMAINS |
| 602 | bool |
Catalin Marinas | 247055a | 2010-09-13 16:03:21 +0100 | [diff] [blame] | 603 | help |
| 604 | This option enables or disables the use of domain switching |
| 605 | via the set_fs() function. |
| 606 | |
Maxime Coquelin stm32 | 6b1814c | 2015-04-10 09:46:46 +0100 | [diff] [blame] | 607 | config CPU_V7M_NUM_IRQ |
| 608 | int "Number of external interrupts connected to the NVIC" |
| 609 | depends on CPU_V7M |
| 610 | default 90 if ARCH_STM32 |
| 611 | default 38 if ARCH_EFM32 |
Stefan Agner | 45b0fa0 | 2015-05-20 00:16:46 +0100 | [diff] [blame] | 612 | default 112 if SOC_VF610 |
Maxime Coquelin stm32 | 6b1814c | 2015-04-10 09:46:46 +0100 | [diff] [blame] | 613 | default 240 |
| 614 | help |
| 615 | This option indicates the number of interrupts connected to the NVIC. |
| 616 | The value can be larger than the real number of interrupts supported |
| 617 | by the system, but must not be lower. |
| 618 | The default value is 240, corresponding to the maximum number of |
| 619 | interrupts supported by the NVIC on Cortex-M family. |
| 620 | |
| 621 | If unsure, keep default value. |
| 622 | |
Lennert Buytenhek | 23bdf86 | 2006-03-28 21:00:40 +0100 | [diff] [blame] | 623 | # |
| 624 | # CPU supports 36-bit I/O |
| 625 | # |
| 626 | config IO_36 |
| 627 | bool |
| 628 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 629 | comment "Processor Features" |
| 630 | |
Catalin Marinas | 497b7e9 | 2011-11-22 17:30:32 +0000 | [diff] [blame] | 631 | config ARM_LPAE |
| 632 | bool "Support for the Large Physical Address Extension" |
Catalin Marinas | 08a183f | 2012-02-14 16:33:27 +0100 | [diff] [blame] | 633 | depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \ |
| 634 | !CPU_32v4 && !CPU_32v3 |
Catalin Marinas | 497b7e9 | 2011-11-22 17:30:32 +0000 | [diff] [blame] | 635 | help |
| 636 | Say Y if you have an ARMv7 processor supporting the LPAE page |
| 637 | table format and you would like to access memory beyond the |
| 638 | 4GB limit. The resulting kernel image will not run on |
| 639 | processors without the LPA extension. |
| 640 | |
| 641 | If unsure, say N. |
| 642 | |
Russell King | d8dc7fb | 2015-04-04 16:58:38 +0100 | [diff] [blame] | 643 | config ARM_PV_FIXUP |
| 644 | def_bool y |
| 645 | depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE |
| 646 | |
Catalin Marinas | 497b7e9 | 2011-11-22 17:30:32 +0000 | [diff] [blame] | 647 | config ARCH_PHYS_ADDR_T_64BIT |
| 648 | def_bool ARM_LPAE |
| 649 | |
| 650 | config ARCH_DMA_ADDR_T_64BIT |
| 651 | bool |
| 652 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 653 | config ARM_THUMB |
Uwe Kleine-König | bc7dea0 | 2011-12-09 20:52:10 +0100 | [diff] [blame] | 654 | bool "Support Thumb user binaries" if !CPU_THUMBONLY |
Uwe Kleine-König | 4477ca4 | 2013-03-21 21:02:37 +0100 | [diff] [blame] | 655 | depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \ |
| 656 | CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \ |
| 657 | CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ |
| 658 | CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \ |
| 659 | CPU_V7 || CPU_FEROCEON || CPU_V7M |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 660 | default y |
| 661 | help |
| 662 | Say Y if you want to include kernel support for running user space |
| 663 | Thumb binaries. |
| 664 | |
| 665 | The Thumb instruction set is a compressed form of the standard ARM |
| 666 | instruction set resulting in smaller binaries at the expense of |
| 667 | slightly less efficient code. |
| 668 | |
| 669 | If you don't know what this all is, saying Y is a safe choice. |
| 670 | |
Catalin Marinas | d7f864b | 2008-04-18 22:43:06 +0100 | [diff] [blame] | 671 | config ARM_THUMBEE |
| 672 | bool "Enable ThumbEE CPU extension" |
| 673 | depends on CPU_V7 |
| 674 | help |
| 675 | Say Y here if you have a CPU with the ThumbEE extension and code to |
| 676 | make use of it. Say N for code that can run on CPUs without ThumbEE. |
| 677 | |
Dave Martin | 5b6728d | 2012-02-17 16:54:28 +0000 | [diff] [blame] | 678 | config ARM_VIRT_EXT |
Will Deacon | 651134b | 2013-01-09 14:29:33 +0000 | [diff] [blame] | 679 | bool |
| 680 | depends on MMU |
| 681 | default y if CPU_V7 |
Dave Martin | 5b6728d | 2012-02-17 16:54:28 +0000 | [diff] [blame] | 682 | help |
| 683 | Enable the kernel to make use of the ARM Virtualization |
| 684 | Extensions to install hypervisors without run-time firmware |
| 685 | assistance. |
| 686 | |
| 687 | A compliant bootloader is required in order to make maximum |
| 688 | use of this feature. Refer to Documentation/arm/Booting for |
| 689 | details. |
| 690 | |
Leif Lindholm | 64d2dc3 | 2010-09-16 18:00:47 +0100 | [diff] [blame] | 691 | config SWP_EMULATE |
Russell King | a11dd73 | 2014-07-04 14:44:36 +0100 | [diff] [blame] | 692 | bool "Emulate SWP/SWPB instructions" if !SMP |
Will Deacon | b6ccb98 | 2014-02-07 19:12:27 +0100 | [diff] [blame] | 693 | depends on CPU_V7 |
Leif Lindholm | 64d2dc3 | 2010-09-16 18:00:47 +0100 | [diff] [blame] | 694 | default y if SMP |
Russell King | b1b3f49 | 2012-10-06 17:12:25 +0100 | [diff] [blame] | 695 | select HAVE_PROC_CPU if PROC_FS |
Leif Lindholm | 64d2dc3 | 2010-09-16 18:00:47 +0100 | [diff] [blame] | 696 | help |
| 697 | ARMv6 architecture deprecates use of the SWP/SWPB instructions. |
| 698 | ARMv7 multiprocessing extensions introduce the ability to disable |
| 699 | these instructions, triggering an undefined instruction exception |
| 700 | when executed. Say Y here to enable software emulation of these |
| 701 | instructions for userspace (not kernel) using LDREX/STREX. |
| 702 | Also creates /proc/cpu/swp_emulation for statistics. |
| 703 | |
| 704 | In some older versions of glibc [<=2.8] SWP is used during futex |
| 705 | trylock() operations with the assumption that the code will not |
| 706 | be preempted. This invalid assumption may be more likely to fail |
| 707 | with SWP emulation enabled, leading to deadlock of the user |
| 708 | application. |
| 709 | |
| 710 | NOTE: when accessing uncached shared regions, LDREX/STREX rely |
| 711 | on an external transaction monitoring block called a global |
| 712 | monitor to maintain update atomicity. If your system does not |
| 713 | implement a global monitor, this option can cause programs that |
| 714 | perform SWP operations to uncached memory to deadlock. |
| 715 | |
| 716 | If unsure, say Y. |
| 717 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 718 | config CPU_BIG_ENDIAN |
| 719 | bool "Build big-endian kernel" |
| 720 | depends on ARCH_SUPPORTS_BIG_ENDIAN |
| 721 | help |
| 722 | Say Y if you plan on running a kernel in big-endian mode. |
| 723 | Note that your board must be properly built and your board |
| 724 | port must properly enable any big-endian related features |
| 725 | of your chipset/board/processor. |
| 726 | |
Catalin Marinas | 2658485 | 2009-05-30 14:00:18 +0100 | [diff] [blame] | 727 | config CPU_ENDIAN_BE8 |
| 728 | bool |
| 729 | depends on CPU_BIG_ENDIAN |
Russell King | e399b1a | 2011-01-17 15:08:32 +0000 | [diff] [blame] | 730 | default CPU_V6 || CPU_V6K || CPU_V7 |
Catalin Marinas | 2658485 | 2009-05-30 14:00:18 +0100 | [diff] [blame] | 731 | help |
| 732 | Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors. |
| 733 | |
| 734 | config CPU_ENDIAN_BE32 |
| 735 | bool |
| 736 | depends on CPU_BIG_ENDIAN |
| 737 | default !CPU_ENDIAN_BE8 |
| 738 | help |
| 739 | Support for the BE-32 (big-endian) mode on pre-ARMv6 processors. |
| 740 | |
Hyok S. Choi | 6afd6fa | 2006-09-28 21:46:34 +0900 | [diff] [blame] | 741 | config CPU_HIGH_VECTOR |
Robert P. J. Day | 6340aa6 | 2007-02-17 19:05:24 +0100 | [diff] [blame] | 742 | depends on !MMU && CPU_CP15 && !CPU_ARM740T |
Hyok S. Choi | 6afd6fa | 2006-09-28 21:46:34 +0900 | [diff] [blame] | 743 | bool "Select the High exception vector" |
Hyok S. Choi | 6afd6fa | 2006-09-28 21:46:34 +0900 | [diff] [blame] | 744 | help |
| 745 | Say Y here to select high exception vector(0xFFFF0000~). |
Will Deacon | 9b7333a | 2012-04-12 17:12:37 +0100 | [diff] [blame] | 746 | The exception vector can vary depending on the platform |
Hyok S. Choi | 6afd6fa | 2006-09-28 21:46:34 +0900 | [diff] [blame] | 747 | design in nommu mode. If your platform needs to select |
| 748 | high exception vector, say Y. |
| 749 | Otherwise or if you are unsure, say N, and the low exception |
| 750 | vector (0x00000000~) will be used. |
| 751 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 752 | config CPU_ICACHE_DISABLE |
Hyok S. Choi | f12d0d7 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 753 | bool "Disable I-Cache (I-bit)" |
Russell King | 357c9c1 | 2012-05-04 12:04:26 +0100 | [diff] [blame] | 754 | depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 755 | help |
| 756 | Say Y here to disable the processor instruction cache. Unless |
| 757 | you have a reason not to or are unsure, say N. |
| 758 | |
| 759 | config CPU_DCACHE_DISABLE |
Hyok S. Choi | f12d0d7 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 760 | bool "Disable D-Cache (C-bit)" |
Florian Fainelli | e1e2f6e | 2015-01-09 19:34:43 +0100 | [diff] [blame] | 761 | depends on CPU_CP15 && !SMP |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 762 | help |
| 763 | Say Y here to disable the processor data cache. Unless |
| 764 | you have a reason not to or are unsure, say N. |
| 765 | |
Hyok S. Choi | f37f46e | 2006-09-26 17:38:32 +0900 | [diff] [blame] | 766 | config CPU_DCACHE_SIZE |
| 767 | hex |
| 768 | depends on CPU_ARM740T || CPU_ARM946E |
| 769 | default 0x00001000 if CPU_ARM740T |
| 770 | default 0x00002000 # default size for ARM946E-S |
| 771 | help |
| 772 | Some cores are synthesizable to have various sized cache. For |
| 773 | ARM946E-S case, it can vary from 0KB to 1MB. |
| 774 | To support such cache operations, it is efficient to know the size |
| 775 | before compile time. |
| 776 | If your SoC is configured to have a different size, define the value |
| 777 | here with proper conditions. |
| 778 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 779 | config CPU_DCACHE_WRITETHROUGH |
| 780 | bool "Force write through D-cache" |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 781 | depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 782 | default y if CPU_ARM925T |
| 783 | help |
| 784 | Say Y here to use the data cache in writethrough mode. Unless you |
| 785 | specifically require this or are unsure, say N. |
| 786 | |
| 787 | config CPU_CACHE_ROUND_ROBIN |
| 788 | bool "Round robin I and D cache replacement algorithm" |
Hyok S. Choi | f37f46e | 2006-09-26 17:38:32 +0900 | [diff] [blame] | 789 | depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 790 | help |
| 791 | Say Y here to use the predictable round-robin cache replacement |
| 792 | policy. Unless you specifically require this or are unsure, say N. |
| 793 | |
| 794 | config CPU_BPREDICT_DISABLE |
| 795 | bool "Disable branch prediction" |
Russell King | e399b1a | 2011-01-17 15:08:32 +0000 | [diff] [blame] | 796 | depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 797 | help |
| 798 | Say Y here to disable branch prediction. If unsure, say N. |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 799 | |
Nicolas Pitre | 4b0e07a | 2005-05-05 23:24:45 +0100 | [diff] [blame] | 800 | config TLS_REG_EMUL |
| 801 | bool |
Russell King | f6f91b0 | 2013-07-23 18:37:00 +0100 | [diff] [blame] | 802 | select NEED_KUSER_HELPERS |
Nicolas Pitre | 4b0e07a | 2005-05-05 23:24:45 +0100 | [diff] [blame] | 803 | help |
Nicolas Pitre | 70489c8 | 2005-05-12 19:27:12 +0100 | [diff] [blame] | 804 | An SMP system using a pre-ARMv6 processor (there are apparently |
| 805 | a few prototypes like that in existence) and therefore access to |
| 806 | that required register must be emulated. |
Nicolas Pitre | 4b0e07a | 2005-05-05 23:24:45 +0100 | [diff] [blame] | 807 | |
Nicolas Pitre | dcef1f6 | 2005-06-08 19:00:47 +0100 | [diff] [blame] | 808 | config NEEDS_SYSCALL_FOR_CMPXCHG |
| 809 | bool |
Russell King | f6f91b0 | 2013-07-23 18:37:00 +0100 | [diff] [blame] | 810 | select NEED_KUSER_HELPERS |
Nicolas Pitre | dcef1f6 | 2005-06-08 19:00:47 +0100 | [diff] [blame] | 811 | help |
| 812 | SMP on a pre-ARMv6 processor? Well OK then. |
| 813 | Forget about fast user space cmpxchg support. |
| 814 | It is just not possible. |
| 815 | |
Russell King | f6f91b0 | 2013-07-23 18:37:00 +0100 | [diff] [blame] | 816 | config NEED_KUSER_HELPERS |
| 817 | bool |
| 818 | |
| 819 | config KUSER_HELPERS |
| 820 | bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS |
Nathan Lynch | 08b964f | 2014-11-10 23:46:27 +0100 | [diff] [blame] | 821 | depends on MMU |
Russell King | f6f91b0 | 2013-07-23 18:37:00 +0100 | [diff] [blame] | 822 | default y |
| 823 | help |
| 824 | Warning: disabling this option may break user programs. |
| 825 | |
| 826 | Provide kuser helpers in the vector page. The kernel provides |
| 827 | helper code to userspace in read only form at a fixed location |
| 828 | in the high vector page to allow userspace to be independent of |
| 829 | the CPU type fitted to the system. This permits binaries to be |
| 830 | run on ARMv4 through to ARMv7 without modification. |
| 831 | |
Nicolas Pitre | ac12450 | 2013-08-14 22:36:32 +0100 | [diff] [blame] | 832 | See Documentation/arm/kernel_user_helpers.txt for details. |
| 833 | |
Russell King | f6f91b0 | 2013-07-23 18:37:00 +0100 | [diff] [blame] | 834 | However, the fixed address nature of these helpers can be used |
| 835 | by ROP (return orientated programming) authors when creating |
| 836 | exploits. |
| 837 | |
| 838 | If all of the binaries and libraries which run on your platform |
| 839 | are built specifically for your platform, and make no use of |
Nicolas Pitre | ac12450 | 2013-08-14 22:36:32 +0100 | [diff] [blame] | 840 | these helpers, then you can turn this option off to hinder |
| 841 | such exploits. However, in that case, if a binary or library |
| 842 | relying on those helpers is run, it will receive a SIGILL signal, |
| 843 | which will terminate the program. |
Russell King | f6f91b0 | 2013-07-23 18:37:00 +0100 | [diff] [blame] | 844 | |
| 845 | Say N here only if you are absolutely certain that you do not |
| 846 | need these helpers; otherwise, the safe option is to say Y. |
| 847 | |
Nathan Lynch | e5b61de | 2015-03-25 19:16:05 +0100 | [diff] [blame] | 848 | config VDSO |
| 849 | bool "Enable VDSO for acceleration of some system calls" |
Nathan Lynch | 5d38000 | 2015-04-17 21:51:38 +0100 | [diff] [blame] | 850 | depends on AEABI && MMU && CPU_V7 |
Nathan Lynch | e5b61de | 2015-03-25 19:16:05 +0100 | [diff] [blame] | 851 | default y if ARM_ARCH_TIMER |
| 852 | select GENERIC_TIME_VSYSCALL |
| 853 | help |
| 854 | Place in the process address space an ELF shared object |
| 855 | providing fast implementations of gettimeofday and |
| 856 | clock_gettime. Systems that implement the ARM architected |
| 857 | timer will receive maximum benefit. |
| 858 | |
| 859 | You must have glibc 2.22 or later for programs to seamlessly |
| 860 | take advantage of this. |
| 861 | |
Catalin Marinas | ad642d9 | 2010-06-21 15:10:07 +0100 | [diff] [blame] | 862 | config DMA_CACHE_RWFO |
| 863 | bool "Enable read/write for ownership DMA cache maintenance" |
Russell King | 3bc28c8 | 2011-01-18 13:30:33 +0000 | [diff] [blame] | 864 | depends on CPU_V6K && SMP |
Catalin Marinas | ad642d9 | 2010-06-21 15:10:07 +0100 | [diff] [blame] | 865 | default y |
| 866 | help |
| 867 | The Snoop Control Unit on ARM11MPCore does not detect the |
| 868 | cache maintenance operations and the dma_{map,unmap}_area() |
| 869 | functions may leave stale cache entries on other CPUs. By |
| 870 | enabling this option, Read or Write For Ownership in the ARMv6 |
| 871 | DMA cache maintenance functions is performed. These LDR/STR |
| 872 | instructions change the cache line state to shared or modified |
| 873 | so that the cache operation has the desired effect. |
| 874 | |
| 875 | Note that the workaround is only valid on processors that do |
| 876 | not perform speculative loads into the D-cache. For such |
| 877 | processors, if cache maintenance operations are not broadcast |
| 878 | in hardware, other workarounds are needed (e.g. cache |
| 879 | maintenance broadcasting in software via FIQ). |
| 880 | |
Catalin Marinas | 953233d | 2007-02-05 14:48:08 +0100 | [diff] [blame] | 881 | config OUTER_CACHE |
| 882 | bool |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 883 | |
Catalin Marinas | 319f551 | 2010-03-24 16:47:53 +0100 | [diff] [blame] | 884 | config OUTER_CACHE_SYNC |
| 885 | bool |
| 886 | help |
| 887 | The outer cache has a outer_cache_fns.sync function pointer |
| 888 | that can be used to drain the write buffer of the outer cache. |
| 889 | |
Lennert Buytenhek | 99c6dc1 | 2008-06-22 22:45:04 +0200 | [diff] [blame] | 890 | config CACHE_FEROCEON_L2 |
| 891 | bool "Enable the Feroceon L2 cache controller" |
Andrew Lunn | ba364fc | 2014-07-10 23:36:21 +0200 | [diff] [blame] | 892 | depends on ARCH_MV78XX0 || ARCH_MVEBU |
Lennert Buytenhek | 99c6dc1 | 2008-06-22 22:45:04 +0200 | [diff] [blame] | 893 | default y |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 894 | select OUTER_CACHE |
Lennert Buytenhek | 99c6dc1 | 2008-06-22 22:45:04 +0200 | [diff] [blame] | 895 | help |
| 896 | This option enables the Feroceon L2 cache controller. |
| 897 | |
Ronen Shitrit | 4360bb4 | 2008-09-23 15:28:10 +0300 | [diff] [blame] | 898 | config CACHE_FEROCEON_L2_WRITETHROUGH |
| 899 | bool "Force Feroceon L2 cache write through" |
| 900 | depends on CACHE_FEROCEON_L2 |
Ronen Shitrit | 4360bb4 | 2008-09-23 15:28:10 +0300 | [diff] [blame] | 901 | help |
| 902 | Say Y here to use the Feroceon L2 cache in writethrough mode. |
| 903 | Unless you specifically require this, say N for writeback mode. |
| 904 | |
Dave Martin | ce5ea9f | 2011-11-29 15:56:19 +0000 | [diff] [blame] | 905 | config MIGHT_HAVE_CACHE_L2X0 |
| 906 | bool |
| 907 | help |
| 908 | This option should be selected by machines which have a L2x0 |
| 909 | or PL310 cache controller, but where its use is optional. |
| 910 | |
| 911 | The only effect of this option is to make CACHE_L2X0 and |
| 912 | related options available to the user for configuration. |
| 913 | |
| 914 | Boards or SoCs which always require the cache controller |
| 915 | support to be present should select CACHE_L2X0 directly |
| 916 | instead of this option, thus preventing the user from |
| 917 | inadvertently configuring a broken kernel. |
| 918 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 919 | config CACHE_L2X0 |
Dave Martin | ce5ea9f | 2011-11-29 15:56:19 +0000 | [diff] [blame] | 920 | bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0 |
| 921 | default MIGHT_HAVE_CACHE_L2X0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 922 | select OUTER_CACHE |
Catalin Marinas | 23107c5 | 2010-03-24 16:48:53 +0100 | [diff] [blame] | 923 | select OUTER_CACHE_SYNC |
Catalin Marinas | ba92795 | 2008-04-18 22:43:17 +0100 | [diff] [blame] | 924 | help |
| 925 | This option enables the L2x0 PrimeCell. |
Eric Miao | 905a09d | 2008-06-06 16:34:03 +0800 | [diff] [blame] | 926 | |
Russell King | a641f3a | 2014-06-19 10:19:10 +0100 | [diff] [blame] | 927 | if CACHE_L2X0 |
| 928 | |
Russell King | c0fe18b | 2014-03-16 12:12:11 +0000 | [diff] [blame] | 929 | config PL310_ERRATA_588369 |
| 930 | bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" |
Russell King | c0fe18b | 2014-03-16 12:12:11 +0000 | [diff] [blame] | 931 | help |
| 932 | The PL310 L2 cache controller implements three types of Clean & |
| 933 | Invalidate maintenance operations: by Physical Address |
| 934 | (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). |
| 935 | They are architecturally defined to behave as the execution of a |
| 936 | clean operation followed immediately by an invalidate operation, |
| 937 | both performing to the same memory location. This functionality |
Shawn Guo | 80d3cb9 | 2014-07-08 02:59:42 +0100 | [diff] [blame] | 938 | is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0) |
| 939 | as clean lines are not invalidated as a result of these operations. |
Russell King | c0fe18b | 2014-03-16 12:12:11 +0000 | [diff] [blame] | 940 | |
| 941 | config PL310_ERRATA_727915 |
| 942 | bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" |
Russell King | c0fe18b | 2014-03-16 12:12:11 +0000 | [diff] [blame] | 943 | help |
| 944 | PL310 implements the Clean & Invalidate by Way L2 cache maintenance |
| 945 | operation (offset 0x7FC). This operation runs in background so that |
| 946 | PL310 can handle normal accesses while it is in progress. Under very |
| 947 | rare circumstances, due to this erratum, write data can be lost when |
| 948 | PL310 treats a cacheable write transaction during a Clean & |
Shawn Guo | 80d3cb9 | 2014-07-08 02:59:42 +0100 | [diff] [blame] | 949 | Invalidate by Way operation. Revisions prior to r3p1 are affected by |
| 950 | this errata (fixed in r3p1). |
Russell King | c0fe18b | 2014-03-16 12:12:11 +0000 | [diff] [blame] | 951 | |
| 952 | config PL310_ERRATA_753970 |
| 953 | bool "PL310 errata: cache sync operation may be faulty" |
Russell King | c0fe18b | 2014-03-16 12:12:11 +0000 | [diff] [blame] | 954 | help |
| 955 | This option enables the workaround for the 753970 PL310 (r3p0) erratum. |
| 956 | |
| 957 | Under some condition the effect of cache sync operation on |
| 958 | the store buffer still remains when the operation completes. |
| 959 | This means that the store buffer is always asked to drain and |
| 960 | this prevents it from merging any further writes. The workaround |
| 961 | is to replace the normal offset of cache sync operation (0x730) |
| 962 | by another offset targeting an unmapped PL310 register 0x740. |
| 963 | This has the same effect as the cache sync operation: store buffer |
| 964 | drain and waiting for all buffers empty. |
| 965 | |
| 966 | config PL310_ERRATA_769419 |
| 967 | bool "PL310 errata: no automatic Store Buffer drain" |
Russell King | c0fe18b | 2014-03-16 12:12:11 +0000 | [diff] [blame] | 968 | help |
| 969 | On revisions of the PL310 prior to r3p2, the Store Buffer does |
| 970 | not automatically drain. This can cause normal, non-cacheable |
| 971 | writes to be retained when the memory system is idle, leading |
| 972 | to suboptimal I/O performance for drivers using coherent DMA. |
| 973 | This option adds a write barrier to the cpu_idle loop so that, |
| 974 | on systems with an outer cache, the store buffer is drained |
| 975 | explicitly. |
| 976 | |
Russell King | a641f3a | 2014-06-19 10:19:10 +0100 | [diff] [blame] | 977 | endif |
| 978 | |
Lennert Buytenhek | 573a652 | 2009-11-24 19:33:52 +0200 | [diff] [blame] | 979 | config CACHE_TAUROS2 |
| 980 | bool "Enable the Tauros2 L2 cache controller" |
Haojian Zhuang | 3f408fa | 2010-11-24 11:54:21 +0800 | [diff] [blame] | 981 | depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4) |
Lennert Buytenhek | 573a652 | 2009-11-24 19:33:52 +0200 | [diff] [blame] | 982 | default y |
| 983 | select OUTER_CACHE |
| 984 | help |
| 985 | This option enables the Tauros2 L2 cache controller (as |
| 986 | found on PJ1/PJ4). |
| 987 | |
Eric Miao | 905a09d | 2008-06-06 16:34:03 +0800 | [diff] [blame] | 988 | config CACHE_XSC3L2 |
| 989 | bool "Enable the L2 cache on XScale3" |
| 990 | depends on CPU_XSC3 |
| 991 | default y |
| 992 | select OUTER_CACHE |
| 993 | help |
| 994 | This option enables the L2 cache on XScale3. |
Kirill A. Shutemov | 910a17e | 2009-09-15 10:23:53 +0100 | [diff] [blame] | 995 | |
Russell King | 5637a12 | 2011-02-14 15:55:45 +0000 | [diff] [blame] | 996 | config ARM_L1_CACHE_SHIFT_6 |
| 997 | bool |
Will Deacon | a092f2b | 2012-01-20 12:01:10 +0100 | [diff] [blame] | 998 | default y if CPU_V7 |
Russell King | 5637a12 | 2011-02-14 15:55:45 +0000 | [diff] [blame] | 999 | help |
| 1000 | Setting ARM L1 cache line size to 64 Bytes. |
| 1001 | |
Kirill A. Shutemov | 910a17e | 2009-09-15 10:23:53 +0100 | [diff] [blame] | 1002 | config ARM_L1_CACHE_SHIFT |
| 1003 | int |
Kukjin Kim | d6d502f | 2010-02-22 00:02:59 +0100 | [diff] [blame] | 1004 | default 6 if ARM_L1_CACHE_SHIFT_6 |
Kirill A. Shutemov | 910a17e | 2009-09-15 10:23:53 +0100 | [diff] [blame] | 1005 | default 5 |
Russell King | 47ab0de | 2010-05-15 11:02:43 +0100 | [diff] [blame] | 1006 | |
| 1007 | config ARM_DMA_MEM_BUFFERABLE |
Russell King | e399b1a | 2011-01-17 15:08:32 +0000 | [diff] [blame] | 1008 | bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7 |
Catalin Marinas | 42c4daf | 2010-07-01 13:22:48 +0100 | [diff] [blame] | 1009 | depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \ |
| 1010 | MACH_REALVIEW_PB11MP) |
Russell King | e399b1a | 2011-01-17 15:08:32 +0000 | [diff] [blame] | 1011 | default y if CPU_V6 || CPU_V6K || CPU_V7 |
Russell King | 47ab0de | 2010-05-15 11:02:43 +0100 | [diff] [blame] | 1012 | help |
| 1013 | Historically, the kernel has used strongly ordered mappings to |
| 1014 | provide DMA coherent memory. With the advent of ARMv7, mapping |
| 1015 | memory with differing types results in unpredictable behaviour, |
| 1016 | so on these CPUs, this option is forced on. |
| 1017 | |
| 1018 | Multiple mappings with differing attributes is also unpredictable |
| 1019 | on ARMv6 CPUs, but since they do not have aggressive speculative |
| 1020 | prefetch, no harm appears to occur. |
| 1021 | |
| 1022 | However, drivers may be missing the necessary barriers for ARMv6, |
| 1023 | and therefore turning this on may result in unpredictable driver |
| 1024 | behaviour. Therefore, we offer this as an option. |
| 1025 | |
| 1026 | You are recommended say 'Y' here and debug any affected drivers. |
Russell King | ac1d426 | 2010-05-17 17:24:04 +0100 | [diff] [blame] | 1027 | |
Catalin Marinas | e7c5650 | 2010-03-24 16:49:54 +0100 | [diff] [blame] | 1028 | config ARCH_HAS_BARRIERS |
| 1029 | bool |
| 1030 | help |
| 1031 | This option allows the use of custom mandatory barriers |
| 1032 | included via the mach/barriers.h file. |
Ben Dooks | d10d2d4 | 2013-02-01 09:41:37 +0000 | [diff] [blame] | 1033 | |
| 1034 | config ARCH_SUPPORTS_BIG_ENDIAN |
| 1035 | bool |
| 1036 | help |
| 1037 | This option specifies the architecture can support big endian |
| 1038 | operation. |
Kees Cook | 1e6b481 | 2014-04-03 17:28:11 -0700 | [diff] [blame] | 1039 | |
| 1040 | config ARM_KERNMEM_PERMS |
| 1041 | bool "Restrict kernel memory permissions" |
Arnd Bergmann | fba2890 | 2015-01-28 17:58:33 +0100 | [diff] [blame] | 1042 | depends on MMU |
Kees Cook | 1e6b481 | 2014-04-03 17:28:11 -0700 | [diff] [blame] | 1043 | help |
| 1044 | If this is set, kernel memory other than kernel text (and rodata) |
| 1045 | will be made non-executable. The tradeoff is that each region is |
| 1046 | padded to section-size (1MiB) boundaries (because their permissions |
| 1047 | are different and splitting the 1M pages into 4K ones causes TLB |
| 1048 | performance problems), wasting memory. |
Kees Cook | 80d6b0c | 2014-04-03 13:29:50 -0700 | [diff] [blame] | 1049 | |
| 1050 | config DEBUG_RODATA |
| 1051 | bool "Make kernel text and rodata read-only" |
| 1052 | depends on ARM_KERNMEM_PERMS |
| 1053 | default y |
| 1054 | help |
| 1055 | If this is set, kernel text and rodata will be made read-only. This |
| 1056 | is to help catch accidental or malicious attempts to change the |
| 1057 | kernel's executable code. Additionally splits rodata from kernel |
| 1058 | text so it can be made explicitly non-executable. This creates |
| 1059 | another section-size padded region, so it can waste more memory |
| 1060 | space while gaining the read-only protections. |