blob: 0c8c5e3375407fad8c6f666c596d1b2c155acc04 [file] [log] [blame]
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +02001/*
2 * Marvell Armada 370/XP SoC timer handling.
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 *
14 * Timer 0 is used as free-running clocksource, while timer 1 is
15 * used as clock_event_device.
Ezequiel Garcia7cd63922013-08-13 11:43:13 -030016 *
17 * ---
18 * Clocksource driver for Armada 370 and Armada XP SoC.
19 * This driver implements one compatible string for each SoC, given
20 * each has its own characteristics:
21 *
22 * * Armada 370 has no 25 MHz fixed timer.
23 *
24 * * Armada XP cannot work properly without such 25 MHz fixed timer as
25 * doing otherwise leads to using a clocksource whose frequency varies
26 * when doing cpufreq frequency changes.
27 *
28 * See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020029 */
30
31#include <linux/init.h>
32#include <linux/platform_device.h>
33#include <linux/kernel.h>
Gregory CLEMENT307c2bf2012-11-17 15:22:25 +010034#include <linux/clk.h>
Stephen Boyd5ddb6d22013-02-15 17:02:16 -080035#include <linux/cpu.h>
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020036#include <linux/timer.h>
37#include <linux/clockchips.h>
38#include <linux/interrupt.h>
39#include <linux/of.h>
40#include <linux/of_irq.h>
41#include <linux/of_address.h>
42#include <linux/irq.h>
43#include <linux/module.h>
Stephen Boyd38ff87f2013-06-01 23:39:40 -070044#include <linux/sched_clock.h>
Gregory CLEMENTddd3f692013-01-25 18:32:42 +010045#include <linux/percpu.h>
Thomas Petazzonif9a49ab2014-11-21 17:00:01 +010046#include <linux/syscore_ops.h>
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020047
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020048/*
49 * Timer block registers.
50 */
51#define TIMER_CTRL_OFF 0x0000
Ezequiel Garciaad48bd62013-08-13 11:43:10 -030052#define TIMER0_EN BIT(0)
53#define TIMER0_RELOAD_EN BIT(1)
54#define TIMER0_25MHZ BIT(11)
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020055#define TIMER0_DIV(div) ((div) << 19)
Ezequiel Garciaad48bd62013-08-13 11:43:10 -030056#define TIMER1_EN BIT(2)
57#define TIMER1_RELOAD_EN BIT(3)
58#define TIMER1_25MHZ BIT(12)
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020059#define TIMER1_DIV(div) ((div) << 22)
60#define TIMER_EVENTS_STATUS 0x0004
61#define TIMER0_CLR_MASK (~0x1)
62#define TIMER1_CLR_MASK (~0x100)
63#define TIMER0_RELOAD_OFF 0x0010
64#define TIMER0_VAL_OFF 0x0014
65#define TIMER1_RELOAD_OFF 0x0018
66#define TIMER1_VAL_OFF 0x001c
67
Gregory CLEMENTddd3f692013-01-25 18:32:42 +010068#define LCL_TIMER_EVENTS_STATUS 0x0028
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020069/* Global timers are connected to the coherency fabric clock, and the
70 below divider reduces their incrementing frequency. */
71#define TIMER_DIVIDER_SHIFT 5
72#define TIMER_DIVIDER (1 << TIMER_DIVIDER_SHIFT)
73
74/*
75 * SoC-specific data.
76 */
Gregory CLEMENTddd3f692013-01-25 18:32:42 +010077static void __iomem *timer_base, *local_base;
78static unsigned int timer_clk;
79static bool timer25Mhz = true;
Ezequiel Garcia08cb8e42013-12-02 11:39:56 +010080static u32 enable_mask;
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020081
82/*
83 * Number of timer ticks per jiffy.
84 */
85static u32 ticks_per_jiffy;
86
Stephen Boyd5ddb6d22013-02-15 17:02:16 -080087static struct clock_event_device __percpu *armada_370_xp_evt;
Gregory CLEMENTddd3f692013-01-25 18:32:42 +010088
Ezequiel Garcia35796982013-08-13 11:43:11 -030089static void local_timer_ctrl_clrset(u32 clr, u32 set)
90{
91 writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set,
92 local_base + TIMER_CTRL_OFF);
93}
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020094
Stephen Boydd9dbcbe2013-07-18 16:21:27 -070095static u64 notrace armada_370_xp_read_sched_clock(void)
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020096{
97 return ~readl(timer_base + TIMER0_VAL_OFF);
98}
99
100/*
101 * Clockevent handling.
102 */
103static int
104armada_370_xp_clkevt_next_event(unsigned long delta,
105 struct clock_event_device *dev)
106{
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200107 /*
108 * Clear clockevent timer interrupt.
109 */
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100110 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200111
112 /*
113 * Setup new clockevent timer value.
114 */
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100115 writel(delta, local_base + TIMER0_VAL_OFF);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200116
117 /*
118 * Enable the timer.
119 */
Ezequiel Garcia08cb8e42013-12-02 11:39:56 +0100120 local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200121 return 0;
122}
123
124static void
125armada_370_xp_clkevt_mode(enum clock_event_mode mode,
126 struct clock_event_device *dev)
127{
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200128 if (mode == CLOCK_EVT_MODE_PERIODIC) {
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100129
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200130 /*
131 * Setup timer to fire at 1/HZ intervals.
132 */
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100133 writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF);
134 writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200135
136 /*
137 * Enable timer.
138 */
Ezequiel Garcia08cb8e42013-12-02 11:39:56 +0100139 local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200140 } else {
141 /*
142 * Disable timer.
143 */
Ezequiel Garcia35796982013-08-13 11:43:11 -0300144 local_timer_ctrl_clrset(TIMER0_EN, 0);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200145
146 /*
147 * ACK pending timer interrupt.
148 */
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100149 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200150 }
151}
152
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800153static int armada_370_xp_clkevt_irq;
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200154
155static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id)
156{
157 /*
158 * ACK timer interrupt and call event handler.
159 */
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800160 struct clock_event_device *evt = dev_id;
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200161
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100162 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
163 evt->event_handler(evt);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200164
165 return IRQ_HANDLED;
166}
167
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100168/*
169 * Setup the local clock events for a CPU.
170 */
Paul Gortmaker8c37bb32013-06-19 11:32:08 -0400171static int armada_370_xp_timer_setup(struct clock_event_device *evt)
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100172{
Ezequiel Garcia35796982013-08-13 11:43:11 -0300173 u32 clr = 0, set = 0;
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100174 int cpu = smp_processor_id();
175
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100176 if (timer25Mhz)
Ezequiel Garcia35796982013-08-13 11:43:11 -0300177 set = TIMER0_25MHZ;
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100178 else
Ezequiel Garcia35796982013-08-13 11:43:11 -0300179 clr = TIMER0_25MHZ;
180 local_timer_ctrl_clrset(clr, set);
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100181
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800182 evt->name = "armada_370_xp_per_cpu_tick",
183 evt->features = CLOCK_EVT_FEAT_ONESHOT |
184 CLOCK_EVT_FEAT_PERIODIC;
185 evt->shift = 32,
186 evt->rating = 300,
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100187 evt->set_next_event = armada_370_xp_clkevt_next_event,
188 evt->set_mode = armada_370_xp_clkevt_mode,
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800189 evt->irq = armada_370_xp_clkevt_irq;
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100190 evt->cpumask = cpumask_of(cpu);
191
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100192 clockevents_config_and_register(evt, timer_clk, 1, 0xfffffffe);
193 enable_percpu_irq(evt->irq, 0);
194
195 return 0;
196}
197
Olof Johansson47dcd352013-07-23 14:51:34 -0700198static void armada_370_xp_timer_stop(struct clock_event_device *evt)
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100199{
200 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
201 disable_percpu_irq(evt->irq);
202}
203
Olof Johansson47dcd352013-07-23 14:51:34 -0700204static int armada_370_xp_timer_cpu_notify(struct notifier_block *self,
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800205 unsigned long action, void *hcpu)
206{
207 /*
208 * Grab cpu pointer in each case to avoid spurious
209 * preemptible warnings
210 */
211 switch (action & ~CPU_TASKS_FROZEN) {
212 case CPU_STARTING:
213 armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt));
214 break;
215 case CPU_DYING:
216 armada_370_xp_timer_stop(this_cpu_ptr(armada_370_xp_evt));
217 break;
218 }
219
220 return NOTIFY_OK;
221}
222
Olof Johansson47dcd352013-07-23 14:51:34 -0700223static struct notifier_block armada_370_xp_timer_cpu_nb = {
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800224 .notifier_call = armada_370_xp_timer_cpu_notify,
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200225};
226
Thomas Petazzonif9a49ab2014-11-21 17:00:01 +0100227static u32 timer0_ctrl_reg, timer0_local_ctrl_reg;
228
229static int armada_370_xp_timer_suspend(void)
230{
231 timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF);
232 timer0_local_ctrl_reg = readl(local_base + TIMER_CTRL_OFF);
233 return 0;
234}
235
236static void armada_370_xp_timer_resume(void)
237{
238 writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
239 writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
240 writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF);
241 writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF);
242}
243
244struct syscore_ops armada_370_xp_timer_syscore_ops = {
245 .suspend = armada_370_xp_timer_suspend,
246 .resume = armada_370_xp_timer_resume,
247};
248
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300249static void __init armada_370_xp_timer_common_init(struct device_node *np)
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200250{
Ezequiel Garcia35796982013-08-13 11:43:11 -0300251 u32 clr = 0, set = 0;
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100252 int res;
253
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200254 timer_base = of_iomap(np, 0);
255 WARN_ON(!timer_base);
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100256 local_base = of_iomap(np, 1);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200257
Ezequiel Garcia08cb8e42013-12-02 11:39:56 +0100258 if (timer25Mhz) {
Linus Torvaldsa4ae54f2013-09-16 16:10:26 -0400259 set = TIMER0_25MHZ;
Ezequiel Garcia08cb8e42013-12-02 11:39:56 +0100260 enable_mask = TIMER0_EN;
261 } else {
Ezequiel Garcia35796982013-08-13 11:43:11 -0300262 clr = TIMER0_25MHZ;
Ezequiel Garcia08cb8e42013-12-02 11:39:56 +0100263 enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
264 }
Ezequiel Garciac8af34b2014-02-19 17:05:26 -0300265 atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set);
Ezequiel Garcia35796982013-08-13 11:43:11 -0300266 local_timer_ctrl_clrset(clr, set);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200267
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100268 /*
269 * We use timer 0 as clocksource, and private(local) timer 0
270 * for clockevents
271 */
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800272 armada_370_xp_clkevt_irq = irq_of_parse_and_map(np, 4);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200273
274 ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
275
276 /*
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200277 * Setup free-running clocksource timer (interrupts
278 * disabled).
279 */
280 writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
281 writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
282
Ezequiel Garciac8af34b2014-02-19 17:05:26 -0300283 atomic_io_modify(timer_base + TIMER_CTRL_OFF,
284 TIMER0_RELOAD_EN | enable_mask,
285 TIMER0_RELOAD_EN | enable_mask);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200286
Ezequiel Garciac813eff2013-11-26 18:20:14 -0300287 /*
288 * Set scale and timer for sched_clock.
289 */
290 sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk);
291
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200292 clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
293 "armada_370_xp_clocksource",
294 timer_clk, 300, 32, clocksource_mmio_readl_down);
295
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800296 register_cpu_notifier(&armada_370_xp_timer_cpu_nb);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200297
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800298 armada_370_xp_evt = alloc_percpu(struct clock_event_device);
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100299
300
301 /*
302 * Setup clockevent timer (interrupt-driven).
303 */
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800304 res = request_percpu_irq(armada_370_xp_clkevt_irq,
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100305 armada_370_xp_timer_interrupt,
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800306 "armada_370_xp_per_cpu_tick",
307 armada_370_xp_evt);
308 /* Immediately configure the timer on the boot CPU */
309 if (!res)
310 armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt));
Thomas Petazzonif9a49ab2014-11-21 17:00:01 +0100311
312 register_syscore_ops(&armada_370_xp_timer_syscore_ops);
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100313}
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300314
315static void __init armada_xp_timer_init(struct device_node *np)
316{
Ezequiel Garcia5e9fe6c2013-08-20 12:45:53 -0300317 struct clk *clk = of_clk_get_by_name(np, "fixed");
318
319 /* The 25Mhz fixed clock is mandatory, and must always be available */
320 BUG_ON(IS_ERR(clk));
Ezequiel Garcia551f2fd2014-11-04 10:21:31 -0300321 clk_prepare_enable(clk);
Ezequiel Garcia5e9fe6c2013-08-20 12:45:53 -0300322 timer_clk = clk_get_rate(clk);
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300323
324 armada_370_xp_timer_common_init(np);
325}
326CLOCKSOURCE_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
327 armada_xp_timer_init);
328
Ezequiel Garcia4a22d9c2014-11-04 10:21:33 -0300329static void __init armada_375_timer_init(struct device_node *np)
330{
331 struct clk *clk;
332
333 clk = of_clk_get_by_name(np, "fixed");
334 if (!IS_ERR(clk)) {
335 clk_prepare_enable(clk);
336 timer_clk = clk_get_rate(clk);
337 } else {
338
339 /*
340 * This fallback is required in order to retain proper
341 * devicetree backwards compatibility.
342 */
343 clk = of_clk_get(np, 0);
344
345 /* Must have at least a clock */
346 BUG_ON(IS_ERR(clk));
347 clk_prepare_enable(clk);
348 timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
349 timer25Mhz = false;
350 }
351
352 armada_370_xp_timer_common_init(np);
353}
354CLOCKSOURCE_OF_DECLARE(armada_375, "marvell,armada-375-timer",
355 armada_375_timer_init);
356
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300357static void __init armada_370_timer_init(struct device_node *np)
358{
359 struct clk *clk = of_clk_get(np, 0);
360
Ezequiel Garciaec8e5112013-08-20 12:45:52 -0300361 BUG_ON(IS_ERR(clk));
Ezequiel Garcia551f2fd2014-11-04 10:21:31 -0300362 clk_prepare_enable(clk);
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300363 timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
364 timer25Mhz = false;
365
366 armada_370_xp_timer_common_init(np);
367}
368CLOCKSOURCE_OF_DECLARE(armada_370, "marvell,armada-370-timer",
369 armada_370_timer_init);