blob: 680e5975217fe59dce8febedc3389e1766704e27 [file] [log] [blame]
Sergei Shtylyov60e7a822007-05-05 22:03:49 +02001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 * Due to massive hardware bugs, UltraDMA is only supported
4 * on the 646U2 and not on the 646U.
5 *
6 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
8 *
9 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
Sergei Shtylyov30e5ffc2009-06-15 18:52:56 +020010 * Copyright (C) 2007,2009 MontaVista Software, Inc. <source@mvista.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 */
12
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#include <linux/module.h>
14#include <linux/types.h>
15#include <linux/pci.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070016#include <linux/ide.h>
17#include <linux/init.h>
18
19#include <asm/io.h>
20
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +020021#define DRV_NAME "cmd64x"
22
Linus Torvalds1da177e2005-04-16 15:20:36 -070023#define CMD_DEBUG 0
24
25#if CMD_DEBUG
26#define cmdprintk(x...) printk(x)
27#else
28#define cmdprintk(x...)
29#endif
30
31/*
32 * CMD64x specific registers definition.
33 */
34#define CFR 0x50
Sergei Shtylyove51e2522007-05-05 22:03:49 +020035#define CFR_INTR_CH0 0x04
Linus Torvalds1da177e2005-04-16 15:20:36 -070036
37#define CMDTIM 0x52
38#define ARTTIM0 0x53
39#define DRWTIM0 0x54
40#define ARTTIM1 0x55
41#define DRWTIM1 0x56
42#define ARTTIM23 0x57
43#define ARTTIM23_DIS_RA2 0x04
44#define ARTTIM23_DIS_RA3 0x08
45#define ARTTIM23_INTR_CH1 0x10
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#define DRWTIM2 0x58
47#define BRST 0x59
48#define DRWTIM3 0x5b
49
50#define BMIDECR0 0x70
51#define MRDMODE 0x71
52#define MRDMODE_INTR_CH0 0x04
53#define MRDMODE_INTR_CH1 0x08
Linus Torvalds1da177e2005-04-16 15:20:36 -070054#define UDIDETCR0 0x73
55#define DTPR0 0x74
56#define BMIDECR1 0x78
57#define BMIDECSR 0x79
Linus Torvalds1da177e2005-04-16 15:20:36 -070058#define UDIDETCR1 0x7B
59#define DTPR1 0x7C
60
Sergei Shtylyove277a1a2007-03-17 21:57:24 +010061static u8 quantize_timing(int timing, int quant)
62{
63 return (timing + quant - 1) / quant;
64}
65
Linus Torvalds1da177e2005-04-16 15:20:36 -070066/*
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020067 * This routine calculates active/recovery counts and then writes them into
68 * the chipset registers.
Linus Torvalds1da177e2005-04-16 15:20:36 -070069 */
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020070static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
Linus Torvalds1da177e2005-04-16 15:20:36 -070071{
Bartlomiej Zolnierkiewiczebae41a2008-04-27 15:38:29 +020072 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
Bartlomiej Zolnierkiewicz30e5ee42008-07-15 21:21:46 +020073 int clock_time = 1000 / (ide_pci_clk ? ide_pci_clk : 33);
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020074 u8 cycle_count, active_count, recovery_count, drwtim;
75 static const u8 recovery_values[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -070076 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020077 static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
Linus Torvalds1da177e2005-04-16 15:20:36 -070078
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020079 cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
80 cycle_time, active_time);
81
82 cycle_count = quantize_timing( cycle_time, clock_time);
83 active_count = quantize_timing(active_time, clock_time);
84 recovery_count = cycle_count - active_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -070085
86 /*
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020087 * In case we've got too long recovery phase, try to lengthen
88 * the active phase
Linus Torvalds1da177e2005-04-16 15:20:36 -070089 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070090 if (recovery_count > 16) {
91 active_count += recovery_count - 16;
92 recovery_count = 16;
93 }
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020094 if (active_count > 16) /* shouldn't actually happen... */
95 active_count = 16;
Linus Torvalds1da177e2005-04-16 15:20:36 -070096
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020097 cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
98 cycle_count, active_count, recovery_count);
Linus Torvalds1da177e2005-04-16 15:20:36 -070099
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200100 /*
101 * Convert values to internal chipset representation
102 */
103 recovery_count = recovery_values[recovery_count];
104 active_count &= 0x0f;
105
106 /* Program the active/recovery counts into the DRWTIM register */
107 drwtim = (active_count << 4) | recovery_count;
108 (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
109 cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
110}
111
112/*
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200113 * This routine writes into the chipset registers
114 * PIO setup/active/recovery timings.
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200115 */
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200116static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200117{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100118 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100119 struct pci_dev *dev = to_pci_dev(hwif->dev);
Bartlomiej Zolnierkiewicz86a0e122008-07-16 20:33:38 +0200120 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
Joao Ramos5bfb151f2009-06-15 22:13:44 +0200121 unsigned long setup_count;
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200122 unsigned int cycle_time;
Joao Ramos5bfb151f2009-06-15 22:13:44 +0200123 u8 arttim = 0;
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200124
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200125 static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
126 static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200127
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200128 cycle_time = ide_pio_cycle_time(drive, pio);
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200129
Bartlomiej Zolnierkiewicz86a0e122008-07-16 20:33:38 +0200130 program_cycle_times(drive, cycle_time, t->active);
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200131
Bartlomiej Zolnierkiewicz86a0e122008-07-16 20:33:38 +0200132 setup_count = quantize_timing(t->setup,
Bartlomiej Zolnierkiewicz30e5ee42008-07-15 21:21:46 +0200133 1000 / (ide_pci_clk ? ide_pci_clk : 33));
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200134
135 /*
136 * The primary channel has individual address setup timing registers
137 * for each drive and the hardware selects the slowest timing itself.
138 * The secondary channel has one common register and we have to select
139 * the slowest address setup timing ourselves.
140 */
141 if (hwif->channel) {
Bartlomiej Zolnierkiewicz5d44a152009-01-06 17:20:55 +0100142 ide_drive_t *pair = ide_get_pair_dev(drive);
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200143
Joao Ramos5bfb151f2009-06-15 22:13:44 +0200144 ide_set_drivedata(drive, (void *)setup_count);
Bartlomiej Zolnierkiewicz5d44a152009-01-06 17:20:55 +0100145
146 if (pair)
Joao Ramos5bfb151f2009-06-15 22:13:44 +0200147 setup_count = max_t(u8, setup_count,
148 (unsigned long)ide_get_drivedata(pair));
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200149 }
150
151 if (setup_count > 5) /* shouldn't actually happen... */
152 setup_count = 5;
153 cmdprintk("Final address setup count: %d\n", setup_count);
154
155 /*
156 * Program the address setup clocks into the ARTTIM registers.
157 * Avoid clearing the secondary channel's interrupt bit.
158 */
159 (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
160 if (hwif->channel)
161 arttim &= ~ARTTIM23_INTR_CH1;
162 arttim &= ~0xc0;
163 arttim |= setup_values[setup_count];
164 (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
165 cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
Sergei Shtylyovf92d50e62007-03-03 17:48:53 +0100166}
167
168/*
169 * Attempts to set drive's PIO mode.
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200170 * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
Sergei Shtylyovf92d50e62007-03-03 17:48:53 +0100171 */
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200172
173static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio)
Sergei Shtylyovf92d50e62007-03-03 17:48:53 +0100174{
175 /*
176 * Filter out the prefetch control values
177 * to prevent PIO5 from being programmed
178 */
179 if (pio == 8 || pio == 9)
180 return;
181
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200182 cmd64x_tune_pio(drive, pio);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183}
184
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200185static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100187 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100188 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200189 u8 unit = drive->dn & 0x01;
190 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191
Sergei Shtylyovf92d50e62007-03-03 17:48:53 +0100192 if (speed >= XFER_SW_DMA_0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193 (void) pci_read_config_byte(dev, pciU, &regU);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194 regU &= ~(unit ? 0xCA : 0x35);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195 }
196
197 switch(speed) {
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200198 case XFER_UDMA_5:
199 regU |= unit ? 0x0A : 0x05;
200 break;
201 case XFER_UDMA_4:
202 regU |= unit ? 0x4A : 0x15;
203 break;
204 case XFER_UDMA_3:
205 regU |= unit ? 0x8A : 0x25;
206 break;
207 case XFER_UDMA_2:
208 regU |= unit ? 0x42 : 0x11;
209 break;
210 case XFER_UDMA_1:
211 regU |= unit ? 0x82 : 0x21;
212 break;
213 case XFER_UDMA_0:
214 regU |= unit ? 0xC2 : 0x31;
215 break;
216 case XFER_MW_DMA_2:
217 program_cycle_times(drive, 120, 70);
218 break;
219 case XFER_MW_DMA_1:
220 program_cycle_times(drive, 150, 80);
221 break;
222 case XFER_MW_DMA_0:
223 program_cycle_times(drive, 480, 215);
224 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225 }
226
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200227 if (speed >= XFER_SW_DMA_0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700228 (void) pci_write_config_byte(dev, pciU, regU);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229}
230
Sergei Shtylyov30e5ffc2009-06-15 18:52:56 +0200231static void cmd648_clear_irq(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100233 ide_hwif_t *hwif = drive->hwif;
Sergei Shtylyov30e5ffc2009-06-15 18:52:56 +0200234 struct pci_dev *dev = to_pci_dev(hwif->dev);
235 unsigned long base = pci_resource_start(dev, 4);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200236 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
237 MRDMODE_INTR_CH0;
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100238 u8 mrdmode = inb(base + 1);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200239
240 /* clear the interrupt bit */
Sergei Shtylyov61832892007-11-13 22:09:14 +0100241 outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100242 base + 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243}
244
Sergei Shtylyov30e5ffc2009-06-15 18:52:56 +0200245static void cmd64x_clear_irq(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100247 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100248 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200249 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
250 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
251 CFR_INTR_CH0;
252 u8 irq_stat = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200254 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
255 /* clear the interrupt bit */
256 (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200257}
258
Sergei Shtylyov628df2f2009-06-15 18:52:59 +0200259static int cmd648_test_irq(ide_hwif_t *hwif)
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200260{
Sergei Shtylyov628df2f2009-06-15 18:52:59 +0200261 struct pci_dev *dev = to_pci_dev(hwif->dev);
262 unsigned long base = pci_resource_start(dev, 4);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200263 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
264 MRDMODE_INTR_CH0;
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100265 u8 mrdmode = inb(base + 1);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200266
Sergei Shtylyov628df2f2009-06-15 18:52:59 +0200267 pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n",
268 hwif->name, mrdmode, irq_mask);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200269
Sergei Shtylyov628df2f2009-06-15 18:52:59 +0200270 return (mrdmode & irq_mask) ? 1 : 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271}
272
Sergei Shtylyov628df2f2009-06-15 18:52:59 +0200273static int cmd64x_test_irq(ide_hwif_t *hwif)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100275 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200276 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
277 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
278 CFR_INTR_CH0;
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200279 u8 irq_stat = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280
Sergei Shtylyove51e2522007-05-05 22:03:49 +0200281 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
282
Sergei Shtylyov628df2f2009-06-15 18:52:59 +0200283 pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n",
284 hwif->name, irq_stat, irq_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285
Sergei Shtylyov628df2f2009-06-15 18:52:59 +0200286 return (irq_stat & irq_mask) ? 1 : 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700287}
288
289/*
290 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
291 * event order for DMA transfers.
292 */
293
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200294static int cmd646_1_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700295{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100296 ide_hwif_t *hwif = drive->hwif;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700297 u8 dma_stat = 0, dma_cmd = 0;
298
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299 /* get DMA status */
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200300 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301 /* read DMA command state */
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200302 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303 /* stop DMA */
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200304 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700305 /* clear the INTR & ERROR bits */
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200306 outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700307 /* verify good DMA status */
308 return (dma_stat & 7) != 4;
309}
310
Bartlomiej Zolnierkiewicz2ed0ef52009-03-24 23:22:53 +0100311static int init_chipset_cmd64x(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700313 u8 mrdmode = 0;
314
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315 /* Set a good latency timer and cache line size value. */
316 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
317 /* FIXME: pci_set_master() to ensure a good latency timer value */
318
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200319 /*
320 * Enable interrupts, select MEMORY READ LINE for reads.
321 *
322 * NOTE: although not mentioned in the PCI0646U specs,
323 * bits 0-1 are write only and won't be read back as
324 * set or not -- PCI0646U2 specs clarify this point.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325 */
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200326 (void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
327 mrdmode &= ~0x30;
328 (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329
Linus Torvalds1da177e2005-04-16 15:20:36 -0700330 return 0;
331}
332
Bartlomiej Zolnierkiewiczf454cbe2008-08-05 18:17:04 +0200333static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100335 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200336 u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200338 switch (dev->device) {
339 case PCI_DEVICE_ID_CMD_648:
340 case PCI_DEVICE_ID_CMD_649:
341 pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
Bartlomiej Zolnierkiewicz49521f92007-07-09 23:17:58 +0200342 return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200343 default:
Bartlomiej Zolnierkiewicz49521f92007-07-09 23:17:58 +0200344 return ATA_CBL_PATA40;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700346}
347
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200348static const struct ide_port_ops cmd64x_port_ops = {
349 .set_pio_mode = cmd64x_set_pio_mode,
350 .set_dma_mode = cmd64x_set_dma_mode,
Sergei Shtylyov30e5ffc2009-06-15 18:52:56 +0200351 .clear_irq = cmd64x_clear_irq,
Sergei Shtylyov628df2f2009-06-15 18:52:59 +0200352 .test_irq = cmd64x_test_irq,
Sergei Shtylyov30e5ffc2009-06-15 18:52:56 +0200353 .cable_detect = cmd64x_cable_detect,
354};
355
356static const struct ide_port_ops cmd648_port_ops = {
357 .set_pio_mode = cmd64x_set_pio_mode,
358 .set_dma_mode = cmd64x_set_dma_mode,
359 .clear_irq = cmd648_clear_irq,
Sergei Shtylyov628df2f2009-06-15 18:52:59 +0200360 .test_irq = cmd648_test_irq,
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200361 .cable_detect = cmd64x_cable_detect,
362};
363
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200364static const struct ide_dma_ops cmd646_rev1_dma_ops = {
365 .dma_host_set = ide_dma_host_set,
366 .dma_setup = ide_dma_setup,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200367 .dma_start = ide_dma_start,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200368 .dma_end = cmd646_1_dma_end,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200369 .dma_test_irq = ide_dma_test_irq,
370 .dma_lost_irq = ide_dma_lost_irq,
Bartlomiej Zolnierkiewicz22117d62009-03-27 12:46:47 +0100371 .dma_timer_expiry = ide_dma_sff_timer_expiry,
Sergei Shtylyov592b5312009-01-06 17:21:02 +0100372 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200373};
374
Bartlomiej Zolnierkiewicz85620432007-10-20 00:32:34 +0200375static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200376 { /* 0: CMD643 */
377 .name = DRV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378 .init_chipset = init_chipset_cmd64x,
Sergei Shtylyov7accbff2007-05-05 22:03:49 +0200379 .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200380 .port_ops = &cmd64x_port_ops,
Bartlomiej Zolnierkiewicz8ac2b42a2008-02-01 23:09:30 +0100381 .host_flags = IDE_HFLAG_CLEAR_SIMPLEX |
Bartlomiej Zolnierkiewicz5e71d9c2008-04-26 17:36:35 +0200382 IDE_HFLAG_ABUSE_PREFETCH,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +0200383 .pio_mask = ATA_PIO5,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +0200384 .mwdma_mask = ATA_MWDMA2,
Bartlomiej Zolnierkiewicz18137202007-05-10 00:01:07 +0200385 .udma_mask = 0x00, /* no udma */
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200386 },
387 { /* 1: CMD646 */
388 .name = DRV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389 .init_chipset = init_chipset_cmd64x,
Sergei Shtylyov7accbff2007-05-05 22:03:49 +0200390 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
Sergei Shtylyov30e5ffc2009-06-15 18:52:56 +0200391 .port_ops = &cmd648_port_ops,
David S. Millere01698a2009-06-21 22:48:03 -0700392 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +0200393 .pio_mask = ATA_PIO5,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +0200394 .mwdma_mask = ATA_MWDMA2,
395 .udma_mask = ATA_UDMA2,
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200396 },
397 { /* 2: CMD648 */
398 .name = DRV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399 .init_chipset = init_chipset_cmd64x,
Sergei Shtylyov7accbff2007-05-05 22:03:49 +0200400 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
Sergei Shtylyov30e5ffc2009-06-15 18:52:56 +0200401 .port_ops = &cmd648_port_ops,
Bartlomiej Zolnierkiewicz5e71d9c2008-04-26 17:36:35 +0200402 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +0200403 .pio_mask = ATA_PIO5,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +0200404 .mwdma_mask = ATA_MWDMA2,
405 .udma_mask = ATA_UDMA4,
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200406 },
407 { /* 3: CMD649 */
408 .name = DRV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700409 .init_chipset = init_chipset_cmd64x,
Sergei Shtylyov7accbff2007-05-05 22:03:49 +0200410 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
Sergei Shtylyov30e5ffc2009-06-15 18:52:56 +0200411 .port_ops = &cmd648_port_ops,
Bartlomiej Zolnierkiewicz5e71d9c2008-04-26 17:36:35 +0200412 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +0200413 .pio_mask = ATA_PIO5,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +0200414 .mwdma_mask = ATA_MWDMA2,
415 .udma_mask = ATA_UDMA5,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700416 }
417};
418
419static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
420{
Bartlomiej Zolnierkiewicz039788e2007-10-20 00:32:34 +0200421 struct ide_port_info d;
Bartlomiej Zolnierkiewiczbfd314a2007-10-19 00:30:09 +0200422 u8 idx = id->driver_data;
Sergei Shtylyov7accbff2007-05-05 22:03:49 +0200423
Bartlomiej Zolnierkiewiczbfd314a2007-10-19 00:30:09 +0200424 d = cmd64x_chipsets[idx];
425
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200426 if (idx == 1) {
427 /*
428 * UltraDMA only supported on PCI646U and PCI646U2, which
429 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
430 * Actually, although the CMD tech support people won't
431 * tell me the details, the 0x03 revision cannot support
432 * UDMA correctly without hardware modifications, and even
433 * then it only works with Quantum disks due to some
434 * hold time assumptions in the 646U part which are fixed
435 * in the 646U2.
436 *
437 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
438 */
439 if (dev->revision < 5) {
440 d.udma_mask = 0x00;
441 /*
442 * The original PCI0646 didn't have the primary
443 * channel enable bit, it appeared starting with
444 * PCI0646U (i.e. revision ID 3).
445 */
446 if (dev->revision < 3) {
447 d.enablebits[0].reg = 0;
Sergei Shtylyov30e5ffc2009-06-15 18:52:56 +0200448 d.port_ops = &cmd64x_port_ops;
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200449 if (dev->revision == 1)
450 d.dma_ops = &cmd646_rev1_dma_ops;
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200451 }
452 }
453 }
Bartlomiej Zolnierkiewiczbfd314a2007-10-19 00:30:09 +0200454
Bartlomiej Zolnierkiewicz6cdf6eb2008-07-24 22:53:14 +0200455 return ide_pci_init_one(dev, &d, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456}
457
Bartlomiej Zolnierkiewicz9cbcc5e2007-10-16 22:29:56 +0200458static const struct pci_device_id cmd64x_pci_tbl[] = {
459 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
460 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
461 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
462 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700463 { 0, },
464};
465MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
466
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +0200467static struct pci_driver cmd64x_pci_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700468 .name = "CMD64x_IDE",
469 .id_table = cmd64x_pci_tbl,
470 .probe = cmd64x_init_one,
Bartlomiej Zolnierkiewicze2b15b42008-07-24 22:53:20 +0200471 .remove = ide_pci_remove,
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +0200472 .suspend = ide_pci_suspend,
473 .resume = ide_pci_resume,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474};
475
Bartlomiej Zolnierkiewicz82ab1ee2007-01-27 13:46:56 +0100476static int __init cmd64x_ide_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700477{
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +0200478 return ide_pci_register_driver(&cmd64x_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700479}
480
Bartlomiej Zolnierkiewicze2b15b42008-07-24 22:53:20 +0200481static void __exit cmd64x_ide_exit(void)
482{
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +0200483 pci_unregister_driver(&cmd64x_pci_driver);
Bartlomiej Zolnierkiewicze2b15b42008-07-24 22:53:20 +0200484}
485
Linus Torvalds1da177e2005-04-16 15:20:36 -0700486module_init(cmd64x_ide_init);
Bartlomiej Zolnierkiewicze2b15b42008-07-24 22:53:20 +0200487module_exit(cmd64x_ide_exit);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488
489MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
490MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
491MODULE_LICENSE("GPL");