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Graeme Gregory518fb722011-05-02 16:20:08 -05001/*
2 * tps65910.c -- TI tps65910
3 *
4 * Copyright 2010 Texas Instruments Inc.
5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/err.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
23#include <linux/delay.h>
24#include <linux/slab.h>
25#include <linux/gpio.h>
26#include <linux/mfd/tps65910.h>
27
Graeme Gregory518fb722011-05-02 16:20:08 -050028#define TPS65910_SUPPLY_STATE_ENABLED 0x1
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +053029#define EXT_SLEEP_CONTROL (TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 | \
30 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 | \
Laxman Dewanganf30b0712012-03-07 18:21:49 +053031 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 | \
32 TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
Graeme Gregory518fb722011-05-02 16:20:08 -050033
34/* supported VIO voltages in milivolts */
35static const u16 VIO_VSEL_table[] = {
36 1500, 1800, 2500, 3300,
37};
38
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -050039/* VSEL tables for TPS65910 specific LDOs and dcdc's */
40
41/* supported VDD3 voltages in milivolts */
Graeme Gregory518fb722011-05-02 16:20:08 -050042static const u16 VDD3_VSEL_table[] = {
43 5000,
44};
45
46/* supported VDIG1 voltages in milivolts */
47static const u16 VDIG1_VSEL_table[] = {
48 1200, 1500, 1800, 2700,
49};
50
51/* supported VDIG2 voltages in milivolts */
52static const u16 VDIG2_VSEL_table[] = {
53 1000, 1100, 1200, 1800,
54};
55
56/* supported VPLL voltages in milivolts */
57static const u16 VPLL_VSEL_table[] = {
58 1000, 1100, 1800, 2500,
59};
60
61/* supported VDAC voltages in milivolts */
62static const u16 VDAC_VSEL_table[] = {
63 1800, 2600, 2800, 2850,
64};
65
66/* supported VAUX1 voltages in milivolts */
67static const u16 VAUX1_VSEL_table[] = {
68 1800, 2500, 2800, 2850,
69};
70
71/* supported VAUX2 voltages in milivolts */
72static const u16 VAUX2_VSEL_table[] = {
73 1800, 2800, 2900, 3300,
74};
75
76/* supported VAUX33 voltages in milivolts */
77static const u16 VAUX33_VSEL_table[] = {
78 1800, 2000, 2800, 3300,
79};
80
81/* supported VMMC voltages in milivolts */
82static const u16 VMMC_VSEL_table[] = {
83 1800, 2800, 3000, 3300,
84};
85
86struct tps_info {
87 const char *name;
88 unsigned min_uV;
89 unsigned max_uV;
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +053090 u8 n_voltages;
91 const u16 *voltage_table;
Laxman Dewangan0651eed2012-03-13 11:35:20 +053092 int enable_time_us;
Graeme Gregory518fb722011-05-02 16:20:08 -050093};
94
95static struct tps_info tps65910_regs[] = {
96 {
97 .name = "VRTC",
Laxman Dewangan0651eed2012-03-13 11:35:20 +053098 .enable_time_us = 2200,
Graeme Gregory518fb722011-05-02 16:20:08 -050099 },
100 {
101 .name = "VIO",
102 .min_uV = 1500000,
103 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530104 .n_voltages = ARRAY_SIZE(VIO_VSEL_table),
105 .voltage_table = VIO_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530106 .enable_time_us = 350,
Graeme Gregory518fb722011-05-02 16:20:08 -0500107 },
108 {
109 .name = "VDD1",
110 .min_uV = 600000,
111 .max_uV = 4500000,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530112 .enable_time_us = 350,
Graeme Gregory518fb722011-05-02 16:20:08 -0500113 },
114 {
115 .name = "VDD2",
116 .min_uV = 600000,
117 .max_uV = 4500000,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530118 .enable_time_us = 350,
Graeme Gregory518fb722011-05-02 16:20:08 -0500119 },
120 {
121 .name = "VDD3",
122 .min_uV = 5000000,
123 .max_uV = 5000000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530124 .n_voltages = ARRAY_SIZE(VDD3_VSEL_table),
125 .voltage_table = VDD3_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530126 .enable_time_us = 200,
Graeme Gregory518fb722011-05-02 16:20:08 -0500127 },
128 {
129 .name = "VDIG1",
130 .min_uV = 1200000,
131 .max_uV = 2700000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530132 .n_voltages = ARRAY_SIZE(VDIG1_VSEL_table),
133 .voltage_table = VDIG1_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530134 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500135 },
136 {
137 .name = "VDIG2",
138 .min_uV = 1000000,
139 .max_uV = 1800000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530140 .n_voltages = ARRAY_SIZE(VDIG2_VSEL_table),
141 .voltage_table = VDIG2_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530142 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500143 },
144 {
145 .name = "VPLL",
146 .min_uV = 1000000,
147 .max_uV = 2500000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530148 .n_voltages = ARRAY_SIZE(VPLL_VSEL_table),
149 .voltage_table = VPLL_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530150 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500151 },
152 {
153 .name = "VDAC",
154 .min_uV = 1800000,
155 .max_uV = 2850000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530156 .n_voltages = ARRAY_SIZE(VDAC_VSEL_table),
157 .voltage_table = VDAC_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530158 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500159 },
160 {
161 .name = "VAUX1",
162 .min_uV = 1800000,
163 .max_uV = 2850000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530164 .n_voltages = ARRAY_SIZE(VAUX1_VSEL_table),
165 .voltage_table = VAUX1_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530166 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500167 },
168 {
169 .name = "VAUX2",
170 .min_uV = 1800000,
171 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530172 .n_voltages = ARRAY_SIZE(VAUX2_VSEL_table),
173 .voltage_table = VAUX2_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530174 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500175 },
176 {
177 .name = "VAUX33",
178 .min_uV = 1800000,
179 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530180 .n_voltages = ARRAY_SIZE(VAUX33_VSEL_table),
181 .voltage_table = VAUX33_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530182 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500183 },
184 {
185 .name = "VMMC",
186 .min_uV = 1800000,
187 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530188 .n_voltages = ARRAY_SIZE(VMMC_VSEL_table),
189 .voltage_table = VMMC_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530190 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500191 },
192};
193
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500194static struct tps_info tps65911_regs[] = {
195 {
Laxman Dewanganc2f8efd2012-01-18 20:46:56 +0530196 .name = "VRTC",
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530197 .enable_time_us = 2200,
Laxman Dewanganc2f8efd2012-01-18 20:46:56 +0530198 },
199 {
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500200 .name = "VIO",
201 .min_uV = 1500000,
202 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530203 .n_voltages = ARRAY_SIZE(VIO_VSEL_table),
204 .voltage_table = VIO_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530205 .enable_time_us = 350,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500206 },
207 {
208 .name = "VDD1",
209 .min_uV = 600000,
210 .max_uV = 4500000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530211 .n_voltages = 73,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530212 .enable_time_us = 350,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500213 },
214 {
215 .name = "VDD2",
216 .min_uV = 600000,
217 .max_uV = 4500000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530218 .n_voltages = 73,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530219 .enable_time_us = 350,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500220 },
221 {
222 .name = "VDDCTRL",
223 .min_uV = 600000,
224 .max_uV = 1400000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530225 .n_voltages = 65,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530226 .enable_time_us = 900,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500227 },
228 {
229 .name = "LDO1",
230 .min_uV = 1000000,
231 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530232 .n_voltages = 47,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530233 .enable_time_us = 420,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500234 },
235 {
236 .name = "LDO2",
237 .min_uV = 1000000,
238 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530239 .n_voltages = 47,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530240 .enable_time_us = 420,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500241 },
242 {
243 .name = "LDO3",
244 .min_uV = 1000000,
245 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530246 .n_voltages = 24,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530247 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500248 },
249 {
250 .name = "LDO4",
251 .min_uV = 1000000,
252 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530253 .n_voltages = 47,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530254 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500255 },
256 {
257 .name = "LDO5",
258 .min_uV = 1000000,
259 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530260 .n_voltages = 24,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530261 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500262 },
263 {
264 .name = "LDO6",
265 .min_uV = 1000000,
266 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530267 .n_voltages = 24,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530268 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500269 },
270 {
271 .name = "LDO7",
272 .min_uV = 1000000,
273 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530274 .n_voltages = 24,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530275 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500276 },
277 {
278 .name = "LDO8",
279 .min_uV = 1000000,
280 .max_uV = 3300000,
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530281 .n_voltages = 24,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530282 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500283 },
284};
285
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530286#define EXT_CONTROL_REG_BITS(id, regs_offs, bits) (((regs_offs) << 8) | (bits))
287static unsigned int tps65910_ext_sleep_control[] = {
288 0,
289 EXT_CONTROL_REG_BITS(VIO, 1, 0),
290 EXT_CONTROL_REG_BITS(VDD1, 1, 1),
291 EXT_CONTROL_REG_BITS(VDD2, 1, 2),
292 EXT_CONTROL_REG_BITS(VDD3, 1, 3),
293 EXT_CONTROL_REG_BITS(VDIG1, 0, 1),
294 EXT_CONTROL_REG_BITS(VDIG2, 0, 2),
295 EXT_CONTROL_REG_BITS(VPLL, 0, 6),
296 EXT_CONTROL_REG_BITS(VDAC, 0, 7),
297 EXT_CONTROL_REG_BITS(VAUX1, 0, 3),
298 EXT_CONTROL_REG_BITS(VAUX2, 0, 4),
299 EXT_CONTROL_REG_BITS(VAUX33, 0, 5),
300 EXT_CONTROL_REG_BITS(VMMC, 0, 0),
301};
302
303static unsigned int tps65911_ext_sleep_control[] = {
304 0,
305 EXT_CONTROL_REG_BITS(VIO, 1, 0),
306 EXT_CONTROL_REG_BITS(VDD1, 1, 1),
307 EXT_CONTROL_REG_BITS(VDD2, 1, 2),
308 EXT_CONTROL_REG_BITS(VDDCTRL, 1, 3),
309 EXT_CONTROL_REG_BITS(LDO1, 0, 1),
310 EXT_CONTROL_REG_BITS(LDO2, 0, 2),
311 EXT_CONTROL_REG_BITS(LDO3, 0, 7),
312 EXT_CONTROL_REG_BITS(LDO4, 0, 6),
313 EXT_CONTROL_REG_BITS(LDO5, 0, 3),
314 EXT_CONTROL_REG_BITS(LDO6, 0, 0),
315 EXT_CONTROL_REG_BITS(LDO7, 0, 5),
316 EXT_CONTROL_REG_BITS(LDO8, 0, 4),
317};
318
Graeme Gregory518fb722011-05-02 16:20:08 -0500319struct tps65910_reg {
Axel Lin39aa9b62011-07-11 09:57:43 +0800320 struct regulator_desc *desc;
Graeme Gregory518fb722011-05-02 16:20:08 -0500321 struct tps65910 *mfd;
Axel Lin39aa9b62011-07-11 09:57:43 +0800322 struct regulator_dev **rdev;
323 struct tps_info **info;
Graeme Gregory518fb722011-05-02 16:20:08 -0500324 struct mutex mutex;
Axel Lin39aa9b62011-07-11 09:57:43 +0800325 int num_regulators;
Graeme Gregory518fb722011-05-02 16:20:08 -0500326 int mode;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500327 int (*get_ctrl_reg)(int);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530328 unsigned int *ext_sleep_control;
329 unsigned int board_ext_control[TPS65910_NUM_REGS];
Graeme Gregory518fb722011-05-02 16:20:08 -0500330};
331
332static inline int tps65910_read(struct tps65910_reg *pmic, u8 reg)
333{
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700334 unsigned int val;
Graeme Gregory518fb722011-05-02 16:20:08 -0500335 int err;
336
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700337 err = tps65910_reg_read(pmic->mfd, reg, &val);
Graeme Gregory518fb722011-05-02 16:20:08 -0500338 if (err)
339 return err;
340
341 return val;
342}
343
Graeme Gregory518fb722011-05-02 16:20:08 -0500344static int tps65910_modify_bits(struct tps65910_reg *pmic, u8 reg,
345 u8 set_mask, u8 clear_mask)
346{
347 int err, data;
348
349 mutex_lock(&pmic->mutex);
350
351 data = tps65910_read(pmic, reg);
352 if (data < 0) {
353 dev_err(pmic->mfd->dev, "Read from reg 0x%x failed\n", reg);
354 err = data;
355 goto out;
356 }
357
358 data &= ~clear_mask;
359 data |= set_mask;
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700360 err = tps65910_reg_write(pmic->mfd, reg, data);
Graeme Gregory518fb722011-05-02 16:20:08 -0500361 if (err)
362 dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg);
363
364out:
365 mutex_unlock(&pmic->mutex);
366 return err;
367}
368
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700369static int tps65910_reg_read_locked(struct tps65910_reg *pmic, u8 reg)
Graeme Gregory518fb722011-05-02 16:20:08 -0500370{
371 int data;
372
373 mutex_lock(&pmic->mutex);
374
375 data = tps65910_read(pmic, reg);
376 if (data < 0)
377 dev_err(pmic->mfd->dev, "Read from reg 0x%x failed\n", reg);
378
379 mutex_unlock(&pmic->mutex);
380 return data;
381}
382
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700383static int tps65910_reg_write_locked(struct tps65910_reg *pmic, u8 reg, u8 val)
Graeme Gregory518fb722011-05-02 16:20:08 -0500384{
385 int err;
386
387 mutex_lock(&pmic->mutex);
388
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700389 err = tps65910_reg_write(pmic->mfd, reg, val);
Graeme Gregory518fb722011-05-02 16:20:08 -0500390 if (err < 0)
391 dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg);
392
393 mutex_unlock(&pmic->mutex);
394 return err;
395}
396
397static int tps65910_get_ctrl_register(int id)
398{
399 switch (id) {
400 case TPS65910_REG_VRTC:
401 return TPS65910_VRTC;
402 case TPS65910_REG_VIO:
403 return TPS65910_VIO;
404 case TPS65910_REG_VDD1:
405 return TPS65910_VDD1;
406 case TPS65910_REG_VDD2:
407 return TPS65910_VDD2;
408 case TPS65910_REG_VDD3:
409 return TPS65910_VDD3;
410 case TPS65910_REG_VDIG1:
411 return TPS65910_VDIG1;
412 case TPS65910_REG_VDIG2:
413 return TPS65910_VDIG2;
414 case TPS65910_REG_VPLL:
415 return TPS65910_VPLL;
416 case TPS65910_REG_VDAC:
417 return TPS65910_VDAC;
418 case TPS65910_REG_VAUX1:
419 return TPS65910_VAUX1;
420 case TPS65910_REG_VAUX2:
421 return TPS65910_VAUX2;
422 case TPS65910_REG_VAUX33:
423 return TPS65910_VAUX33;
424 case TPS65910_REG_VMMC:
425 return TPS65910_VMMC;
426 default:
427 return -EINVAL;
428 }
429}
430
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500431static int tps65911_get_ctrl_register(int id)
432{
433 switch (id) {
434 case TPS65910_REG_VRTC:
435 return TPS65910_VRTC;
436 case TPS65910_REG_VIO:
437 return TPS65910_VIO;
438 case TPS65910_REG_VDD1:
439 return TPS65910_VDD1;
440 case TPS65910_REG_VDD2:
441 return TPS65910_VDD2;
442 case TPS65911_REG_VDDCTRL:
443 return TPS65911_VDDCTRL;
444 case TPS65911_REG_LDO1:
445 return TPS65911_LDO1;
446 case TPS65911_REG_LDO2:
447 return TPS65911_LDO2;
448 case TPS65911_REG_LDO3:
449 return TPS65911_LDO3;
450 case TPS65911_REG_LDO4:
451 return TPS65911_LDO4;
452 case TPS65911_REG_LDO5:
453 return TPS65911_LDO5;
454 case TPS65911_REG_LDO6:
455 return TPS65911_LDO6;
456 case TPS65911_REG_LDO7:
457 return TPS65911_LDO7;
458 case TPS65911_REG_LDO8:
459 return TPS65911_LDO8;
460 default:
461 return -EINVAL;
462 }
463}
464
Graeme Gregory518fb722011-05-02 16:20:08 -0500465static int tps65910_is_enabled(struct regulator_dev *dev)
466{
467 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
468 int reg, value, id = rdev_get_id(dev);
469
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500470 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500471 if (reg < 0)
472 return reg;
473
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700474 value = tps65910_reg_read_locked(pmic, reg);
Graeme Gregory518fb722011-05-02 16:20:08 -0500475 if (value < 0)
476 return value;
477
478 return value & TPS65910_SUPPLY_STATE_ENABLED;
479}
480
481static int tps65910_enable(struct regulator_dev *dev)
482{
483 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
484 struct tps65910 *mfd = pmic->mfd;
485 int reg, id = rdev_get_id(dev);
486
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500487 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500488 if (reg < 0)
489 return reg;
490
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700491 return tps65910_reg_set_bits(mfd, reg, TPS65910_SUPPLY_STATE_ENABLED);
Graeme Gregory518fb722011-05-02 16:20:08 -0500492}
493
494static int tps65910_disable(struct regulator_dev *dev)
495{
496 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
497 struct tps65910 *mfd = pmic->mfd;
498 int reg, id = rdev_get_id(dev);
499
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500500 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500501 if (reg < 0)
502 return reg;
503
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700504 return tps65910_reg_clear_bits(mfd, reg, TPS65910_SUPPLY_STATE_ENABLED);
Graeme Gregory518fb722011-05-02 16:20:08 -0500505}
506
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530507static int tps65910_enable_time(struct regulator_dev *dev)
508{
509 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
510 int id = rdev_get_id(dev);
511 return pmic->info[id]->enable_time_us;
512}
Graeme Gregory518fb722011-05-02 16:20:08 -0500513
514static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode)
515{
516 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
517 struct tps65910 *mfd = pmic->mfd;
518 int reg, value, id = rdev_get_id(dev);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500519
520 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500521 if (reg < 0)
522 return reg;
523
524 switch (mode) {
525 case REGULATOR_MODE_NORMAL:
526 return tps65910_modify_bits(pmic, reg, LDO_ST_ON_BIT,
527 LDO_ST_MODE_BIT);
528 case REGULATOR_MODE_IDLE:
529 value = LDO_ST_ON_BIT | LDO_ST_MODE_BIT;
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700530 return tps65910_reg_set_bits(mfd, reg, value);
Graeme Gregory518fb722011-05-02 16:20:08 -0500531 case REGULATOR_MODE_STANDBY:
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700532 return tps65910_reg_clear_bits(mfd, reg, LDO_ST_ON_BIT);
Graeme Gregory518fb722011-05-02 16:20:08 -0500533 }
534
535 return -EINVAL;
536}
537
538static unsigned int tps65910_get_mode(struct regulator_dev *dev)
539{
540 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
541 int reg, value, id = rdev_get_id(dev);
542
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500543 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500544 if (reg < 0)
545 return reg;
546
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700547 value = tps65910_reg_read_locked(pmic, reg);
Graeme Gregory518fb722011-05-02 16:20:08 -0500548 if (value < 0)
549 return value;
550
Axel Lin58599392012-03-13 07:15:27 +0800551 if (!(value & LDO_ST_ON_BIT))
Graeme Gregory518fb722011-05-02 16:20:08 -0500552 return REGULATOR_MODE_STANDBY;
553 else if (value & LDO_ST_MODE_BIT)
554 return REGULATOR_MODE_IDLE;
555 else
556 return REGULATOR_MODE_NORMAL;
557}
558
Laxman Dewangan18039e02012-03-14 13:00:58 +0530559static int tps65910_get_voltage_dcdc_sel(struct regulator_dev *dev)
Graeme Gregory518fb722011-05-02 16:20:08 -0500560{
561 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
Laxman Dewangan18039e02012-03-14 13:00:58 +0530562 int id = rdev_get_id(dev);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500563 int opvsel = 0, srvsel = 0, vselmax = 0, mult = 0, sr = 0;
Graeme Gregory518fb722011-05-02 16:20:08 -0500564
565 switch (id) {
566 case TPS65910_REG_VDD1:
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700567 opvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD1_OP);
568 mult = tps65910_reg_read_locked(pmic, TPS65910_VDD1);
Graeme Gregory518fb722011-05-02 16:20:08 -0500569 mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT;
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700570 srvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD1_SR);
Graeme Gregory518fb722011-05-02 16:20:08 -0500571 sr = opvsel & VDD1_OP_CMD_MASK;
572 opvsel &= VDD1_OP_SEL_MASK;
573 srvsel &= VDD1_SR_SEL_MASK;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500574 vselmax = 75;
Graeme Gregory518fb722011-05-02 16:20:08 -0500575 break;
576 case TPS65910_REG_VDD2:
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700577 opvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD2_OP);
578 mult = tps65910_reg_read_locked(pmic, TPS65910_VDD2);
Graeme Gregory518fb722011-05-02 16:20:08 -0500579 mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT;
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700580 srvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD2_SR);
Graeme Gregory518fb722011-05-02 16:20:08 -0500581 sr = opvsel & VDD2_OP_CMD_MASK;
582 opvsel &= VDD2_OP_SEL_MASK;
583 srvsel &= VDD2_SR_SEL_MASK;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500584 vselmax = 75;
585 break;
586 case TPS65911_REG_VDDCTRL:
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700587 opvsel = tps65910_reg_read_locked(pmic, TPS65911_VDDCTRL_OP);
588 srvsel = tps65910_reg_read_locked(pmic, TPS65911_VDDCTRL_SR);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500589 sr = opvsel & VDDCTRL_OP_CMD_MASK;
590 opvsel &= VDDCTRL_OP_SEL_MASK;
591 srvsel &= VDDCTRL_SR_SEL_MASK;
592 vselmax = 64;
Graeme Gregory518fb722011-05-02 16:20:08 -0500593 break;
594 }
595
596 /* multiplier 0 == 1 but 2,3 normal */
597 if (!mult)
598 mult=1;
599
600 if (sr) {
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500601 /* normalise to valid range */
602 if (srvsel < 3)
603 srvsel = 3;
604 if (srvsel > vselmax)
605 srvsel = vselmax;
Laxman Dewangan18039e02012-03-14 13:00:58 +0530606 return srvsel - 3;
Graeme Gregory518fb722011-05-02 16:20:08 -0500607 } else {
608
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500609 /* normalise to valid range*/
610 if (opvsel < 3)
611 opvsel = 3;
612 if (opvsel > vselmax)
613 opvsel = vselmax;
Laxman Dewangan18039e02012-03-14 13:00:58 +0530614 return opvsel - 3;
Graeme Gregory518fb722011-05-02 16:20:08 -0500615 }
Laxman Dewangan18039e02012-03-14 13:00:58 +0530616 return -EINVAL;
Graeme Gregory518fb722011-05-02 16:20:08 -0500617}
618
619static int tps65910_get_voltage(struct regulator_dev *dev)
620{
621 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
622 int reg, value, id = rdev_get_id(dev), voltage = 0;
623
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500624 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500625 if (reg < 0)
626 return reg;
627
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700628 value = tps65910_reg_read_locked(pmic, reg);
Graeme Gregory518fb722011-05-02 16:20:08 -0500629 if (value < 0)
630 return value;
631
632 switch (id) {
633 case TPS65910_REG_VIO:
634 case TPS65910_REG_VDIG1:
635 case TPS65910_REG_VDIG2:
636 case TPS65910_REG_VPLL:
637 case TPS65910_REG_VDAC:
638 case TPS65910_REG_VAUX1:
639 case TPS65910_REG_VAUX2:
640 case TPS65910_REG_VAUX33:
641 case TPS65910_REG_VMMC:
642 value &= LDO_SEL_MASK;
643 value >>= LDO_SEL_SHIFT;
644 break;
645 default:
646 return -EINVAL;
647 }
648
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530649 voltage = pmic->info[id]->voltage_table[value] * 1000;
Graeme Gregory518fb722011-05-02 16:20:08 -0500650
651 return voltage;
652}
653
654static int tps65910_get_voltage_vdd3(struct regulator_dev *dev)
655{
656 return 5 * 1000 * 1000;
657}
658
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500659static int tps65911_get_voltage(struct regulator_dev *dev)
660{
661 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
662 int step_mv, id = rdev_get_id(dev);
663 u8 value, reg;
664
665 reg = pmic->get_ctrl_reg(id);
666
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700667 value = tps65910_reg_read_locked(pmic, reg);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500668
669 switch (id) {
670 case TPS65911_REG_LDO1:
671 case TPS65911_REG_LDO2:
672 case TPS65911_REG_LDO4:
673 value &= LDO1_SEL_MASK;
674 value >>= LDO_SEL_SHIFT;
675 /* The first 5 values of the selector correspond to 1V */
676 if (value < 5)
677 value = 0;
678 else
679 value -= 4;
680
681 step_mv = 50;
682 break;
683 case TPS65911_REG_LDO3:
684 case TPS65911_REG_LDO5:
685 case TPS65911_REG_LDO6:
686 case TPS65911_REG_LDO7:
687 case TPS65911_REG_LDO8:
688 value &= LDO3_SEL_MASK;
689 value >>= LDO_SEL_SHIFT;
690 /* The first 3 values of the selector correspond to 1V */
691 if (value < 3)
692 value = 0;
693 else
694 value -= 2;
695
696 step_mv = 100;
697 break;
698 case TPS65910_REG_VIO:
Laxman Dewangane882eae2012-02-17 18:56:11 +0530699 value &= LDO_SEL_MASK;
700 value >>= LDO_SEL_SHIFT;
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530701 return pmic->info[id]->voltage_table[value] * 1000;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500702 default:
703 return -EINVAL;
704 }
705
706 return (LDO_MIN_VOLT + value * step_mv) * 1000;
707}
708
Axel Lin94732b92012-03-09 10:22:20 +0800709static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev,
710 unsigned selector)
Graeme Gregory518fb722011-05-02 16:20:08 -0500711{
712 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
713 int id = rdev_get_id(dev), vsel;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500714 int dcdc_mult = 0;
Graeme Gregory518fb722011-05-02 16:20:08 -0500715
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500716 switch (id) {
717 case TPS65910_REG_VDD1:
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530718 dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500719 if (dcdc_mult == 1)
720 dcdc_mult--;
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530721 vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
Graeme Gregory518fb722011-05-02 16:20:08 -0500722
Graeme Gregory518fb722011-05-02 16:20:08 -0500723 tps65910_modify_bits(pmic, TPS65910_VDD1,
724 (dcdc_mult << VDD1_VGAIN_SEL_SHIFT),
725 VDD1_VGAIN_SEL_MASK);
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700726 tps65910_reg_write_locked(pmic, TPS65910_VDD1_OP, vsel);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500727 break;
728 case TPS65910_REG_VDD2:
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530729 dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500730 if (dcdc_mult == 1)
731 dcdc_mult--;
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530732 vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500733
Graeme Gregory518fb722011-05-02 16:20:08 -0500734 tps65910_modify_bits(pmic, TPS65910_VDD2,
735 (dcdc_mult << VDD2_VGAIN_SEL_SHIFT),
736 VDD1_VGAIN_SEL_MASK);
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700737 tps65910_reg_write_locked(pmic, TPS65910_VDD2_OP, vsel);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500738 break;
739 case TPS65911_REG_VDDCTRL:
Laxman Dewanganc4632ae2012-03-07 16:39:05 +0530740 vsel = selector + 3;
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700741 tps65910_reg_write_locked(pmic, TPS65911_VDDCTRL_OP, vsel);
Graeme Gregory518fb722011-05-02 16:20:08 -0500742 }
743
744 return 0;
745}
746
Axel Lin94732b92012-03-09 10:22:20 +0800747static int tps65910_set_voltage_sel(struct regulator_dev *dev,
748 unsigned selector)
Graeme Gregory518fb722011-05-02 16:20:08 -0500749{
750 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
751 int reg, id = rdev_get_id(dev);
752
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500753 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500754 if (reg < 0)
755 return reg;
756
757 switch (id) {
758 case TPS65910_REG_VIO:
759 case TPS65910_REG_VDIG1:
760 case TPS65910_REG_VDIG2:
761 case TPS65910_REG_VPLL:
762 case TPS65910_REG_VDAC:
763 case TPS65910_REG_VAUX1:
764 case TPS65910_REG_VAUX2:
765 case TPS65910_REG_VAUX33:
766 case TPS65910_REG_VMMC:
767 return tps65910_modify_bits(pmic, reg,
768 (selector << LDO_SEL_SHIFT), LDO_SEL_MASK);
769 }
770
771 return -EINVAL;
772}
773
Axel Lin94732b92012-03-09 10:22:20 +0800774static int tps65911_set_voltage_sel(struct regulator_dev *dev,
775 unsigned selector)
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500776{
777 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
778 int reg, id = rdev_get_id(dev);
779
780 reg = pmic->get_ctrl_reg(id);
781 if (reg < 0)
782 return reg;
783
784 switch (id) {
785 case TPS65911_REG_LDO1:
786 case TPS65911_REG_LDO2:
787 case TPS65911_REG_LDO4:
788 return tps65910_modify_bits(pmic, reg,
789 (selector << LDO_SEL_SHIFT), LDO1_SEL_MASK);
790 case TPS65911_REG_LDO3:
791 case TPS65911_REG_LDO5:
792 case TPS65911_REG_LDO6:
793 case TPS65911_REG_LDO7:
794 case TPS65911_REG_LDO8:
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500795 return tps65910_modify_bits(pmic, reg,
796 (selector << LDO_SEL_SHIFT), LDO3_SEL_MASK);
Laxman Dewangane882eae2012-02-17 18:56:11 +0530797 case TPS65910_REG_VIO:
798 return tps65910_modify_bits(pmic, reg,
799 (selector << LDO_SEL_SHIFT), LDO_SEL_MASK);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500800 }
801
802 return -EINVAL;
803}
804
805
Graeme Gregory518fb722011-05-02 16:20:08 -0500806static int tps65910_list_voltage_dcdc(struct regulator_dev *dev,
807 unsigned selector)
808{
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500809 int volt, mult = 1, id = rdev_get_id(dev);
Graeme Gregory518fb722011-05-02 16:20:08 -0500810
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500811 switch (id) {
812 case TPS65910_REG_VDD1:
813 case TPS65910_REG_VDD2:
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530814 mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500815 volt = VDD1_2_MIN_VOLT +
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530816 (selector % VDD1_2_NUM_VOLT_FINE) * VDD1_2_OFFSET;
Axel Lind04156b2011-07-10 21:44:09 +0800817 break;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500818 case TPS65911_REG_VDDCTRL:
819 volt = VDDCTRL_MIN_VOLT + (selector * VDDCTRL_OFFSET);
Axel Lind04156b2011-07-10 21:44:09 +0800820 break;
821 default:
822 BUG();
823 return -EINVAL;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500824 }
Graeme Gregory518fb722011-05-02 16:20:08 -0500825
826 return volt * 100 * mult;
827}
828
829static int tps65910_list_voltage(struct regulator_dev *dev,
830 unsigned selector)
831{
832 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
833 int id = rdev_get_id(dev), voltage;
834
835 if (id < TPS65910_REG_VIO || id > TPS65910_REG_VMMC)
836 return -EINVAL;
837
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530838 if (selector >= pmic->info[id]->n_voltages)
Graeme Gregory518fb722011-05-02 16:20:08 -0500839 return -EINVAL;
840 else
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530841 voltage = pmic->info[id]->voltage_table[selector] * 1000;
Graeme Gregory518fb722011-05-02 16:20:08 -0500842
843 return voltage;
844}
845
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500846static int tps65911_list_voltage(struct regulator_dev *dev, unsigned selector)
847{
848 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
849 int step_mv = 0, id = rdev_get_id(dev);
850
851 switch(id) {
852 case TPS65911_REG_LDO1:
853 case TPS65911_REG_LDO2:
854 case TPS65911_REG_LDO4:
855 /* The first 5 values of the selector correspond to 1V */
856 if (selector < 5)
857 selector = 0;
858 else
859 selector -= 4;
860
861 step_mv = 50;
862 break;
863 case TPS65911_REG_LDO3:
864 case TPS65911_REG_LDO5:
865 case TPS65911_REG_LDO6:
866 case TPS65911_REG_LDO7:
867 case TPS65911_REG_LDO8:
868 /* The first 3 values of the selector correspond to 1V */
869 if (selector < 3)
870 selector = 0;
871 else
872 selector -= 2;
873
874 step_mv = 100;
875 break;
876 case TPS65910_REG_VIO:
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530877 return pmic->info[id]->voltage_table[selector] * 1000;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500878 default:
879 return -EINVAL;
880 }
881
882 return (LDO_MIN_VOLT + selector * step_mv) * 1000;
883}
884
Laxman Dewangan18039e02012-03-14 13:00:58 +0530885static int tps65910_set_voltage_dcdc_time_sel(struct regulator_dev *dev,
886 unsigned int old_selector, unsigned int new_selector)
887{
888 int id = rdev_get_id(dev);
889 int old_volt, new_volt;
890
891 old_volt = tps65910_list_voltage_dcdc(dev, old_selector);
892 if (old_volt < 0)
893 return old_volt;
894
895 new_volt = tps65910_list_voltage_dcdc(dev, new_selector);
896 if (new_volt < 0)
897 return new_volt;
898
899 /* VDD1 and VDD2 are 12.5mV/us, VDDCTRL is 100mV/20us */
900 switch (id) {
901 case TPS65910_REG_VDD1:
902 case TPS65910_REG_VDD2:
903 return DIV_ROUND_UP(abs(old_volt - new_volt), 12500);
904 case TPS65911_REG_VDDCTRL:
905 return DIV_ROUND_UP(abs(old_volt - new_volt), 5000);
906 }
907 return -EINVAL;
908}
909
Graeme Gregory518fb722011-05-02 16:20:08 -0500910/* Regulator ops (except VRTC) */
911static struct regulator_ops tps65910_ops_dcdc = {
912 .is_enabled = tps65910_is_enabled,
913 .enable = tps65910_enable,
914 .disable = tps65910_disable,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530915 .enable_time = tps65910_enable_time,
Graeme Gregory518fb722011-05-02 16:20:08 -0500916 .set_mode = tps65910_set_mode,
917 .get_mode = tps65910_get_mode,
Laxman Dewangan18039e02012-03-14 13:00:58 +0530918 .get_voltage_sel = tps65910_get_voltage_dcdc_sel,
Axel Lin94732b92012-03-09 10:22:20 +0800919 .set_voltage_sel = tps65910_set_voltage_dcdc_sel,
Laxman Dewangan18039e02012-03-14 13:00:58 +0530920 .set_voltage_time_sel = tps65910_set_voltage_dcdc_time_sel,
Graeme Gregory518fb722011-05-02 16:20:08 -0500921 .list_voltage = tps65910_list_voltage_dcdc,
922};
923
924static struct regulator_ops tps65910_ops_vdd3 = {
925 .is_enabled = tps65910_is_enabled,
926 .enable = tps65910_enable,
927 .disable = tps65910_disable,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530928 .enable_time = tps65910_enable_time,
Graeme Gregory518fb722011-05-02 16:20:08 -0500929 .set_mode = tps65910_set_mode,
930 .get_mode = tps65910_get_mode,
931 .get_voltage = tps65910_get_voltage_vdd3,
932 .list_voltage = tps65910_list_voltage,
933};
934
935static struct regulator_ops tps65910_ops = {
936 .is_enabled = tps65910_is_enabled,
937 .enable = tps65910_enable,
938 .disable = tps65910_disable,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530939 .enable_time = tps65910_enable_time,
Graeme Gregory518fb722011-05-02 16:20:08 -0500940 .set_mode = tps65910_set_mode,
941 .get_mode = tps65910_get_mode,
942 .get_voltage = tps65910_get_voltage,
Axel Lin94732b92012-03-09 10:22:20 +0800943 .set_voltage_sel = tps65910_set_voltage_sel,
Graeme Gregory518fb722011-05-02 16:20:08 -0500944 .list_voltage = tps65910_list_voltage,
945};
946
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500947static struct regulator_ops tps65911_ops = {
948 .is_enabled = tps65910_is_enabled,
949 .enable = tps65910_enable,
950 .disable = tps65910_disable,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530951 .enable_time = tps65910_enable_time,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500952 .set_mode = tps65910_set_mode,
953 .get_mode = tps65910_get_mode,
954 .get_voltage = tps65911_get_voltage,
Axel Lin94732b92012-03-09 10:22:20 +0800955 .set_voltage_sel = tps65911_set_voltage_sel,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500956 .list_voltage = tps65911_list_voltage,
957};
958
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530959static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic,
960 int id, int ext_sleep_config)
961{
962 struct tps65910 *mfd = pmic->mfd;
963 u8 regoffs = (pmic->ext_sleep_control[id] >> 8) & 0xFF;
964 u8 bit_pos = (1 << pmic->ext_sleep_control[id] & 0xFF);
965 int ret;
966
967 /*
968 * Regulator can not be control from multiple external input EN1, EN2
969 * and EN3 together.
970 */
971 if (ext_sleep_config & EXT_SLEEP_CONTROL) {
972 int en_count;
973 en_count = ((ext_sleep_config &
974 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) != 0);
975 en_count += ((ext_sleep_config &
976 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) != 0);
977 en_count += ((ext_sleep_config &
978 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) != 0);
Laxman Dewanganf30b0712012-03-07 18:21:49 +0530979 en_count += ((ext_sleep_config &
980 TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) != 0);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530981 if (en_count > 1) {
982 dev_err(mfd->dev,
983 "External sleep control flag is not proper\n");
984 return -EINVAL;
985 }
986 }
987
988 pmic->board_ext_control[id] = ext_sleep_config;
989
990 /* External EN1 control */
991 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1)
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700992 ret = tps65910_reg_set_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530993 TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
994 else
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700995 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530996 TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
997 if (ret < 0) {
998 dev_err(mfd->dev,
999 "Error in configuring external control EN1\n");
1000 return ret;
1001 }
1002
1003 /* External EN2 control */
1004 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2)
Rhyland Klein3f7e8272012-05-08 11:42:38 -07001005 ret = tps65910_reg_set_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301006 TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
1007 else
Rhyland Klein3f7e8272012-05-08 11:42:38 -07001008 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301009 TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
1010 if (ret < 0) {
1011 dev_err(mfd->dev,
1012 "Error in configuring external control EN2\n");
1013 return ret;
1014 }
1015
1016 /* External EN3 control for TPS65910 LDO only */
1017 if ((tps65910_chip_id(mfd) == TPS65910) &&
1018 (id >= TPS65910_REG_VDIG1)) {
1019 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3)
Rhyland Klein3f7e8272012-05-08 11:42:38 -07001020 ret = tps65910_reg_set_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301021 TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
1022 else
Rhyland Klein3f7e8272012-05-08 11:42:38 -07001023 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301024 TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
1025 if (ret < 0) {
1026 dev_err(mfd->dev,
1027 "Error in configuring external control EN3\n");
1028 return ret;
1029 }
1030 }
1031
1032 /* Return if no external control is selected */
1033 if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) {
1034 /* Clear all sleep controls */
Rhyland Klein3f7e8272012-05-08 11:42:38 -07001035 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301036 TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
1037 if (!ret)
Rhyland Klein3f7e8272012-05-08 11:42:38 -07001038 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301039 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
1040 if (ret < 0)
1041 dev_err(mfd->dev,
1042 "Error in configuring SLEEP register\n");
1043 return ret;
1044 }
1045
1046 /*
1047 * For regulator that has separate operational and sleep register make
1048 * sure that operational is used and clear sleep register to turn
1049 * regulator off when external control is inactive
1050 */
1051 if ((id == TPS65910_REG_VDD1) ||
1052 (id == TPS65910_REG_VDD2) ||
1053 ((id == TPS65911_REG_VDDCTRL) &&
1054 (tps65910_chip_id(mfd) == TPS65911))) {
1055 int op_reg_add = pmic->get_ctrl_reg(id) + 1;
1056 int sr_reg_add = pmic->get_ctrl_reg(id) + 2;
Rhyland Klein3f7e8272012-05-08 11:42:38 -07001057 int opvsel = tps65910_reg_read_locked(pmic, op_reg_add);
1058 int srvsel = tps65910_reg_read_locked(pmic, sr_reg_add);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301059 if (opvsel & VDD1_OP_CMD_MASK) {
1060 u8 reg_val = srvsel & VDD1_OP_SEL_MASK;
Rhyland Klein3f7e8272012-05-08 11:42:38 -07001061 ret = tps65910_reg_write_locked(pmic, op_reg_add,
1062 reg_val);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301063 if (ret < 0) {
1064 dev_err(mfd->dev,
1065 "Error in configuring op register\n");
1066 return ret;
1067 }
1068 }
Rhyland Klein3f7e8272012-05-08 11:42:38 -07001069 ret = tps65910_reg_write_locked(pmic, sr_reg_add, 0);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301070 if (ret < 0) {
1071 dev_err(mfd->dev, "Error in settting sr register\n");
1072 return ret;
1073 }
1074 }
1075
Rhyland Klein3f7e8272012-05-08 11:42:38 -07001076 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301077 TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
Laxman Dewanganf30b0712012-03-07 18:21:49 +05301078 if (!ret) {
1079 if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
Rhyland Klein3f7e8272012-05-08 11:42:38 -07001080 ret = tps65910_reg_set_bits(mfd,
Laxman Dewanganf30b0712012-03-07 18:21:49 +05301081 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
1082 else
Rhyland Klein3f7e8272012-05-08 11:42:38 -07001083 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewanganf30b0712012-03-07 18:21:49 +05301084 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
1085 }
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301086 if (ret < 0)
1087 dev_err(mfd->dev,
1088 "Error in configuring SLEEP register\n");
Laxman Dewanganf30b0712012-03-07 18:21:49 +05301089
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301090 return ret;
1091}
1092
Graeme Gregory518fb722011-05-02 16:20:08 -05001093static __devinit int tps65910_probe(struct platform_device *pdev)
1094{
1095 struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001096 struct tps_info *info;
Graeme Gregory518fb722011-05-02 16:20:08 -05001097 struct regulator_init_data *reg_data;
1098 struct regulator_dev *rdev;
1099 struct tps65910_reg *pmic;
1100 struct tps65910_board *pmic_plat_data;
Graeme Gregory518fb722011-05-02 16:20:08 -05001101 int i, err;
1102
1103 pmic_plat_data = dev_get_platdata(tps65910->dev);
1104 if (!pmic_plat_data)
1105 return -EINVAL;
1106
Graeme Gregory518fb722011-05-02 16:20:08 -05001107 pmic = kzalloc(sizeof(*pmic), GFP_KERNEL);
1108 if (!pmic)
1109 return -ENOMEM;
1110
1111 mutex_init(&pmic->mutex);
1112 pmic->mfd = tps65910;
1113 platform_set_drvdata(pdev, pmic);
1114
1115 /* Give control of all register to control port */
Rhyland Klein3f7e8272012-05-08 11:42:38 -07001116 tps65910_reg_set_bits(pmic->mfd, TPS65910_DEVCTRL,
Graeme Gregory518fb722011-05-02 16:20:08 -05001117 DEVCTRL_SR_CTL_I2C_SEL_MASK);
1118
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001119 switch(tps65910_chip_id(tps65910)) {
1120 case TPS65910:
1121 pmic->get_ctrl_reg = &tps65910_get_ctrl_register;
Axel Lin39aa9b62011-07-11 09:57:43 +08001122 pmic->num_regulators = ARRAY_SIZE(tps65910_regs);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301123 pmic->ext_sleep_control = tps65910_ext_sleep_control;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001124 info = tps65910_regs;
Axel Lind04156b2011-07-10 21:44:09 +08001125 break;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001126 case TPS65911:
1127 pmic->get_ctrl_reg = &tps65911_get_ctrl_register;
Axel Lin39aa9b62011-07-11 09:57:43 +08001128 pmic->num_regulators = ARRAY_SIZE(tps65911_regs);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301129 pmic->ext_sleep_control = tps65911_ext_sleep_control;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001130 info = tps65911_regs;
Axel Lind04156b2011-07-10 21:44:09 +08001131 break;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001132 default:
1133 pr_err("Invalid tps chip version\n");
Axel Lina3ee13e2011-07-10 18:52:07 +08001134 kfree(pmic);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001135 return -ENODEV;
1136 }
1137
Axel Lin39aa9b62011-07-11 09:57:43 +08001138 pmic->desc = kcalloc(pmic->num_regulators,
1139 sizeof(struct regulator_desc), GFP_KERNEL);
1140 if (!pmic->desc) {
1141 err = -ENOMEM;
1142 goto err_free_pmic;
1143 }
1144
1145 pmic->info = kcalloc(pmic->num_regulators,
1146 sizeof(struct tps_info *), GFP_KERNEL);
1147 if (!pmic->info) {
1148 err = -ENOMEM;
1149 goto err_free_desc;
1150 }
1151
1152 pmic->rdev = kcalloc(pmic->num_regulators,
1153 sizeof(struct regulator_dev *), GFP_KERNEL);
1154 if (!pmic->rdev) {
1155 err = -ENOMEM;
1156 goto err_free_info;
1157 }
1158
Kyle Mannac1fc1482011-11-03 12:08:06 -05001159 for (i = 0; i < pmic->num_regulators && i < TPS65910_NUM_REGS;
1160 i++, info++) {
1161
1162 reg_data = pmic_plat_data->tps65910_pmic_init_data[i];
1163
1164 /* Regulator API handles empty constraints but not NULL
1165 * constraints */
1166 if (!reg_data)
1167 continue;
1168
Graeme Gregory518fb722011-05-02 16:20:08 -05001169 /* Register the regulators */
1170 pmic->info[i] = info;
1171
1172 pmic->desc[i].name = info->name;
Axel Lin77fa44d2011-05-12 13:47:50 +08001173 pmic->desc[i].id = i;
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +05301174 pmic->desc[i].n_voltages = info->n_voltages;
Graeme Gregory518fb722011-05-02 16:20:08 -05001175
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001176 if (i == TPS65910_REG_VDD1 || i == TPS65910_REG_VDD2) {
Graeme Gregory518fb722011-05-02 16:20:08 -05001177 pmic->desc[i].ops = &tps65910_ops_dcdc;
Afzal Mohammed780dc9b2011-11-08 18:54:10 +05301178 pmic->desc[i].n_voltages = VDD1_2_NUM_VOLT_FINE *
1179 VDD1_2_NUM_VOLT_COARSE;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001180 } else if (i == TPS65910_REG_VDD3) {
1181 if (tps65910_chip_id(tps65910) == TPS65910)
1182 pmic->desc[i].ops = &tps65910_ops_vdd3;
1183 else
1184 pmic->desc[i].ops = &tps65910_ops_dcdc;
1185 } else {
1186 if (tps65910_chip_id(tps65910) == TPS65910)
1187 pmic->desc[i].ops = &tps65910_ops;
1188 else
1189 pmic->desc[i].ops = &tps65911_ops;
1190 }
Graeme Gregory518fb722011-05-02 16:20:08 -05001191
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301192 err = tps65910_set_ext_sleep_config(pmic, i,
1193 pmic_plat_data->regulator_ext_sleep_control[i]);
1194 /*
1195 * Failing on regulator for configuring externally control
1196 * is not a serious issue, just throw warning.
1197 */
1198 if (err < 0)
1199 dev_warn(tps65910->dev,
1200 "Failed to initialise ext control config\n");
1201
Graeme Gregory518fb722011-05-02 16:20:08 -05001202 pmic->desc[i].type = REGULATOR_VOLTAGE;
1203 pmic->desc[i].owner = THIS_MODULE;
1204
1205 rdev = regulator_register(&pmic->desc[i],
Rajendra Nayak2c043bc2011-11-18 16:47:19 +05301206 tps65910->dev, reg_data, pmic, NULL);
Graeme Gregory518fb722011-05-02 16:20:08 -05001207 if (IS_ERR(rdev)) {
1208 dev_err(tps65910->dev,
1209 "failed to register %s regulator\n",
1210 pdev->name);
1211 err = PTR_ERR(rdev);
Axel Lin39aa9b62011-07-11 09:57:43 +08001212 goto err_unregister_regulator;
Graeme Gregory518fb722011-05-02 16:20:08 -05001213 }
1214
1215 /* Save regulator for cleanup */
1216 pmic->rdev[i] = rdev;
1217 }
1218 return 0;
1219
Axel Lin39aa9b62011-07-11 09:57:43 +08001220err_unregister_regulator:
Graeme Gregory518fb722011-05-02 16:20:08 -05001221 while (--i >= 0)
1222 regulator_unregister(pmic->rdev[i]);
Axel Lin39aa9b62011-07-11 09:57:43 +08001223 kfree(pmic->rdev);
1224err_free_info:
1225 kfree(pmic->info);
1226err_free_desc:
1227 kfree(pmic->desc);
1228err_free_pmic:
Graeme Gregory518fb722011-05-02 16:20:08 -05001229 kfree(pmic);
1230 return err;
1231}
1232
1233static int __devexit tps65910_remove(struct platform_device *pdev)
1234{
Axel Lin39aa9b62011-07-11 09:57:43 +08001235 struct tps65910_reg *pmic = platform_get_drvdata(pdev);
Graeme Gregory518fb722011-05-02 16:20:08 -05001236 int i;
1237
Axel Lin39aa9b62011-07-11 09:57:43 +08001238 for (i = 0; i < pmic->num_regulators; i++)
1239 regulator_unregister(pmic->rdev[i]);
Graeme Gregory518fb722011-05-02 16:20:08 -05001240
Axel Lin39aa9b62011-07-11 09:57:43 +08001241 kfree(pmic->rdev);
1242 kfree(pmic->info);
1243 kfree(pmic->desc);
1244 kfree(pmic);
Graeme Gregory518fb722011-05-02 16:20:08 -05001245 return 0;
1246}
1247
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301248static void tps65910_shutdown(struct platform_device *pdev)
1249{
1250 struct tps65910_reg *pmic = platform_get_drvdata(pdev);
1251 int i;
1252
1253 /*
1254 * Before bootloader jumps to kernel, it makes sure that required
1255 * external control signals are in desired state so that given rails
1256 * can be configure accordingly.
1257 * If rails are configured to be controlled from external control
1258 * then before shutting down/rebooting the system, the external
1259 * control configuration need to be remove from the rails so that
1260 * its output will be available as per register programming even
1261 * if external controls are removed. This is require when the POR
1262 * value of the control signals are not in active state and before
1263 * bootloader initializes it, the system requires the rail output
1264 * to be active for booting.
1265 */
1266 for (i = 0; i < pmic->num_regulators; i++) {
1267 int err;
1268 if (!pmic->rdev[i])
1269 continue;
1270
1271 err = tps65910_set_ext_sleep_config(pmic, i, 0);
1272 if (err < 0)
1273 dev_err(&pdev->dev,
1274 "Error in clearing external control\n");
1275 }
1276}
1277
Graeme Gregory518fb722011-05-02 16:20:08 -05001278static struct platform_driver tps65910_driver = {
1279 .driver = {
1280 .name = "tps65910-pmic",
1281 .owner = THIS_MODULE,
1282 },
1283 .probe = tps65910_probe,
1284 .remove = __devexit_p(tps65910_remove),
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301285 .shutdown = tps65910_shutdown,
Graeme Gregory518fb722011-05-02 16:20:08 -05001286};
1287
1288static int __init tps65910_init(void)
1289{
1290 return platform_driver_register(&tps65910_driver);
1291}
1292subsys_initcall(tps65910_init);
1293
1294static void __exit tps65910_cleanup(void)
1295{
1296 platform_driver_unregister(&tps65910_driver);
1297}
1298module_exit(tps65910_cleanup);
1299
1300MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
Axel Linae0e6542012-02-21 10:14:55 +08001301MODULE_DESCRIPTION("TPS65910/TPS65911 voltage regulator driver");
Graeme Gregory518fb722011-05-02 16:20:08 -05001302MODULE_LICENSE("GPL v2");
1303MODULE_ALIAS("platform:tps65910-pmic");