Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #include <linux/console.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 30 | #include <drm/drmP.h> |
| 31 | #include <drm/drm_crtc_helper.h> |
| 32 | #include <drm/radeon_drm.h> |
Lukas Wunner | b875194 | 2016-06-08 18:47:27 +0200 | [diff] [blame] | 33 | #include <linux/pm_runtime.h> |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 34 | #include <linux/vgaarb.h> |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 35 | #include <linux/vga_switcheroo.h> |
Matthew Garrett | bcc65fd | 2011-08-08 16:21:16 +0000 | [diff] [blame] | 36 | #include <linux/efi.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 37 | #include "radeon_reg.h" |
| 38 | #include "radeon.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 39 | #include "atom.h" |
| 40 | |
Jerome Glisse | 1b5331d | 2010-04-12 20:21:53 +0000 | [diff] [blame] | 41 | static const char radeon_family_name[][16] = { |
| 42 | "R100", |
| 43 | "RV100", |
| 44 | "RS100", |
| 45 | "RV200", |
| 46 | "RS200", |
| 47 | "R200", |
| 48 | "RV250", |
| 49 | "RS300", |
| 50 | "RV280", |
| 51 | "R300", |
| 52 | "R350", |
| 53 | "RV350", |
| 54 | "RV380", |
| 55 | "R420", |
| 56 | "R423", |
| 57 | "RV410", |
| 58 | "RS400", |
| 59 | "RS480", |
| 60 | "RS600", |
| 61 | "RS690", |
| 62 | "RS740", |
| 63 | "RV515", |
| 64 | "R520", |
| 65 | "RV530", |
| 66 | "RV560", |
| 67 | "RV570", |
| 68 | "R580", |
| 69 | "R600", |
| 70 | "RV610", |
| 71 | "RV630", |
| 72 | "RV670", |
| 73 | "RV620", |
| 74 | "RV635", |
| 75 | "RS780", |
| 76 | "RS880", |
| 77 | "RV770", |
| 78 | "RV730", |
| 79 | "RV710", |
| 80 | "RV740", |
| 81 | "CEDAR", |
| 82 | "REDWOOD", |
| 83 | "JUNIPER", |
| 84 | "CYPRESS", |
| 85 | "HEMLOCK", |
Alex Deucher | b08ebe7 | 2010-12-03 15:34:16 -0500 | [diff] [blame] | 86 | "PALM", |
Alex Deucher | 4df64e6 | 2011-05-31 15:42:46 -0400 | [diff] [blame] | 87 | "SUMO", |
| 88 | "SUMO2", |
Alex Deucher | 1fe1830 | 2011-01-06 21:19:12 -0500 | [diff] [blame] | 89 | "BARTS", |
| 90 | "TURKS", |
| 91 | "CAICOS", |
Alex Deucher | b7cfc9f | 2011-03-02 20:07:27 -0500 | [diff] [blame] | 92 | "CAYMAN", |
Alex Deucher | 8848f75 | 2012-03-20 17:18:28 -0400 | [diff] [blame] | 93 | "ARUBA", |
Alex Deucher | cb28bb3 | 2012-03-20 17:17:59 -0400 | [diff] [blame] | 94 | "TAHITI", |
| 95 | "PITCAIRN", |
| 96 | "VERDE", |
Alex Deucher | 624d352 | 2012-12-18 17:01:35 -0500 | [diff] [blame] | 97 | "OLAND", |
Alex Deucher | b5d9d72 | 2012-07-26 18:53:55 -0400 | [diff] [blame] | 98 | "HAINAN", |
Alex Deucher | 6eac752e | 2013-06-07 11:36:11 -0400 | [diff] [blame] | 99 | "BONAIRE", |
| 100 | "KAVERI", |
| 101 | "KABINI", |
Alex Deucher | 3bf599e | 2013-08-06 15:13:36 -0400 | [diff] [blame] | 102 | "HAWAII", |
Samuel Li | b0a9f22 | 2014-04-30 18:40:48 -0400 | [diff] [blame] | 103 | "MULLINS", |
Jerome Glisse | 1b5331d | 2010-04-12 20:21:53 +0000 | [diff] [blame] | 104 | "LAST", |
| 105 | }; |
| 106 | |
Alex Deucher | 066f1f0 | 2016-10-31 10:41:49 -0400 | [diff] [blame] | 107 | #if defined(CONFIG_VGA_SWITCHEROO) |
| 108 | bool radeon_has_atpx_dgpu_power_cntl(void); |
| 109 | bool radeon_is_atpx_hybrid(void); |
| 110 | #else |
| 111 | static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } |
| 112 | static inline bool radeon_is_atpx_hybrid(void) { return false; } |
| 113 | #endif |
| 114 | |
Alex Deucher | 4807c5a | 2014-07-18 11:54:20 -0400 | [diff] [blame] | 115 | #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0) |
| 116 | #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1) |
| 117 | |
| 118 | struct radeon_px_quirk { |
| 119 | u32 chip_vendor; |
| 120 | u32 chip_device; |
| 121 | u32 subsys_vendor; |
| 122 | u32 subsys_device; |
| 123 | u32 px_quirk_flags; |
| 124 | }; |
| 125 | |
| 126 | static struct radeon_px_quirk radeon_px_quirk_list[] = { |
| 127 | /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m) |
| 128 | * https://bugzilla.kernel.org/show_bug.cgi?id=74551 |
| 129 | */ |
| 130 | { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX }, |
| 131 | /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU |
| 132 | * https://bugzilla.kernel.org/show_bug.cgi?id=51381 |
| 133 | */ |
| 134 | { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX }, |
Alex Deucher | ff1b129 | 2014-09-22 17:28:29 -0400 | [diff] [blame] | 135 | /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU |
| 136 | * https://bugzilla.kernel.org/show_bug.cgi?id=51381 |
| 137 | */ |
| 138 | { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, |
Alex Deucher | 61ea7c2 | 2017-06-19 12:52:47 -0400 | [diff] [blame] | 139 | /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU |
| 140 | * https://bugs.freedesktop.org/show_bug.cgi?id=101491 |
| 141 | */ |
| 142 | { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, |
Alex Deucher | 4807c5a | 2014-07-18 11:54:20 -0400 | [diff] [blame] | 143 | /* macbook pro 8.2 */ |
| 144 | { PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP }, |
| 145 | { 0, 0, 0, 0, 0 }, |
| 146 | }; |
| 147 | |
Alex Deucher | 90c4cde | 2014-04-10 22:29:01 -0400 | [diff] [blame] | 148 | bool radeon_is_px(struct drm_device *dev) |
| 149 | { |
| 150 | struct radeon_device *rdev = dev->dev_private; |
| 151 | |
| 152 | if (rdev->flags & RADEON_IS_PX) |
| 153 | return true; |
| 154 | return false; |
| 155 | } |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 156 | |
Alex Deucher | 4807c5a | 2014-07-18 11:54:20 -0400 | [diff] [blame] | 157 | static void radeon_device_handle_px_quirks(struct radeon_device *rdev) |
| 158 | { |
| 159 | struct radeon_px_quirk *p = radeon_px_quirk_list; |
| 160 | |
| 161 | /* Apply PX quirks */ |
| 162 | while (p && p->chip_device != 0) { |
| 163 | if (rdev->pdev->vendor == p->chip_vendor && |
| 164 | rdev->pdev->device == p->chip_device && |
| 165 | rdev->pdev->subsystem_vendor == p->subsys_vendor && |
| 166 | rdev->pdev->subsystem_device == p->subsys_device) { |
| 167 | rdev->px_quirk_flags = p->px_quirk_flags; |
| 168 | break; |
| 169 | } |
| 170 | ++p; |
| 171 | } |
| 172 | |
| 173 | if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX) |
| 174 | rdev->flags &= ~RADEON_IS_PX; |
Alex Deucher | 066f1f0 | 2016-10-31 10:41:49 -0400 | [diff] [blame] | 175 | |
| 176 | /* disable PX is the system doesn't support dGPU power control or hybrid gfx */ |
| 177 | if (!radeon_is_atpx_hybrid() && |
| 178 | !radeon_has_atpx_dgpu_power_cntl()) |
| 179 | rdev->flags &= ~RADEON_IS_PX; |
Alex Deucher | 4807c5a | 2014-07-18 11:54:20 -0400 | [diff] [blame] | 180 | } |
| 181 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 182 | /** |
Alex Deucher | 2e1b65f | 2013-02-26 11:26:51 -0500 | [diff] [blame] | 183 | * radeon_program_register_sequence - program an array of registers. |
| 184 | * |
| 185 | * @rdev: radeon_device pointer |
| 186 | * @registers: pointer to the register array |
| 187 | * @array_size: size of the register array |
| 188 | * |
| 189 | * Programs an array or registers with and and or masks. |
| 190 | * This is a helper for setting golden registers. |
| 191 | */ |
| 192 | void radeon_program_register_sequence(struct radeon_device *rdev, |
| 193 | const u32 *registers, |
| 194 | const u32 array_size) |
| 195 | { |
| 196 | u32 tmp, reg, and_mask, or_mask; |
| 197 | int i; |
| 198 | |
| 199 | if (array_size % 3) |
| 200 | return; |
| 201 | |
| 202 | for (i = 0; i < array_size; i +=3) { |
| 203 | reg = registers[i + 0]; |
| 204 | and_mask = registers[i + 1]; |
| 205 | or_mask = registers[i + 2]; |
| 206 | |
| 207 | if (and_mask == 0xffffffff) { |
| 208 | tmp = or_mask; |
| 209 | } else { |
| 210 | tmp = RREG32(reg); |
| 211 | tmp &= ~and_mask; |
| 212 | tmp |= or_mask; |
| 213 | } |
| 214 | WREG32(reg, tmp); |
| 215 | } |
| 216 | } |
| 217 | |
Alex Deucher | 1a0041b | 2013-10-02 13:01:36 -0400 | [diff] [blame] | 218 | void radeon_pci_config_reset(struct radeon_device *rdev) |
| 219 | { |
| 220 | pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA); |
| 221 | } |
| 222 | |
Alex Deucher | 2e1b65f | 2013-02-26 11:26:51 -0500 | [diff] [blame] | 223 | /** |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 224 | * radeon_surface_init - Clear GPU surface registers. |
| 225 | * |
| 226 | * @rdev: radeon_device pointer |
| 227 | * |
| 228 | * Clear GPU surface registers (r1xx-r5xx). |
Michel Dänzer | b1e3a6d | 2009-06-23 16:12:54 +0200 | [diff] [blame] | 229 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 230 | void radeon_surface_init(struct radeon_device *rdev) |
Michel Dänzer | b1e3a6d | 2009-06-23 16:12:54 +0200 | [diff] [blame] | 231 | { |
| 232 | /* FIXME: check this out */ |
| 233 | if (rdev->family < CHIP_R600) { |
| 234 | int i; |
| 235 | |
Dave Airlie | 550e2d9 | 2009-12-09 14:15:38 +1000 | [diff] [blame] | 236 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
| 237 | if (rdev->surface_regs[i].bo) |
| 238 | radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); |
| 239 | else |
| 240 | radeon_clear_surface_reg(rdev, i); |
Michel Dänzer | b1e3a6d | 2009-06-23 16:12:54 +0200 | [diff] [blame] | 241 | } |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 242 | /* enable surfaces */ |
| 243 | WREG32(RADEON_SURFACE_CNTL, 0); |
Michel Dänzer | b1e3a6d | 2009-06-23 16:12:54 +0200 | [diff] [blame] | 244 | } |
| 245 | } |
| 246 | |
| 247 | /* |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 248 | * GPU scratch registers helpers function. |
| 249 | */ |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 250 | /** |
| 251 | * radeon_scratch_init - Init scratch register driver information. |
| 252 | * |
| 253 | * @rdev: radeon_device pointer |
| 254 | * |
| 255 | * Init CP scratch register driver information (r1xx-r5xx) |
| 256 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 257 | void radeon_scratch_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 258 | { |
| 259 | int i; |
| 260 | |
| 261 | /* FIXME: check this out */ |
| 262 | if (rdev->family < CHIP_R300) { |
| 263 | rdev->scratch.num_reg = 5; |
| 264 | } else { |
| 265 | rdev->scratch.num_reg = 7; |
| 266 | } |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 267 | rdev->scratch.reg_base = RADEON_SCRATCH_REG0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 268 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
| 269 | rdev->scratch.free[i] = true; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 270 | rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 271 | } |
| 272 | } |
| 273 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 274 | /** |
| 275 | * radeon_scratch_get - Allocate a scratch register |
| 276 | * |
| 277 | * @rdev: radeon_device pointer |
| 278 | * @reg: scratch register mmio offset |
| 279 | * |
| 280 | * Allocate a CP scratch register for use by the driver (all asics). |
| 281 | * Returns 0 on success or -EINVAL on failure. |
| 282 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 283 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) |
| 284 | { |
| 285 | int i; |
| 286 | |
| 287 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
| 288 | if (rdev->scratch.free[i]) { |
| 289 | rdev->scratch.free[i] = false; |
| 290 | *reg = rdev->scratch.reg[i]; |
| 291 | return 0; |
| 292 | } |
| 293 | } |
| 294 | return -EINVAL; |
| 295 | } |
| 296 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 297 | /** |
| 298 | * radeon_scratch_free - Free a scratch register |
| 299 | * |
| 300 | * @rdev: radeon_device pointer |
| 301 | * @reg: scratch register mmio offset |
| 302 | * |
| 303 | * Free a CP scratch register allocated for use by the driver (all asics) |
| 304 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 305 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) |
| 306 | { |
| 307 | int i; |
| 308 | |
| 309 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
| 310 | if (rdev->scratch.reg[i] == reg) { |
| 311 | rdev->scratch.free[i] = true; |
| 312 | return; |
| 313 | } |
| 314 | } |
| 315 | } |
| 316 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 317 | /* |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 318 | * GPU doorbell aperture helpers function. |
| 319 | */ |
| 320 | /** |
| 321 | * radeon_doorbell_init - Init doorbell driver information. |
| 322 | * |
| 323 | * @rdev: radeon_device pointer |
| 324 | * |
| 325 | * Init doorbell driver information (CIK) |
| 326 | * Returns 0 on success, error on failure. |
| 327 | */ |
Rashika Kheria | 28f5a6c | 2014-01-06 20:51:40 +0530 | [diff] [blame] | 328 | static int radeon_doorbell_init(struct radeon_device *rdev) |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 329 | { |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 330 | /* doorbell bar mapping */ |
| 331 | rdev->doorbell.base = pci_resource_start(rdev->pdev, 2); |
| 332 | rdev->doorbell.size = pci_resource_len(rdev->pdev, 2); |
| 333 | |
Andrew Lewycky | d5754ab | 2013-11-13 15:54:17 -0500 | [diff] [blame] | 334 | rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS); |
| 335 | if (rdev->doorbell.num_doorbells == 0) |
| 336 | return -EINVAL; |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 337 | |
Andrew Lewycky | d5754ab | 2013-11-13 15:54:17 -0500 | [diff] [blame] | 338 | rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32)); |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 339 | if (rdev->doorbell.ptr == NULL) { |
| 340 | return -ENOMEM; |
| 341 | } |
| 342 | DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base); |
| 343 | DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size); |
| 344 | |
Andrew Lewycky | d5754ab | 2013-11-13 15:54:17 -0500 | [diff] [blame] | 345 | memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used)); |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 346 | |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 347 | return 0; |
| 348 | } |
| 349 | |
| 350 | /** |
| 351 | * radeon_doorbell_fini - Tear down doorbell driver information. |
| 352 | * |
| 353 | * @rdev: radeon_device pointer |
| 354 | * |
| 355 | * Tear down doorbell driver information (CIK) |
| 356 | */ |
Rashika Kheria | 28f5a6c | 2014-01-06 20:51:40 +0530 | [diff] [blame] | 357 | static void radeon_doorbell_fini(struct radeon_device *rdev) |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 358 | { |
| 359 | iounmap(rdev->doorbell.ptr); |
| 360 | rdev->doorbell.ptr = NULL; |
| 361 | } |
| 362 | |
| 363 | /** |
Andrew Lewycky | d5754ab | 2013-11-13 15:54:17 -0500 | [diff] [blame] | 364 | * radeon_doorbell_get - Allocate a doorbell entry |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 365 | * |
| 366 | * @rdev: radeon_device pointer |
Andrew Lewycky | d5754ab | 2013-11-13 15:54:17 -0500 | [diff] [blame] | 367 | * @doorbell: doorbell index |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 368 | * |
Andrew Lewycky | d5754ab | 2013-11-13 15:54:17 -0500 | [diff] [blame] | 369 | * Allocate a doorbell for use by the driver (all asics). |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 370 | * Returns 0 on success or -EINVAL on failure. |
| 371 | */ |
| 372 | int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell) |
| 373 | { |
Andrew Lewycky | d5754ab | 2013-11-13 15:54:17 -0500 | [diff] [blame] | 374 | unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells); |
| 375 | if (offset < rdev->doorbell.num_doorbells) { |
| 376 | __set_bit(offset, rdev->doorbell.used); |
| 377 | *doorbell = offset; |
| 378 | return 0; |
| 379 | } else { |
| 380 | return -EINVAL; |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 381 | } |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 382 | } |
| 383 | |
| 384 | /** |
Andrew Lewycky | d5754ab | 2013-11-13 15:54:17 -0500 | [diff] [blame] | 385 | * radeon_doorbell_free - Free a doorbell entry |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 386 | * |
| 387 | * @rdev: radeon_device pointer |
Andrew Lewycky | d5754ab | 2013-11-13 15:54:17 -0500 | [diff] [blame] | 388 | * @doorbell: doorbell index |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 389 | * |
Andrew Lewycky | d5754ab | 2013-11-13 15:54:17 -0500 | [diff] [blame] | 390 | * Free a doorbell allocated for use by the driver (all asics) |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 391 | */ |
| 392 | void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell) |
| 393 | { |
Andrew Lewycky | d5754ab | 2013-11-13 15:54:17 -0500 | [diff] [blame] | 394 | if (doorbell < rdev->doorbell.num_doorbells) |
| 395 | __clear_bit(doorbell, rdev->doorbell.used); |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 396 | } |
| 397 | |
Oded Gabbay | ebff845 | 2014-01-28 14:43:19 +0200 | [diff] [blame] | 398 | /** |
| 399 | * radeon_doorbell_get_kfd_info - Report doorbell configuration required to |
| 400 | * setup KFD |
| 401 | * |
| 402 | * @rdev: radeon_device pointer |
| 403 | * @aperture_base: output returning doorbell aperture base physical address |
| 404 | * @aperture_size: output returning doorbell aperture size in bytes |
| 405 | * @start_offset: output returning # of doorbell bytes reserved for radeon. |
| 406 | * |
| 407 | * Radeon and the KFD share the doorbell aperture. Radeon sets it up, |
| 408 | * takes doorbells required for its own rings and reports the setup to KFD. |
| 409 | * Radeon reserved doorbells are at the start of the doorbell aperture. |
| 410 | */ |
| 411 | void radeon_doorbell_get_kfd_info(struct radeon_device *rdev, |
| 412 | phys_addr_t *aperture_base, |
| 413 | size_t *aperture_size, |
| 414 | size_t *start_offset) |
| 415 | { |
| 416 | /* The first num_doorbells are used by radeon. |
| 417 | * KFD takes whatever's left in the aperture. */ |
| 418 | if (rdev->doorbell.size > rdev->doorbell.num_doorbells * sizeof(u32)) { |
| 419 | *aperture_base = rdev->doorbell.base; |
| 420 | *aperture_size = rdev->doorbell.size; |
| 421 | *start_offset = rdev->doorbell.num_doorbells * sizeof(u32); |
| 422 | } else { |
| 423 | *aperture_base = 0; |
| 424 | *aperture_size = 0; |
| 425 | *start_offset = 0; |
| 426 | } |
| 427 | } |
| 428 | |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 429 | /* |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 430 | * radeon_wb_*() |
| 431 | * Writeback is the the method by which the the GPU updates special pages |
| 432 | * in memory with the status of certain GPU events (fences, ring pointers, |
| 433 | * etc.). |
| 434 | */ |
| 435 | |
| 436 | /** |
| 437 | * radeon_wb_disable - Disable Writeback |
| 438 | * |
| 439 | * @rdev: radeon_device pointer |
| 440 | * |
| 441 | * Disables Writeback (all asics). Used for suspend. |
| 442 | */ |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 443 | void radeon_wb_disable(struct radeon_device *rdev) |
| 444 | { |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 445 | rdev->wb.enabled = false; |
| 446 | } |
| 447 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 448 | /** |
| 449 | * radeon_wb_fini - Disable Writeback and free memory |
| 450 | * |
| 451 | * @rdev: radeon_device pointer |
| 452 | * |
| 453 | * Disables Writeback and frees the Writeback memory (all asics). |
| 454 | * Used at driver shutdown. |
| 455 | */ |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 456 | void radeon_wb_fini(struct radeon_device *rdev) |
| 457 | { |
| 458 | radeon_wb_disable(rdev); |
| 459 | if (rdev->wb.wb_obj) { |
Jerome Glisse | 089920f | 2013-06-06 17:51:21 -0400 | [diff] [blame] | 460 | if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) { |
| 461 | radeon_bo_kunmap(rdev->wb.wb_obj); |
| 462 | radeon_bo_unpin(rdev->wb.wb_obj); |
| 463 | radeon_bo_unreserve(rdev->wb.wb_obj); |
| 464 | } |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 465 | radeon_bo_unref(&rdev->wb.wb_obj); |
| 466 | rdev->wb.wb = NULL; |
| 467 | rdev->wb.wb_obj = NULL; |
| 468 | } |
| 469 | } |
| 470 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 471 | /** |
| 472 | * radeon_wb_init- Init Writeback driver info and allocate memory |
| 473 | * |
| 474 | * @rdev: radeon_device pointer |
| 475 | * |
| 476 | * Disables Writeback and frees the Writeback memory (all asics). |
| 477 | * Used at driver startup. |
| 478 | * Returns 0 on success or an -error on failure. |
| 479 | */ |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 480 | int radeon_wb_init(struct radeon_device *rdev) |
| 481 | { |
| 482 | int r; |
| 483 | |
| 484 | if (rdev->wb.wb_obj == NULL) { |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 485 | r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, |
Maarten Lankhorst | 831b696 | 2014-09-18 14:11:56 +0200 | [diff] [blame] | 486 | RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL, |
Michel Dänzer | 02376d8 | 2014-07-17 19:01:08 +0900 | [diff] [blame] | 487 | &rdev->wb.wb_obj); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 488 | if (r) { |
| 489 | dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); |
| 490 | return r; |
| 491 | } |
Jerome Glisse | 089920f | 2013-06-06 17:51:21 -0400 | [diff] [blame] | 492 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
| 493 | if (unlikely(r != 0)) { |
| 494 | radeon_wb_fini(rdev); |
| 495 | return r; |
| 496 | } |
| 497 | r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, |
| 498 | &rdev->wb.gpu_addr); |
| 499 | if (r) { |
| 500 | radeon_bo_unreserve(rdev->wb.wb_obj); |
| 501 | dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); |
| 502 | radeon_wb_fini(rdev); |
| 503 | return r; |
| 504 | } |
| 505 | r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 506 | radeon_bo_unreserve(rdev->wb.wb_obj); |
Jerome Glisse | 089920f | 2013-06-06 17:51:21 -0400 | [diff] [blame] | 507 | if (r) { |
| 508 | dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); |
| 509 | radeon_wb_fini(rdev); |
| 510 | return r; |
| 511 | } |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 512 | } |
| 513 | |
Alex Deucher | e6ba759 | 2011-06-13 22:02:51 +0000 | [diff] [blame] | 514 | /* clear wb memory */ |
| 515 | memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE); |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 516 | /* disable event_write fences */ |
| 517 | rdev->wb.use_event = false; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 518 | /* disabled via module param */ |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 519 | if (radeon_no_wb == 1) { |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 520 | rdev->wb.enabled = false; |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 521 | } else { |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 522 | if (rdev->flags & RADEON_IS_AGP) { |
Alex Deucher | 28eebb7 | 2012-01-03 09:48:38 -0500 | [diff] [blame] | 523 | /* often unreliable on AGP */ |
| 524 | rdev->wb.enabled = false; |
| 525 | } else if (rdev->family < CHIP_R300) { |
| 526 | /* often unreliable on pre-r300 */ |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 527 | rdev->wb.enabled = false; |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 528 | } else { |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 529 | rdev->wb.enabled = true; |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 530 | /* event_write fences are only available on r600+ */ |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 531 | if (rdev->family >= CHIP_R600) { |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 532 | rdev->wb.use_event = true; |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 533 | } |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 534 | } |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 535 | } |
Alex Deucher | c994ead | 2012-05-03 17:06:28 -0400 | [diff] [blame] | 536 | /* always use writeback/events on NI, APUs */ |
| 537 | if (rdev->family >= CHIP_PALM) { |
Alex Deucher | 7d52785 | 2011-01-06 21:19:27 -0500 | [diff] [blame] | 538 | rdev->wb.enabled = true; |
| 539 | rdev->wb.use_event = true; |
| 540 | } |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 541 | |
| 542 | dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); |
| 543 | |
| 544 | return 0; |
| 545 | } |
| 546 | |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 547 | /** |
| 548 | * radeon_vram_location - try to find VRAM location |
| 549 | * @rdev: radeon device structure holding all necessary informations |
| 550 | * @mc: memory controller structure holding memory informations |
| 551 | * @base: base address at which to put VRAM |
| 552 | * |
| 553 | * Function will place try to place VRAM at base address provided |
| 554 | * as parameter (which is so far either PCI aperture address or |
| 555 | * for IGP TOM base address). |
| 556 | * |
| 557 | * If there is not enough space to fit the unvisible VRAM in the 32bits |
| 558 | * address space then we limit the VRAM size to the aperture. |
| 559 | * |
| 560 | * If we are using AGP and if the AGP aperture doesn't allow us to have |
| 561 | * room for all the VRAM than we restrict the VRAM to the PCI aperture |
| 562 | * size and print a warning. |
| 563 | * |
| 564 | * This function will never fails, worst case are limiting VRAM. |
| 565 | * |
| 566 | * Note: GTT start, end, size should be initialized before calling this |
| 567 | * function on AGP platform. |
| 568 | * |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 569 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 570 | * this shouldn't be a problem as we are using the PCI aperture as a reference. |
| 571 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but |
| 572 | * not IGP. |
| 573 | * |
| 574 | * Note: we use mc_vram_size as on some board we need to program the mc to |
| 575 | * cover the whole aperture even if VRAM size is inferior to aperture size |
| 576 | * Novell bug 204882 + along with lots of ubuntu ones |
| 577 | * |
| 578 | * Note: when limiting vram it's safe to overwritte real_vram_size because |
| 579 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie |
| 580 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu |
| 581 | * ones) |
| 582 | * |
| 583 | * Note: IGP TOM addr should be the same as the aperture addr, we don't |
| 584 | * explicitly check for that thought. |
| 585 | * |
| 586 | * FIXME: when reducing VRAM size align new size on power of 2. |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 587 | */ |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 588 | void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 589 | { |
Christian König | 1bcb04f | 2012-10-23 15:53:16 +0200 | [diff] [blame] | 590 | uint64_t limit = (uint64_t)radeon_vram_limit << 20; |
| 591 | |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 592 | mc->vram_start = base; |
Alex Deucher | 9ed8b1f | 2013-04-08 11:13:01 -0400 | [diff] [blame] | 593 | if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 594 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
| 595 | mc->real_vram_size = mc->aper_size; |
| 596 | mc->mc_vram_size = mc->aper_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 597 | } |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 598 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
Jerome Glisse | 2cbeb4e | 2010-08-16 11:54:36 -0400 | [diff] [blame] | 599 | if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 600 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
| 601 | mc->real_vram_size = mc->aper_size; |
| 602 | mc->mc_vram_size = mc->aper_size; |
| 603 | } |
| 604 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
Christian König | 1bcb04f | 2012-10-23 15:53:16 +0200 | [diff] [blame] | 605 | if (limit && limit < mc->real_vram_size) |
| 606 | mc->real_vram_size = limit; |
Alex Deucher | dd7cc55 | 2010-12-03 14:37:21 -0500 | [diff] [blame] | 607 | dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 608 | mc->mc_vram_size >> 20, mc->vram_start, |
| 609 | mc->vram_end, mc->real_vram_size >> 20); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 610 | } |
| 611 | |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 612 | /** |
| 613 | * radeon_gtt_location - try to find GTT location |
| 614 | * @rdev: radeon device structure holding all necessary informations |
| 615 | * @mc: memory controller structure holding memory informations |
| 616 | * |
| 617 | * Function will place try to place GTT before or after VRAM. |
| 618 | * |
| 619 | * If GTT size is bigger than space left then we ajust GTT size. |
| 620 | * Thus function will never fails. |
| 621 | * |
| 622 | * FIXME: when reducing GTT size align new size on power of 2. |
| 623 | */ |
| 624 | void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
| 625 | { |
| 626 | u64 size_af, size_bf; |
| 627 | |
Alex Deucher | 9ed8b1f | 2013-04-08 11:13:01 -0400 | [diff] [blame] | 628 | size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; |
Alex Deucher | 8d369bb | 2010-07-15 10:51:10 -0400 | [diff] [blame] | 629 | size_bf = mc->vram_start & ~mc->gtt_base_align; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 630 | if (size_bf > size_af) { |
| 631 | if (mc->gtt_size > size_bf) { |
| 632 | dev_warn(rdev->dev, "limiting GTT\n"); |
| 633 | mc->gtt_size = size_bf; |
| 634 | } |
Alex Deucher | 8d369bb | 2010-07-15 10:51:10 -0400 | [diff] [blame] | 635 | mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 636 | } else { |
| 637 | if (mc->gtt_size > size_af) { |
| 638 | dev_warn(rdev->dev, "limiting GTT\n"); |
| 639 | mc->gtt_size = size_af; |
| 640 | } |
Alex Deucher | 8d369bb | 2010-07-15 10:51:10 -0400 | [diff] [blame] | 641 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 642 | } |
| 643 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; |
Alex Deucher | dd7cc55 | 2010-12-03 14:37:21 -0500 | [diff] [blame] | 644 | dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 645 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); |
| 646 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 647 | |
| 648 | /* |
| 649 | * GPU helpers function. |
| 650 | */ |
Alex Deucher | 05082b8 | 2016-06-13 15:37:34 -0400 | [diff] [blame] | 651 | |
| 652 | /** |
| 653 | * radeon_device_is_virtual - check if we are running is a virtual environment |
| 654 | * |
| 655 | * Check if the asic has been passed through to a VM (all asics). |
| 656 | * Used at driver startup. |
| 657 | * Returns true if virtual or false if not. |
| 658 | */ |
Alex Deucher | a801abe | 2016-08-22 14:29:44 -0400 | [diff] [blame] | 659 | bool radeon_device_is_virtual(void) |
Alex Deucher | 05082b8 | 2016-06-13 15:37:34 -0400 | [diff] [blame] | 660 | { |
| 661 | #ifdef CONFIG_X86 |
| 662 | return boot_cpu_has(X86_FEATURE_HYPERVISOR); |
| 663 | #else |
| 664 | return false; |
| 665 | #endif |
| 666 | } |
| 667 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 668 | /** |
| 669 | * radeon_card_posted - check if the hw has already been initialized |
| 670 | * |
| 671 | * @rdev: radeon_device pointer |
| 672 | * |
| 673 | * Check if the asic has been initialized (all asics). |
| 674 | * Used at driver startup. |
| 675 | * Returns true if initialized or false if not. |
| 676 | */ |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 677 | bool radeon_card_posted(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 678 | { |
| 679 | uint32_t reg; |
| 680 | |
Alex Deucher | 884031f | 2016-09-19 12:35:22 -0400 | [diff] [blame] | 681 | /* for pass through, always force asic_init for CI */ |
| 682 | if (rdev->family >= CHIP_BONAIRE && |
| 683 | radeon_device_is_virtual()) |
Alex Deucher | 05082b8 | 2016-06-13 15:37:34 -0400 | [diff] [blame] | 684 | return false; |
| 685 | |
Alex Deucher | 50a583f | 2013-05-22 13:29:33 -0400 | [diff] [blame] | 686 | /* required for EFI mode on macbook2,1 which uses an r5xx asic */ |
Matt Fleming | 83e6818 | 2012-11-14 09:42:35 +0000 | [diff] [blame] | 687 | if (efi_enabled(EFI_BOOT) && |
Alex Deucher | 50a583f | 2013-05-22 13:29:33 -0400 | [diff] [blame] | 688 | (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && |
| 689 | (rdev->family < CHIP_R600)) |
Matthew Garrett | bcc65fd | 2011-08-08 16:21:16 +0000 | [diff] [blame] | 690 | return false; |
| 691 | |
Alex Deucher | 2cf3a4f | 2013-05-22 11:30:34 -0400 | [diff] [blame] | 692 | if (ASIC_IS_NODCE(rdev)) |
| 693 | goto check_memsize; |
| 694 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 695 | /* first check CRTCs */ |
Alex Deucher | 09fb8bd | 2013-05-22 11:22:51 -0400 | [diff] [blame] | 696 | if (ASIC_IS_DCE4(rdev)) { |
Alex Deucher | 1800740 | 2010-11-22 17:56:28 -0500 | [diff] [blame] | 697 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
| 698 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); |
Alex Deucher | 09fb8bd | 2013-05-22 11:22:51 -0400 | [diff] [blame] | 699 | if (rdev->num_crtc >= 4) { |
| 700 | reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | |
| 701 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); |
| 702 | } |
| 703 | if (rdev->num_crtc >= 6) { |
| 704 | reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | |
| 705 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); |
| 706 | } |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 707 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
| 708 | return true; |
| 709 | } else if (ASIC_IS_AVIVO(rdev)) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 710 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
| 711 | RREG32(AVIVO_D2CRTC_CONTROL); |
| 712 | if (reg & AVIVO_CRTC_EN) { |
| 713 | return true; |
| 714 | } |
| 715 | } else { |
| 716 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | |
| 717 | RREG32(RADEON_CRTC2_GEN_CNTL); |
| 718 | if (reg & RADEON_CRTC_EN) { |
| 719 | return true; |
| 720 | } |
| 721 | } |
| 722 | |
Alex Deucher | 2cf3a4f | 2013-05-22 11:30:34 -0400 | [diff] [blame] | 723 | check_memsize: |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 724 | /* then check MEM_SIZE, in case the crtcs are off */ |
| 725 | if (rdev->family >= CHIP_R600) |
| 726 | reg = RREG32(R600_CONFIG_MEMSIZE); |
| 727 | else |
| 728 | reg = RREG32(RADEON_CONFIG_MEMSIZE); |
| 729 | |
| 730 | if (reg) |
| 731 | return true; |
| 732 | |
| 733 | return false; |
| 734 | |
| 735 | } |
| 736 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 737 | /** |
| 738 | * radeon_update_bandwidth_info - update display bandwidth params |
| 739 | * |
| 740 | * @rdev: radeon_device pointer |
| 741 | * |
| 742 | * Used when sclk/mclk are switched or display modes are set. |
| 743 | * params are used to calculate display watermarks (all asics) |
| 744 | */ |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 745 | void radeon_update_bandwidth_info(struct radeon_device *rdev) |
| 746 | { |
| 747 | fixed20_12 a; |
Alex Deucher | 8807286 | 2010-08-10 12:33:20 -0400 | [diff] [blame] | 748 | u32 sclk = rdev->pm.current_sclk; |
| 749 | u32 mclk = rdev->pm.current_mclk; |
| 750 | |
| 751 | /* sclk/mclk in Mhz */ |
| 752 | a.full = dfixed_const(100); |
| 753 | rdev->pm.sclk.full = dfixed_const(sclk); |
| 754 | rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); |
| 755 | rdev->pm.mclk.full = dfixed_const(mclk); |
| 756 | rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 757 | |
| 758 | if (rdev->flags & RADEON_IS_IGP) { |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 759 | a.full = dfixed_const(16); |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 760 | /* core_bandwidth = sclk(Mhz) * 16 */ |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 761 | rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 762 | } |
| 763 | } |
| 764 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 765 | /** |
| 766 | * radeon_boot_test_post_card - check and possibly initialize the hw |
| 767 | * |
| 768 | * @rdev: radeon_device pointer |
| 769 | * |
| 770 | * Check if the asic is initialized and if not, attempt to initialize |
| 771 | * it (all asics). |
| 772 | * Returns true if initialized or false if not. |
| 773 | */ |
Dave Airlie | 72542d7 | 2009-12-01 14:06:31 +1000 | [diff] [blame] | 774 | bool radeon_boot_test_post_card(struct radeon_device *rdev) |
| 775 | { |
| 776 | if (radeon_card_posted(rdev)) |
| 777 | return true; |
| 778 | |
| 779 | if (rdev->bios) { |
| 780 | DRM_INFO("GPU not posted. posting now...\n"); |
| 781 | if (rdev->is_atom_bios) |
| 782 | atom_asic_init(rdev->mode_info.atom_context); |
| 783 | else |
| 784 | radeon_combios_asic_init(rdev->ddev); |
| 785 | return true; |
| 786 | } else { |
| 787 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
| 788 | return false; |
| 789 | } |
| 790 | } |
| 791 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 792 | /** |
| 793 | * radeon_dummy_page_init - init dummy page used by the driver |
| 794 | * |
| 795 | * @rdev: radeon_device pointer |
| 796 | * |
| 797 | * Allocate the dummy page used by the driver (all asics). |
| 798 | * This dummy page is used by the driver as a filler for gart entries |
| 799 | * when pages are taken out of the GART |
| 800 | * Returns 0 on sucess, -ENOMEM on failure. |
| 801 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 802 | int radeon_dummy_page_init(struct radeon_device *rdev) |
| 803 | { |
Dave Airlie | 8256856 | 2010-02-05 16:00:07 +1000 | [diff] [blame] | 804 | if (rdev->dummy_page.page) |
| 805 | return 0; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 806 | rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); |
| 807 | if (rdev->dummy_page.page == NULL) |
| 808 | return -ENOMEM; |
| 809 | rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, |
| 810 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
Benjamin Herrenschmidt | a30f6fb7 | 2010-08-10 14:48:58 +1000 | [diff] [blame] | 811 | if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) { |
| 812 | dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n"); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 813 | __free_page(rdev->dummy_page.page); |
| 814 | rdev->dummy_page.page = NULL; |
| 815 | return -ENOMEM; |
| 816 | } |
Michel Dänzer | cb65890 | 2015-01-21 17:36:35 +0900 | [diff] [blame] | 817 | rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr, |
| 818 | RADEON_GART_PAGE_DUMMY); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 819 | return 0; |
| 820 | } |
| 821 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 822 | /** |
| 823 | * radeon_dummy_page_fini - free dummy page used by the driver |
| 824 | * |
| 825 | * @rdev: radeon_device pointer |
| 826 | * |
| 827 | * Frees the dummy page used by the driver (all asics). |
| 828 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 829 | void radeon_dummy_page_fini(struct radeon_device *rdev) |
| 830 | { |
| 831 | if (rdev->dummy_page.page == NULL) |
| 832 | return; |
| 833 | pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, |
| 834 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
| 835 | __free_page(rdev->dummy_page.page); |
| 836 | rdev->dummy_page.page = NULL; |
| 837 | } |
| 838 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 839 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 840 | /* ATOM accessor methods */ |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 841 | /* |
| 842 | * ATOM is an interpreted byte code stored in tables in the vbios. The |
| 843 | * driver registers callbacks to access registers and the interpreter |
| 844 | * in the driver parses the tables and executes then to program specific |
| 845 | * actions (set display modes, asic init, etc.). See radeon_atombios.c, |
| 846 | * atombios.h, and atom.c |
| 847 | */ |
| 848 | |
| 849 | /** |
| 850 | * cail_pll_read - read PLL register |
| 851 | * |
| 852 | * @info: atom card_info pointer |
| 853 | * @reg: PLL register offset |
| 854 | * |
| 855 | * Provides a PLL register accessor for the atom interpreter (r4xx+). |
| 856 | * Returns the value of the PLL register. |
| 857 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 858 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) |
| 859 | { |
| 860 | struct radeon_device *rdev = info->dev->dev_private; |
| 861 | uint32_t r; |
| 862 | |
| 863 | r = rdev->pll_rreg(rdev, reg); |
| 864 | return r; |
| 865 | } |
| 866 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 867 | /** |
| 868 | * cail_pll_write - write PLL register |
| 869 | * |
| 870 | * @info: atom card_info pointer |
| 871 | * @reg: PLL register offset |
| 872 | * @val: value to write to the pll register |
| 873 | * |
| 874 | * Provides a PLL register accessor for the atom interpreter (r4xx+). |
| 875 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 876 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) |
| 877 | { |
| 878 | struct radeon_device *rdev = info->dev->dev_private; |
| 879 | |
| 880 | rdev->pll_wreg(rdev, reg, val); |
| 881 | } |
| 882 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 883 | /** |
| 884 | * cail_mc_read - read MC (Memory Controller) register |
| 885 | * |
| 886 | * @info: atom card_info pointer |
| 887 | * @reg: MC register offset |
| 888 | * |
| 889 | * Provides an MC register accessor for the atom interpreter (r4xx+). |
| 890 | * Returns the value of the MC register. |
| 891 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 892 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) |
| 893 | { |
| 894 | struct radeon_device *rdev = info->dev->dev_private; |
| 895 | uint32_t r; |
| 896 | |
| 897 | r = rdev->mc_rreg(rdev, reg); |
| 898 | return r; |
| 899 | } |
| 900 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 901 | /** |
| 902 | * cail_mc_write - write MC (Memory Controller) register |
| 903 | * |
| 904 | * @info: atom card_info pointer |
| 905 | * @reg: MC register offset |
| 906 | * @val: value to write to the pll register |
| 907 | * |
| 908 | * Provides a MC register accessor for the atom interpreter (r4xx+). |
| 909 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 910 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) |
| 911 | { |
| 912 | struct radeon_device *rdev = info->dev->dev_private; |
| 913 | |
| 914 | rdev->mc_wreg(rdev, reg, val); |
| 915 | } |
| 916 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 917 | /** |
| 918 | * cail_reg_write - write MMIO register |
| 919 | * |
| 920 | * @info: atom card_info pointer |
| 921 | * @reg: MMIO register offset |
| 922 | * @val: value to write to the pll register |
| 923 | * |
| 924 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). |
| 925 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 926 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) |
| 927 | { |
| 928 | struct radeon_device *rdev = info->dev->dev_private; |
| 929 | |
| 930 | WREG32(reg*4, val); |
| 931 | } |
| 932 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 933 | /** |
| 934 | * cail_reg_read - read MMIO register |
| 935 | * |
| 936 | * @info: atom card_info pointer |
| 937 | * @reg: MMIO register offset |
| 938 | * |
| 939 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). |
| 940 | * Returns the value of the MMIO register. |
| 941 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 942 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) |
| 943 | { |
| 944 | struct radeon_device *rdev = info->dev->dev_private; |
| 945 | uint32_t r; |
| 946 | |
| 947 | r = RREG32(reg*4); |
| 948 | return r; |
| 949 | } |
| 950 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 951 | /** |
| 952 | * cail_ioreg_write - write IO register |
| 953 | * |
| 954 | * @info: atom card_info pointer |
| 955 | * @reg: IO register offset |
| 956 | * @val: value to write to the pll register |
| 957 | * |
| 958 | * Provides a IO register accessor for the atom interpreter (r4xx+). |
| 959 | */ |
Alex Deucher | 351a52a | 2010-06-30 11:52:50 -0400 | [diff] [blame] | 960 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) |
| 961 | { |
| 962 | struct radeon_device *rdev = info->dev->dev_private; |
| 963 | |
| 964 | WREG32_IO(reg*4, val); |
| 965 | } |
| 966 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 967 | /** |
| 968 | * cail_ioreg_read - read IO register |
| 969 | * |
| 970 | * @info: atom card_info pointer |
| 971 | * @reg: IO register offset |
| 972 | * |
| 973 | * Provides an IO register accessor for the atom interpreter (r4xx+). |
| 974 | * Returns the value of the IO register. |
| 975 | */ |
Alex Deucher | 351a52a | 2010-06-30 11:52:50 -0400 | [diff] [blame] | 976 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) |
| 977 | { |
| 978 | struct radeon_device *rdev = info->dev->dev_private; |
| 979 | uint32_t r; |
| 980 | |
| 981 | r = RREG32_IO(reg*4); |
| 982 | return r; |
| 983 | } |
| 984 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 985 | /** |
| 986 | * radeon_atombios_init - init the driver info and callbacks for atombios |
| 987 | * |
| 988 | * @rdev: radeon_device pointer |
| 989 | * |
| 990 | * Initializes the driver info and register access callbacks for the |
| 991 | * ATOM interpreter (r4xx+). |
| 992 | * Returns 0 on sucess, -ENOMEM on failure. |
| 993 | * Called at driver startup. |
| 994 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 995 | int radeon_atombios_init(struct radeon_device *rdev) |
| 996 | { |
Mathias Fröhlich | 61c4b24 | 2009-10-27 15:08:01 -0400 | [diff] [blame] | 997 | struct card_info *atom_card_info = |
| 998 | kzalloc(sizeof(struct card_info), GFP_KERNEL); |
| 999 | |
| 1000 | if (!atom_card_info) |
| 1001 | return -ENOMEM; |
| 1002 | |
| 1003 | rdev->mode_info.atom_card_info = atom_card_info; |
| 1004 | atom_card_info->dev = rdev->ddev; |
| 1005 | atom_card_info->reg_read = cail_reg_read; |
| 1006 | atom_card_info->reg_write = cail_reg_write; |
Alex Deucher | 351a52a | 2010-06-30 11:52:50 -0400 | [diff] [blame] | 1007 | /* needed for iio ops */ |
| 1008 | if (rdev->rio_mem) { |
| 1009 | atom_card_info->ioreg_read = cail_ioreg_read; |
| 1010 | atom_card_info->ioreg_write = cail_ioreg_write; |
| 1011 | } else { |
| 1012 | DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); |
| 1013 | atom_card_info->ioreg_read = cail_reg_read; |
| 1014 | atom_card_info->ioreg_write = cail_reg_write; |
| 1015 | } |
Mathias Fröhlich | 61c4b24 | 2009-10-27 15:08:01 -0400 | [diff] [blame] | 1016 | atom_card_info->mc_read = cail_mc_read; |
| 1017 | atom_card_info->mc_write = cail_mc_write; |
| 1018 | atom_card_info->pll_read = cail_pll_read; |
| 1019 | atom_card_info->pll_write = cail_pll_write; |
| 1020 | |
| 1021 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); |
Tim Gardner | 0e34d09 | 2013-02-11 14:34:32 -0700 | [diff] [blame] | 1022 | if (!rdev->mode_info.atom_context) { |
| 1023 | radeon_atombios_fini(rdev); |
| 1024 | return -ENOMEM; |
| 1025 | } |
| 1026 | |
Rafał Miłecki | c31ad97 | 2009-12-17 00:00:46 +0100 | [diff] [blame] | 1027 | mutex_init(&rdev->mode_info.atom_context->mutex); |
Dave Airlie | 1c94984 | 2014-11-11 09:16:15 +1000 | [diff] [blame] | 1028 | mutex_init(&rdev->mode_info.atom_context->scratch_mutex); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1029 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
Dave Airlie | d904ef9 | 2009-11-17 06:29:46 +1000 | [diff] [blame] | 1030 | atom_allocate_fb_scratch(rdev->mode_info.atom_context); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1031 | return 0; |
| 1032 | } |
| 1033 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 1034 | /** |
| 1035 | * radeon_atombios_fini - free the driver info and callbacks for atombios |
| 1036 | * |
| 1037 | * @rdev: radeon_device pointer |
| 1038 | * |
| 1039 | * Frees the driver info and register access callbacks for the ATOM |
| 1040 | * interpreter (r4xx+). |
| 1041 | * Called at driver shutdown. |
| 1042 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1043 | void radeon_atombios_fini(struct radeon_device *rdev) |
| 1044 | { |
Jerome Glisse | 4a04a84 | 2009-12-09 17:39:16 +0100 | [diff] [blame] | 1045 | if (rdev->mode_info.atom_context) { |
| 1046 | kfree(rdev->mode_info.atom_context->scratch); |
Jerome Glisse | 4a04a84 | 2009-12-09 17:39:16 +0100 | [diff] [blame] | 1047 | } |
Tim Gardner | 0e34d09 | 2013-02-11 14:34:32 -0700 | [diff] [blame] | 1048 | kfree(rdev->mode_info.atom_context); |
| 1049 | rdev->mode_info.atom_context = NULL; |
Mathias Fröhlich | 61c4b24 | 2009-10-27 15:08:01 -0400 | [diff] [blame] | 1050 | kfree(rdev->mode_info.atom_card_info); |
Tim Gardner | 0e34d09 | 2013-02-11 14:34:32 -0700 | [diff] [blame] | 1051 | rdev->mode_info.atom_card_info = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1052 | } |
| 1053 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 1054 | /* COMBIOS */ |
| 1055 | /* |
| 1056 | * COMBIOS is the bios format prior to ATOM. It provides |
| 1057 | * command tables similar to ATOM, but doesn't have a unified |
| 1058 | * parser. See radeon_combios.c |
| 1059 | */ |
| 1060 | |
| 1061 | /** |
| 1062 | * radeon_combios_init - init the driver info for combios |
| 1063 | * |
| 1064 | * @rdev: radeon_device pointer |
| 1065 | * |
| 1066 | * Initializes the driver info for combios (r1xx-r3xx). |
| 1067 | * Returns 0 on sucess. |
| 1068 | * Called at driver startup. |
| 1069 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1070 | int radeon_combios_init(struct radeon_device *rdev) |
| 1071 | { |
| 1072 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); |
| 1073 | return 0; |
| 1074 | } |
| 1075 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 1076 | /** |
| 1077 | * radeon_combios_fini - free the driver info for combios |
| 1078 | * |
| 1079 | * @rdev: radeon_device pointer |
| 1080 | * |
| 1081 | * Frees the driver info for combios (r1xx-r3xx). |
| 1082 | * Called at driver shutdown. |
| 1083 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1084 | void radeon_combios_fini(struct radeon_device *rdev) |
| 1085 | { |
| 1086 | } |
| 1087 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 1088 | /* if we get transitioned to only one device, take VGA back */ |
| 1089 | /** |
| 1090 | * radeon_vga_set_decode - enable/disable vga decode |
| 1091 | * |
| 1092 | * @cookie: radeon_device pointer |
| 1093 | * @state: enable/disable vga decode |
| 1094 | * |
| 1095 | * Enable/disable vga decode (all asics). |
| 1096 | * Returns VGA resource flags. |
| 1097 | */ |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1098 | static unsigned int radeon_vga_set_decode(void *cookie, bool state) |
| 1099 | { |
| 1100 | struct radeon_device *rdev = cookie; |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1101 | radeon_vga_set_state(rdev, state); |
| 1102 | if (state) |
| 1103 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | |
| 1104 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
| 1105 | else |
| 1106 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
| 1107 | } |
Dave Airlie | c1176d6 | 2009-10-08 14:03:05 +1000 | [diff] [blame] | 1108 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 1109 | /** |
Christian König | 1bcb04f | 2012-10-23 15:53:16 +0200 | [diff] [blame] | 1110 | * radeon_check_pot_argument - check that argument is a power of two |
| 1111 | * |
| 1112 | * @arg: value to check |
| 1113 | * |
| 1114 | * Validates that a certain argument is a power of two (all asics). |
| 1115 | * Returns true if argument is valid. |
| 1116 | */ |
| 1117 | static bool radeon_check_pot_argument(int arg) |
| 1118 | { |
| 1119 | return (arg & (arg - 1)) == 0; |
| 1120 | } |
| 1121 | |
| 1122 | /** |
Grigori Goronzy | 5e3c4f9 | 2015-07-03 01:54:12 +0200 | [diff] [blame] | 1123 | * Determine a sensible default GART size according to ASIC family. |
| 1124 | * |
| 1125 | * @family ASIC family name |
| 1126 | */ |
| 1127 | static int radeon_gart_size_auto(enum radeon_family family) |
| 1128 | { |
| 1129 | /* default to a larger gart size on newer asics */ |
| 1130 | if (family >= CHIP_TAHITI) |
| 1131 | return 2048; |
| 1132 | else if (family >= CHIP_RV770) |
| 1133 | return 1024; |
| 1134 | else |
| 1135 | return 512; |
| 1136 | } |
| 1137 | |
| 1138 | /** |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 1139 | * radeon_check_arguments - validate module params |
| 1140 | * |
| 1141 | * @rdev: radeon_device pointer |
| 1142 | * |
| 1143 | * Validates certain module parameters and updates |
| 1144 | * the associated values used by the driver (all asics). |
| 1145 | */ |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 1146 | static void radeon_check_arguments(struct radeon_device *rdev) |
Jerome Glisse | 3642133 | 2009-12-11 21:18:34 +0100 | [diff] [blame] | 1147 | { |
| 1148 | /* vramlimit must be a power of two */ |
Christian König | 1bcb04f | 2012-10-23 15:53:16 +0200 | [diff] [blame] | 1149 | if (!radeon_check_pot_argument(radeon_vram_limit)) { |
Jerome Glisse | 3642133 | 2009-12-11 21:18:34 +0100 | [diff] [blame] | 1150 | dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", |
| 1151 | radeon_vram_limit); |
| 1152 | radeon_vram_limit = 0; |
Jerome Glisse | 3642133 | 2009-12-11 21:18:34 +0100 | [diff] [blame] | 1153 | } |
Christian König | 1bcb04f | 2012-10-23 15:53:16 +0200 | [diff] [blame] | 1154 | |
Alex Deucher | edcd26e | 2013-07-05 17:16:51 -0400 | [diff] [blame] | 1155 | if (radeon_gart_size == -1) { |
Grigori Goronzy | 5e3c4f9 | 2015-07-03 01:54:12 +0200 | [diff] [blame] | 1156 | radeon_gart_size = radeon_gart_size_auto(rdev->family); |
Alex Deucher | edcd26e | 2013-07-05 17:16:51 -0400 | [diff] [blame] | 1157 | } |
Jerome Glisse | 3642133 | 2009-12-11 21:18:34 +0100 | [diff] [blame] | 1158 | /* gtt size must be power of two and greater or equal to 32M */ |
Christian König | 1bcb04f | 2012-10-23 15:53:16 +0200 | [diff] [blame] | 1159 | if (radeon_gart_size < 32) { |
Alex Deucher | edcd26e | 2013-07-05 17:16:51 -0400 | [diff] [blame] | 1160 | dev_warn(rdev->dev, "gart size (%d) too small\n", |
Jerome Glisse | 3642133 | 2009-12-11 21:18:34 +0100 | [diff] [blame] | 1161 | radeon_gart_size); |
Grigori Goronzy | 5e3c4f9 | 2015-07-03 01:54:12 +0200 | [diff] [blame] | 1162 | radeon_gart_size = radeon_gart_size_auto(rdev->family); |
Christian König | 1bcb04f | 2012-10-23 15:53:16 +0200 | [diff] [blame] | 1163 | } else if (!radeon_check_pot_argument(radeon_gart_size)) { |
Jerome Glisse | 3642133 | 2009-12-11 21:18:34 +0100 | [diff] [blame] | 1164 | dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", |
| 1165 | radeon_gart_size); |
Grigori Goronzy | 5e3c4f9 | 2015-07-03 01:54:12 +0200 | [diff] [blame] | 1166 | radeon_gart_size = radeon_gart_size_auto(rdev->family); |
Jerome Glisse | 3642133 | 2009-12-11 21:18:34 +0100 | [diff] [blame] | 1167 | } |
Christian König | 1bcb04f | 2012-10-23 15:53:16 +0200 | [diff] [blame] | 1168 | rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; |
| 1169 | |
Jerome Glisse | 3642133 | 2009-12-11 21:18:34 +0100 | [diff] [blame] | 1170 | /* AGP mode can only be -1, 1, 2, 4, 8 */ |
| 1171 | switch (radeon_agpmode) { |
| 1172 | case -1: |
| 1173 | case 0: |
| 1174 | case 1: |
| 1175 | case 2: |
| 1176 | case 4: |
| 1177 | case 8: |
| 1178 | break; |
| 1179 | default: |
| 1180 | dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " |
| 1181 | "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); |
| 1182 | radeon_agpmode = 0; |
| 1183 | break; |
| 1184 | } |
Christian König | c1c4413 | 2014-06-05 23:47:32 -0400 | [diff] [blame] | 1185 | |
| 1186 | if (!radeon_check_pot_argument(radeon_vm_size)) { |
| 1187 | dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n", |
| 1188 | radeon_vm_size); |
Christian König | 20b2656 | 2014-07-18 13:56:56 +0200 | [diff] [blame] | 1189 | radeon_vm_size = 4; |
Christian König | c1c4413 | 2014-06-05 23:47:32 -0400 | [diff] [blame] | 1190 | } |
| 1191 | |
Christian König | 20b2656 | 2014-07-18 13:56:56 +0200 | [diff] [blame] | 1192 | if (radeon_vm_size < 1) { |
Alexandre Demers | 13c240e | 2016-01-07 19:22:44 -0500 | [diff] [blame] | 1193 | dev_warn(rdev->dev, "VM size (%d) too small, min is 1GB\n", |
Christian König | c1c4413 | 2014-06-05 23:47:32 -0400 | [diff] [blame] | 1194 | radeon_vm_size); |
Christian König | 20b2656 | 2014-07-18 13:56:56 +0200 | [diff] [blame] | 1195 | radeon_vm_size = 4; |
Christian König | c1c4413 | 2014-06-05 23:47:32 -0400 | [diff] [blame] | 1196 | } |
| 1197 | |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 1198 | /* |
| 1199 | * Max GPUVM size for Cayman, SI and CI are 40 bits. |
| 1200 | */ |
Christian König | 20b2656 | 2014-07-18 13:56:56 +0200 | [diff] [blame] | 1201 | if (radeon_vm_size > 1024) { |
| 1202 | dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n", |
Christian König | c1c4413 | 2014-06-05 23:47:32 -0400 | [diff] [blame] | 1203 | radeon_vm_size); |
Christian König | 20b2656 | 2014-07-18 13:56:56 +0200 | [diff] [blame] | 1204 | radeon_vm_size = 4; |
Christian König | c1c4413 | 2014-06-05 23:47:32 -0400 | [diff] [blame] | 1205 | } |
Christian König | 4510fb9 | 2014-06-05 23:56:50 -0400 | [diff] [blame] | 1206 | |
| 1207 | /* defines number of bits in page table versus page directory, |
| 1208 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the |
| 1209 | * page table and the remaining bits are in the page directory */ |
Christian König | dfc230f | 2014-07-19 13:55:58 +0200 | [diff] [blame] | 1210 | if (radeon_vm_block_size == -1) { |
| 1211 | |
| 1212 | /* Total bits covered by PD + PTs */ |
Alex Deucher | 8e66e13 | 2014-10-15 17:20:55 -0400 | [diff] [blame] | 1213 | unsigned bits = ilog2(radeon_vm_size) + 18; |
Christian König | dfc230f | 2014-07-19 13:55:58 +0200 | [diff] [blame] | 1214 | |
| 1215 | /* Make sure the PD is 4K in size up to 8GB address space. |
| 1216 | Above that split equal between PD and PTs */ |
| 1217 | if (radeon_vm_size <= 8) |
| 1218 | radeon_vm_block_size = bits - 9; |
| 1219 | else |
| 1220 | radeon_vm_block_size = (bits + 3) / 2; |
| 1221 | |
| 1222 | } else if (radeon_vm_block_size < 9) { |
Christian König | 20b2656 | 2014-07-18 13:56:56 +0200 | [diff] [blame] | 1223 | dev_warn(rdev->dev, "VM page table size (%d) too small\n", |
Christian König | 4510fb9 | 2014-06-05 23:56:50 -0400 | [diff] [blame] | 1224 | radeon_vm_block_size); |
| 1225 | radeon_vm_block_size = 9; |
| 1226 | } |
| 1227 | |
| 1228 | if (radeon_vm_block_size > 24 || |
Christian König | 20b2656 | 2014-07-18 13:56:56 +0200 | [diff] [blame] | 1229 | (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) { |
| 1230 | dev_warn(rdev->dev, "VM page table size (%d) too large\n", |
Christian König | 4510fb9 | 2014-06-05 23:56:50 -0400 | [diff] [blame] | 1231 | radeon_vm_block_size); |
| 1232 | radeon_vm_block_size = 9; |
| 1233 | } |
Jerome Glisse | 3642133 | 2009-12-11 21:18:34 +0100 | [diff] [blame] | 1234 | } |
| 1235 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 1236 | /** |
| 1237 | * radeon_switcheroo_set_state - set switcheroo state |
| 1238 | * |
| 1239 | * @pdev: pci dev pointer |
Lukas Wunner | 8e5de1d | 2015-09-05 11:14:43 +0200 | [diff] [blame] | 1240 | * @state: vga_switcheroo state |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 1241 | * |
| 1242 | * Callback for the switcheroo driver. Suspends or resumes the |
| 1243 | * the asics before or after it is powered up using ACPI methods. |
| 1244 | */ |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1245 | static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
| 1246 | { |
| 1247 | struct drm_device *dev = pci_get_drvdata(pdev); |
Alex Deucher | 4807c5a | 2014-07-18 11:54:20 -0400 | [diff] [blame] | 1248 | struct radeon_device *rdev = dev->dev_private; |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 1249 | |
Alex Deucher | 90c4cde | 2014-04-10 22:29:01 -0400 | [diff] [blame] | 1250 | if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF) |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 1251 | return; |
| 1252 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1253 | if (state == VGA_SWITCHEROO_ON) { |
Maarten Lankhorst | d1f9809 | 2013-01-07 15:18:47 +0100 | [diff] [blame] | 1254 | unsigned d3_delay = dev->pdev->d3_delay; |
| 1255 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1256 | printk(KERN_INFO "radeon: switched on\n"); |
| 1257 | /* don't suspend or resume card normally */ |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 1258 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
Maarten Lankhorst | d1f9809 | 2013-01-07 15:18:47 +0100 | [diff] [blame] | 1259 | |
Alex Deucher | 4807c5a | 2014-07-18 11:54:20 -0400 | [diff] [blame] | 1260 | if (d3_delay < 20 && (rdev->px_quirk_flags & RADEON_PX_QUIRK_LONG_WAKEUP)) |
Maarten Lankhorst | d1f9809 | 2013-01-07 15:18:47 +0100 | [diff] [blame] | 1261 | dev->pdev->d3_delay = 20; |
| 1262 | |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 1263 | radeon_resume_kms(dev, true, true); |
Maarten Lankhorst | d1f9809 | 2013-01-07 15:18:47 +0100 | [diff] [blame] | 1264 | |
| 1265 | dev->pdev->d3_delay = d3_delay; |
| 1266 | |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 1267 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
Dave Airlie | fbf8176 | 2010-06-01 09:09:06 +1000 | [diff] [blame] | 1268 | drm_kms_helper_poll_enable(dev); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1269 | } else { |
| 1270 | printk(KERN_INFO "radeon: switched off\n"); |
Dave Airlie | fbf8176 | 2010-06-01 09:09:06 +1000 | [diff] [blame] | 1271 | drm_kms_helper_poll_disable(dev); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 1272 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
Jérome Glisse | 274ad65 | 2016-03-18 16:58:39 +0100 | [diff] [blame] | 1273 | radeon_suspend_kms(dev, true, true, false); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 1274 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1275 | } |
| 1276 | } |
| 1277 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 1278 | /** |
| 1279 | * radeon_switcheroo_can_switch - see if switcheroo state can change |
| 1280 | * |
| 1281 | * @pdev: pci dev pointer |
| 1282 | * |
| 1283 | * Callback for the switcheroo driver. Check of the switcheroo |
| 1284 | * state can be changed. |
| 1285 | * Returns true if the state can be changed, false if not. |
| 1286 | */ |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1287 | static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) |
| 1288 | { |
| 1289 | struct drm_device *dev = pci_get_drvdata(pdev); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1290 | |
Daniel Vetter | fc8fd40 | 2013-11-03 20:46:34 +0100 | [diff] [blame] | 1291 | /* |
| 1292 | * FIXME: open_count is protected by drm_global_mutex but that would lead to |
| 1293 | * locking inversion with the driver load path. And the access here is |
| 1294 | * completely racy anyway. So don't bother with locking for now. |
| 1295 | */ |
| 1296 | return dev->open_count == 0; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1297 | } |
| 1298 | |
Takashi Iwai | 26ec685 | 2012-05-11 07:51:17 +0200 | [diff] [blame] | 1299 | static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = { |
| 1300 | .set_gpu_state = radeon_switcheroo_set_state, |
| 1301 | .reprobe = NULL, |
| 1302 | .can_switch = radeon_switcheroo_can_switch, |
| 1303 | }; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1304 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 1305 | /** |
| 1306 | * radeon_device_init - initialize the driver |
| 1307 | * |
| 1308 | * @rdev: radeon_device pointer |
| 1309 | * @pdev: drm dev pointer |
| 1310 | * @pdev: pci dev pointer |
| 1311 | * @flags: driver flags |
| 1312 | * |
| 1313 | * Initializes the driver info and hw (all asics). |
| 1314 | * Returns 0 for success or an error on failure. |
| 1315 | * Called at driver startup. |
| 1316 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1317 | int radeon_device_init(struct radeon_device *rdev, |
| 1318 | struct drm_device *ddev, |
| 1319 | struct pci_dev *pdev, |
| 1320 | uint32_t flags) |
| 1321 | { |
Alex Deucher | 351a52a | 2010-06-30 11:52:50 -0400 | [diff] [blame] | 1322 | int r, i; |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 1323 | int dma_bits; |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 1324 | bool runtime = false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1325 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1326 | rdev->shutdown = false; |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1327 | rdev->dev = &pdev->dev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1328 | rdev->ddev = ddev; |
| 1329 | rdev->pdev = pdev; |
| 1330 | rdev->flags = flags; |
| 1331 | rdev->family = flags & RADEON_FAMILY_MASK; |
| 1332 | rdev->is_atom_bios = false; |
| 1333 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; |
Alex Deucher | edcd26e | 2013-07-05 17:16:51 -0400 | [diff] [blame] | 1334 | rdev->mc.gtt_size = 512 * 1024 * 1024; |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 1335 | rdev->accel_working = false; |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 1336 | /* set up ring ids */ |
| 1337 | for (i = 0; i < RADEON_NUM_RINGS; i++) { |
| 1338 | rdev->ring[i].idx = i; |
| 1339 | } |
Maarten Lankhorst | 954605c | 2014-01-09 11:03:12 +0100 | [diff] [blame] | 1340 | rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS); |
Jerome Glisse | 1b5331d | 2010-04-12 20:21:53 +0000 | [diff] [blame] | 1341 | |
Alex Deucher | fe0d36e | 2016-04-14 13:16:35 -0400 | [diff] [blame] | 1342 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
| 1343 | radeon_family_name[rdev->family], pdev->vendor, pdev->device, |
| 1344 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); |
Jerome Glisse | 1b5331d | 2010-04-12 20:21:53 +0000 | [diff] [blame] | 1345 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1346 | /* mutex initialization are all done here so we |
| 1347 | * can recall function without having locking issues */ |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 1348 | mutex_init(&rdev->ring_lock); |
Alex Deucher | 40bacf1 | 2009-12-23 03:23:21 -0500 | [diff] [blame] | 1349 | mutex_init(&rdev->dc_hw_i2c_mutex); |
Christian Koenig | c20dc36 | 2012-05-16 21:45:24 +0200 | [diff] [blame] | 1350 | atomic_set(&rdev->ih.lock, 0); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1351 | mutex_init(&rdev->gem.mutex); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1352 | mutex_init(&rdev->pm.mutex); |
Marek Olšák | 6759a0a | 2012-08-09 16:34:17 +0200 | [diff] [blame] | 1353 | mutex_init(&rdev->gpu_clock_mutex); |
Alex Deucher | f61d5b46 | 2013-08-06 12:40:16 -0400 | [diff] [blame] | 1354 | mutex_init(&rdev->srbm_mutex); |
Oded Gabbay | 1c0a462 | 2014-07-14 15:36:08 +0300 | [diff] [blame] | 1355 | mutex_init(&rdev->grbm_idx_mutex); |
Christian König | db7fce3 | 2012-05-11 14:57:18 +0200 | [diff] [blame] | 1356 | init_rwsem(&rdev->pm.mclk_lock); |
Jerome Glisse | dee53e7 | 2012-07-02 12:45:19 -0400 | [diff] [blame] | 1357 | init_rwsem(&rdev->exclusive_lock); |
Rafał Miłecki | 73a6d3f | 2010-01-08 00:22:47 +0100 | [diff] [blame] | 1358 | init_waitqueue_head(&rdev->irq.vblank_queue); |
Christian König | 341cb9e | 2014-08-07 09:36:03 +0200 | [diff] [blame] | 1359 | mutex_init(&rdev->mn_lock); |
| 1360 | hash_init(rdev->mn_hash); |
Alex Deucher | 1b9c3dd | 2012-05-10 13:00:06 -0400 | [diff] [blame] | 1361 | r = radeon_gem_init(rdev); |
| 1362 | if (r) |
| 1363 | return r; |
Christian König | 529364e | 2014-02-20 19:33:15 +0100 | [diff] [blame] | 1364 | |
Christian König | c1c4413 | 2014-06-05 23:47:32 -0400 | [diff] [blame] | 1365 | radeon_check_arguments(rdev); |
Alex Deucher | 23d4f1f | 2012-10-08 09:45:46 -0400 | [diff] [blame] | 1366 | /* Adjust VM size here. |
Christian König | c1c4413 | 2014-06-05 23:47:32 -0400 | [diff] [blame] | 1367 | * Max GPUVM size for cayman+ is 40 bits. |
Alex Deucher | 23d4f1f | 2012-10-08 09:45:46 -0400 | [diff] [blame] | 1368 | */ |
Christian König | 20b2656 | 2014-07-18 13:56:56 +0200 | [diff] [blame] | 1369 | rdev->vm_manager.max_pfn = radeon_vm_size << 18; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1370 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 1371 | /* Set asic functions */ |
| 1372 | r = radeon_asic_init(rdev); |
Jerome Glisse | 3642133 | 2009-12-11 21:18:34 +0100 | [diff] [blame] | 1373 | if (r) |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 1374 | return r; |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 1375 | |
Alex Deucher | f95df9c | 2010-03-21 14:02:25 -0400 | [diff] [blame] | 1376 | /* all of the newer IGP chips have an internal gart |
| 1377 | * However some rs4xx report as AGP, so remove that here. |
| 1378 | */ |
| 1379 | if ((rdev->family >= CHIP_RS400) && |
| 1380 | (rdev->flags & RADEON_IS_IGP)) { |
| 1381 | rdev->flags &= ~RADEON_IS_AGP; |
| 1382 | } |
| 1383 | |
Jerome Glisse | 30256a3 | 2009-11-30 17:47:59 +0100 | [diff] [blame] | 1384 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { |
Jerome Glisse | b574f25 | 2009-10-06 19:04:29 +0200 | [diff] [blame] | 1385 | radeon_agp_disable(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1386 | } |
| 1387 | |
Alex Deucher | 9ed8b1f | 2013-04-08 11:13:01 -0400 | [diff] [blame] | 1388 | /* Set the internal MC address mask |
| 1389 | * This is the max address of the GPU's |
| 1390 | * internal address space. |
| 1391 | */ |
| 1392 | if (rdev->family >= CHIP_CAYMAN) |
| 1393 | rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ |
| 1394 | else if (rdev->family >= CHIP_CEDAR) |
| 1395 | rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ |
| 1396 | else |
| 1397 | rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ |
| 1398 | |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 1399 | /* set DMA mask + need_dma32 flags. |
| 1400 | * PCIE - can handle 40-bits. |
Alex Deucher | 005a83f | 2011-10-05 10:02:57 -0400 | [diff] [blame] | 1401 | * IGP - can handle 40-bits |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 1402 | * AGP - generally dma32 is safest |
Alex Deucher | 005a83f | 2011-10-05 10:02:57 -0400 | [diff] [blame] | 1403 | * PCI - dma32 for legacy pci gart, 40 bits on newer asics |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 1404 | */ |
| 1405 | rdev->need_dma32 = false; |
| 1406 | if (rdev->flags & RADEON_IS_AGP) |
| 1407 | rdev->need_dma32 = true; |
Alex Deucher | 005a83f | 2011-10-05 10:02:57 -0400 | [diff] [blame] | 1408 | if ((rdev->flags & RADEON_IS_PCI) && |
Jerome Glisse | 4a2b666 | 2012-08-28 16:50:22 -0400 | [diff] [blame] | 1409 | (rdev->family <= CHIP_RS740)) |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 1410 | rdev->need_dma32 = true; |
| 1411 | |
| 1412 | dma_bits = rdev->need_dma32 ? 32 : 40; |
| 1413 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1414 | if (r) { |
Daniel Haid | 62fff81 | 2011-06-08 20:04:45 +1000 | [diff] [blame] | 1415 | rdev->need_dma32 = true; |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 1416 | dma_bits = 32; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1417 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
| 1418 | } |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 1419 | r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); |
| 1420 | if (r) { |
| 1421 | pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); |
| 1422 | printk(KERN_WARNING "radeon: No coherent DMA available.\n"); |
| 1423 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1424 | |
| 1425 | /* Registers mapping */ |
| 1426 | /* TODO: block userspace mapping of io register */ |
Daniel Vetter | 2c38515 | 2012-12-02 14:06:15 +0100 | [diff] [blame] | 1427 | spin_lock_init(&rdev->mmio_idx_lock); |
Alex Deucher | fe78118 | 2013-09-03 18:19:42 -0400 | [diff] [blame] | 1428 | spin_lock_init(&rdev->smc_idx_lock); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 1429 | spin_lock_init(&rdev->pll_idx_lock); |
| 1430 | spin_lock_init(&rdev->mc_idx_lock); |
| 1431 | spin_lock_init(&rdev->pcie_idx_lock); |
| 1432 | spin_lock_init(&rdev->pciep_idx_lock); |
| 1433 | spin_lock_init(&rdev->pif_idx_lock); |
| 1434 | spin_lock_init(&rdev->cg_idx_lock); |
| 1435 | spin_lock_init(&rdev->uvd_idx_lock); |
| 1436 | spin_lock_init(&rdev->rcu_idx_lock); |
| 1437 | spin_lock_init(&rdev->didt_idx_lock); |
| 1438 | spin_lock_init(&rdev->end_idx_lock); |
Alex Deucher | efad86db | 2012-12-18 21:24:37 -0500 | [diff] [blame] | 1439 | if (rdev->family >= CHIP_BONAIRE) { |
| 1440 | rdev->rmmio_base = pci_resource_start(rdev->pdev, 5); |
| 1441 | rdev->rmmio_size = pci_resource_len(rdev->pdev, 5); |
| 1442 | } else { |
| 1443 | rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); |
| 1444 | rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); |
| 1445 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1446 | rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); |
| 1447 | if (rdev->rmmio == NULL) { |
| 1448 | return -ENOMEM; |
| 1449 | } |
| 1450 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
| 1451 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
| 1452 | |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 1453 | /* doorbell bar mapping */ |
| 1454 | if (rdev->family >= CHIP_BONAIRE) |
| 1455 | radeon_doorbell_init(rdev); |
| 1456 | |
Alex Deucher | 351a52a | 2010-06-30 11:52:50 -0400 | [diff] [blame] | 1457 | /* io port mapping */ |
| 1458 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
| 1459 | if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { |
| 1460 | rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); |
| 1461 | rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); |
| 1462 | break; |
| 1463 | } |
| 1464 | } |
| 1465 | if (rdev->rio_mem == NULL) |
| 1466 | DRM_ERROR("Unable to find PCI I/O BAR\n"); |
| 1467 | |
Alex Deucher | 4807c5a | 2014-07-18 11:54:20 -0400 | [diff] [blame] | 1468 | if (rdev->flags & RADEON_IS_PX) |
| 1469 | radeon_device_handle_px_quirks(rdev); |
| 1470 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1471 | /* if we have > 1 VGA cards, then disable the radeon VGA resources */ |
Dave Airlie | 93239ea | 2009-10-28 11:09:58 +1000 | [diff] [blame] | 1472 | /* this will fail for cards that aren't VGA class devices, just |
| 1473 | * ignore it */ |
| 1474 | vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 1475 | |
Alex Deucher | bfaddd9 | 2016-04-18 11:19:19 -0400 | [diff] [blame] | 1476 | if (rdev->flags & RADEON_IS_PX) |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 1477 | runtime = true; |
| 1478 | vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime); |
| 1479 | if (runtime) |
| 1480 | vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1481 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1482 | r = radeon_init(rdev); |
Jerome Glisse | b574f25 | 2009-10-06 19:04:29 +0200 | [diff] [blame] | 1483 | if (r) |
Alex Deucher | 2e97140 | 2014-09-12 18:00:53 -0400 | [diff] [blame] | 1484 | goto failed; |
Michel Dänzer | b1e3a6d | 2009-06-23 16:12:54 +0200 | [diff] [blame] | 1485 | |
Jerome Glisse | 409851f | 2013-04-25 22:29:27 -0400 | [diff] [blame] | 1486 | r = radeon_gem_debugfs_init(rdev); |
| 1487 | if (r) { |
| 1488 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); |
| 1489 | } |
| 1490 | |
Dave Airlie | 9843ead | 2015-02-24 09:24:04 +1000 | [diff] [blame] | 1491 | r = radeon_mst_debugfs_init(rdev); |
| 1492 | if (r) { |
| 1493 | DRM_ERROR("registering mst debugfs failed (%d).\n", r); |
| 1494 | } |
| 1495 | |
Jerome Glisse | b574f25 | 2009-10-06 19:04:29 +0200 | [diff] [blame] | 1496 | if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { |
| 1497 | /* Acceleration not working on AGP card try again |
| 1498 | * with fallback to PCI or PCIE GART |
| 1499 | */ |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 1500 | radeon_asic_reset(rdev); |
Jerome Glisse | b574f25 | 2009-10-06 19:04:29 +0200 | [diff] [blame] | 1501 | radeon_fini(rdev); |
| 1502 | radeon_agp_disable(rdev); |
| 1503 | r = radeon_init(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 1504 | if (r) |
Alex Deucher | 2e97140 | 2014-09-12 18:00:53 -0400 | [diff] [blame] | 1505 | goto failed; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1506 | } |
Alex Deucher | 6c7bcce | 2013-12-18 14:07:14 -0500 | [diff] [blame] | 1507 | |
Christian König | 13a7d29 | 2014-08-24 14:52:46 +0200 | [diff] [blame] | 1508 | r = radeon_ib_ring_tests(rdev); |
| 1509 | if (r) |
| 1510 | DRM_ERROR("ib ring test failed (%d).\n", r); |
| 1511 | |
Jérôme Glisse | 6dfd197 | 2015-06-05 13:33:57 -0400 | [diff] [blame] | 1512 | /* |
| 1513 | * Turks/Thames GPU will freeze whole laptop if DPM is not restarted |
| 1514 | * after the CP ring have chew one packet at least. Hence here we stop |
| 1515 | * and restart DPM after the radeon_ib_ring_tests(). |
| 1516 | */ |
| 1517 | if (rdev->pm.dpm_enabled && |
| 1518 | (rdev->pm.pm_method == PM_METHOD_DPM) && |
| 1519 | (rdev->family == CHIP_TURKS) && |
| 1520 | (rdev->flags & RADEON_IS_MOBILITY)) { |
| 1521 | mutex_lock(&rdev->pm.mutex); |
| 1522 | radeon_dpm_disable(rdev); |
| 1523 | radeon_dpm_enable(rdev); |
| 1524 | mutex_unlock(&rdev->pm.mutex); |
| 1525 | } |
| 1526 | |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 1527 | if ((radeon_testing & 1)) { |
Alex Deucher | 4a1132a | 2013-09-23 10:38:26 -0400 | [diff] [blame] | 1528 | if (rdev->accel_working) |
| 1529 | radeon_test_moves(rdev); |
| 1530 | else |
| 1531 | DRM_INFO("radeon: acceleration disabled, skipping move tests\n"); |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 1532 | } |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 1533 | if ((radeon_testing & 2)) { |
Alex Deucher | 4a1132a | 2013-09-23 10:38:26 -0400 | [diff] [blame] | 1534 | if (rdev->accel_working) |
| 1535 | radeon_test_syncing(rdev); |
| 1536 | else |
| 1537 | DRM_INFO("radeon: acceleration disabled, skipping sync tests\n"); |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 1538 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1539 | if (radeon_benchmarking) { |
Alex Deucher | 4a1132a | 2013-09-23 10:38:26 -0400 | [diff] [blame] | 1540 | if (rdev->accel_working) |
| 1541 | radeon_benchmark(rdev, radeon_benchmarking); |
| 1542 | else |
| 1543 | DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1544 | } |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 1545 | return 0; |
Alex Deucher | 2e97140 | 2014-09-12 18:00:53 -0400 | [diff] [blame] | 1546 | |
| 1547 | failed: |
Lukas Wunner | b875194 | 2016-06-08 18:47:27 +0200 | [diff] [blame] | 1548 | /* balance pm_runtime_get_sync() in radeon_driver_unload_kms() */ |
| 1549 | if (radeon_is_px(ddev)) |
| 1550 | pm_runtime_put_noidle(ddev->dev); |
Alex Deucher | 2e97140 | 2014-09-12 18:00:53 -0400 | [diff] [blame] | 1551 | if (runtime) |
| 1552 | vga_switcheroo_fini_domain_pm_ops(rdev->dev); |
| 1553 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1554 | } |
| 1555 | |
Christian König | 4d8bf9a | 2011-10-24 14:54:54 +0200 | [diff] [blame] | 1556 | static void radeon_debugfs_remove_files(struct radeon_device *rdev); |
| 1557 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 1558 | /** |
| 1559 | * radeon_device_fini - tear down the driver |
| 1560 | * |
| 1561 | * @rdev: radeon_device pointer |
| 1562 | * |
| 1563 | * Tear down the driver info (all asics). |
| 1564 | * Called at driver shutdown. |
| 1565 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1566 | void radeon_device_fini(struct radeon_device *rdev) |
| 1567 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1568 | DRM_INFO("radeon: finishing device.\n"); |
| 1569 | rdev->shutdown = true; |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 1570 | /* evict vram memory */ |
| 1571 | radeon_bo_evict_vram(rdev); |
Jerome Glisse | 62a8ea3 | 2009-10-01 18:02:11 +0200 | [diff] [blame] | 1572 | radeon_fini(rdev); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1573 | vga_switcheroo_unregister_client(rdev->pdev); |
Alex Deucher | 2e97140 | 2014-09-12 18:00:53 -0400 | [diff] [blame] | 1574 | if (rdev->flags & RADEON_IS_PX) |
| 1575 | vga_switcheroo_fini_domain_pm_ops(rdev->dev); |
Dave Airlie | c1176d6 | 2009-10-08 14:03:05 +1000 | [diff] [blame] | 1576 | vga_client_register(rdev->pdev, NULL, NULL, NULL); |
Alex Deucher | e0a2ca7 | 2010-07-08 12:24:52 -0400 | [diff] [blame] | 1577 | if (rdev->rio_mem) |
| 1578 | pci_iounmap(rdev->pdev, rdev->rio_mem); |
Alex Deucher | 351a52a | 2010-06-30 11:52:50 -0400 | [diff] [blame] | 1579 | rdev->rio_mem = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1580 | iounmap(rdev->rmmio); |
| 1581 | rdev->rmmio = NULL; |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 1582 | if (rdev->family >= CHIP_BONAIRE) |
| 1583 | radeon_doorbell_fini(rdev); |
Christian König | 4d8bf9a | 2011-10-24 14:54:54 +0200 | [diff] [blame] | 1584 | radeon_debugfs_remove_files(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1585 | } |
| 1586 | |
| 1587 | |
| 1588 | /* |
| 1589 | * Suspend & resume. |
| 1590 | */ |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 1591 | /** |
| 1592 | * radeon_suspend_kms - initiate device suspend |
| 1593 | * |
| 1594 | * @pdev: drm dev pointer |
| 1595 | * @state: suspend state |
| 1596 | * |
| 1597 | * Puts the hw in the suspend state (all asics). |
| 1598 | * Returns 0 for success or an error on failure. |
| 1599 | * Called at driver suspend. |
| 1600 | */ |
Jérome Glisse | 274ad65 | 2016-03-18 16:58:39 +0100 | [diff] [blame] | 1601 | int radeon_suspend_kms(struct drm_device *dev, bool suspend, |
| 1602 | bool fbcon, bool freeze) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1603 | { |
Darren Jenkins | 875c186 | 2009-12-30 12:18:30 +1100 | [diff] [blame] | 1604 | struct radeon_device *rdev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1605 | struct drm_crtc *crtc; |
Alex Deucher | d8dcaa1 | 2010-06-02 12:08:41 -0400 | [diff] [blame] | 1606 | struct drm_connector *connector; |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 1607 | int i, r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1608 | |
Darren Jenkins | 875c186 | 2009-12-30 12:18:30 +1100 | [diff] [blame] | 1609 | if (dev == NULL || dev->dev_private == NULL) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1610 | return -ENODEV; |
| 1611 | } |
Dave Airlie | 7473e83 | 2012-09-13 12:02:30 +1000 | [diff] [blame] | 1612 | |
Darren Jenkins | 875c186 | 2009-12-30 12:18:30 +1100 | [diff] [blame] | 1613 | rdev = dev->dev_private; |
| 1614 | |
Alex Deucher | f2aba35 | 2016-09-19 12:20:18 -0400 | [diff] [blame] | 1615 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1616 | return 0; |
Alex Deucher | d8dcaa1 | 2010-06-02 12:08:41 -0400 | [diff] [blame] | 1617 | |
Seth Forshee | 86698c2 | 2012-01-31 19:06:25 -0600 | [diff] [blame] | 1618 | drm_kms_helper_poll_disable(dev); |
| 1619 | |
Daniel Vetter | 6adaed5 | 2015-09-23 20:26:45 +0200 | [diff] [blame] | 1620 | drm_modeset_lock_all(dev); |
Alex Deucher | d8dcaa1 | 2010-06-02 12:08:41 -0400 | [diff] [blame] | 1621 | /* turn off display hw */ |
| 1622 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 1623 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); |
| 1624 | } |
Daniel Vetter | 6adaed5 | 2015-09-23 20:26:45 +0200 | [diff] [blame] | 1625 | drm_modeset_unlock_all(dev); |
Alex Deucher | d8dcaa1 | 2010-06-02 12:08:41 -0400 | [diff] [blame] | 1626 | |
Grigori Goronzy | f3cbb17 | 2015-07-07 16:27:29 +0900 | [diff] [blame] | 1627 | /* unpin the front buffers and cursors */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1628 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
Grigori Goronzy | f3cbb17 | 2015-07-07 16:27:29 +0900 | [diff] [blame] | 1629 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1630 | struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1631 | struct radeon_bo *robj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1632 | |
Grigori Goronzy | f3cbb17 | 2015-07-07 16:27:29 +0900 | [diff] [blame] | 1633 | if (radeon_crtc->cursor_bo) { |
| 1634 | struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); |
| 1635 | r = radeon_bo_reserve(robj, false); |
| 1636 | if (r == 0) { |
| 1637 | radeon_bo_unpin(robj); |
| 1638 | radeon_bo_unreserve(robj); |
| 1639 | } |
| 1640 | } |
| 1641 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1642 | if (rfb == NULL || rfb->obj == NULL) { |
| 1643 | continue; |
| 1644 | } |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 1645 | robj = gem_to_radeon_bo(rfb->obj); |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 1646 | /* don't unpin kernel fb objects */ |
| 1647 | if (!radeon_fbdev_robj_is_fb(rdev, robj)) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1648 | r = radeon_bo_reserve(robj, false); |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 1649 | if (r == 0) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1650 | radeon_bo_unpin(robj); |
| 1651 | radeon_bo_unreserve(robj); |
| 1652 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1653 | } |
| 1654 | } |
| 1655 | /* evict vram memory */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1656 | radeon_bo_evict_vram(rdev); |
Christian König | 8a47cc9 | 2012-05-09 15:34:48 +0200 | [diff] [blame] | 1657 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1658 | /* wait for gpu to finish processing current batch */ |
Jerome Glisse | 5f8f635 | 2012-12-17 11:04:32 -0500 | [diff] [blame] | 1659 | for (i = 0; i < RADEON_NUM_RINGS; i++) { |
Christian König | 3761552 | 2014-02-18 15:58:31 +0100 | [diff] [blame] | 1660 | r = radeon_fence_wait_empty(rdev, i); |
Jerome Glisse | 5f8f635 | 2012-12-17 11:04:32 -0500 | [diff] [blame] | 1661 | if (r) { |
| 1662 | /* delay GPU reset to resume */ |
Christian König | eb98c70 | 2014-08-27 15:21:56 +0200 | [diff] [blame] | 1663 | radeon_fence_driver_force_completion(rdev, i); |
Jerome Glisse | 5f8f635 | 2012-12-17 11:04:32 -0500 | [diff] [blame] | 1664 | } |
| 1665 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1666 | |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 1667 | radeon_save_bios_scratch_regs(rdev); |
| 1668 | |
Jerome Glisse | 62a8ea3 | 2009-10-01 18:02:11 +0200 | [diff] [blame] | 1669 | radeon_suspend(rdev); |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 1670 | radeon_hpd_fini(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1671 | /* evict remaining vram memory */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1672 | radeon_bo_evict_vram(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1673 | |
Jerome Glisse | 10b0612 | 2010-05-21 18:48:54 +0200 | [diff] [blame] | 1674 | radeon_agp_suspend(rdev); |
| 1675 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1676 | pci_save_state(dev->pdev); |
Jérôme Glisse | ccaa2c1 | 2016-06-07 17:43:04 -0400 | [diff] [blame] | 1677 | if (freeze && rdev->family >= CHIP_CEDAR) { |
Jérome Glisse | 274ad65 | 2016-03-18 16:58:39 +0100 | [diff] [blame] | 1678 | rdev->asic->asic_reset(rdev, true); |
| 1679 | pci_restore_state(dev->pdev); |
| 1680 | } else if (suspend) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1681 | /* Shut down the device */ |
| 1682 | pci_disable_device(dev->pdev); |
| 1683 | pci_set_power_state(dev->pdev, PCI_D3hot); |
| 1684 | } |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 1685 | |
| 1686 | if (fbcon) { |
| 1687 | console_lock(); |
| 1688 | radeon_fbdev_set_suspend(rdev, 1); |
| 1689 | console_unlock(); |
| 1690 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1691 | return 0; |
| 1692 | } |
| 1693 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 1694 | /** |
| 1695 | * radeon_resume_kms - initiate device resume |
| 1696 | * |
| 1697 | * @pdev: drm dev pointer |
| 1698 | * |
| 1699 | * Bring the hw back to operating state (all asics). |
| 1700 | * Returns 0 for success or an error on failure. |
| 1701 | * Called at driver resume. |
| 1702 | */ |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 1703 | int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1704 | { |
Cedric Godin | 09bdf59 | 2010-06-11 14:40:56 -0400 | [diff] [blame] | 1705 | struct drm_connector *connector; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1706 | struct radeon_device *rdev = dev->dev_private; |
Grigori Goronzy | f3cbb17 | 2015-07-07 16:27:29 +0900 | [diff] [blame] | 1707 | struct drm_crtc *crtc; |
Christian König | 04eb220 | 2012-07-07 12:47:58 +0200 | [diff] [blame] | 1708 | int r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1709 | |
Alex Deucher | f2aba35 | 2016-09-19 12:20:18 -0400 | [diff] [blame] | 1710 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1711 | return 0; |
| 1712 | |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 1713 | if (fbcon) { |
| 1714 | console_lock(); |
| 1715 | } |
Dave Airlie | 7473e83 | 2012-09-13 12:02:30 +1000 | [diff] [blame] | 1716 | if (resume) { |
| 1717 | pci_set_power_state(dev->pdev, PCI_D0); |
| 1718 | pci_restore_state(dev->pdev); |
| 1719 | if (pci_enable_device(dev->pdev)) { |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 1720 | if (fbcon) |
| 1721 | console_unlock(); |
Dave Airlie | 7473e83 | 2012-09-13 12:02:30 +1000 | [diff] [blame] | 1722 | return -1; |
| 1723 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1724 | } |
Dave Airlie | 0ebf171 | 2009-11-05 15:39:10 +1000 | [diff] [blame] | 1725 | /* resume AGP if in use */ |
| 1726 | radeon_agp_resume(rdev); |
Jerome Glisse | 62a8ea3 | 2009-10-01 18:02:11 +0200 | [diff] [blame] | 1727 | radeon_resume(rdev); |
Christian König | 04eb220 | 2012-07-07 12:47:58 +0200 | [diff] [blame] | 1728 | |
| 1729 | r = radeon_ib_ring_tests(rdev); |
| 1730 | if (r) |
| 1731 | DRM_ERROR("ib ring test failed (%d).\n", r); |
| 1732 | |
Alex Deucher | bc6a629 | 2014-02-25 12:01:28 -0500 | [diff] [blame] | 1733 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { |
Alex Deucher | 6c7bcce | 2013-12-18 14:07:14 -0500 | [diff] [blame] | 1734 | /* do dpm late init */ |
| 1735 | r = radeon_pm_late_init(rdev); |
| 1736 | if (r) { |
| 1737 | rdev->pm.dpm_enabled = false; |
| 1738 | DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); |
| 1739 | } |
Alex Deucher | bc6a629 | 2014-02-25 12:01:28 -0500 | [diff] [blame] | 1740 | } else { |
| 1741 | /* resume old pm late */ |
| 1742 | radeon_pm_resume(rdev); |
Alex Deucher | 6c7bcce | 2013-12-18 14:07:14 -0500 | [diff] [blame] | 1743 | } |
| 1744 | |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 1745 | radeon_restore_bios_scratch_regs(rdev); |
Cedric Godin | 09bdf59 | 2010-06-11 14:40:56 -0400 | [diff] [blame] | 1746 | |
Grigori Goronzy | f3cbb17 | 2015-07-07 16:27:29 +0900 | [diff] [blame] | 1747 | /* pin cursors */ |
| 1748 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 1749 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1750 | |
| 1751 | if (radeon_crtc->cursor_bo) { |
| 1752 | struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); |
| 1753 | r = radeon_bo_reserve(robj, false); |
| 1754 | if (r == 0) { |
| 1755 | /* Only 27 bit offset for legacy cursor */ |
| 1756 | r = radeon_bo_pin_restricted(robj, |
| 1757 | RADEON_GEM_DOMAIN_VRAM, |
| 1758 | ASIC_IS_AVIVO(rdev) ? |
| 1759 | 0 : 1 << 27, |
| 1760 | &radeon_crtc->cursor_addr); |
| 1761 | if (r != 0) |
| 1762 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); |
| 1763 | radeon_bo_unreserve(robj); |
| 1764 | } |
| 1765 | } |
| 1766 | } |
| 1767 | |
Alex Deucher | 3fa47d9 | 2012-01-20 14:56:39 -0500 | [diff] [blame] | 1768 | /* init dig PHYs, disp eng pll */ |
| 1769 | if (rdev->is_atom_bios) { |
Alex Deucher | ac89af1 | 2011-05-22 13:20:36 -0400 | [diff] [blame] | 1770 | radeon_atom_encoder_init(rdev); |
Alex Deucher | f3f1f03 | 2012-03-20 17:18:04 -0400 | [diff] [blame] | 1771 | radeon_atom_disp_eng_pll_init(rdev); |
Alex Deucher | bced76f | 2012-09-14 09:45:50 -0400 | [diff] [blame] | 1772 | /* turn on the BL */ |
| 1773 | if (rdev->mode_info.bl_encoder) { |
| 1774 | u8 bl_level = radeon_get_backlight_level(rdev, |
| 1775 | rdev->mode_info.bl_encoder); |
| 1776 | radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, |
| 1777 | bl_level); |
| 1778 | } |
Alex Deucher | 3fa47d9 | 2012-01-20 14:56:39 -0500 | [diff] [blame] | 1779 | } |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 1780 | /* reset hpd state */ |
| 1781 | radeon_hpd_init(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1782 | /* blat the mode back in */ |
Dave Airlie | ec9954f | 2014-03-27 14:09:19 +1000 | [diff] [blame] | 1783 | if (fbcon) { |
| 1784 | drm_helper_resume_force_mode(dev); |
| 1785 | /* turn on display hw */ |
Daniel Vetter | 6adaed5 | 2015-09-23 20:26:45 +0200 | [diff] [blame] | 1786 | drm_modeset_lock_all(dev); |
Dave Airlie | ec9954f | 2014-03-27 14:09:19 +1000 | [diff] [blame] | 1787 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 1788 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); |
| 1789 | } |
Daniel Vetter | 6adaed5 | 2015-09-23 20:26:45 +0200 | [diff] [blame] | 1790 | drm_modeset_unlock_all(dev); |
Alex Deucher | a93f344 | 2010-12-20 11:22:29 -0500 | [diff] [blame] | 1791 | } |
Seth Forshee | 86698c2 | 2012-01-31 19:06:25 -0600 | [diff] [blame] | 1792 | |
| 1793 | drm_kms_helper_poll_enable(dev); |
Daniel Vetter | 18ee37a | 2014-05-30 16:41:23 +0200 | [diff] [blame] | 1794 | |
Alex Deucher | 3640da2 | 2014-05-30 12:40:15 -0400 | [diff] [blame] | 1795 | /* set the power state here in case we are a PX system or headless */ |
| 1796 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) |
| 1797 | radeon_pm_compute_clocks(rdev); |
| 1798 | |
Daniel Vetter | 18ee37a | 2014-05-30 16:41:23 +0200 | [diff] [blame] | 1799 | if (fbcon) { |
| 1800 | radeon_fbdev_set_suspend(rdev, 0); |
| 1801 | console_unlock(); |
| 1802 | } |
| 1803 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1804 | return 0; |
| 1805 | } |
| 1806 | |
Alex Deucher | 0c19511 | 2012-07-17 14:02:33 -0400 | [diff] [blame] | 1807 | /** |
| 1808 | * radeon_gpu_reset - reset the asic |
| 1809 | * |
| 1810 | * @rdev: radeon device pointer |
| 1811 | * |
| 1812 | * Attempt the reset the GPU if it has hung (all asics). |
| 1813 | * Returns 0 for success or an error on failure. |
| 1814 | */ |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 1815 | int radeon_gpu_reset(struct radeon_device *rdev) |
| 1816 | { |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 1817 | unsigned ring_sizes[RADEON_NUM_RINGS]; |
| 1818 | uint32_t *ring_data[RADEON_NUM_RINGS]; |
| 1819 | |
| 1820 | bool saved = false; |
| 1821 | |
| 1822 | int i, r; |
Dave Airlie | 8fd1b84 | 2011-02-10 14:46:06 +1000 | [diff] [blame] | 1823 | int resched; |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 1824 | |
Jerome Glisse | dee53e7 | 2012-07-02 12:45:19 -0400 | [diff] [blame] | 1825 | down_write(&rdev->exclusive_lock); |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 1826 | |
| 1827 | if (!rdev->needs_reset) { |
| 1828 | up_write(&rdev->exclusive_lock); |
| 1829 | return 0; |
| 1830 | } |
| 1831 | |
Marek Olšák | 72b9076 | 2015-04-29 19:40:33 +0200 | [diff] [blame] | 1832 | atomic_inc(&rdev->gpu_reset_counter); |
| 1833 | |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 1834 | radeon_save_bios_scratch_regs(rdev); |
Dave Airlie | 8fd1b84 | 2011-02-10 14:46:06 +1000 | [diff] [blame] | 1835 | /* block TTM */ |
| 1836 | resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 1837 | radeon_suspend(rdev); |
Alex Deucher | 73ef0e0 | 2014-08-18 16:51:46 -0400 | [diff] [blame] | 1838 | radeon_hpd_fini(rdev); |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 1839 | |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 1840 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
| 1841 | ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], |
| 1842 | &ring_data[i]); |
| 1843 | if (ring_sizes[i]) { |
| 1844 | saved = true; |
| 1845 | dev_info(rdev->dev, "Saved %d dwords of commands " |
| 1846 | "on ring %d.\n", ring_sizes[i], i); |
| 1847 | } |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 1848 | } |
Michel Dänzer | 7a1619b | 2011-11-10 18:57:26 +0100 | [diff] [blame] | 1849 | |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 1850 | r = radeon_asic_reset(rdev); |
| 1851 | if (!r) { |
| 1852 | dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); |
| 1853 | radeon_resume(rdev); |
| 1854 | } |
| 1855 | |
| 1856 | radeon_restore_bios_scratch_regs(rdev); |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 1857 | |
Maarten Lankhorst | 9bb39ff | 2014-08-27 16:45:18 -0400 | [diff] [blame] | 1858 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
| 1859 | if (!r && ring_data[i]) { |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 1860 | radeon_ring_restore(rdev, &rdev->ring[i], |
| 1861 | ring_sizes[i], ring_data[i]); |
Maarten Lankhorst | 9bb39ff | 2014-08-27 16:45:18 -0400 | [diff] [blame] | 1862 | } else { |
Christian König | eb98c70 | 2014-08-27 15:21:56 +0200 | [diff] [blame] | 1863 | radeon_fence_driver_force_completion(rdev, i); |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 1864 | kfree(ring_data[i]); |
| 1865 | } |
| 1866 | } |
| 1867 | |
Alex Deucher | c940b44 | 2014-08-18 11:57:28 -0400 | [diff] [blame] | 1868 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { |
| 1869 | /* do dpm late init */ |
| 1870 | r = radeon_pm_late_init(rdev); |
| 1871 | if (r) { |
| 1872 | rdev->pm.dpm_enabled = false; |
| 1873 | DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); |
| 1874 | } |
| 1875 | } else { |
| 1876 | /* resume old pm late */ |
| 1877 | radeon_pm_resume(rdev); |
| 1878 | } |
| 1879 | |
Alex Deucher | 73ef0e0 | 2014-08-18 16:51:46 -0400 | [diff] [blame] | 1880 | /* init dig PHYs, disp eng pll */ |
| 1881 | if (rdev->is_atom_bios) { |
| 1882 | radeon_atom_encoder_init(rdev); |
| 1883 | radeon_atom_disp_eng_pll_init(rdev); |
| 1884 | /* turn on the BL */ |
| 1885 | if (rdev->mode_info.bl_encoder) { |
| 1886 | u8 bl_level = radeon_get_backlight_level(rdev, |
| 1887 | rdev->mode_info.bl_encoder); |
| 1888 | radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, |
| 1889 | bl_level); |
| 1890 | } |
| 1891 | } |
| 1892 | /* reset hpd state */ |
| 1893 | radeon_hpd_init(rdev); |
| 1894 | |
Maarten Lankhorst | 9bb39ff | 2014-08-27 16:45:18 -0400 | [diff] [blame] | 1895 | ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); |
Christian König | 3c03638 | 2014-08-27 15:22:01 +0200 | [diff] [blame] | 1896 | |
| 1897 | rdev->in_reset = true; |
| 1898 | rdev->needs_reset = false; |
| 1899 | |
Maarten Lankhorst | 9bb39ff | 2014-08-27 16:45:18 -0400 | [diff] [blame] | 1900 | downgrade_write(&rdev->exclusive_lock); |
| 1901 | |
Jerome Glisse | d349357 | 2012-12-14 16:20:46 -0500 | [diff] [blame] | 1902 | drm_helper_resume_force_mode(rdev->ddev); |
| 1903 | |
Alex Deucher | c940b44 | 2014-08-18 11:57:28 -0400 | [diff] [blame] | 1904 | /* set the power state here in case we are a PX system or headless */ |
| 1905 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) |
| 1906 | radeon_pm_compute_clocks(rdev); |
| 1907 | |
Maarten Lankhorst | 9bb39ff | 2014-08-27 16:45:18 -0400 | [diff] [blame] | 1908 | if (!r) { |
| 1909 | r = radeon_ib_ring_tests(rdev); |
| 1910 | if (r && saved) |
| 1911 | r = -EAGAIN; |
| 1912 | } else { |
Michel Dänzer | 7a1619b | 2011-11-10 18:57:26 +0100 | [diff] [blame] | 1913 | /* bad news, how to tell it to userspace ? */ |
| 1914 | dev_info(rdev->dev, "GPU reset failed\n"); |
| 1915 | } |
| 1916 | |
Maarten Lankhorst | 9bb39ff | 2014-08-27 16:45:18 -0400 | [diff] [blame] | 1917 | rdev->needs_reset = r == -EAGAIN; |
| 1918 | rdev->in_reset = false; |
| 1919 | |
| 1920 | up_read(&rdev->exclusive_lock); |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 1921 | return r; |
| 1922 | } |
| 1923 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1924 | |
| 1925 | /* |
| 1926 | * Debugfs |
| 1927 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1928 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
| 1929 | struct drm_info_list *files, |
| 1930 | unsigned nfiles) |
| 1931 | { |
| 1932 | unsigned i; |
| 1933 | |
Christian König | 4d8bf9a | 2011-10-24 14:54:54 +0200 | [diff] [blame] | 1934 | for (i = 0; i < rdev->debugfs_count; i++) { |
| 1935 | if (rdev->debugfs[i].files == files) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1936 | /* Already registered */ |
| 1937 | return 0; |
| 1938 | } |
| 1939 | } |
Michael Witten | c245cb9 | 2011-09-16 20:45:30 +0000 | [diff] [blame] | 1940 | |
Christian König | 4d8bf9a | 2011-10-24 14:54:54 +0200 | [diff] [blame] | 1941 | i = rdev->debugfs_count + 1; |
Michael Witten | c245cb9 | 2011-09-16 20:45:30 +0000 | [diff] [blame] | 1942 | if (i > RADEON_DEBUGFS_MAX_COMPONENTS) { |
| 1943 | DRM_ERROR("Reached maximum number of debugfs components.\n"); |
| 1944 | DRM_ERROR("Report so we increase " |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 1945 | "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1946 | return -EINVAL; |
| 1947 | } |
Christian König | 4d8bf9a | 2011-10-24 14:54:54 +0200 | [diff] [blame] | 1948 | rdev->debugfs[rdev->debugfs_count].files = files; |
| 1949 | rdev->debugfs[rdev->debugfs_count].num_files = nfiles; |
| 1950 | rdev->debugfs_count = i; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1951 | #if defined(CONFIG_DEBUG_FS) |
| 1952 | drm_debugfs_create_files(files, nfiles, |
| 1953 | rdev->ddev->control->debugfs_root, |
| 1954 | rdev->ddev->control); |
| 1955 | drm_debugfs_create_files(files, nfiles, |
| 1956 | rdev->ddev->primary->debugfs_root, |
| 1957 | rdev->ddev->primary); |
| 1958 | #endif |
| 1959 | return 0; |
| 1960 | } |
| 1961 | |
Christian König | 4d8bf9a | 2011-10-24 14:54:54 +0200 | [diff] [blame] | 1962 | static void radeon_debugfs_remove_files(struct radeon_device *rdev) |
| 1963 | { |
| 1964 | #if defined(CONFIG_DEBUG_FS) |
| 1965 | unsigned i; |
| 1966 | |
| 1967 | for (i = 0; i < rdev->debugfs_count; i++) { |
| 1968 | drm_debugfs_remove_files(rdev->debugfs[i].files, |
| 1969 | rdev->debugfs[i].num_files, |
| 1970 | rdev->ddev->control); |
| 1971 | drm_debugfs_remove_files(rdev->debugfs[i].files, |
| 1972 | rdev->debugfs[i].num_files, |
| 1973 | rdev->ddev->primary); |
| 1974 | } |
| 1975 | #endif |
| 1976 | } |