Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 28 | #include <drm/drmP.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 29 | #include "radeon.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/radeon_drm.h> |
Marek Olšák | 6759a0a | 2012-08-09 16:34:17 +0200 | [diff] [blame] | 31 | #include "radeon_asic.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 32 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 33 | #include <linux/vga_switcheroo.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 34 | #include <linux/slab.h> |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 35 | #include <linux/pm_runtime.h> |
Alex Deucher | 7848865 | 2014-03-11 15:02:30 -0400 | [diff] [blame] | 36 | |
Oded Gabbay | e28740e | 2014-07-15 13:53:32 +0300 | [diff] [blame] | 37 | #include "radeon_kfd.h" |
| 38 | |
Alex Deucher | 7848865 | 2014-03-11 15:02:30 -0400 | [diff] [blame] | 39 | #if defined(CONFIG_VGA_SWITCHEROO) |
Alex Deucher | 90c4cde | 2014-04-10 22:29:01 -0400 | [diff] [blame] | 40 | bool radeon_has_atpx(void); |
Alex Deucher | 7848865 | 2014-03-11 15:02:30 -0400 | [diff] [blame] | 41 | #else |
Alex Deucher | 90c4cde | 2014-04-10 22:29:01 -0400 | [diff] [blame] | 42 | static inline bool radeon_has_atpx(void) { return false; } |
Alex Deucher | 7848865 | 2014-03-11 15:02:30 -0400 | [diff] [blame] | 43 | #endif |
| 44 | |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 45 | /** |
| 46 | * radeon_driver_unload_kms - Main unload function for KMS. |
| 47 | * |
| 48 | * @dev: drm dev pointer |
| 49 | * |
| 50 | * This is the main unload function for KMS (all asics). |
| 51 | * It calls radeon_modeset_fini() to tear down the |
| 52 | * displays, and radeon_device_fini() to tear down |
| 53 | * the rest of the device (CP, writeback, etc.). |
| 54 | * Returns 0 on success. |
| 55 | */ |
Jerome Glisse | cf0fe45 | 2009-12-09 18:21:55 +0100 | [diff] [blame] | 56 | int radeon_driver_unload_kms(struct drm_device *dev) |
| 57 | { |
| 58 | struct radeon_device *rdev = dev->dev_private; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 59 | |
Jerome Glisse | cf0fe45 | 2009-12-09 18:21:55 +0100 | [diff] [blame] | 60 | if (rdev == NULL) |
| 61 | return 0; |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 62 | |
Alex Deucher | 0cd9cb7 | 2013-04-12 19:15:52 -0400 | [diff] [blame] | 63 | if (rdev->rmmio == NULL) |
| 64 | goto done_free; |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 65 | |
Lukas Wunner | 19de659 | 2016-06-08 18:47:27 +0200 | [diff] [blame] | 66 | if (radeon_is_px(dev)) { |
| 67 | pm_runtime_get_sync(dev->dev); |
Lukas Wunner | 8fecb6a | 2016-06-08 18:47:27 +0200 | [diff] [blame] | 68 | pm_runtime_forbid(dev->dev); |
Lukas Wunner | 19de659 | 2016-06-08 18:47:27 +0200 | [diff] [blame] | 69 | } |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 70 | |
Oded Gabbay | e28740e | 2014-07-15 13:53:32 +0300 | [diff] [blame] | 71 | radeon_kfd_device_fini(rdev); |
| 72 | |
Alex Deucher | c491707 | 2012-07-31 17:14:35 -0400 | [diff] [blame] | 73 | radeon_acpi_fini(rdev); |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 74 | |
Jerome Glisse | cf0fe45 | 2009-12-09 18:21:55 +0100 | [diff] [blame] | 75 | radeon_modeset_fini(rdev); |
| 76 | radeon_device_fini(rdev); |
Alex Deucher | 0cd9cb7 | 2013-04-12 19:15:52 -0400 | [diff] [blame] | 77 | |
| 78 | done_free: |
Jerome Glisse | cf0fe45 | 2009-12-09 18:21:55 +0100 | [diff] [blame] | 79 | kfree(rdev); |
| 80 | dev->dev_private = NULL; |
| 81 | return 0; |
| 82 | } |
| 83 | |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 84 | /** |
| 85 | * radeon_driver_load_kms - Main load function for KMS. |
| 86 | * |
| 87 | * @dev: drm dev pointer |
| 88 | * @flags: device flags |
| 89 | * |
| 90 | * This is the main load function for KMS (all asics). |
| 91 | * It calls radeon_device_init() to set up the non-display |
| 92 | * parts of the chip (asic init, CP, writeback, etc.), and |
| 93 | * radeon_modeset_init() to set up the display parts |
| 94 | * (crtcs, encoders, hotplug detect, etc.). |
| 95 | * Returns 0 on success, error on failure. |
| 96 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 97 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
| 98 | { |
| 99 | struct radeon_device *rdev; |
Alberto Milone | d7a2952 | 2010-07-06 11:40:24 -0400 | [diff] [blame] | 100 | int r, acpi_status; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 101 | |
| 102 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); |
| 103 | if (rdev == NULL) { |
| 104 | return -ENOMEM; |
| 105 | } |
| 106 | dev->dev_private = (void *)rdev; |
| 107 | |
| 108 | /* update BUS flag */ |
Dave Airlie | 8410ea3 | 2010-12-15 03:16:38 +1000 | [diff] [blame] | 109 | if (drm_pci_device_is_agp(dev)) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 110 | flags |= RADEON_IS_AGP; |
Jon Mason | 58b6542 | 2011-06-27 16:07:50 +0000 | [diff] [blame] | 111 | } else if (pci_is_pcie(dev->pdev)) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 112 | flags |= RADEON_IS_PCIE; |
| 113 | } else { |
| 114 | flags |= RADEON_IS_PCI; |
| 115 | } |
| 116 | |
Alex Deucher | 73acacc | 2014-04-15 12:44:35 -0400 | [diff] [blame] | 117 | if ((radeon_runtime_pm != 0) && |
| 118 | radeon_has_atpx() && |
| 119 | ((flags & RADEON_IS_IGP) == 0)) |
Alex Deucher | 90c4cde | 2014-04-10 22:29:01 -0400 | [diff] [blame] | 120 | flags |= RADEON_IS_PX; |
| 121 | |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 122 | /* radeon_device_init should report only fatal error |
| 123 | * like memory allocation failure or iomapping failure, |
| 124 | * or memory manager initialization failure, it must |
| 125 | * properly initialize the GPU MC controller and permit |
| 126 | * VRAM allocation |
| 127 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 128 | r = radeon_device_init(rdev, dev, dev->pdev, flags); |
| 129 | if (r) { |
Jerome Glisse | cf0fe45 | 2009-12-09 18:21:55 +0100 | [diff] [blame] | 130 | dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); |
| 131 | goto out; |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 132 | } |
Alberto Milone | d7a2952 | 2010-07-06 11:40:24 -0400 | [diff] [blame] | 133 | |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 134 | /* Again modeset_init should fail only on fatal error |
| 135 | * otherwise it should provide enough functionalities |
| 136 | * for shadowfb to run |
| 137 | */ |
| 138 | r = radeon_modeset_init(rdev); |
Jerome Glisse | cf0fe45 | 2009-12-09 18:21:55 +0100 | [diff] [blame] | 139 | if (r) |
| 140 | dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); |
Luca Tettamanti | fda4b25 | 2012-07-30 21:20:35 +0200 | [diff] [blame] | 141 | |
| 142 | /* Call ACPI methods: require modeset init |
| 143 | * but failure is not fatal |
| 144 | */ |
| 145 | if (!r) { |
| 146 | acpi_status = radeon_acpi_init(rdev); |
| 147 | if (acpi_status) |
| 148 | dev_dbg(&dev->pdev->dev, |
| 149 | "Error during ACPI methods call\n"); |
| 150 | } |
| 151 | |
Oded Gabbay | e28740e | 2014-07-15 13:53:32 +0300 | [diff] [blame] | 152 | radeon_kfd_device_probe(rdev); |
| 153 | radeon_kfd_device_init(rdev); |
| 154 | |
Alex Deucher | 90c4cde | 2014-04-10 22:29:01 -0400 | [diff] [blame] | 155 | if (radeon_is_px(dev)) { |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 156 | pm_runtime_use_autosuspend(dev->dev); |
| 157 | pm_runtime_set_autosuspend_delay(dev->dev, 5000); |
| 158 | pm_runtime_set_active(dev->dev); |
| 159 | pm_runtime_allow(dev->dev); |
| 160 | pm_runtime_mark_last_busy(dev->dev); |
| 161 | pm_runtime_put_autosuspend(dev->dev); |
| 162 | } |
| 163 | |
Jerome Glisse | cf0fe45 | 2009-12-09 18:21:55 +0100 | [diff] [blame] | 164 | out: |
| 165 | if (r) |
| 166 | radeon_driver_unload_kms(dev); |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 167 | |
| 168 | |
Jerome Glisse | cf0fe45 | 2009-12-09 18:21:55 +0100 | [diff] [blame] | 169 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 170 | } |
| 171 | |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 172 | /** |
| 173 | * radeon_set_filp_rights - Set filp right. |
| 174 | * |
| 175 | * @dev: drm dev pointer |
| 176 | * @owner: drm file |
| 177 | * @applier: drm file |
| 178 | * @value: value |
| 179 | * |
| 180 | * Sets the filp rights for the device (all asics). |
| 181 | */ |
Marek Olšák | 9eba4a9 | 2011-01-05 05:46:48 +0100 | [diff] [blame] | 182 | static void radeon_set_filp_rights(struct drm_device *dev, |
| 183 | struct drm_file **owner, |
| 184 | struct drm_file *applier, |
| 185 | uint32_t *value) |
| 186 | { |
Daniel Vetter | 45c1da5 | 2015-10-15 09:36:34 +0200 | [diff] [blame] | 187 | struct radeon_device *rdev = dev->dev_private; |
| 188 | |
| 189 | mutex_lock(&rdev->gem.mutex); |
Marek Olšák | 9eba4a9 | 2011-01-05 05:46:48 +0100 | [diff] [blame] | 190 | if (*value == 1) { |
| 191 | /* wants rights */ |
| 192 | if (!*owner) |
| 193 | *owner = applier; |
| 194 | } else if (*value == 0) { |
| 195 | /* revokes rights */ |
| 196 | if (*owner == applier) |
| 197 | *owner = NULL; |
| 198 | } |
| 199 | *value = *owner == applier ? 1 : 0; |
Daniel Vetter | 45c1da5 | 2015-10-15 09:36:34 +0200 | [diff] [blame] | 200 | mutex_unlock(&rdev->gem.mutex); |
Marek Olšák | 9eba4a9 | 2011-01-05 05:46:48 +0100 | [diff] [blame] | 201 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 202 | |
| 203 | /* |
Marek Olšák | 9eba4a9 | 2011-01-05 05:46:48 +0100 | [diff] [blame] | 204 | * Userspace get information ioctl |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 205 | */ |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 206 | /** |
| 207 | * radeon_info_ioctl - answer a device specific request. |
| 208 | * |
| 209 | * @rdev: radeon device pointer |
| 210 | * @data: request object |
| 211 | * @filp: drm filp |
| 212 | * |
| 213 | * This function is used to pass device specific parameters to the userspace |
| 214 | * drivers. Examples include: pci device id, pipeline parms, tiling params, |
| 215 | * etc. (all asics). |
| 216 | * Returns 0 on success, -EINVAL on failure. |
| 217 | */ |
Rashika Kheria | 5520345 | 2014-01-06 20:53:07 +0530 | [diff] [blame] | 218 | static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 219 | { |
| 220 | struct radeon_device *rdev = dev->dev_private; |
Marek Olšák | 6759a0a | 2012-08-09 16:34:17 +0200 | [diff] [blame] | 221 | struct drm_radeon_info *info = data; |
Jerome Glisse | bc35afd | 2010-05-12 18:01:13 +0200 | [diff] [blame] | 222 | struct radeon_mode_info *minfo = &rdev->mode_info; |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 223 | uint32_t *value, value_tmp, *value_ptr, value_size; |
| 224 | uint64_t value64; |
Jerome Glisse | bc35afd | 2010-05-12 18:01:13 +0200 | [diff] [blame] | 225 | struct drm_crtc *crtc; |
| 226 | int i, found; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 227 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 228 | value_ptr = (uint32_t *)((unsigned long)info->value); |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 229 | value = &value_tmp; |
| 230 | value_size = sizeof(uint32_t); |
Dr. David Alan Gilbert | d8ab355 | 2010-08-02 09:43:52 +1000 | [diff] [blame] | 231 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 232 | switch (info->request) { |
| 233 | case RADEON_INFO_DEVICE_ID: |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 234 | *value = dev->pdev->device; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 235 | break; |
| 236 | case RADEON_INFO_NUM_GB_PIPES: |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 237 | *value = rdev->num_gb_pipes; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 238 | break; |
Alex Deucher | f779b3e | 2009-08-19 19:11:39 -0400 | [diff] [blame] | 239 | case RADEON_INFO_NUM_Z_PIPES: |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 240 | *value = rdev->num_z_pipes; |
Alex Deucher | f779b3e | 2009-08-19 19:11:39 -0400 | [diff] [blame] | 241 | break; |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 242 | case RADEON_INFO_ACCEL_WORKING: |
Alex Deucher | 148a03b | 2010-06-03 19:00:03 -0400 | [diff] [blame] | 243 | /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ |
| 244 | if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 245 | *value = false; |
Alex Deucher | 148a03b | 2010-06-03 19:00:03 -0400 | [diff] [blame] | 246 | else |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 247 | *value = rdev->accel_working; |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 248 | break; |
Jerome Glisse | bc35afd | 2010-05-12 18:01:13 +0200 | [diff] [blame] | 249 | case RADEON_INFO_CRTC_FROM_ID: |
Daniel Vetter | 1d6ac18 | 2013-12-11 11:34:44 +0100 | [diff] [blame] | 250 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 251 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
| 252 | return -EFAULT; |
| 253 | } |
Jerome Glisse | bc35afd | 2010-05-12 18:01:13 +0200 | [diff] [blame] | 254 | for (i = 0, found = 0; i < rdev->num_crtc; i++) { |
| 255 | crtc = (struct drm_crtc *)minfo->crtcs[i]; |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 256 | if (crtc && crtc->base.id == *value) { |
Alex Deucher | 0baf2d8 | 2010-07-21 14:05:35 -0400 | [diff] [blame] | 257 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 258 | *value = radeon_crtc->crtc_id; |
Jerome Glisse | bc35afd | 2010-05-12 18:01:13 +0200 | [diff] [blame] | 259 | found = 1; |
| 260 | break; |
| 261 | } |
| 262 | } |
| 263 | if (!found) { |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 264 | DRM_DEBUG_KMS("unknown crtc id %d\n", *value); |
Jerome Glisse | bc35afd | 2010-05-12 18:01:13 +0200 | [diff] [blame] | 265 | return -EINVAL; |
| 266 | } |
| 267 | break; |
Alex Deucher | 148a03b | 2010-06-03 19:00:03 -0400 | [diff] [blame] | 268 | case RADEON_INFO_ACCEL_WORKING2: |
Alex Deucher | 3c64bd2 | 2014-08-01 20:05:30 +0200 | [diff] [blame] | 269 | if (rdev->family == CHIP_HAWAII) { |
Andreas Boll | 9eb401a | 2014-08-01 20:05:32 +0200 | [diff] [blame] | 270 | if (rdev->accel_working) { |
| 271 | if (rdev->new_fw) |
| 272 | *value = 3; |
| 273 | else |
| 274 | *value = 2; |
| 275 | } else { |
Alex Deucher | 3c64bd2 | 2014-08-01 20:05:30 +0200 | [diff] [blame] | 276 | *value = 0; |
Andreas Boll | 9eb401a | 2014-08-01 20:05:32 +0200 | [diff] [blame] | 277 | } |
Alex Deucher | 3c64bd2 | 2014-08-01 20:05:30 +0200 | [diff] [blame] | 278 | } else { |
| 279 | *value = rdev->accel_working; |
| 280 | } |
Alex Deucher | 148a03b | 2010-06-03 19:00:03 -0400 | [diff] [blame] | 281 | break; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 282 | case RADEON_INFO_TILING_CONFIG: |
Alex Deucher | 64f759c | 2012-07-06 17:40:32 -0400 | [diff] [blame] | 283 | if (rdev->family >= CHIP_BONAIRE) |
| 284 | *value = rdev->config.cik.tile_config; |
| 285 | else if (rdev->family >= CHIP_TAHITI) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 286 | *value = rdev->config.si.tile_config; |
Michel Dänzer | c1b2f69 | 2012-03-20 17:18:26 -0400 | [diff] [blame] | 287 | else if (rdev->family >= CHIP_CAYMAN) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 288 | *value = rdev->config.cayman.tile_config; |
Alex Deucher | fecf1d0 | 2011-03-02 20:07:29 -0500 | [diff] [blame] | 289 | else if (rdev->family >= CHIP_CEDAR) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 290 | *value = rdev->config.evergreen.tile_config; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 291 | else if (rdev->family >= CHIP_RV770) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 292 | *value = rdev->config.rv770.tile_config; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 293 | else if (rdev->family >= CHIP_R600) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 294 | *value = rdev->config.r600.tile_config; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 295 | else { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 296 | DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 297 | return -EINVAL; |
| 298 | } |
Alex Deucher | b824b36 | 2010-08-12 08:25:47 -0400 | [diff] [blame] | 299 | break; |
Dave Airlie | ab9e1f5 | 2010-07-13 11:11:11 +1000 | [diff] [blame] | 300 | case RADEON_INFO_WANT_HYPERZ: |
Marek Olšák | 43861f7 | 2010-08-07 03:36:34 +0200 | [diff] [blame] | 301 | /* The "value" here is both an input and output parameter. |
| 302 | * If the input value is 1, filp requests hyper-z access. |
| 303 | * If the input value is 0, filp revokes its hyper-z access. |
| 304 | * |
| 305 | * When returning, the value is 1 if filp owns hyper-z access, |
| 306 | * 0 otherwise. */ |
Daniel Vetter | 1d6ac18 | 2013-12-11 11:34:44 +0100 | [diff] [blame] | 307 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 308 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
| 309 | return -EFAULT; |
| 310 | } |
| 311 | if (*value >= 2) { |
| 312 | DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value); |
Marek Olšák | 43861f7 | 2010-08-07 03:36:34 +0200 | [diff] [blame] | 313 | return -EINVAL; |
Dave Airlie | ab9e1f5 | 2010-07-13 11:11:11 +1000 | [diff] [blame] | 314 | } |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 315 | radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value); |
Marek Olšák | 9eba4a9 | 2011-01-05 05:46:48 +0100 | [diff] [blame] | 316 | break; |
| 317 | case RADEON_INFO_WANT_CMASK: |
| 318 | /* The same logic as Hyper-Z. */ |
Daniel Vetter | 1d6ac18 | 2013-12-11 11:34:44 +0100 | [diff] [blame] | 319 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 320 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
| 321 | return -EFAULT; |
| 322 | } |
| 323 | if (*value >= 2) { |
| 324 | DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value); |
Marek Olšák | 9eba4a9 | 2011-01-05 05:46:48 +0100 | [diff] [blame] | 325 | return -EINVAL; |
Marek Olšák | 43861f7 | 2010-08-07 03:36:34 +0200 | [diff] [blame] | 326 | } |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 327 | radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value); |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 328 | break; |
Alex Deucher | 58bbf01 | 2011-01-24 17:14:26 -0500 | [diff] [blame] | 329 | case RADEON_INFO_CLOCK_CRYSTAL_FREQ: |
| 330 | /* return clock value in KHz */ |
Alex Deucher | 454d2e2 | 2013-02-14 10:04:02 -0500 | [diff] [blame] | 331 | if (rdev->asic->get_xclk) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 332 | *value = radeon_get_xclk(rdev) * 10; |
Alex Deucher | 454d2e2 | 2013-02-14 10:04:02 -0500 | [diff] [blame] | 333 | else |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 334 | *value = rdev->clock.spll.reference_freq * 10; |
Alex Deucher | 58bbf01 | 2011-01-24 17:14:26 -0500 | [diff] [blame] | 335 | break; |
Dave Airlie | 486af18 | 2011-03-01 14:32:27 +1000 | [diff] [blame] | 336 | case RADEON_INFO_NUM_BACKENDS: |
Alex Deucher | 64f759c | 2012-07-06 17:40:32 -0400 | [diff] [blame] | 337 | if (rdev->family >= CHIP_BONAIRE) |
| 338 | *value = rdev->config.cik.max_backends_per_se * |
| 339 | rdev->config.cik.max_shader_engines; |
| 340 | else if (rdev->family >= CHIP_TAHITI) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 341 | *value = rdev->config.si.max_backends_per_se * |
Michel Dänzer | c1b2f69 | 2012-03-20 17:18:26 -0400 | [diff] [blame] | 342 | rdev->config.si.max_shader_engines; |
| 343 | else if (rdev->family >= CHIP_CAYMAN) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 344 | *value = rdev->config.cayman.max_backends_per_se * |
Alex Deucher | fecf1d0 | 2011-03-02 20:07:29 -0500 | [diff] [blame] | 345 | rdev->config.cayman.max_shader_engines; |
| 346 | else if (rdev->family >= CHIP_CEDAR) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 347 | *value = rdev->config.evergreen.max_backends; |
Dave Airlie | 486af18 | 2011-03-01 14:32:27 +1000 | [diff] [blame] | 348 | else if (rdev->family >= CHIP_RV770) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 349 | *value = rdev->config.rv770.max_backends; |
Dave Airlie | 486af18 | 2011-03-01 14:32:27 +1000 | [diff] [blame] | 350 | else if (rdev->family >= CHIP_R600) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 351 | *value = rdev->config.r600.max_backends; |
Dave Airlie | 486af18 | 2011-03-01 14:32:27 +1000 | [diff] [blame] | 352 | else { |
| 353 | return -EINVAL; |
| 354 | } |
| 355 | break; |
Alex Deucher | 6565945 | 2011-04-26 13:27:43 -0400 | [diff] [blame] | 356 | case RADEON_INFO_NUM_TILE_PIPES: |
Alex Deucher | 64f759c | 2012-07-06 17:40:32 -0400 | [diff] [blame] | 357 | if (rdev->family >= CHIP_BONAIRE) |
| 358 | *value = rdev->config.cik.max_tile_pipes; |
| 359 | else if (rdev->family >= CHIP_TAHITI) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 360 | *value = rdev->config.si.max_tile_pipes; |
Michel Dänzer | c1b2f69 | 2012-03-20 17:18:26 -0400 | [diff] [blame] | 361 | else if (rdev->family >= CHIP_CAYMAN) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 362 | *value = rdev->config.cayman.max_tile_pipes; |
Alex Deucher | 6565945 | 2011-04-26 13:27:43 -0400 | [diff] [blame] | 363 | else if (rdev->family >= CHIP_CEDAR) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 364 | *value = rdev->config.evergreen.max_tile_pipes; |
Alex Deucher | 6565945 | 2011-04-26 13:27:43 -0400 | [diff] [blame] | 365 | else if (rdev->family >= CHIP_RV770) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 366 | *value = rdev->config.rv770.max_tile_pipes; |
Alex Deucher | 6565945 | 2011-04-26 13:27:43 -0400 | [diff] [blame] | 367 | else if (rdev->family >= CHIP_R600) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 368 | *value = rdev->config.r600.max_tile_pipes; |
Alex Deucher | 6565945 | 2011-04-26 13:27:43 -0400 | [diff] [blame] | 369 | else { |
| 370 | return -EINVAL; |
| 371 | } |
| 372 | break; |
Alex Deucher | 8aeb96f | 2011-05-03 19:28:02 -0400 | [diff] [blame] | 373 | case RADEON_INFO_FUSION_GART_WORKING: |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 374 | *value = 1; |
Alex Deucher | 8aeb96f | 2011-05-03 19:28:02 -0400 | [diff] [blame] | 375 | break; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 376 | case RADEON_INFO_BACKEND_MAP: |
Alex Deucher | 64f759c | 2012-07-06 17:40:32 -0400 | [diff] [blame] | 377 | if (rdev->family >= CHIP_BONAIRE) |
Michel Dänzer | 1ddce27 | 2013-11-18 18:25:59 +0900 | [diff] [blame] | 378 | *value = rdev->config.cik.backend_map; |
Alex Deucher | 64f759c | 2012-07-06 17:40:32 -0400 | [diff] [blame] | 379 | else if (rdev->family >= CHIP_TAHITI) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 380 | *value = rdev->config.si.backend_map; |
Michel Dänzer | c1b2f69 | 2012-03-20 17:18:26 -0400 | [diff] [blame] | 381 | else if (rdev->family >= CHIP_CAYMAN) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 382 | *value = rdev->config.cayman.backend_map; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 383 | else if (rdev->family >= CHIP_CEDAR) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 384 | *value = rdev->config.evergreen.backend_map; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 385 | else if (rdev->family >= CHIP_RV770) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 386 | *value = rdev->config.rv770.backend_map; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 387 | else if (rdev->family >= CHIP_R600) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 388 | *value = rdev->config.r600.backend_map; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 389 | else { |
| 390 | return -EINVAL; |
| 391 | } |
| 392 | break; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 393 | case RADEON_INFO_VA_START: |
| 394 | /* this is where we report if vm is supported or not */ |
| 395 | if (rdev->family < CHIP_CAYMAN) |
| 396 | return -EINVAL; |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 397 | *value = RADEON_VA_RESERVED_SIZE; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 398 | break; |
| 399 | case RADEON_INFO_IB_VM_MAX_SIZE: |
| 400 | /* this is where we report if vm is supported or not */ |
| 401 | if (rdev->family < CHIP_CAYMAN) |
| 402 | return -EINVAL; |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 403 | *value = RADEON_IB_VM_MAX_SIZE; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 404 | break; |
Tom Stellard | 609c1e1 | 2012-03-20 17:17:55 -0400 | [diff] [blame] | 405 | case RADEON_INFO_MAX_PIPES: |
Alex Deucher | 64f759c | 2012-07-06 17:40:32 -0400 | [diff] [blame] | 406 | if (rdev->family >= CHIP_BONAIRE) |
| 407 | *value = rdev->config.cik.max_cu_per_sh; |
| 408 | else if (rdev->family >= CHIP_TAHITI) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 409 | *value = rdev->config.si.max_cu_per_sh; |
Michel Dänzer | c1b2f69 | 2012-03-20 17:18:26 -0400 | [diff] [blame] | 410 | else if (rdev->family >= CHIP_CAYMAN) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 411 | *value = rdev->config.cayman.max_pipes_per_simd; |
Tom Stellard | 609c1e1 | 2012-03-20 17:17:55 -0400 | [diff] [blame] | 412 | else if (rdev->family >= CHIP_CEDAR) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 413 | *value = rdev->config.evergreen.max_pipes; |
Tom Stellard | 609c1e1 | 2012-03-20 17:17:55 -0400 | [diff] [blame] | 414 | else if (rdev->family >= CHIP_RV770) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 415 | *value = rdev->config.rv770.max_pipes; |
Tom Stellard | 609c1e1 | 2012-03-20 17:17:55 -0400 | [diff] [blame] | 416 | else if (rdev->family >= CHIP_R600) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 417 | *value = rdev->config.r600.max_pipes; |
Tom Stellard | 609c1e1 | 2012-03-20 17:17:55 -0400 | [diff] [blame] | 418 | else { |
| 419 | return -EINVAL; |
| 420 | } |
| 421 | break; |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 422 | case RADEON_INFO_TIMESTAMP: |
| 423 | if (rdev->family < CHIP_R600) { |
| 424 | DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); |
| 425 | return -EINVAL; |
| 426 | } |
| 427 | value = (uint32_t*)&value64; |
| 428 | value_size = sizeof(uint64_t); |
| 429 | value64 = radeon_get_gpu_clock_counter(rdev); |
| 430 | break; |
Alex Deucher | 2e1a767 | 2012-12-04 12:55:37 -0500 | [diff] [blame] | 431 | case RADEON_INFO_MAX_SE: |
Alex Deucher | 64f759c | 2012-07-06 17:40:32 -0400 | [diff] [blame] | 432 | if (rdev->family >= CHIP_BONAIRE) |
| 433 | *value = rdev->config.cik.max_shader_engines; |
| 434 | else if (rdev->family >= CHIP_TAHITI) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 435 | *value = rdev->config.si.max_shader_engines; |
Alex Deucher | 2e1a767 | 2012-12-04 12:55:37 -0500 | [diff] [blame] | 436 | else if (rdev->family >= CHIP_CAYMAN) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 437 | *value = rdev->config.cayman.max_shader_engines; |
Alex Deucher | 2e1a767 | 2012-12-04 12:55:37 -0500 | [diff] [blame] | 438 | else if (rdev->family >= CHIP_CEDAR) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 439 | *value = rdev->config.evergreen.num_ses; |
Alex Deucher | 2e1a767 | 2012-12-04 12:55:37 -0500 | [diff] [blame] | 440 | else |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 441 | *value = 1; |
Alex Deucher | 2e1a767 | 2012-12-04 12:55:37 -0500 | [diff] [blame] | 442 | break; |
| 443 | case RADEON_INFO_MAX_SH_PER_SE: |
Alex Deucher | 64f759c | 2012-07-06 17:40:32 -0400 | [diff] [blame] | 444 | if (rdev->family >= CHIP_BONAIRE) |
| 445 | *value = rdev->config.cik.max_sh_per_se; |
| 446 | else if (rdev->family >= CHIP_TAHITI) |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 447 | *value = rdev->config.si.max_sh_per_se; |
Alex Deucher | 2e1a767 | 2012-12-04 12:55:37 -0500 | [diff] [blame] | 448 | else |
| 449 | return -EINVAL; |
| 450 | break; |
Samuel Li | a0a53aa | 2013-04-08 17:25:47 -0400 | [diff] [blame] | 451 | case RADEON_INFO_FASTFB_WORKING: |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 452 | *value = rdev->fastfb_working; |
Samuel Li | a0a53aa | 2013-04-08 17:25:47 -0400 | [diff] [blame] | 453 | break; |
Christian König | 902aaef | 2013-04-09 10:35:42 -0400 | [diff] [blame] | 454 | case RADEON_INFO_RING_WORKING: |
Daniel Vetter | 1d6ac18 | 2013-12-11 11:34:44 +0100 | [diff] [blame] | 455 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 456 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
| 457 | return -EFAULT; |
| 458 | } |
| 459 | switch (*value) { |
Christian König | 902aaef | 2013-04-09 10:35:42 -0400 | [diff] [blame] | 460 | case RADEON_CS_RING_GFX: |
| 461 | case RADEON_CS_RING_COMPUTE: |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 462 | *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; |
Christian König | 902aaef | 2013-04-09 10:35:42 -0400 | [diff] [blame] | 463 | break; |
| 464 | case RADEON_CS_RING_DMA: |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 465 | *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready; |
| 466 | *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready; |
Christian König | 902aaef | 2013-04-09 10:35:42 -0400 | [diff] [blame] | 467 | break; |
| 468 | case RADEON_CS_RING_UVD: |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 469 | *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready; |
Christian König | 902aaef | 2013-04-09 10:35:42 -0400 | [diff] [blame] | 470 | break; |
Christian König | f7ba8b0 | 2014-01-27 10:16:06 -0700 | [diff] [blame] | 471 | case RADEON_CS_RING_VCE: |
| 472 | *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready; |
| 473 | break; |
Christian König | 902aaef | 2013-04-09 10:35:42 -0400 | [diff] [blame] | 474 | default: |
| 475 | return -EINVAL; |
| 476 | } |
| 477 | break; |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 478 | case RADEON_INFO_SI_TILE_MODE_ARRAY: |
Alex Deucher | 64f759c | 2012-07-06 17:40:32 -0400 | [diff] [blame] | 479 | if (rdev->family >= CHIP_BONAIRE) { |
Alex Deucher | 39aee49 | 2013-04-10 13:41:25 -0400 | [diff] [blame] | 480 | value = rdev->config.cik.tile_mode_array; |
| 481 | value_size = sizeof(uint32_t)*32; |
| 482 | } else if (rdev->family >= CHIP_TAHITI) { |
| 483 | value = rdev->config.si.tile_mode_array; |
| 484 | value_size = sizeof(uint32_t)*32; |
| 485 | } else { |
| 486 | DRM_DEBUG_KMS("tile mode array is si+ only!\n"); |
Alex Deucher | 64f759c | 2012-07-06 17:40:32 -0400 | [diff] [blame] | 487 | return -EINVAL; |
| 488 | } |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 489 | break; |
Michel Dänzer | 32f79a8 | 2013-11-18 18:26:00 +0900 | [diff] [blame] | 490 | case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY: |
| 491 | if (rdev->family >= CHIP_BONAIRE) { |
| 492 | value = rdev->config.cik.macrotile_mode_array; |
| 493 | value_size = sizeof(uint32_t)*16; |
| 494 | } else { |
| 495 | DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n"); |
| 496 | return -EINVAL; |
| 497 | } |
| 498 | break; |
Tom Stellard | e5b9e75 | 2013-08-16 17:47:39 -0400 | [diff] [blame] | 499 | case RADEON_INFO_SI_CP_DMA_COMPUTE: |
| 500 | *value = 1; |
| 501 | break; |
Marek Olšák | 439a1cf | 2013-12-22 02:18:01 +0100 | [diff] [blame] | 502 | case RADEON_INFO_SI_BACKEND_ENABLED_MASK: |
| 503 | if (rdev->family >= CHIP_BONAIRE) { |
| 504 | *value = rdev->config.cik.backend_enable_mask; |
| 505 | } else if (rdev->family >= CHIP_TAHITI) { |
| 506 | *value = rdev->config.si.backend_enable_mask; |
| 507 | } else { |
| 508 | DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); |
| 509 | } |
| 510 | break; |
Alex Deucher | f5f1f89 | 2014-01-20 18:20:29 -0500 | [diff] [blame] | 511 | case RADEON_INFO_MAX_SCLK: |
| 512 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && |
| 513 | rdev->pm.dpm_enabled) |
| 514 | *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; |
| 515 | else |
| 516 | *value = rdev->pm.default_sclk * 10; |
| 517 | break; |
Christian König | 98ccc29 | 2014-01-23 09:50:49 -0700 | [diff] [blame] | 518 | case RADEON_INFO_VCE_FW_VERSION: |
| 519 | *value = rdev->vce.fw_version; |
| 520 | break; |
| 521 | case RADEON_INFO_VCE_FB_VERSION: |
| 522 | *value = rdev->vce.fb_version; |
| 523 | break; |
Marek Olšák | 67e8e3f | 2014-03-02 00:56:18 +0100 | [diff] [blame] | 524 | case RADEON_INFO_NUM_BYTES_MOVED: |
| 525 | value = (uint32_t*)&value64; |
| 526 | value_size = sizeof(uint64_t); |
| 527 | value64 = atomic64_read(&rdev->num_bytes_moved); |
| 528 | break; |
| 529 | case RADEON_INFO_VRAM_USAGE: |
| 530 | value = (uint32_t*)&value64; |
| 531 | value_size = sizeof(uint64_t); |
| 532 | value64 = atomic64_read(&rdev->vram_usage); |
| 533 | break; |
| 534 | case RADEON_INFO_GTT_USAGE: |
| 535 | value = (uint32_t*)&value64; |
| 536 | value_size = sizeof(uint64_t); |
| 537 | value64 = atomic64_read(&rdev->gtt_usage); |
| 538 | break; |
Alex Deucher | 65fcf66 | 2014-06-02 16:13:21 -0400 | [diff] [blame] | 539 | case RADEON_INFO_ACTIVE_CU_COUNT: |
| 540 | if (rdev->family >= CHIP_BONAIRE) |
| 541 | *value = rdev->config.cik.active_cus; |
| 542 | else if (rdev->family >= CHIP_TAHITI) |
| 543 | *value = rdev->config.si.active_cus; |
| 544 | else if (rdev->family >= CHIP_CAYMAN) |
| 545 | *value = rdev->config.cayman.active_simds; |
| 546 | else if (rdev->family >= CHIP_CEDAR) |
| 547 | *value = rdev->config.evergreen.active_simds; |
| 548 | else if (rdev->family >= CHIP_RV770) |
| 549 | *value = rdev->config.rv770.active_simds; |
| 550 | else if (rdev->family >= CHIP_R600) |
| 551 | *value = rdev->config.r600.active_simds; |
| 552 | else |
| 553 | *value = 1; |
| 554 | break; |
Alex Deucher | d6d2a18 | 2014-09-30 10:04:40 -0400 | [diff] [blame] | 555 | case RADEON_INFO_CURRENT_GPU_TEMP: |
| 556 | /* get temperature in millidegrees C */ |
| 557 | if (rdev->asic->pm.get_temperature) |
| 558 | *value = radeon_get_temperature(rdev); |
| 559 | else |
| 560 | *value = 0; |
| 561 | break; |
Alex Deucher | 5c363a8 | 2014-09-30 11:33:30 -0400 | [diff] [blame] | 562 | case RADEON_INFO_CURRENT_GPU_SCLK: |
| 563 | /* get sclk in Mhz */ |
| 564 | if (rdev->pm.dpm_enabled) |
| 565 | *value = radeon_dpm_get_current_sclk(rdev) / 100; |
| 566 | else |
| 567 | *value = rdev->pm.current_sclk / 100; |
| 568 | break; |
| 569 | case RADEON_INFO_CURRENT_GPU_MCLK: |
| 570 | /* get mclk in Mhz */ |
| 571 | if (rdev->pm.dpm_enabled) |
| 572 | *value = radeon_dpm_get_current_mclk(rdev) / 100; |
| 573 | else |
| 574 | *value = rdev->pm.current_mclk / 100; |
| 575 | break; |
Alex Deucher | 4535cb9 | 2014-10-01 11:26:50 -0400 | [diff] [blame] | 576 | case RADEON_INFO_READ_REG: |
| 577 | if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { |
| 578 | DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); |
| 579 | return -EFAULT; |
| 580 | } |
| 581 | if (radeon_get_allowed_info_register(rdev, *value, value)) |
| 582 | return -EINVAL; |
| 583 | break; |
Michel Dänzer | 3bc980b | 2015-06-16 17:28:16 +0900 | [diff] [blame] | 584 | case RADEON_INFO_VA_UNMAP_WORKING: |
| 585 | *value = true; |
| 586 | break; |
Marek Olšák | 72b9076 | 2015-04-29 19:40:33 +0200 | [diff] [blame] | 587 | case RADEON_INFO_GPU_RESET_COUNTER: |
| 588 | *value = atomic_read(&rdev->gpu_reset_counter); |
| 589 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 590 | default: |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 591 | DRM_DEBUG_KMS("Invalid request %d\n", info->request); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 592 | return -EINVAL; |
| 593 | } |
Daniel Vetter | 1d6ac18 | 2013-12-11 11:34:44 +0100 | [diff] [blame] | 594 | if (copy_to_user(value_ptr, (char*)value, value_size)) { |
Marek Olšák | 6759a0a | 2012-08-09 16:34:17 +0200 | [diff] [blame] | 595 | DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 596 | return -EFAULT; |
| 597 | } |
| 598 | return 0; |
| 599 | } |
| 600 | |
| 601 | |
| 602 | /* |
| 603 | * Outdated mess for old drm with Xorg being in charge (void function now). |
| 604 | */ |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 605 | /** |
Alex Deucher | 8c70e1c | 2015-10-02 16:52:58 -0400 | [diff] [blame] | 606 | * radeon_driver_lastclose_kms - drm callback for last close |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 607 | * |
| 608 | * @dev: drm dev pointer |
| 609 | * |
Lukas Wunner | 8e5de1d | 2015-09-05 11:14:43 +0200 | [diff] [blame] | 610 | * Switch vga_switcheroo state after last close (all asics). |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 611 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 612 | void radeon_driver_lastclose_kms(struct drm_device *dev) |
| 613 | { |
Alex Deucher | 8c70e1c | 2015-10-02 16:52:58 -0400 | [diff] [blame] | 614 | struct radeon_device *rdev = dev->dev_private; |
| 615 | |
| 616 | radeon_fbdev_restore_mode(rdev); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 617 | vga_switcheroo_process_delayed_switch(); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 618 | } |
| 619 | |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 620 | /** |
| 621 | * radeon_driver_open_kms - drm callback for open |
| 622 | * |
| 623 | * @dev: drm dev pointer |
| 624 | * @file_priv: drm file |
| 625 | * |
| 626 | * On device open, init vm on cayman+ (all asics). |
| 627 | * Returns 0 on success, error on failure. |
| 628 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 629 | int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) |
| 630 | { |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 631 | struct radeon_device *rdev = dev->dev_private; |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 632 | int r; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 633 | |
| 634 | file_priv->driver_priv = NULL; |
| 635 | |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 636 | r = pm_runtime_get_sync(dev->dev); |
| 637 | if (r < 0) |
| 638 | return r; |
| 639 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 640 | /* new gpu have virtual address space support */ |
| 641 | if (rdev->family >= CHIP_CAYMAN) { |
| 642 | struct radeon_fpriv *fpriv; |
Christian König | cc9e67e | 2014-07-18 13:48:10 +0200 | [diff] [blame] | 643 | struct radeon_vm *vm; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 644 | |
| 645 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); |
| 646 | if (unlikely(!fpriv)) { |
Alex Deucher | 32c59dc | 2016-08-31 17:27:03 -0400 | [diff] [blame] | 647 | r = -ENOMEM; |
| 648 | goto out_suspend; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 649 | } |
| 650 | |
Jérôme Glisse | 24f47ac | 2014-05-07 16:35:24 -0400 | [diff] [blame] | 651 | if (rdev->accel_working) { |
Alex Deucher | 544143f | 2015-01-28 14:36:26 -0500 | [diff] [blame] | 652 | vm = &fpriv->vm; |
| 653 | r = radeon_vm_init(rdev, vm); |
| 654 | if (r) { |
| 655 | kfree(fpriv); |
Alex Deucher | 32c59dc | 2016-08-31 17:27:03 -0400 | [diff] [blame] | 656 | goto out_suspend; |
Alex Deucher | 544143f | 2015-01-28 14:36:26 -0500 | [diff] [blame] | 657 | } |
| 658 | |
Jérôme Glisse | 24f47ac | 2014-05-07 16:35:24 -0400 | [diff] [blame] | 659 | r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); |
| 660 | if (r) { |
Christian König | cc9e67e | 2014-07-18 13:48:10 +0200 | [diff] [blame] | 661 | radeon_vm_fini(rdev, vm); |
Jérôme Glisse | 24f47ac | 2014-05-07 16:35:24 -0400 | [diff] [blame] | 662 | kfree(fpriv); |
Alex Deucher | 32c59dc | 2016-08-31 17:27:03 -0400 | [diff] [blame] | 663 | goto out_suspend; |
Jérôme Glisse | 24f47ac | 2014-05-07 16:35:24 -0400 | [diff] [blame] | 664 | } |
| 665 | |
| 666 | /* map the ib pool buffer read only into |
| 667 | * virtual address space */ |
Christian König | cc9e67e | 2014-07-18 13:48:10 +0200 | [diff] [blame] | 668 | vm->ib_bo_va = radeon_vm_bo_add(rdev, vm, |
| 669 | rdev->ring_tmp_bo.bo); |
| 670 | r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va, |
| 671 | RADEON_VA_IB_OFFSET, |
Jérôme Glisse | 24f47ac | 2014-05-07 16:35:24 -0400 | [diff] [blame] | 672 | RADEON_VM_PAGE_READABLE | |
| 673 | RADEON_VM_PAGE_SNOOPED); |
Jérôme Glisse | 24f47ac | 2014-05-07 16:35:24 -0400 | [diff] [blame] | 674 | if (r) { |
Christian König | cc9e67e | 2014-07-18 13:48:10 +0200 | [diff] [blame] | 675 | radeon_vm_fini(rdev, vm); |
Jérôme Glisse | 24f47ac | 2014-05-07 16:35:24 -0400 | [diff] [blame] | 676 | kfree(fpriv); |
Alex Deucher | 32c59dc | 2016-08-31 17:27:03 -0400 | [diff] [blame] | 677 | goto out_suspend; |
Jérôme Glisse | 24f47ac | 2014-05-07 16:35:24 -0400 | [diff] [blame] | 678 | } |
Quentin Casasnovas | 74073c9 | 2014-03-18 17:16:52 +0100 | [diff] [blame] | 679 | } |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 680 | file_priv->driver_priv = fpriv; |
| 681 | } |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 682 | |
Alex Deucher | 32c59dc | 2016-08-31 17:27:03 -0400 | [diff] [blame] | 683 | out_suspend: |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 684 | pm_runtime_mark_last_busy(dev->dev); |
| 685 | pm_runtime_put_autosuspend(dev->dev); |
Alex Deucher | 32c59dc | 2016-08-31 17:27:03 -0400 | [diff] [blame] | 686 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 687 | } |
| 688 | |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 689 | /** |
| 690 | * radeon_driver_postclose_kms - drm callback for post close |
| 691 | * |
| 692 | * @dev: drm dev pointer |
| 693 | * @file_priv: drm file |
| 694 | * |
| 695 | * On device post close, tear down vm on cayman+ (all asics). |
| 696 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 697 | void radeon_driver_postclose_kms(struct drm_device *dev, |
| 698 | struct drm_file *file_priv) |
| 699 | { |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 700 | struct radeon_device *rdev = dev->dev_private; |
| 701 | |
| 702 | /* new gpu have virtual address space support */ |
| 703 | if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { |
| 704 | struct radeon_fpriv *fpriv = file_priv->driver_priv; |
Christian König | cc9e67e | 2014-07-18 13:48:10 +0200 | [diff] [blame] | 705 | struct radeon_vm *vm = &fpriv->vm; |
Christian König | d72d43c | 2012-10-09 13:31:18 +0200 | [diff] [blame] | 706 | int r; |
| 707 | |
Jérôme Glisse | 24f47ac | 2014-05-07 16:35:24 -0400 | [diff] [blame] | 708 | if (rdev->accel_working) { |
| 709 | r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); |
| 710 | if (!r) { |
Christian König | cc9e67e | 2014-07-18 13:48:10 +0200 | [diff] [blame] | 711 | if (vm->ib_bo_va) |
| 712 | radeon_vm_bo_rmv(rdev, vm->ib_bo_va); |
Jérôme Glisse | 24f47ac | 2014-05-07 16:35:24 -0400 | [diff] [blame] | 713 | radeon_bo_unreserve(rdev->ring_tmp_bo.bo); |
| 714 | } |
Alex Deucher | 544143f | 2015-01-28 14:36:26 -0500 | [diff] [blame] | 715 | radeon_vm_fini(rdev, vm); |
Christian König | d72d43c | 2012-10-09 13:31:18 +0200 | [diff] [blame] | 716 | } |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 717 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 718 | kfree(fpriv); |
| 719 | file_priv->driver_priv = NULL; |
| 720 | } |
Alex Deucher | 9b96b63 | 2016-08-31 17:23:31 -0400 | [diff] [blame] | 721 | pm_runtime_mark_last_busy(dev->dev); |
| 722 | pm_runtime_put_autosuspend(dev->dev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 723 | } |
| 724 | |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 725 | /** |
| 726 | * radeon_driver_preclose_kms - drm callback for pre close |
| 727 | * |
| 728 | * @dev: drm dev pointer |
| 729 | * @file_priv: drm file |
| 730 | * |
| 731 | * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx |
| 732 | * (all asics). |
| 733 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 734 | void radeon_driver_preclose_kms(struct drm_device *dev, |
| 735 | struct drm_file *file_priv) |
| 736 | { |
Dave Airlie | ab9e1f5 | 2010-07-13 11:11:11 +1000 | [diff] [blame] | 737 | struct radeon_device *rdev = dev->dev_private; |
Daniel Vetter | 45c1da5 | 2015-10-15 09:36:34 +0200 | [diff] [blame] | 738 | |
Alex Deucher | 9b96b63 | 2016-08-31 17:23:31 -0400 | [diff] [blame] | 739 | pm_runtime_get_sync(dev->dev); |
| 740 | |
Daniel Vetter | 45c1da5 | 2015-10-15 09:36:34 +0200 | [diff] [blame] | 741 | mutex_lock(&rdev->gem.mutex); |
Dave Airlie | ab9e1f5 | 2010-07-13 11:11:11 +1000 | [diff] [blame] | 742 | if (rdev->hyperz_filp == file_priv) |
| 743 | rdev->hyperz_filp = NULL; |
Marek Olšák | dca0d61 | 2011-01-27 22:46:15 +0100 | [diff] [blame] | 744 | if (rdev->cmask_filp == file_priv) |
| 745 | rdev->cmask_filp = NULL; |
Daniel Vetter | 45c1da5 | 2015-10-15 09:36:34 +0200 | [diff] [blame] | 746 | mutex_unlock(&rdev->gem.mutex); |
| 747 | |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 748 | radeon_uvd_free_handles(rdev, file_priv); |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 749 | radeon_vce_free_handles(rdev, file_priv); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 750 | } |
| 751 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 752 | /* |
| 753 | * VBlank related functions. |
| 754 | */ |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 755 | /** |
| 756 | * radeon_get_vblank_counter_kms - get frame count |
| 757 | * |
| 758 | * @dev: drm dev pointer |
Thierry Reding | 4e926d2 | 2015-12-16 15:31:47 +0100 | [diff] [blame] | 759 | * @pipe: crtc to get the frame count from |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 760 | * |
| 761 | * Gets the frame count on the requested crtc (all asics). |
| 762 | * Returns frame count on success, -EINVAL on failure. |
| 763 | */ |
Thierry Reding | 4e926d2 | 2015-12-16 15:31:47 +0100 | [diff] [blame] | 764 | u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 765 | { |
Mario Kleiner | c55d21e | 2015-11-25 20:14:31 +0100 | [diff] [blame] | 766 | int vpos, hpos, stat; |
| 767 | u32 count; |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 768 | struct radeon_device *rdev = dev->dev_private; |
| 769 | |
Thierry Reding | 85a21ea | 2016-01-04 18:19:12 +0100 | [diff] [blame] | 770 | if (pipe >= rdev->num_crtc) { |
Thierry Reding | 4e926d2 | 2015-12-16 15:31:47 +0100 | [diff] [blame] | 771 | DRM_ERROR("Invalid crtc %u\n", pipe); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 772 | return -EINVAL; |
| 773 | } |
| 774 | |
Mario Kleiner | c55d21e | 2015-11-25 20:14:31 +0100 | [diff] [blame] | 775 | /* The hw increments its frame counter at start of vsync, not at start |
| 776 | * of vblank, as is required by DRM core vblank counter handling. |
| 777 | * Cook the hw count here to make it appear to the caller as if it |
| 778 | * incremented at start of vblank. We measure distance to start of |
| 779 | * vblank in vpos. vpos therefore will be >= 0 between start of vblank |
| 780 | * and start of vsync, so vpos >= 0 means to bump the hw frame counter |
| 781 | * result by 1 to give the proper appearance to caller. |
| 782 | */ |
Thierry Reding | 4e926d2 | 2015-12-16 15:31:47 +0100 | [diff] [blame] | 783 | if (rdev->mode_info.crtcs[pipe]) { |
Mario Kleiner | c55d21e | 2015-11-25 20:14:31 +0100 | [diff] [blame] | 784 | /* Repeat readout if needed to provide stable result if |
| 785 | * we cross start of vsync during the queries. |
| 786 | */ |
| 787 | do { |
Thierry Reding | 4e926d2 | 2015-12-16 15:31:47 +0100 | [diff] [blame] | 788 | count = radeon_get_vblank_counter(rdev, pipe); |
Mario Kleiner | c55d21e | 2015-11-25 20:14:31 +0100 | [diff] [blame] | 789 | /* Ask radeon_get_crtc_scanoutpos to return vpos as |
| 790 | * distance to start of vblank, instead of regular |
| 791 | * vertical scanout pos. |
| 792 | */ |
| 793 | stat = radeon_get_crtc_scanoutpos( |
Thierry Reding | 4e926d2 | 2015-12-16 15:31:47 +0100 | [diff] [blame] | 794 | dev, pipe, GET_DISTANCE_TO_VBLANKSTART, |
Mario Kleiner | c55d21e | 2015-11-25 20:14:31 +0100 | [diff] [blame] | 795 | &vpos, &hpos, NULL, NULL, |
Thierry Reding | 4e926d2 | 2015-12-16 15:31:47 +0100 | [diff] [blame] | 796 | &rdev->mode_info.crtcs[pipe]->base.hwmode); |
| 797 | } while (count != radeon_get_vblank_counter(rdev, pipe)); |
Mario Kleiner | c55d21e | 2015-11-25 20:14:31 +0100 | [diff] [blame] | 798 | |
| 799 | if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != |
| 800 | (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { |
| 801 | DRM_DEBUG_VBL("Query failed! stat %d\n", stat); |
| 802 | } |
| 803 | else { |
Thierry Reding | 4e926d2 | 2015-12-16 15:31:47 +0100 | [diff] [blame] | 804 | DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n", |
| 805 | pipe, vpos); |
Mario Kleiner | c55d21e | 2015-11-25 20:14:31 +0100 | [diff] [blame] | 806 | |
| 807 | /* Bump counter if we are at >= leading edge of vblank, |
| 808 | * but before vsync where vpos would turn negative and |
| 809 | * the hw counter really increments. |
| 810 | */ |
| 811 | if (vpos >= 0) |
| 812 | count++; |
| 813 | } |
| 814 | } |
| 815 | else { |
| 816 | /* Fallback to use value as is. */ |
Thierry Reding | 4e926d2 | 2015-12-16 15:31:47 +0100 | [diff] [blame] | 817 | count = radeon_get_vblank_counter(rdev, pipe); |
Mario Kleiner | c55d21e | 2015-11-25 20:14:31 +0100 | [diff] [blame] | 818 | DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); |
| 819 | } |
| 820 | |
| 821 | return count; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 822 | } |
| 823 | |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 824 | /** |
| 825 | * radeon_enable_vblank_kms - enable vblank interrupt |
| 826 | * |
| 827 | * @dev: drm dev pointer |
| 828 | * @crtc: crtc to enable vblank interrupt for |
| 829 | * |
| 830 | * Enable the interrupt on the requested crtc (all asics). |
| 831 | * Returns 0 on success, -EINVAL on failure. |
| 832 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 833 | int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) |
| 834 | { |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 835 | struct radeon_device *rdev = dev->dev_private; |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 836 | unsigned long irqflags; |
| 837 | int r; |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 838 | |
Dave Airlie | 9c950a4 | 2010-04-23 13:21:58 +1000 | [diff] [blame] | 839 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 840 | DRM_ERROR("Invalid crtc %d\n", crtc); |
| 841 | return -EINVAL; |
| 842 | } |
| 843 | |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 844 | spin_lock_irqsave(&rdev->irq.lock, irqflags); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 845 | rdev->irq.crtc_vblank_int[crtc] = true; |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 846 | r = radeon_irq_set(rdev); |
| 847 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); |
| 848 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 849 | } |
| 850 | |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 851 | /** |
| 852 | * radeon_disable_vblank_kms - disable vblank interrupt |
| 853 | * |
| 854 | * @dev: drm dev pointer |
| 855 | * @crtc: crtc to disable vblank interrupt for |
| 856 | * |
| 857 | * Disable the interrupt on the requested crtc (all asics). |
| 858 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 859 | void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) |
| 860 | { |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 861 | struct radeon_device *rdev = dev->dev_private; |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 862 | unsigned long irqflags; |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 863 | |
Dave Airlie | 9c950a4 | 2010-04-23 13:21:58 +1000 | [diff] [blame] | 864 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 865 | DRM_ERROR("Invalid crtc %d\n", crtc); |
| 866 | return; |
| 867 | } |
| 868 | |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 869 | spin_lock_irqsave(&rdev->irq.lock, irqflags); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 870 | rdev->irq.crtc_vblank_int[crtc] = false; |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 871 | radeon_irq_set(rdev); |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 872 | spin_unlock_irqrestore(&rdev->irq.lock, irqflags); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 873 | } |
| 874 | |
Alex Deucher | f482a14 | 2012-07-17 14:02:34 -0400 | [diff] [blame] | 875 | /** |
| 876 | * radeon_get_vblank_timestamp_kms - get vblank timestamp |
| 877 | * |
| 878 | * @dev: drm dev pointer |
| 879 | * @crtc: crtc to get the timestamp for |
| 880 | * @max_error: max error |
| 881 | * @vblank_time: time value |
| 882 | * @flags: flags passed to the driver |
| 883 | * |
| 884 | * Gets the timestamp on the requested crtc based on the |
| 885 | * scanout position. (all asics). |
| 886 | * Returns postive status flags on success, negative error on failure. |
| 887 | */ |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 888 | int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, |
| 889 | int *max_error, |
| 890 | struct timeval *vblank_time, |
| 891 | unsigned flags) |
| 892 | { |
| 893 | struct drm_crtc *drmcrtc; |
| 894 | struct radeon_device *rdev = dev->dev_private; |
| 895 | |
| 896 | if (crtc < 0 || crtc >= dev->num_crtcs) { |
| 897 | DRM_ERROR("Invalid crtc %d\n", crtc); |
| 898 | return -EINVAL; |
| 899 | } |
| 900 | |
| 901 | /* Get associated drm_crtc: */ |
| 902 | drmcrtc = &rdev->mode_info.crtcs[crtc]->base; |
Petr Mladek | f5475cc | 2014-11-27 16:57:21 +0100 | [diff] [blame] | 903 | if (!drmcrtc) |
| 904 | return -EINVAL; |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 905 | |
| 906 | /* Helper routine in DRM core does all the work: */ |
| 907 | return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, |
| 908 | vblank_time, flags, |
Ville Syrjälä | eba1f35 | 2015-09-14 22:43:43 +0300 | [diff] [blame] | 909 | &drmcrtc->hwmode); |
Mario Kleiner | f5a8020 | 2010-10-23 04:42:17 +0200 | [diff] [blame] | 910 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 911 | |
Rob Clark | baa7094 | 2013-08-02 13:27:49 -0400 | [diff] [blame] | 912 | const struct drm_ioctl_desc radeon_ioctls_kms[] = { |
Daniel Vetter | 4b63539 | 2015-09-08 13:56:26 +0200 | [diff] [blame] | 913 | DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 914 | DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 915 | DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 916 | DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 917 | DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH), |
| 918 | DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH), |
| 919 | DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH), |
| 920 | DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH), |
| 921 | DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH), |
| 922 | DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH), |
| 923 | DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH), |
| 924 | DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH), |
| 925 | DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH), |
| 926 | DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH), |
| 927 | DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 928 | DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH), |
| 929 | DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH), |
| 930 | DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH), |
| 931 | DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH), |
| 932 | DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH), |
| 933 | DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH), |
| 934 | DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 935 | DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH), |
| 936 | DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH), |
| 937 | DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH), |
| 938 | DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH), |
| 939 | DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH), |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 940 | /* KMS */ |
Daniel Vetter | f8c4714 | 2015-09-08 13:56:30 +0200 | [diff] [blame] | 941 | DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
| 942 | DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
| 943 | DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
| 944 | DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
| 945 | DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH), |
| 946 | DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH), |
| 947 | DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
| 948 | DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
| 949 | DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
| 950 | DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
| 951 | DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
| 952 | DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
| 953 | DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
| 954 | DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
| 955 | DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 956 | }; |
Damien Lespiau | f95aeb1 | 2014-06-09 14:39:49 +0100 | [diff] [blame] | 957 | int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms); |