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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * sata_sis.c - Silicon Integrated Systems SATA
3 *
4 * Maintained by: Uwe Koziolek
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004 Uwe Koziolek
9 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware documentation available under NDA.
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 *
31 */
32
Linus Torvalds1da177e2005-04-16 15:20:36 -070033#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/pci.h>
36#include <linux/init.h>
37#include <linux/blkdev.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050040#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070041#include <scsi/scsi_host.h>
42#include <linux/libata.h>
Alan4bb64fb2007-02-16 01:40:04 -080043#include "sis.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070044
45#define DRV_NAME "sata_sis"
Jeff Garzik2a3103c2007-08-31 04:54:06 -040046#define DRV_VERSION "1.0"
Linus Torvalds1da177e2005-04-16 15:20:36 -070047
48enum {
49 sis_180 = 0,
50 SIS_SCR_PCI_BAR = 5,
51
52 /* PCI configuration registers */
53 SIS_GENCTL = 0x54, /* IDE General Control register */
54 SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
Arnaud Patardf2c853b2005-09-07 22:44:48 +020055 SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
56 SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
57 SIS_PMR = 0x90, /* port mapping register */
Jeff Garzik8add7882005-09-08 23:07:29 -040058 SIS_PMR_COMBINED = 0x30,
Linus Torvalds1da177e2005-04-16 15:20:36 -070059
60 /* random bits */
61 SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
62
63 GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
64};
65
Jeff Garzik5796d1c2007-10-26 00:03:37 -040066static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heo82ef04f2008-07-31 17:02:40 +090067static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
68static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
Linus Torvalds1da177e2005-04-16 15:20:36 -070069
Jeff Garzik3b7d6972005-11-10 11:04:11 -050070static const struct pci_device_id sis_pci_tbl[] = {
Jeff Garzik5796d1c2007-10-26 00:03:37 -040071 { PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
72 { PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */
73 { PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */
74 { PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */
75 { PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/680 */
76 { PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L/968/680 */
Jeff Garzik2d2744f2006-09-28 20:21:59 -040077
Linus Torvalds1da177e2005-04-16 15:20:36 -070078 { } /* terminate list */
79};
80
Linus Torvalds1da177e2005-04-16 15:20:36 -070081static struct pci_driver sis_pci_driver = {
82 .name = DRV_NAME,
83 .id_table = sis_pci_tbl,
84 .probe = sis_init_one,
85 .remove = ata_pci_remove_one,
86};
87
Jeff Garzik193515d2005-11-07 00:59:37 -050088static struct scsi_host_template sis_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +090089 ATA_BMDMA_SHT(DRV_NAME),
Linus Torvalds1da177e2005-04-16 15:20:36 -070090};
91
Tejun Heo029cfd62008-03-25 12:22:49 +090092static struct ata_port_operations sis_ops = {
93 .inherits = &ata_bmdma_port_ops,
Linus Torvalds1da177e2005-04-16 15:20:36 -070094 .scr_read = sis_scr_read,
95 .scr_write = sis_scr_write,
Linus Torvalds1da177e2005-04-16 15:20:36 -070096};
97
Tejun Heo1626aeb2007-05-04 12:43:58 +020098static const struct ata_port_info sis_port_info = {
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +030099 .flags = ATA_FLAG_SATA,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100100 .pio_mask = ATA_PIO4,
101 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400102 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700103 .port_ops = &sis_ops,
104};
105
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106MODULE_AUTHOR("Uwe Koziolek");
Chris Dunlop142924c2011-10-24 10:38:18 +1100107MODULE_DESCRIPTION("low-level driver for Silicon Integrated Systems SATA controller");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700108MODULE_LICENSE("GPL");
109MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
110MODULE_VERSION(DRV_VERSION);
111
Tejun Heo72fee382009-09-01 23:19:10 +0900112static unsigned int get_scr_cfg_addr(struct ata_link *link, unsigned int sc_reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113{
Tejun Heo72fee382009-09-01 23:19:10 +0900114 struct ata_port *ap = link->ap;
Alan9b14dec2007-01-08 16:11:07 +0000115 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116 unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
Alan9b14dec2007-01-08 16:11:07 +0000117 u8 pmr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118
Alan9b14dec2007-01-08 16:11:07 +0000119 if (ap->port_no) {
Uwe Koziolek3f3e7312006-12-04 01:34:42 +0100120 switch (pdev->device) {
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400121 case 0x0180:
122 case 0x0181:
123 pci_read_config_byte(pdev, SIS_PMR, &pmr);
124 if ((pmr & SIS_PMR_COMBINED) == 0)
125 addr += SIS180_SATA1_OFS;
126 break;
Jeff Garzik8add7882005-09-08 23:07:29 -0400127
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400128 case 0x0182:
129 case 0x0183:
130 case 0x1182:
131 addr += SIS182_SATA1_OFS;
132 break;
Uwe Koziolek3f3e7312006-12-04 01:34:42 +0100133 }
134 }
Tejun Heo72fee382009-09-01 23:19:10 +0900135 if (link->pmp)
136 addr += 0x10;
137
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138 return addr;
139}
140
Tejun Heo82ef04f2008-07-31 17:02:40 +0900141static u32 sis_scr_cfg_read(struct ata_link *link,
142 unsigned int sc_reg, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900144 struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
Tejun Heo72fee382009-09-01 23:19:10 +0900145 unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146
147 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
Tejun Heo8e5443a2008-04-24 10:52:44 +0900148 return -EINVAL;
Arnaud Patardf2c853b2005-09-07 22:44:48 +0200149
Tejun Heoaaa092a2007-10-18 11:53:39 +0900150 pci_read_config_dword(pdev, cfg_addr, val);
Tejun Heoaaa092a2007-10-18 11:53:39 +0900151 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152}
153
Tejun Heo82ef04f2008-07-31 17:02:40 +0900154static int sis_scr_cfg_write(struct ata_link *link,
155 unsigned int sc_reg, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700156{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900157 struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
Tejun Heo72fee382009-09-01 23:19:10 +0900158 unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg);
Jeff Garzik8add7882005-09-08 23:07:29 -0400159
Linus Torvalds1da177e2005-04-16 15:20:36 -0700160 pci_write_config_dword(pdev, cfg_addr, val);
Tejun Heo8e5443a2008-04-24 10:52:44 +0900161 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700162}
163
Tejun Heo82ef04f2008-07-31 17:02:40 +0900164static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900166 struct ata_port *ap = link->ap;
Tejun Heo72fee382009-09-01 23:19:10 +0900167 void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10;
Arnaud Patardf2c853b2005-09-07 22:44:48 +0200168
Linus Torvalds1da177e2005-04-16 15:20:36 -0700169 if (sc_reg > SCR_CONTROL)
Tejun Heoda3dbb12007-07-16 14:29:40 +0900170 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171
172 if (ap->flags & SIS_FLAG_CFGSCR)
Tejun Heo82ef04f2008-07-31 17:02:40 +0900173 return sis_scr_cfg_read(link, sc_reg, val);
Arnaud Patardf2c853b2005-09-07 22:44:48 +0200174
Tejun Heo72fee382009-09-01 23:19:10 +0900175 *val = ioread32(base + sc_reg * 4);
Tejun Heoda3dbb12007-07-16 14:29:40 +0900176 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177}
178
Tejun Heo82ef04f2008-07-31 17:02:40 +0900179static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900181 struct ata_port *ap = link->ap;
Tejun Heo72fee382009-09-01 23:19:10 +0900182 void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10;
Arnaud Patardf2c853b2005-09-07 22:44:48 +0200183
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184 if (sc_reg > SCR_CONTROL)
Tejun Heoda3dbb12007-07-16 14:29:40 +0900185 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186
187 if (ap->flags & SIS_FLAG_CFGSCR)
Tejun Heo82ef04f2008-07-31 17:02:40 +0900188 return sis_scr_cfg_write(link, sc_reg, val);
Tejun Heo72fee382009-09-01 23:19:10 +0900189
190 iowrite32(val, base + (sc_reg * 4));
191 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192}
193
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400194static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195{
Tejun Heo9a829cc2007-04-17 23:44:08 +0900196 struct ata_port_info pi = sis_port_info;
Uwe Koziolekddfc87a2007-05-25 09:48:52 +0200197 const struct ata_port_info *ppi[] = { &pi, &pi };
Tejun Heo9a829cc2007-04-17 23:44:08 +0900198 struct ata_host *host;
Uwe Koziolek4adccf62006-11-08 09:57:00 +0100199 u32 genctl, val;
Arnaud Patardf2c853b2005-09-07 22:44:48 +0200200 u8 pmr;
Uwe Koziolek3f3e7312006-12-04 01:34:42 +0100201 u8 port2_start = 0x20;
Tejun Heo72fee382009-09-01 23:19:10 +0900202 int i, rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203
Joe Perches06296a12011-04-15 15:52:00 -0700204 ata_print_version_once(&pdev->dev, DRV_VERSION);
Jeff Garzika9524a72005-10-30 14:39:11 -0500205
Tejun Heo24dc5f32007-01-20 16:00:28 +0900206 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700207 if (rc)
208 return rc;
209
Linus Torvalds1da177e2005-04-16 15:20:36 -0700210 /* check and see if the SCRs are in IO space or PCI cfg space */
211 pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
212 if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
Tejun Heocf0e8122006-10-27 19:08:47 -0700213 pi.flags |= SIS_FLAG_CFGSCR;
Jeff Garzik8a60a072005-07-31 13:13:24 -0400214
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215 /* if hardware thinks SCRs are in IO space, but there are
216 * no IO resources assigned, change to PCI cfg space.
217 */
Tejun Heocf0e8122006-10-27 19:08:47 -0700218 if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219 ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
220 (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
221 genctl &= ~GENCTL_IOMAPPED_SCR;
222 pci_write_config_dword(pdev, SIS_GENCTL, genctl);
Tejun Heocf0e8122006-10-27 19:08:47 -0700223 pi.flags |= SIS_FLAG_CFGSCR;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224 }
225
Arnaud Patardf2c853b2005-09-07 22:44:48 +0200226 pci_read_config_byte(pdev, SIS_PMR, &pmr);
Uwe Koziolek3f3e7312006-12-04 01:34:42 +0100227 switch (ent->device) {
228 case 0x0180:
229 case 0x0181:
Alan9b14dec2007-01-08 16:11:07 +0000230
231 /* The PATA-handling is provided by pata_sis */
232 switch (pmr & 0x30) {
233 case 0x10:
Uwe Kozioleka3cabb22007-06-14 23:40:43 +0200234 ppi[1] = &sis_info133_for_sata;
Alan9b14dec2007-01-08 16:11:07 +0000235 break;
Jeff Garzika84471f2007-02-26 05:51:33 -0500236
Alan9b14dec2007-01-08 16:11:07 +0000237 case 0x30:
Uwe Kozioleka3cabb22007-06-14 23:40:43 +0200238 ppi[0] = &sis_info133_for_sata;
Alan9b14dec2007-01-08 16:11:07 +0000239 break;
240 }
Arnaud Patardf2c853b2005-09-07 22:44:48 +0200241 if ((pmr & SIS_PMR_COMBINED) == 0) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700242 dev_info(&pdev->dev,
243 "Detected SiS 180/181/964 chipset in SATA mode\n");
Arnaud Patard39eb9362005-09-13 00:36:45 +0200244 port2_start = 64;
Uwe Koziolek3f3e7312006-12-04 01:34:42 +0100245 } else {
Joe Perchesa44fec12011-04-15 15:51:58 -0700246 dev_info(&pdev->dev,
247 "Detected SiS 180/181 chipset in combined mode\n");
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400248 port2_start = 0;
Uwe Koziolek4adccf62006-11-08 09:57:00 +0100249 pi.flags |= ATA_FLAG_SLAVE_POSS;
Arnaud Patardf2c853b2005-09-07 22:44:48 +0200250 }
Uwe Koziolek3f3e7312006-12-04 01:34:42 +0100251 break;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500252
Uwe Koziolek3f3e7312006-12-04 01:34:42 +0100253 case 0x0182:
254 case 0x0183:
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400255 pci_read_config_dword(pdev, 0x6C, &val);
Uwe Koziolek4adccf62006-11-08 09:57:00 +0100256 if (val & (1L << 31)) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700257 dev_info(&pdev->dev, "Detected SiS 182/965 chipset\n");
Uwe Koziolek4adccf62006-11-08 09:57:00 +0100258 pi.flags |= ATA_FLAG_SLAVE_POSS;
Uwe Koziolek3f3e7312006-12-04 01:34:42 +0100259 } else {
Joe Perchesa44fec12011-04-15 15:51:58 -0700260 dev_info(&pdev->dev, "Detected SiS 182/965L chipset\n");
Uwe Koziolek3f3e7312006-12-04 01:34:42 +0100261 }
262 break;
263
264 case 0x1182:
Joe Perchesa44fec12011-04-15 15:51:58 -0700265 dev_info(&pdev->dev,
266 "Detected SiS 1182/966/680 SATA controller\n");
Uwe Kozioleka3cabb22007-06-14 23:40:43 +0200267 pi.flags |= ATA_FLAG_SLAVE_POSS;
268 break;
269
Uwe Koziolek3f3e7312006-12-04 01:34:42 +0100270 case 0x1183:
Joe Perchesa44fec12011-04-15 15:51:58 -0700271 dev_info(&pdev->dev,
272 "Detected SiS 1183/966/966L/968/680 controller in PATA mode\n");
Uwe Kozioleka3cabb22007-06-14 23:40:43 +0200273 ppi[0] = &sis_info133_for_sata;
274 ppi[1] = &sis_info133_for_sata;
Uwe Koziolek3f3e7312006-12-04 01:34:42 +0100275 break;
Arnaud Patardf2c853b2005-09-07 22:44:48 +0200276 }
277
Tejun Heo1c5afdf2010-05-19 22:10:22 +0200278 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
Tejun Heo9a829cc2007-04-17 23:44:08 +0900279 if (rc)
280 return rc;
Tejun Heocf0e8122006-10-27 19:08:47 -0700281
Tejun Heo72fee382009-09-01 23:19:10 +0900282 for (i = 0; i < 2; i++) {
283 struct ata_port *ap = host->ports[i];
284
285 if (ap->flags & ATA_FLAG_SATA &&
286 ap->flags & ATA_FLAG_SLAVE_POSS) {
287 rc = ata_slave_link_init(ap);
288 if (rc)
289 return rc;
290 }
291 }
292
Tejun Heo9a829cc2007-04-17 23:44:08 +0900293 if (!(pi.flags & SIS_FLAG_CFGSCR)) {
Al Viroedceec32007-03-14 09:19:00 +0000294 void __iomem *mmio;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900295
Tejun Heo9a829cc2007-04-17 23:44:08 +0900296 rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
297 if (rc)
298 return rc;
299 mmio = host->iomap[SIS_SCR_PCI_BAR];
Tejun Heo0d5ff562007-02-01 15:06:36 +0900300
Tejun Heo9a829cc2007-04-17 23:44:08 +0900301 host->ports[0]->ioaddr.scr_addr = mmio;
302 host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303 }
304
305 pci_set_master(pdev);
Brett M Russa04ce0f2005-08-15 15:23:41 -0400306 pci_intx(pdev, 1);
Tejun Heoc3b28892010-05-19 22:10:21 +0200307 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
Tejun Heo9363c382008-04-07 22:47:16 +0900308 IRQF_SHARED, &sis_sht);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700309}
310
Axel Lin2fc75da2012-04-19 13:43:05 +0800311module_pci_driver(sis_pci_driver);