blob: 135a08f615cd066802f9888cfe860239e05c3984 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
Jesse Barnes585fb112008-07-29 11:54:06 -070033#include "i915_reg.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080034#include "intel_bios.h"
Keith Packard0839ccb2008-10-30 19:38:48 -070035#include <linux/io-mapping.h>
Jesse Barnes585fb112008-07-29 11:54:06 -070036
Linus Torvalds1da177e2005-04-16 15:20:36 -070037/* General customization:
38 */
39
40#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
41
42#define DRIVER_NAME "i915"
43#define DRIVER_DESC "Intel Graphics"
Eric Anholt673a3942008-07-30 12:06:12 -070044#define DRIVER_DATE "20080730"
Linus Torvalds1da177e2005-04-16 15:20:36 -070045
Jesse Barnes317c35d2008-08-25 15:11:06 -070046enum pipe {
47 PIPE_A = 0,
48 PIPE_B,
49};
50
Keith Packard52440212008-11-18 09:30:25 -080051#define I915_NUM_PIPE 2
52
Linus Torvalds1da177e2005-04-16 15:20:36 -070053/* Interface history:
54 *
55 * 1.1: Original.
Dave Airlie0d6aa602006-01-02 20:14:23 +110056 * 1.2: Add Power Management
57 * 1.3: Add vblank support
Dave Airliede227f52006-01-25 15:31:43 +110058 * 1.4: Fix cmdbuffer path, add heap destroy
Dave Airlie702880f2006-06-24 17:07:34 +100059 * 1.5: Add vblank pipe configuration
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +100060 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
61 * - Support vertical blank on secondary display pipe
Linus Torvalds1da177e2005-04-16 15:20:36 -070062 */
63#define DRIVER_MAJOR 1
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +100064#define DRIVER_MINOR 6
Linus Torvalds1da177e2005-04-16 15:20:36 -070065#define DRIVER_PATCHLEVEL 0
66
Eric Anholt673a3942008-07-30 12:06:12 -070067#define WATCH_COHERENCY 0
68#define WATCH_BUF 0
69#define WATCH_EXEC 0
70#define WATCH_LRU 0
71#define WATCH_RELOC 0
72#define WATCH_INACTIVE 0
73#define WATCH_PWRITE 0
74
Dave Airlie71acb5e2008-12-30 20:31:46 +100075#define I915_GEM_PHYS_CURSOR_0 1
76#define I915_GEM_PHYS_CURSOR_1 2
77#define I915_GEM_PHYS_OVERLAY_REGS 3
78#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
79
80struct drm_i915_gem_phys_object {
81 int id;
82 struct page **page_list;
83 drm_dma_handle_t *handle;
84 struct drm_gem_object *cur_obj;
85};
86
Linus Torvalds1da177e2005-04-16 15:20:36 -070087typedef struct _drm_i915_ring_buffer {
88 int tail_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -070089 unsigned long Size;
90 u8 *virtual_start;
91 int head;
92 int tail;
93 int space;
94 drm_local_map_t map;
Eric Anholt673a3942008-07-30 12:06:12 -070095 struct drm_gem_object *ring_obj;
Linus Torvalds1da177e2005-04-16 15:20:36 -070096} drm_i915_ring_buffer_t;
97
98struct mem_block {
99 struct mem_block *next;
100 struct mem_block *prev;
101 int start;
102 int size;
Eric Anholt6c340ea2007-08-25 20:23:09 +1000103 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104};
105
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700106struct opregion_header;
107struct opregion_acpi;
108struct opregion_swsci;
109struct opregion_asle;
110
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100111struct intel_opregion {
112 struct opregion_header *header;
113 struct opregion_acpi *acpi;
114 struct opregion_swsci *swsci;
115 struct opregion_asle *asle;
116 int enabled;
117};
118
Dave Airlie7c1c2872008-11-28 14:22:24 +1000119struct drm_i915_master_private {
120 drm_local_map_t *sarea;
121 struct _drm_i915_sarea *sarea_priv;
122};
Jesse Barnesde151cf2008-11-12 10:03:55 -0800123#define I915_FENCE_REG_NONE -1
124
125struct drm_i915_fence_reg {
126 struct drm_gem_object *obj;
127};
Dave Airlie7c1c2872008-11-28 14:22:24 +1000128
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129typedef struct drm_i915_private {
Eric Anholt673a3942008-07-30 12:06:12 -0700130 struct drm_device *dev;
131
Dave Airlieac5c4e72008-12-19 15:38:34 +1000132 int has_gem;
133
Eric Anholt3043c602008-10-02 12:24:47 -0700134 void __iomem *regs;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136 drm_i915_ring_buffer_t ring;
137
Dave Airlie9c8da5e2005-07-10 15:38:56 +1000138 drm_dma_handle_t *status_page_dmah;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139 void *hw_status_page;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140 dma_addr_t dma_status_page;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700141 uint32_t counter;
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000142 unsigned int status_gfx_addr;
143 drm_local_map_t hws_map;
Eric Anholt673a3942008-07-30 12:06:12 -0700144 struct drm_gem_object *hws_obj;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000146 unsigned int cpp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147 int back_offset;
148 int front_offset;
149 int current_page;
150 int page_flipping;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151
152 wait_queue_head_t irq_queue;
153 atomic_t irq_received;
Eric Anholted4cb412008-07-29 12:10:39 -0700154 /** Protects user_irq_refcount and irq_mask_reg */
155 spinlock_t user_irq_lock;
156 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
157 int user_irq_refcount;
158 /** Cached value of IMR to avoid reads in updating the bitfield */
159 u32 irq_mask_reg;
Keith Packard7c463582008-11-04 02:03:27 -0800160 u32 pipestat[2];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161
162 int tex_lru_log_granularity;
163 int allow_batchbuffer;
164 struct mem_block *agp_heap;
Dave Airlie0d6aa602006-01-02 20:14:23 +1100165 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
Dave Airlie702880f2006-06-24 17:07:34 +1000166 int vblank_pipe;
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000167
Jesse Barnes79e53942008-11-07 14:24:08 -0800168 bool cursor_needs_physical;
169
170 struct drm_mm vram;
171
172 int irq_enabled;
173
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100174 struct intel_opregion opregion;
175
Jesse Barnes79e53942008-11-07 14:24:08 -0800176 /* LVDS info */
177 int backlight_duty_cycle; /* restore backlight to this value */
178 bool panel_wants_dither;
179 struct drm_display_mode *panel_fixed_mode;
180 struct drm_display_mode *vbt_mode; /* if any */
181
182 /* Feature bits from the VBIOS */
Hannes Eder95281e32008-12-18 15:09:00 +0100183 unsigned int int_tv_support:1;
184 unsigned int lvds_dither:1;
185 unsigned int lvds_vbt:1;
186 unsigned int int_crt_support:1;
Kristian Høgsberg43565a02009-02-13 20:56:52 -0500187 unsigned int lvds_use_ssc:1;
188 int lvds_ssc_freq;
Jesse Barnes79e53942008-11-07 14:24:08 -0800189
Jesse Barnesde151cf2008-11-12 10:03:55 -0800190 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
191 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
192 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
193
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000194 /* Register state */
195 u8 saveLBB;
196 u32 saveDSPACNTR;
197 u32 saveDSPBCNTR;
Keith Packarde948e992008-05-07 12:27:53 +1000198 u32 saveDSPARB;
Keith Packard881ee982008-11-02 23:08:44 -0800199 u32 saveRENDERSTANDBY;
Peng Li461cba22008-11-18 12:39:02 +0800200 u32 saveHWS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000201 u32 savePIPEACONF;
202 u32 savePIPEBCONF;
203 u32 savePIPEASRC;
204 u32 savePIPEBSRC;
205 u32 saveFPA0;
206 u32 saveFPA1;
207 u32 saveDPLL_A;
208 u32 saveDPLL_A_MD;
209 u32 saveHTOTAL_A;
210 u32 saveHBLANK_A;
211 u32 saveHSYNC_A;
212 u32 saveVTOTAL_A;
213 u32 saveVBLANK_A;
214 u32 saveVSYNC_A;
215 u32 saveBCLRPAT_A;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000216 u32 savePIPEASTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000217 u32 saveDSPASTRIDE;
218 u32 saveDSPASIZE;
219 u32 saveDSPAPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700220 u32 saveDSPAADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000221 u32 saveDSPASURF;
222 u32 saveDSPATILEOFF;
223 u32 savePFIT_PGM_RATIOS;
224 u32 saveBLC_PWM_CTL;
225 u32 saveBLC_PWM_CTL2;
226 u32 saveFPB0;
227 u32 saveFPB1;
228 u32 saveDPLL_B;
229 u32 saveDPLL_B_MD;
230 u32 saveHTOTAL_B;
231 u32 saveHBLANK_B;
232 u32 saveHSYNC_B;
233 u32 saveVTOTAL_B;
234 u32 saveVBLANK_B;
235 u32 saveVSYNC_B;
236 u32 saveBCLRPAT_B;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000237 u32 savePIPEBSTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000238 u32 saveDSPBSTRIDE;
239 u32 saveDSPBSIZE;
240 u32 saveDSPBPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700241 u32 saveDSPBADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000242 u32 saveDSPBSURF;
243 u32 saveDSPBTILEOFF;
Jesse Barnes585fb112008-07-29 11:54:06 -0700244 u32 saveVGA0;
245 u32 saveVGA1;
246 u32 saveVGA_PD;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000247 u32 saveVGACNTRL;
248 u32 saveADPA;
249 u32 saveLVDS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700250 u32 savePP_ON_DELAYS;
251 u32 savePP_OFF_DELAYS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000252 u32 saveDVOA;
253 u32 saveDVOB;
254 u32 saveDVOC;
255 u32 savePP_ON;
256 u32 savePP_OFF;
257 u32 savePP_CONTROL;
Jesse Barnes585fb112008-07-29 11:54:06 -0700258 u32 savePP_DIVISOR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000259 u32 savePFIT_CONTROL;
260 u32 save_palette_a[256];
261 u32 save_palette_b[256];
262 u32 saveFBC_CFB_BASE;
263 u32 saveFBC_LL_BASE;
264 u32 saveFBC_CONTROL;
265 u32 saveFBC_CONTROL2;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000266 u32 saveIER;
267 u32 saveIIR;
268 u32 saveIMR;
Keith Packard1f84e552008-02-16 19:19:29 -0800269 u32 saveCACHE_MODE_0;
Keith Packarde948e992008-05-07 12:27:53 +1000270 u32 saveD_STATE;
Jesse Barnes585fb112008-07-29 11:54:06 -0700271 u32 saveCG_2D_DIS;
Keith Packard1f84e552008-02-16 19:19:29 -0800272 u32 saveMI_ARB_STATE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000273 u32 saveSWF0[16];
274 u32 saveSWF1[16];
275 u32 saveSWF2[3];
276 u8 saveMSR;
277 u8 saveSR[8];
Jesse Barnes123f7942008-02-07 11:15:20 -0800278 u8 saveGR[25];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000279 u8 saveAR_INDEX;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000280 u8 saveAR[21];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000281 u8 saveDACMASK;
282 u8 saveDACDATA[256*3]; /* 256 3-byte colors */
Jesse Barnesa59e1222008-05-07 12:25:46 +1000283 u8 saveCR[37];
Eric Anholt673a3942008-07-30 12:06:12 -0700284
285 struct {
286 struct drm_mm gtt_space;
287
Keith Packard0839ccb2008-10-30 19:38:48 -0700288 struct io_mapping *gtt_mapping;
Eric Anholtab657db12009-01-23 12:57:47 -0800289 int gtt_mtrr;
Keith Packard0839ccb2008-10-30 19:38:48 -0700290
Eric Anholt673a3942008-07-30 12:06:12 -0700291 /**
292 * List of objects currently involved in rendering from the
293 * ringbuffer.
294 *
Eric Anholtce44b0e2008-11-06 16:00:31 -0800295 * Includes buffers having the contents of their GPU caches
296 * flushed, not necessarily primitives. last_rendering_seqno
297 * represents when the rendering involved will be completed.
298 *
Eric Anholt673a3942008-07-30 12:06:12 -0700299 * A reference is held on the buffer while on this list.
300 */
301 struct list_head active_list;
302
303 /**
304 * List of objects which are not in the ringbuffer but which
305 * still have a write_domain which needs to be flushed before
306 * unbinding.
307 *
Eric Anholtce44b0e2008-11-06 16:00:31 -0800308 * last_rendering_seqno is 0 while an object is in this list.
309 *
Eric Anholt673a3942008-07-30 12:06:12 -0700310 * A reference is held on the buffer while on this list.
311 */
312 struct list_head flushing_list;
313
314 /**
315 * LRU list of objects which are not in the ringbuffer and
316 * are ready to unbind, but are still in the GTT.
317 *
Eric Anholtce44b0e2008-11-06 16:00:31 -0800318 * last_rendering_seqno is 0 while an object is in this list.
319 *
Eric Anholt673a3942008-07-30 12:06:12 -0700320 * A reference is not held on the buffer while on this list,
321 * as merely being GTT-bound shouldn't prevent its being
322 * freed, and we'll pull it off the list in the free path.
323 */
324 struct list_head inactive_list;
325
326 /**
327 * List of breadcrumbs associated with GPU requests currently
328 * outstanding.
329 */
330 struct list_head request_list;
331
332 /**
333 * We leave the user IRQ off as much as possible,
334 * but this means that requests will finish and never
335 * be retired once the system goes idle. Set a timer to
336 * fire periodically while the ring is running. When it
337 * fires, go retire requests.
338 */
339 struct delayed_work retire_work;
340
341 uint32_t next_gem_seqno;
342
343 /**
344 * Waiting sequence number, if any
345 */
346 uint32_t waiting_gem_seqno;
347
348 /**
349 * Last seq seen at irq time
350 */
351 uint32_t irq_gem_seqno;
352
353 /**
354 * Flag if the X Server, and thus DRM, is not currently in
355 * control of the device.
356 *
357 * This is set between LeaveVT and EnterVT. It needs to be
358 * replaced with a semaphore. It also needs to be
359 * transitioned away from for kernel modesetting.
360 */
361 int suspended;
362
363 /**
364 * Flag if the hardware appears to be wedged.
365 *
366 * This is set when attempts to idle the device timeout.
367 * It prevents command submission from occuring and makes
368 * every pending request fail
369 */
370 int wedged;
371
372 /** Bit 6 swizzling required for X tiling */
373 uint32_t bit_6_swizzle_x;
374 /** Bit 6 swizzling required for Y tiling */
375 uint32_t bit_6_swizzle_y;
Dave Airlie71acb5e2008-12-30 20:31:46 +1000376
377 /* storage for physical objects */
378 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
Eric Anholt673a3942008-07-30 12:06:12 -0700379 } mm;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380} drm_i915_private_t;
381
Eric Anholt673a3942008-07-30 12:06:12 -0700382/** driver private structure attached to each drm_gem_object */
383struct drm_i915_gem_object {
384 struct drm_gem_object *obj;
385
386 /** Current space allocated to this object in the GTT, if any. */
387 struct drm_mm_node *gtt_space;
388
389 /** This object's place on the active/flushing/inactive lists */
390 struct list_head list;
391
392 /**
393 * This is set if the object is on the active or flushing lists
394 * (has pending rendering), and is not set if it's on inactive (ready
395 * to be unbound).
396 */
397 int active;
398
399 /**
400 * This is set if the object has been written to since last bound
401 * to the GTT
402 */
403 int dirty;
404
405 /** AGP memory structure for our GTT binding. */
406 DRM_AGP_MEM *agp_mem;
407
408 struct page **page_list;
409
410 /**
411 * Current offset of the object in GTT space.
412 *
413 * This is the same as gtt_space->start
414 */
415 uint32_t gtt_offset;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800416 /**
417 * Required alignment for the object
418 */
419 uint32_t gtt_alignment;
420 /**
421 * Fake offset for use by mmap(2)
422 */
423 uint64_t mmap_offset;
424
425 /**
426 * Fence register bits (if any) for this object. Will be set
427 * as needed when mapped into the GTT.
428 * Protected by dev->struct_mutex.
429 */
430 int fence_reg;
Eric Anholt673a3942008-07-30 12:06:12 -0700431
432 /** Boolean whether this object has a valid gtt offset. */
433 int gtt_bound;
434
435 /** How many users have pinned this object in GTT space */
436 int pin_count;
437
438 /** Breadcrumb of last rendering to the buffer. */
439 uint32_t last_rendering_seqno;
440
441 /** Current tiling mode for the object. */
442 uint32_t tiling_mode;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800443 uint32_t stride;
Eric Anholt673a3942008-07-30 12:06:12 -0700444
Keith Packardba1eb1d2008-10-14 19:55:10 -0700445 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
446 uint32_t agp_type;
447
Eric Anholt673a3942008-07-30 12:06:12 -0700448 /**
Eric Anholte47c68e2008-11-14 13:35:19 -0800449 * If present, while GEM_DOMAIN_CPU is in the read domain this array
450 * flags which individual pages are valid.
Eric Anholt673a3942008-07-30 12:06:12 -0700451 */
452 uint8_t *page_cpu_valid;
Jesse Barnes79e53942008-11-07 14:24:08 -0800453
454 /** User space pin count and filp owning the pin */
455 uint32_t user_pin_count;
456 struct drm_file *pin_filp;
Dave Airlie71acb5e2008-12-30 20:31:46 +1000457
458 /** for phy allocated objects */
459 struct drm_i915_gem_phys_object *phys_obj;
Eric Anholt673a3942008-07-30 12:06:12 -0700460};
461
462/**
463 * Request queue structure.
464 *
465 * The request queue allows us to note sequence numbers that have been emitted
466 * and may be associated with active buffers to be retired.
467 *
468 * By keeping this list, we can avoid having to do questionable
469 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
470 * an emission time with seqnos for tracking how far ahead of the GPU we are.
471 */
472struct drm_i915_gem_request {
473 /** GEM sequence number associated with this request. */
474 uint32_t seqno;
475
476 /** Time at which this request was emitted, in jiffies. */
477 unsigned long emitted_jiffies;
478
Eric Anholt673a3942008-07-30 12:06:12 -0700479 struct list_head list;
480};
481
482struct drm_i915_file_private {
483 struct {
484 uint32_t last_gem_seqno;
485 uint32_t last_gem_throttle_seqno;
486 } mm;
487};
488
Jesse Barnes79e53942008-11-07 14:24:08 -0800489enum intel_chip_family {
490 CHIP_I8XX = 0x01,
491 CHIP_I9XX = 0x02,
492 CHIP_I915 = 0x04,
493 CHIP_I965 = 0x08,
494};
495
Eric Anholtc153f452007-09-03 12:06:45 +1000496extern struct drm_ioctl_desc i915_ioctls[];
Dave Airlieb3a83632005-09-30 18:37:36 +1000497extern int i915_max_ioctl;
Jesse Barnes79e53942008-11-07 14:24:08 -0800498extern unsigned int i915_fbpercrtc;
Dave Airlieb3a83632005-09-30 18:37:36 +1000499
Dave Airlie7c1c2872008-11-28 14:22:24 +1000500extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
501extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
502
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503 /* i915_dma.c */
Dave Airlie84b1fd12007-07-11 15:53:27 +1000504extern void i915_kernel_lost_context(struct drm_device * dev);
Dave Airlie22eae942005-11-10 22:16:34 +1100505extern int i915_driver_load(struct drm_device *, unsigned long flags);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000506extern int i915_driver_unload(struct drm_device *);
Eric Anholt673a3942008-07-30 12:06:12 -0700507extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000508extern void i915_driver_lastclose(struct drm_device * dev);
Eric Anholt6c340ea2007-08-25 20:23:09 +1000509extern void i915_driver_preclose(struct drm_device *dev,
510 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700511extern void i915_driver_postclose(struct drm_device *dev,
512 struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000513extern int i915_driver_device_is_agp(struct drm_device * dev);
Dave Airlie0d6aa602006-01-02 20:14:23 +1100514extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
515 unsigned long arg);
Eric Anholt673a3942008-07-30 12:06:12 -0700516extern int i915_emit_box(struct drm_device *dev,
517 struct drm_clip_rect __user *boxes,
518 int i, int DR1, int DR4);
Dave Airlieaf6061a2008-05-07 12:15:39 +1000519
Linus Torvalds1da177e2005-04-16 15:20:36 -0700520/* i915_irq.c */
Eric Anholtc153f452007-09-03 12:06:45 +1000521extern int i915_irq_emit(struct drm_device *dev, void *data,
522 struct drm_file *file_priv);
523extern int i915_irq_wait(struct drm_device *dev, void *data,
524 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700525void i915_user_irq_get(struct drm_device *dev);
526void i915_user_irq_put(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -0800527extern void i915_enable_interrupt (struct drm_device *dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528
529extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000530extern void i915_driver_irq_preinstall(struct drm_device * dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700531extern int i915_driver_irq_postinstall(struct drm_device *dev);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000532extern void i915_driver_irq_uninstall(struct drm_device * dev);
Eric Anholtc153f452007-09-03 12:06:45 +1000533extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
534 struct drm_file *file_priv);
535extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
536 struct drm_file *file_priv);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700537extern int i915_enable_vblank(struct drm_device *dev, int crtc);
538extern void i915_disable_vblank(struct drm_device *dev, int crtc);
539extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800540extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
Eric Anholtc153f452007-09-03 12:06:45 +1000541extern int i915_vblank_swap(struct drm_device *dev, void *data,
542 struct drm_file *file_priv);
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100543extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700544
Keith Packard7c463582008-11-04 02:03:27 -0800545void
546i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
547
548void
549i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
550
551
Linus Torvalds1da177e2005-04-16 15:20:36 -0700552/* i915_mem.c */
Eric Anholtc153f452007-09-03 12:06:45 +1000553extern int i915_mem_alloc(struct drm_device *dev, void *data,
554 struct drm_file *file_priv);
555extern int i915_mem_free(struct drm_device *dev, void *data,
556 struct drm_file *file_priv);
557extern int i915_mem_init_heap(struct drm_device *dev, void *data,
558 struct drm_file *file_priv);
559extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
560 struct drm_file *file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700561extern void i915_mem_takedown(struct mem_block **heap);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000562extern void i915_mem_release(struct drm_device * dev,
Eric Anholt6c340ea2007-08-25 20:23:09 +1000563 struct drm_file *file_priv, struct mem_block *heap);
Eric Anholt673a3942008-07-30 12:06:12 -0700564/* i915_gem.c */
565int i915_gem_init_ioctl(struct drm_device *dev, void *data,
566 struct drm_file *file_priv);
567int i915_gem_create_ioctl(struct drm_device *dev, void *data,
568 struct drm_file *file_priv);
569int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
570 struct drm_file *file_priv);
571int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
572 struct drm_file *file_priv);
573int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
574 struct drm_file *file_priv);
Jesse Barnesde151cf2008-11-12 10:03:55 -0800575int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
576 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700577int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
578 struct drm_file *file_priv);
579int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
580 struct drm_file *file_priv);
581int i915_gem_execbuffer(struct drm_device *dev, void *data,
582 struct drm_file *file_priv);
583int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
584 struct drm_file *file_priv);
585int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
586 struct drm_file *file_priv);
587int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
588 struct drm_file *file_priv);
589int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
590 struct drm_file *file_priv);
591int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
592 struct drm_file *file_priv);
593int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
594 struct drm_file *file_priv);
595int i915_gem_set_tiling(struct drm_device *dev, void *data,
596 struct drm_file *file_priv);
597int i915_gem_get_tiling(struct drm_device *dev, void *data,
598 struct drm_file *file_priv);
Eric Anholt5a125c32008-10-22 21:40:13 -0700599int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
600 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700601void i915_gem_load(struct drm_device *dev);
602int i915_gem_proc_init(struct drm_minor *minor);
603void i915_gem_proc_cleanup(struct drm_minor *minor);
604int i915_gem_init_object(struct drm_gem_object *obj);
605void i915_gem_free_object(struct drm_gem_object *obj);
606int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
607void i915_gem_object_unpin(struct drm_gem_object *obj);
Jesse Barnes0f973f22009-01-26 17:10:45 -0800608int i915_gem_object_unbind(struct drm_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700609void i915_gem_lastclose(struct drm_device *dev);
610uint32_t i915_get_gem_seqno(struct drm_device *dev);
611void i915_gem_retire_requests(struct drm_device *dev);
612void i915_gem_retire_work_handler(struct work_struct *work);
613void i915_gem_clflush_object(struct drm_gem_object *obj);
Jesse Barnes79e53942008-11-07 14:24:08 -0800614int i915_gem_object_set_domain(struct drm_gem_object *obj,
615 uint32_t read_domains,
616 uint32_t write_domain);
617int i915_gem_init_ringbuffer(struct drm_device *dev);
618void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
619int i915_gem_do_init(struct drm_device *dev, unsigned long start,
620 unsigned long end);
Jesse Barnesde151cf2008-11-12 10:03:55 -0800621int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
Jesse Barnes79e53942008-11-07 14:24:08 -0800622int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
623 int write);
Dave Airlie71acb5e2008-12-30 20:31:46 +1000624int i915_gem_attach_phys_object(struct drm_device *dev,
625 struct drm_gem_object *obj, int id);
626void i915_gem_detach_phys_object(struct drm_device *dev,
627 struct drm_gem_object *obj);
628void i915_gem_free_all_phys_object(struct drm_device *dev);
Eric Anholt673a3942008-07-30 12:06:12 -0700629
630/* i915_gem_tiling.c */
631void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
632
633/* i915_gem_debug.c */
634void i915_gem_dump_object(struct drm_gem_object *obj, int len,
635 const char *where, uint32_t mark);
636#if WATCH_INACTIVE
637void i915_verify_inactive(struct drm_device *dev, char *file, int line);
638#else
639#define i915_verify_inactive(dev, file, line)
640#endif
641void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
642void i915_gem_dump_object(struct drm_gem_object *obj, int len,
643 const char *where, uint32_t mark);
644void i915_dump_lru(struct drm_device *dev, const char *where);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700645
Jesse Barnes317c35d2008-08-25 15:11:06 -0700646/* i915_suspend.c */
647extern int i915_save_state(struct drm_device *dev);
648extern int i915_restore_state(struct drm_device *dev);
649
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700650/* i915_suspend.c */
651extern int i915_save_state(struct drm_device *dev);
652extern int i915_restore_state(struct drm_device *dev);
653
Len Brown65e082c2008-10-24 17:18:10 -0400654#ifdef CONFIG_ACPI
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100655/* i915_opregion.c */
656extern int intel_opregion_init(struct drm_device *dev);
657extern void intel_opregion_free(struct drm_device *dev);
658extern void opregion_asle_intr(struct drm_device *dev);
659extern void opregion_enable_asle(struct drm_device *dev);
Len Brown65e082c2008-10-24 17:18:10 -0400660#else
661static inline int intel_opregion_init(struct drm_device *dev) { return 0; }
662static inline void intel_opregion_free(struct drm_device *dev) { return; }
663static inline void opregion_asle_intr(struct drm_device *dev) { return; }
664static inline void opregion_enable_asle(struct drm_device *dev) { return; }
665#endif
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100666
Jesse Barnes79e53942008-11-07 14:24:08 -0800667/* modesetting */
668extern void intel_modeset_init(struct drm_device *dev);
669extern void intel_modeset_cleanup(struct drm_device *dev);
670
Eric Anholt546b0972008-09-01 16:45:29 -0700671/**
672 * Lock test for when it's just for synchronization of ring access.
673 *
674 * In that case, we don't need to do it when GEM is initialized as nobody else
675 * has access to the ring.
676 */
677#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
678 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
679 LOCK_TEST_WITH_RETURN(dev, file_priv); \
680} while (0)
681
Eric Anholt3043c602008-10-02 12:24:47 -0700682#define I915_READ(reg) readl(dev_priv->regs + (reg))
683#define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
684#define I915_READ16(reg) readw(dev_priv->regs + (reg))
685#define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
686#define I915_READ8(reg) readb(dev_priv->regs + (reg))
687#define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
Jesse Barnesde151cf2008-11-12 10:03:55 -0800688#ifdef writeq
689#define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
690#else
691#define I915_WRITE64(reg, val) (writel(val, dev_priv->regs + (reg)), \
692 writel(upper_32_bits(val), dev_priv->regs + \
693 (reg) + 4))
694#endif
Eric Anholt7d573822009-01-02 13:33:00 -0800695#define POSTING_READ(reg) (void)I915_READ(reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700696
697#define I915_VERBOSE 0
698
699#define RING_LOCALS unsigned int outring, ringmask, outcount; \
700 volatile char *virt;
701
702#define BEGIN_LP_RING(n) do { \
703 if (I915_VERBOSE) \
Márton Németh3e684ea2008-01-24 15:58:57 +1000704 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
705 if (dev_priv->ring.space < (n)*4) \
Harvey Harrisonbf9d8922008-04-30 00:55:10 -0700706 i915_wait_ring(dev, (n)*4, __func__); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700707 outcount = 0; \
708 outring = dev_priv->ring.tail; \
709 ringmask = dev_priv->ring.tail_mask; \
710 virt = dev_priv->ring.virtual_start; \
711} while (0)
712
713#define OUT_RING(n) do { \
714 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
Alan Hourihanec29b6692006-08-12 16:29:24 +1000715 *(volatile unsigned int *)(virt + outring) = (n); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700716 outcount++; \
717 outring += 4; \
718 outring &= ringmask; \
719} while (0)
720
721#define ADVANCE_LP_RING() do { \
722 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
723 dev_priv->ring.tail = outring; \
724 dev_priv->ring.space -= outcount * 4; \
Jesse Barnes585fb112008-07-29 11:54:06 -0700725 I915_WRITE(PRB0_TAIL, outring); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726} while(0)
727
Jesse Barnes585fb112008-07-29 11:54:06 -0700728/**
729 * Reads a dword out of the status page, which is written to from the command
730 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
731 * MI_STORE_DATA_IMM.
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000732 *
Jesse Barnes585fb112008-07-29 11:54:06 -0700733 * The following dwords have a reserved meaning:
Keith Packard0cdad7e2008-10-14 17:19:38 -0700734 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
735 * 0x04: ring 0 head pointer
736 * 0x05: ring 1 head pointer (915-class)
737 * 0x06: ring 2 head pointer (915-class)
738 * 0x10-0x1b: Context status DWords (GM45)
739 * 0x1f: Last written status offset. (GM45)
Jesse Barnes585fb112008-07-29 11:54:06 -0700740 *
Keith Packard0cdad7e2008-10-14 17:19:38 -0700741 * The area from dword 0x20 to 0x3ff is available for driver usage.
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000742 */
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000743#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
Keith Packard0baf8232008-11-08 11:44:14 +1000744#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
Keith Packard0cdad7e2008-10-14 17:19:38 -0700745#define I915_GEM_HWS_INDEX 0x20
Keith Packard0baf8232008-11-08 11:44:14 +1000746#define I915_BREADCRUMB_INDEX 0x21
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000747
Jesse Barnes585fb112008-07-29 11:54:06 -0700748extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000749
750#define IS_I830(dev) ((dev)->pci_device == 0x3577)
751#define IS_845G(dev) ((dev)->pci_device == 0x2562)
752#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
753#define IS_I855(dev) ((dev)->pci_device == 0x3582)
754#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
755
Carlos Martín4d1f7882008-01-23 16:41:17 +1000756#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000757#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
758#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
Jesse Barnes3bf48462008-04-06 11:55:04 -0700759#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
760 (dev)->pci_device == 0x27AE)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000761#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
762 (dev)->pci_device == 0x2982 || \
763 (dev)->pci_device == 0x2992 || \
764 (dev)->pci_device == 0x29A2 || \
765 (dev)->pci_device == 0x2A02 || \
Zhenyu Wang5f5f9d42008-01-24 16:46:36 +1000766 (dev)->pci_device == 0x2A12 || \
Zhenyu Wangd3adbc02008-06-20 12:12:56 +1000767 (dev)->pci_device == 0x2A42 || \
768 (dev)->pci_device == 0x2E02 || \
769 (dev)->pci_device == 0x2E12 || \
770 (dev)->pci_device == 0x2E22)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000771
772#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
773
Jesse Barnesb9bfdfe2008-08-25 15:16:19 -0700774#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
Zhenyu Wang5f5f9d42008-01-24 16:46:36 +1000775
Zhenyu Wangd3adbc02008-06-20 12:12:56 +1000776#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
777 (dev)->pci_device == 0x2E12 || \
Eric Anholt60fd99e2008-12-03 22:50:02 -0800778 (dev)->pci_device == 0x2E22 || \
779 IS_GM45(dev))
Zhenyu Wangd3adbc02008-06-20 12:12:56 +1000780
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000781#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
782 (dev)->pci_device == 0x29B2 || \
783 (dev)->pci_device == 0x29D2)
784
785#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
786 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
787
788#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
Jesse Barnesb9bfdfe2008-08-25 15:16:19 -0700789 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000790
Jesse Barnesb9bfdfe2008-08-25 15:16:19 -0700791#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
Jesse Barnes0f973f22009-01-26 17:10:45 -0800792/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
793 * rows, which changed the alignment requirements and fence programming.
794 */
795#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
796 IS_I915GM(dev)))
Eric Anholt7d573822009-01-02 13:33:00 -0800797#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev))
Zhenyu Wangb39d50e2008-02-19 20:59:09 +1000798
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000799#define PRIMARY_RINGBUFFER_SIZE (128*1024)
Dave Airlie0d6aa602006-01-02 20:14:23 +1100800
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801#endif