blob: cd007a67b3021e6e384889bf06ff7c9b292a7906 [file] [log] [blame]
Vladimir Barinov3d9edf02007-07-10 13:03:43 +01001/*
2 * TI DaVinci GPIO Support
3 *
David Brownelldce11152008-09-07 23:41:04 -07004 * Copyright (c) 2006-2007 David Brownell
Vladimir Barinov3d9edf02007-07-10 13:03:43 +01005 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
Russell King2f8163b2011-07-26 10:53:52 +010012#include <linux/gpio.h>
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010013#include <linux/errno.h>
14#include <linux/kernel.h>
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010015#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
KV Sujith118150f2013-08-18 10:48:58 +053018#include <linux/irq.h>
Lad, Prabhakar9211ff32013-11-21 23:45:27 +053019#include <linux/irqdomain.h>
KV Sujithc7708442013-11-21 23:45:29 +053020#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
KV Sujith118150f2013-08-18 10:48:58 +053023#include <linux/platform_device.h>
24#include <linux/platform_data/gpio-davinci.h>
Grygorii Strashko0d978eb2013-11-26 21:40:09 +020025#include <linux/irqchip/chained_irq.h>
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010026
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040027struct davinci_gpio_regs {
28 u32 dir;
29 u32 out_data;
30 u32 set_data;
31 u32 clr_data;
32 u32 in_data;
33 u32 set_rising;
34 u32 clr_rising;
35 u32 set_falling;
36 u32 clr_falling;
37 u32 intstat;
38};
39
Grygorii Strashko0c6feb02014-02-13 17:58:45 +020040typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
41
Philip Avinash131a10a2013-08-18 10:48:57 +053042#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
43
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040044static void __iomem *gpio_base;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010045
KV Sujith118150f2013-08-18 10:48:58 +053046static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010047{
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040048 void __iomem *ptr;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040049
50 if (gpio < 32 * 1)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040051 ptr = gpio_base + 0x10;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040052 else if (gpio < 32 * 2)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040053 ptr = gpio_base + 0x38;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040054 else if (gpio < 32 * 3)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040055 ptr = gpio_base + 0x60;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040056 else if (gpio < 32 * 4)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040057 ptr = gpio_base + 0x88;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040058 else if (gpio < 32 * 5)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040059 ptr = gpio_base + 0xb0;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040060 else
61 ptr = NULL;
62 return ptr;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010063}
64
Thomas Gleixner1765d672015-07-13 01:18:56 +020065static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
Kevin Hilman21ce8732010-02-25 16:49:56 -080066{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040067 struct davinci_gpio_regs __iomem *g;
Kevin Hilman21ce8732010-02-25 16:49:56 -080068
Thomas Gleixner1765d672015-07-13 01:18:56 +020069 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
Kevin Hilman21ce8732010-02-25 16:49:56 -080070
71 return g;
72}
73
KV Sujith118150f2013-08-18 10:48:58 +053074static int davinci_gpio_irq_setup(struct platform_device *pdev);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010075
76/*--------------------------------------------------------------------------*/
77
Cyril Chemparathy5b3a05c2010-05-01 18:38:27 -040078/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040079static inline int __davinci_direction(struct gpio_chip *chip,
80 unsigned offset, bool out, int value)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010081{
Linus Walleij72a1ca22015-12-04 16:25:04 +010082 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040083 struct davinci_gpio_regs __iomem *g = d->regs;
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -040084 unsigned long flags;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010085 u32 temp;
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040086 u32 mask = 1 << offset;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010087
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -040088 spin_lock_irqsave(&d->lock, flags);
Lad, Prabhakar388291c2013-12-11 23:22:07 +053089 temp = readl_relaxed(&g->dir);
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040090 if (out) {
91 temp &= ~mask;
Lad, Prabhakar388291c2013-12-11 23:22:07 +053092 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040093 } else {
94 temp |= mask;
95 }
Lad, Prabhakar388291c2013-12-11 23:22:07 +053096 writel_relaxed(temp, &g->dir);
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -040097 spin_unlock_irqrestore(&d->lock, flags);
David Brownelldce11152008-09-07 23:41:04 -070098
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010099 return 0;
100}
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100101
Cyril Chemparathyba4a9842010-05-01 18:37:51 -0400102static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
103{
104 return __davinci_direction(chip, offset, false, 0);
105}
106
107static int
108davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
109{
110 return __davinci_direction(chip, offset, true, value);
111}
112
David Brownelldce11152008-09-07 23:41:04 -0700113/*
114 * Read the pin's value (works even if it's set up as output);
115 * returns zero/nonzero.
116 *
117 * Note that changes are synched to the GPIO clock, so reading values back
118 * right after you've set them may give old values.
119 */
120static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100121{
Linus Walleij72a1ca22015-12-04 16:25:04 +0100122 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400123 struct davinci_gpio_regs __iomem *g = d->regs;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100124
Linus Walleij5b8d8fb2015-12-21 10:33:27 +0100125 return !!((1 << offset) & readl_relaxed(&g->in_data));
David Brownelldce11152008-09-07 23:41:04 -0700126}
127
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100128/*
David Brownelldce11152008-09-07 23:41:04 -0700129 * Assuming the pin is muxed as a gpio output, set its output value.
130 */
131static void
132davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
133{
Linus Walleij72a1ca22015-12-04 16:25:04 +0100134 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400135 struct davinci_gpio_regs __iomem *g = d->regs;
David Brownelldce11152008-09-07 23:41:04 -0700136
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530137 writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data);
David Brownelldce11152008-09-07 23:41:04 -0700138}
139
KV Sujithc7708442013-11-21 23:45:29 +0530140static struct davinci_gpio_platform_data *
141davinci_gpio_get_pdata(struct platform_device *pdev)
142{
143 struct device_node *dn = pdev->dev.of_node;
144 struct davinci_gpio_platform_data *pdata;
145 int ret;
146 u32 val;
147
148 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
Nizam Haiderab128af2015-11-23 20:53:18 +0530149 return dev_get_platdata(&pdev->dev);
KV Sujithc7708442013-11-21 23:45:29 +0530150
151 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
152 if (!pdata)
153 return NULL;
154
155 ret = of_property_read_u32(dn, "ti,ngpio", &val);
156 if (ret)
157 goto of_err;
158
159 pdata->ngpio = val;
160
161 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
162 if (ret)
163 goto of_err;
164
165 pdata->gpio_unbanked = val;
166
167 return pdata;
168
169of_err:
170 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
171 return NULL;
172}
173
Alexander Holler758afe42014-03-05 12:21:01 +0100174#ifdef CONFIG_OF_GPIO
175static int davinci_gpio_of_xlate(struct gpio_chip *gc,
176 const struct of_phandle_args *gpiospec,
177 u32 *flags)
178{
Linus Walleij58383c72015-11-04 09:56:26 +0100179 struct davinci_gpio_controller *chips = dev_get_drvdata(gc->parent);
180 struct davinci_gpio_platform_data *pdata = dev_get_platdata(gc->parent);
Alexander Holler758afe42014-03-05 12:21:01 +0100181
182 if (gpiospec->args[0] > pdata->ngpio)
183 return -EINVAL;
184
185 if (gc != &chips[gpiospec->args[0] / 32].chip)
186 return -EINVAL;
187
188 if (flags)
189 *flags = gpiospec->args[1];
190
191 return gpiospec->args[0] % 32;
192}
193#endif
194
KV Sujith118150f2013-08-18 10:48:58 +0530195static int davinci_gpio_probe(struct platform_device *pdev)
David Brownelldce11152008-09-07 23:41:04 -0700196{
197 int i, base;
Lokesh Vutla6ec9249a2016-01-28 19:08:51 +0530198 unsigned ngpio, nbank;
KV Sujith118150f2013-08-18 10:48:58 +0530199 struct davinci_gpio_controller *chips;
200 struct davinci_gpio_platform_data *pdata;
201 struct davinci_gpio_regs __iomem *regs;
202 struct device *dev = &pdev->dev;
203 struct resource *res;
David Brownelldce11152008-09-07 23:41:04 -0700204
KV Sujithc7708442013-11-21 23:45:29 +0530205 pdata = davinci_gpio_get_pdata(pdev);
KV Sujith118150f2013-08-18 10:48:58 +0530206 if (!pdata) {
207 dev_err(dev, "No platform data found\n");
208 return -EINVAL;
209 }
Cyril Chemparathy686b6342010-05-01 18:37:54 -0400210
KV Sujithc7708442013-11-21 23:45:29 +0530211 dev->platform_data = pdata;
212
Mark A. Greera9949552009-04-15 12:40:35 -0700213 /*
214 * The gpio banks conceptually expose a segmented bitmap,
David Brownell474dad52008-12-07 11:46:23 -0800215 * and "ngpio" is one more than the largest zero-based
216 * bit index that's valid.
217 */
KV Sujith118150f2013-08-18 10:48:58 +0530218 ngpio = pdata->ngpio;
Mark A. Greera9949552009-04-15 12:40:35 -0700219 if (ngpio == 0) {
KV Sujith118150f2013-08-18 10:48:58 +0530220 dev_err(dev, "How many GPIOs?\n");
David Brownell474dad52008-12-07 11:46:23 -0800221 return -EINVAL;
222 }
223
Grygorii Strashkoc21d5002013-11-21 17:34:35 +0200224 if (WARN_ON(ARCH_NR_GPIOS < ngpio))
225 ngpio = ARCH_NR_GPIOS;
David Brownell474dad52008-12-07 11:46:23 -0800226
Lokesh Vutla6ec9249a2016-01-28 19:08:51 +0530227 nbank = DIV_ROUND_UP(ngpio, 32);
KV Sujith118150f2013-08-18 10:48:58 +0530228 chips = devm_kzalloc(dev,
Lokesh Vutla6ec9249a2016-01-28 19:08:51 +0530229 nbank * sizeof(struct davinci_gpio_controller),
KV Sujith118150f2013-08-18 10:48:58 +0530230 GFP_KERNEL);
Jingoo Han9ea9363c2014-04-29 17:33:26 +0900231 if (!chips)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -0400232 return -ENOMEM;
KV Sujith118150f2013-08-18 10:48:58 +0530233
234 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
KV Sujith118150f2013-08-18 10:48:58 +0530235 gpio_base = devm_ioremap_resource(dev, res);
236 if (IS_ERR(gpio_base))
237 return PTR_ERR(gpio_base);
Cyril Chemparathyb8d44292010-05-07 17:06:32 -0400238
David Brownell474dad52008-12-07 11:46:23 -0800239 for (i = 0, base = 0; base < ngpio; i++, base += 32) {
David Brownelldce11152008-09-07 23:41:04 -0700240 chips[i].chip.label = "DaVinci";
241
242 chips[i].chip.direction_input = davinci_direction_in;
243 chips[i].chip.get = davinci_gpio_get;
244 chips[i].chip.direction_output = davinci_direction_out;
245 chips[i].chip.set = davinci_gpio_set;
246
247 chips[i].chip.base = base;
David Brownell474dad52008-12-07 11:46:23 -0800248 chips[i].chip.ngpio = ngpio - base;
David Brownelldce11152008-09-07 23:41:04 -0700249 if (chips[i].chip.ngpio > 32)
250 chips[i].chip.ngpio = 32;
251
KV Sujithc7708442013-11-21 23:45:29 +0530252#ifdef CONFIG_OF_GPIO
Alexander Holler758afe42014-03-05 12:21:01 +0100253 chips[i].chip.of_gpio_n_cells = 2;
254 chips[i].chip.of_xlate = davinci_gpio_of_xlate;
Linus Walleij6ddbaed2015-12-04 14:13:59 +0100255 chips[i].chip.parent = dev;
KV Sujithc7708442013-11-21 23:45:29 +0530256 chips[i].chip.of_node = dev->of_node;
257#endif
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -0400258 spin_lock_init(&chips[i].lock);
259
Cyril Chemparathyc12f4152010-05-01 18:37:53 -0400260 regs = gpio2regs(base);
261 chips[i].regs = regs;
262 chips[i].set_data = &regs->set_data;
263 chips[i].clr_data = &regs->clr_data;
264 chips[i].in_data = &regs->in_data;
David Brownelldce11152008-09-07 23:41:04 -0700265
Linus Walleij72a1ca22015-12-04 16:25:04 +0100266 gpiochip_add_data(&chips[i].chip, &chips[i]);
David Brownelldce11152008-09-07 23:41:04 -0700267 }
268
KV Sujith118150f2013-08-18 10:48:58 +0530269 platform_set_drvdata(pdev, chips);
270 davinci_gpio_irq_setup(pdev);
David Brownelldce11152008-09-07 23:41:04 -0700271 return 0;
272}
David Brownelldce11152008-09-07 23:41:04 -0700273
274/*--------------------------------------------------------------------------*/
275/*
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100276 * We expect irqs will normally be set up as input pins, but they can also be
277 * used as output pins ... which is convenient for testing.
278 *
David Brownell474dad52008-12-07 11:46:23 -0800279 * NOTE: The first few GPIOs also have direct INTC hookups in addition
David Brownell7a360712009-06-25 17:01:31 -0700280 * to their GPIOBNK0 irq, with a bit less overhead.
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100281 *
David Brownell474dad52008-12-07 11:46:23 -0800282 * All those INTC hookups (direct, plus several IRQ banks) can also
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100283 * serve as EDMA event triggers.
284 */
285
Lennert Buytenhek23265442010-11-29 10:27:27 +0100286static void gpio_irq_disable(struct irq_data *d)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100287{
Thomas Gleixner1765d672015-07-13 01:18:56 +0200288 struct davinci_gpio_regs __iomem *g = irq2regs(d);
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100289 u32 mask = (u32) irq_data_get_irq_handler_data(d);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100290
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530291 writel_relaxed(mask, &g->clr_falling);
292 writel_relaxed(mask, &g->clr_rising);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100293}
294
Lennert Buytenhek23265442010-11-29 10:27:27 +0100295static void gpio_irq_enable(struct irq_data *d)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100296{
Thomas Gleixner1765d672015-07-13 01:18:56 +0200297 struct davinci_gpio_regs __iomem *g = irq2regs(d);
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100298 u32 mask = (u32) irq_data_get_irq_handler_data(d);
Thomas Gleixner5093aec2011-03-24 12:47:04 +0100299 unsigned status = irqd_get_trigger_type(d);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100300
David Brownelldf4aab42009-05-04 13:14:27 -0700301 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
302 if (!status)
303 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
304
305 if (status & IRQ_TYPE_EDGE_FALLING)
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530306 writel_relaxed(mask, &g->set_falling);
David Brownelldf4aab42009-05-04 13:14:27 -0700307 if (status & IRQ_TYPE_EDGE_RISING)
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530308 writel_relaxed(mask, &g->set_rising);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100309}
310
Lennert Buytenhek23265442010-11-29 10:27:27 +0100311static int gpio_irq_type(struct irq_data *d, unsigned trigger)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100312{
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100313 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
314 return -EINVAL;
315
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100316 return 0;
317}
318
319static struct irq_chip gpio_irqchip = {
320 .name = "GPIO",
Lennert Buytenhek23265442010-11-29 10:27:27 +0100321 .irq_enable = gpio_irq_enable,
322 .irq_disable = gpio_irq_disable,
323 .irq_set_type = gpio_irq_type,
Thomas Gleixner5093aec2011-03-24 12:47:04 +0100324 .flags = IRQCHIP_SET_TYPE_MASKED,
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100325};
326
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200327static void gpio_irq_handler(struct irq_desc *desc)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100328{
Thomas Gleixnerc3ca1e62015-07-12 23:47:32 +0200329 unsigned int irq = irq_desc_get_irq(desc);
Thomas Gleixner74164012011-06-06 11:51:43 +0200330 struct davinci_gpio_regs __iomem *g;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100331 u32 mask = 0xffff;
Ido Yarivf299bb92011-07-12 00:03:11 +0300332 struct davinci_gpio_controller *d;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100333
Ido Yarivf299bb92011-07-12 00:03:11 +0300334 d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
335 g = (struct davinci_gpio_regs __iomem *)d->regs;
Thomas Gleixner74164012011-06-06 11:51:43 +0200336
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100337 /* we only care about one bank */
338 if (irq & 1)
339 mask <<= 16;
340
341 /* temporarily mask (level sensitive) parent IRQ */
Grygorii Strashko0d978eb2013-11-26 21:40:09 +0200342 chained_irq_enter(irq_desc_get_chip(desc), desc);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100343 while (1) {
344 u32 status;
Lad, Prabhakar9211ff32013-11-21 23:45:27 +0530345 int bit;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100346
347 /* ack any irqs */
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530348 status = readl_relaxed(&g->intstat) & mask;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100349 if (!status)
350 break;
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530351 writel_relaxed(status, &g->intstat);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100352
353 /* now demux them to the right lowlevel handler */
Ido Yarivf299bb92011-07-12 00:03:11 +0300354
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100355 while (status) {
Lad, Prabhakar9211ff32013-11-21 23:45:27 +0530356 bit = __ffs(status);
357 status &= ~BIT(bit);
358 generic_handle_irq(
359 irq_find_mapping(d->irq_domain,
360 d->chip.base + bit));
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100361 }
362 }
Grygorii Strashko0d978eb2013-11-26 21:40:09 +0200363 chained_irq_exit(irq_desc_get_chip(desc), desc);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100364 /* now it may re-trigger */
365}
366
David Brownell7a360712009-06-25 17:01:31 -0700367static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
368{
Linus Walleij72a1ca22015-12-04 16:25:04 +0100369 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
David Brownell7a360712009-06-25 17:01:31 -0700370
Grygorii Strashko6075a8b2013-12-18 12:07:51 +0200371 if (d->irq_domain)
372 return irq_create_mapping(d->irq_domain, d->chip.base + offset);
373 else
374 return -ENXIO;
David Brownell7a360712009-06-25 17:01:31 -0700375}
376
377static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
378{
Linus Walleij72a1ca22015-12-04 16:25:04 +0100379 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
David Brownell7a360712009-06-25 17:01:31 -0700380
Philip Avinash131a10a2013-08-18 10:48:57 +0530381 /*
382 * NOTE: we assume for now that only irqs in the first gpio_chip
David Brownell7a360712009-06-25 17:01:31 -0700383 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
384 */
Lad, Prabhakar34af1ab2013-11-08 12:15:55 +0530385 if (offset < d->gpio_unbanked)
KV Sujith118150f2013-08-18 10:48:58 +0530386 return d->gpio_irq + offset;
David Brownell7a360712009-06-25 17:01:31 -0700387 else
388 return -ENODEV;
389}
390
Sekhar Noriab2dde92012-03-11 18:16:11 +0530391static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
David Brownell7a360712009-06-25 17:01:31 -0700392{
Sekhar Noriab2dde92012-03-11 18:16:11 +0530393 struct davinci_gpio_controller *d;
394 struct davinci_gpio_regs __iomem *g;
Sekhar Noriab2dde92012-03-11 18:16:11 +0530395 u32 mask;
396
Jiang Liuc16edb82015-06-01 16:05:19 +0800397 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
Sekhar Noriab2dde92012-03-11 18:16:11 +0530398 g = (struct davinci_gpio_regs __iomem *)d->regs;
KV Sujith118150f2013-08-18 10:48:58 +0530399 mask = __gpio_mask(data->irq - d->gpio_irq);
David Brownell7a360712009-06-25 17:01:31 -0700400
401 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
402 return -EINVAL;
403
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530404 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
David Brownell7a360712009-06-25 17:01:31 -0700405 ? &g->set_falling : &g->clr_falling);
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530406 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
David Brownell7a360712009-06-25 17:01:31 -0700407 ? &g->set_rising : &g->clr_rising);
408
409 return 0;
410}
411
Lad, Prabhakar9211ff32013-11-21 23:45:27 +0530412static int
413davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
414 irq_hw_number_t hw)
415{
416 struct davinci_gpio_regs __iomem *g = gpio2regs(hw);
417
418 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
419 "davinci_gpio");
420 irq_set_irq_type(irq, IRQ_TYPE_NONE);
421 irq_set_chip_data(irq, (__force void *)g);
422 irq_set_handler_data(irq, (void *)__gpio_mask(hw));
Lad, Prabhakar9211ff32013-11-21 23:45:27 +0530423
424 return 0;
425}
426
427static const struct irq_domain_ops davinci_gpio_irq_ops = {
428 .map = davinci_gpio_irq_map,
429 .xlate = irq_domain_xlate_onetwocell,
430};
431
Grygorii Strashko0c6feb02014-02-13 17:58:45 +0200432static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
433{
434 static struct irq_chip_type gpio_unbanked;
435
436 gpio_unbanked = *container_of(irq_get_chip(irq),
437 struct irq_chip_type, chip);
438
439 return &gpio_unbanked.chip;
440};
441
442static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
443{
444 static struct irq_chip gpio_unbanked;
445
446 gpio_unbanked = *irq_get_chip(irq);
447 return &gpio_unbanked;
448};
449
450static const struct of_device_id davinci_gpio_ids[];
451
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100452/*
David Brownell474dad52008-12-07 11:46:23 -0800453 * NOTE: for suspend/resume, probably best to make a platform_device with
454 * suspend_late/resume_resume calls hooking into results of the set_wake()
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100455 * calls ... so if no gpios are wakeup events the clock can be disabled,
456 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
David Brownell474dad52008-12-07 11:46:23 -0800457 * (dm6446) can be set appropriately for GPIOV33 pins.
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100458 */
459
KV Sujith118150f2013-08-18 10:48:58 +0530460static int davinci_gpio_irq_setup(struct platform_device *pdev)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100461{
Alexander Shiyan58c0f5a2014-02-15 17:12:05 +0400462 unsigned gpio, bank;
463 int irq;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100464 struct clk *clk;
David Brownell474dad52008-12-07 11:46:23 -0800465 u32 binten = 0;
Mark A. Greera9949552009-04-15 12:40:35 -0700466 unsigned ngpio, bank_irq;
KV Sujith118150f2013-08-18 10:48:58 +0530467 struct device *dev = &pdev->dev;
468 struct resource *res;
469 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
470 struct davinci_gpio_platform_data *pdata = dev->platform_data;
471 struct davinci_gpio_regs __iomem *g;
Grygorii Strashko6075a8b2013-12-18 12:07:51 +0200472 struct irq_domain *irq_domain = NULL;
Grygorii Strashko0c6feb02014-02-13 17:58:45 +0200473 const struct of_device_id *match;
474 struct irq_chip *irq_chip;
475 gpio_get_irq_chip_cb_t gpio_get_irq_chip;
476
477 /*
478 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
479 */
480 gpio_get_irq_chip = davinci_gpio_get_irq_chip;
481 match = of_match_device(of_match_ptr(davinci_gpio_ids),
482 dev);
483 if (match)
484 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
David Brownell474dad52008-12-07 11:46:23 -0800485
KV Sujith118150f2013-08-18 10:48:58 +0530486 ngpio = pdata->ngpio;
487 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
488 if (!res) {
489 dev_err(dev, "Invalid IRQ resource\n");
490 return -EBUSY;
David Brownell474dad52008-12-07 11:46:23 -0800491 }
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100492
KV Sujith118150f2013-08-18 10:48:58 +0530493 bank_irq = res->start;
494
495 if (!bank_irq) {
496 dev_err(dev, "Invalid IRQ resource\n");
497 return -ENODEV;
498 }
499
500 clk = devm_clk_get(dev, "gpio");
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100501 if (IS_ERR(clk)) {
502 printk(KERN_ERR "Error %ld getting gpio clock?\n",
503 PTR_ERR(clk));
David Brownell474dad52008-12-07 11:46:23 -0800504 return PTR_ERR(clk);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100505 }
Murali Karicherice6b6582012-08-30 14:03:57 -0400506 clk_prepare_enable(clk);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100507
Grygorii Strashko6075a8b2013-12-18 12:07:51 +0200508 if (!pdata->gpio_unbanked) {
509 irq = irq_alloc_descs(-1, 0, ngpio, 0);
510 if (irq < 0) {
511 dev_err(dev, "Couldn't allocate IRQ numbers\n");
512 return irq;
513 }
Lad, Prabhakar9211ff32013-11-21 23:45:27 +0530514
Keerthy310a7e62016-01-28 19:08:50 +0530515 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
Grygorii Strashko6075a8b2013-12-18 12:07:51 +0200516 &davinci_gpio_irq_ops,
517 chips);
518 if (!irq_domain) {
519 dev_err(dev, "Couldn't register an IRQ domain\n");
520 return -ENODEV;
521 }
Lad, Prabhakar9211ff32013-11-21 23:45:27 +0530522 }
523
Philip Avinash131a10a2013-08-18 10:48:57 +0530524 /*
525 * Arrange gpio_to_irq() support, handling either direct IRQs or
David Brownell7a360712009-06-25 17:01:31 -0700526 * banked IRQs. Having GPIOs in the first GPIO bank use direct
527 * IRQs, while the others use banked IRQs, would need some setup
528 * tweaks to recognize hardware which can do that.
529 */
530 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
531 chips[bank].chip.to_irq = gpio_to_irq_banked;
Grygorii Strashko6075a8b2013-12-18 12:07:51 +0200532 chips[bank].irq_domain = irq_domain;
David Brownell7a360712009-06-25 17:01:31 -0700533 }
534
535 /*
536 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
537 * controller only handling trigger modes. We currently assume no
538 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
539 */
KV Sujith118150f2013-08-18 10:48:58 +0530540 if (pdata->gpio_unbanked) {
David Brownell7a360712009-06-25 17:01:31 -0700541 /* pass "bank 0" GPIO IRQs to AINTC */
542 chips[0].chip.to_irq = gpio_to_irq_unbanked;
Lad, Prabhakar34af1ab2013-11-08 12:15:55 +0530543 chips[0].gpio_irq = bank_irq;
544 chips[0].gpio_unbanked = pdata->gpio_unbanked;
Vitaly Andrianov3685bbc2015-07-02 14:31:30 -0400545 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
David Brownell7a360712009-06-25 17:01:31 -0700546
547 /* AINTC handles mask/unmask; GPIO handles triggering */
548 irq = bank_irq;
Grygorii Strashko0c6feb02014-02-13 17:58:45 +0200549 irq_chip = gpio_get_irq_chip(irq);
550 irq_chip->name = "GPIO-AINTC";
551 irq_chip->irq_set_type = gpio_irq_type_unbanked;
David Brownell7a360712009-06-25 17:01:31 -0700552
553 /* default trigger: both edges */
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400554 g = gpio2regs(0);
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530555 writel_relaxed(~0, &g->set_falling);
556 writel_relaxed(~0, &g->set_rising);
David Brownell7a360712009-06-25 17:01:31 -0700557
558 /* set the direct IRQs up to use that irqchip */
KV Sujith118150f2013-08-18 10:48:58 +0530559 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
Grygorii Strashko0c6feb02014-02-13 17:58:45 +0200560 irq_set_chip(irq, irq_chip);
Sekhar Noriab2dde92012-03-11 18:16:11 +0530561 irq_set_handler_data(irq, &chips[gpio / 32]);
Thomas Gleixner5093aec2011-03-24 12:47:04 +0100562 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
David Brownell7a360712009-06-25 17:01:31 -0700563 }
564
565 goto done;
566 }
567
568 /*
569 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
570 * then chain through our own handler.
571 */
Lad, Prabhakar9211ff32013-11-21 23:45:27 +0530572 for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) {
David Brownell7a360712009-06-25 17:01:31 -0700573 /* disabled by default, enabled only as needed */
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400574 g = gpio2regs(gpio);
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530575 writel_relaxed(~0, &g->clr_falling);
576 writel_relaxed(~0, &g->clr_rising);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100577
Ido Yarivf299bb92011-07-12 00:03:11 +0300578 /*
579 * Each chip handles 32 gpios, and each irq bank consists of 16
580 * gpio irqs. Pass the irq bank's corresponding controller to
581 * the chained irq handler.
582 */
Thomas Gleixnerbdac2b62015-07-13 23:22:44 +0200583 irq_set_chained_handler_and_data(bank_irq, gpio_irq_handler,
584 &chips[gpio / 32]);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100585
David Brownell474dad52008-12-07 11:46:23 -0800586 binten |= BIT(bank);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100587 }
588
David Brownell7a360712009-06-25 17:01:31 -0700589done:
Philip Avinash131a10a2013-08-18 10:48:57 +0530590 /*
591 * BINTEN -- per-bank interrupt enable. genirq would also let these
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100592 * bits be set/cleared dynamically.
593 */
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530594 writel_relaxed(binten, gpio_base + BINTEN);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100595
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100596 return 0;
597}
KV Sujith118150f2013-08-18 10:48:58 +0530598
KV Sujithc7708442013-11-21 23:45:29 +0530599#if IS_ENABLED(CONFIG_OF)
600static const struct of_device_id davinci_gpio_ids[] = {
Grygorii Strashko0c6feb02014-02-13 17:58:45 +0200601 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
602 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
KV Sujithc7708442013-11-21 23:45:29 +0530603 { /* sentinel */ },
604};
605MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
606#endif
607
KV Sujith118150f2013-08-18 10:48:58 +0530608static struct platform_driver davinci_gpio_driver = {
609 .probe = davinci_gpio_probe,
610 .driver = {
KV Sujithc7708442013-11-21 23:45:29 +0530611 .name = "davinci_gpio",
KV Sujithc7708442013-11-21 23:45:29 +0530612 .of_match_table = of_match_ptr(davinci_gpio_ids),
KV Sujith118150f2013-08-18 10:48:58 +0530613 },
614};
615
616/**
617 * GPIO driver registration needs to be done before machine_init functions
618 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
619 */
620static int __init davinci_gpio_drv_reg(void)
621{
622 return platform_driver_register(&davinci_gpio_driver);
623}
624postcore_initcall(davinci_gpio_drv_reg);