Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 1 | |
| 2 | /* |
| 3 | * Copyright 2013 Freescale Semiconductor, Inc. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | */ |
| 10 | |
Shawn Guo | e164153 | 2013-02-20 10:32:52 +0800 | [diff] [blame] | 11 | #include "imx6q-pinfunc.h" |
Shawn Guo | c56009b2f | 2013-07-11 13:58:36 +0800 | [diff] [blame] | 12 | #include "imx6qdl.dtsi" |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 13 | |
| 14 | / { |
| 15 | cpus { |
| 16 | #address-cells = <1>; |
| 17 | #size-cells = <0>; |
| 18 | |
| 19 | cpu@0 { |
| 20 | compatible = "arm,cortex-a9"; |
Lorenzo Pieralisi | 7925e89 | 2013-04-18 18:34:06 +0100 | [diff] [blame] | 21 | device_type = "cpu"; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 22 | reg = <0>; |
| 23 | next-level-cache = <&L2>; |
| 24 | operating-points = < |
| 25 | /* kHz uV */ |
| 26 | 1200000 1275000 |
| 27 | 996000 1250000 |
| 28 | 792000 1150000 |
| 29 | 396000 950000 |
| 30 | >; |
| 31 | clock-latency = <61036>; /* two CLK32 periods */ |
| 32 | clocks = <&clks 104>, <&clks 6>, <&clks 16>, |
| 33 | <&clks 17>, <&clks 170>; |
| 34 | clock-names = "arm", "pll2_pfd2_396m", "step", |
| 35 | "pll1_sw", "pll1_sys"; |
| 36 | arm-supply = <®_arm>; |
| 37 | pu-supply = <®_pu>; |
| 38 | soc-supply = <®_soc>; |
| 39 | }; |
| 40 | |
| 41 | cpu@1 { |
| 42 | compatible = "arm,cortex-a9"; |
Lorenzo Pieralisi | 7925e89 | 2013-04-18 18:34:06 +0100 | [diff] [blame] | 43 | device_type = "cpu"; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 44 | reg = <1>; |
| 45 | next-level-cache = <&L2>; |
| 46 | }; |
| 47 | |
| 48 | cpu@2 { |
| 49 | compatible = "arm,cortex-a9"; |
Lorenzo Pieralisi | 7925e89 | 2013-04-18 18:34:06 +0100 | [diff] [blame] | 50 | device_type = "cpu"; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 51 | reg = <2>; |
| 52 | next-level-cache = <&L2>; |
| 53 | }; |
| 54 | |
| 55 | cpu@3 { |
| 56 | compatible = "arm,cortex-a9"; |
Lorenzo Pieralisi | 7925e89 | 2013-04-18 18:34:06 +0100 | [diff] [blame] | 57 | device_type = "cpu"; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 58 | reg = <3>; |
| 59 | next-level-cache = <&L2>; |
| 60 | }; |
| 61 | }; |
| 62 | |
| 63 | soc { |
Shawn Guo | 951ebf5 | 2013-07-23 15:25:13 +0800 | [diff] [blame] | 64 | ocram: sram@00900000 { |
| 65 | compatible = "mmio-sram"; |
| 66 | reg = <0x00900000 0x40000>; |
| 67 | clocks = <&clks 142>; |
| 68 | }; |
| 69 | |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 70 | aips-bus@02000000 { /* AIPS1 */ |
| 71 | spba-bus@02000000 { |
| 72 | ecspi5: ecspi@02018000 { |
| 73 | #address-cells = <1>; |
| 74 | #size-cells = <0>; |
| 75 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 76 | reg = <0x02018000 0x4000>; |
| 77 | interrupts = <0 35 0x04>; |
| 78 | clocks = <&clks 116>, <&clks 116>; |
| 79 | clock-names = "ipg", "per"; |
| 80 | status = "disabled"; |
| 81 | }; |
| 82 | }; |
| 83 | |
| 84 | iomuxc: iomuxc@020e0000 { |
| 85 | compatible = "fsl,imx6q-iomuxc"; |
Shawn Guo | b72ce92 | 2013-07-12 11:38:50 +0800 | [diff] [blame] | 86 | |
| 87 | ipu2 { |
| 88 | pinctrl_ipu2_1: ipu2grp-1 { |
| 89 | fsl,pins = < |
| 90 | MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10 |
| 91 | MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10 |
| 92 | MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10 |
| 93 | MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10 |
| 94 | MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000 |
| 95 | MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10 |
| 96 | MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10 |
| 97 | MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10 |
| 98 | MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10 |
| 99 | MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10 |
| 100 | MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10 |
| 101 | MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10 |
| 102 | MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10 |
| 103 | MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10 |
| 104 | MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10 |
| 105 | MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10 |
| 106 | MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10 |
| 107 | MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10 |
| 108 | MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10 |
| 109 | MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10 |
| 110 | MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10 |
| 111 | MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10 |
| 112 | MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10 |
| 113 | MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10 |
| 114 | MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10 |
| 115 | MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10 |
| 116 | MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10 |
| 117 | MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10 |
| 118 | MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10 |
| 119 | >; |
| 120 | }; |
| 121 | }; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 122 | }; |
| 123 | }; |
| 124 | |
Richard Zhu | 0fb1f80 | 2013-07-16 11:28:46 +0800 | [diff] [blame] | 125 | sata: sata@02200000 { |
| 126 | compatible = "fsl,imx6q-ahci"; |
| 127 | reg = <0x02200000 0x4000>; |
| 128 | interrupts = <0 39 0x04>; |
| 129 | clocks = <&clks 154>, <&clks 187>, <&clks 105>; |
| 130 | clock-names = "sata", "sata_ref", "ahb"; |
| 131 | status = "disabled"; |
| 132 | }; |
| 133 | |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 134 | ipu2: ipu@02800000 { |
Philipp Zabel | 4520e69 | 2014-03-05 10:21:01 +0100 | [diff] [blame^] | 135 | #address-cells = <1>; |
| 136 | #size-cells = <0>; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 137 | compatible = "fsl,imx6q-ipu"; |
| 138 | reg = <0x02800000 0x400000>; |
| 139 | interrupts = <0 8 0x4 0 7 0x4>; |
| 140 | clocks = <&clks 133>, <&clks 134>, <&clks 137>; |
| 141 | clock-names = "bus", "di0", "di1"; |
Philipp Zabel | 09ebf36 | 2013-03-28 17:35:20 +0100 | [diff] [blame] | 142 | resets = <&src 4>; |
Philipp Zabel | 4520e69 | 2014-03-05 10:21:01 +0100 | [diff] [blame^] | 143 | |
| 144 | ipu2_di0: port@2 { |
| 145 | #address-cells = <1>; |
| 146 | #size-cells = <0>; |
| 147 | reg = <2>; |
| 148 | |
| 149 | ipu2_di0_disp0: endpoint@0 { |
| 150 | }; |
| 151 | |
| 152 | ipu2_di0_hdmi: endpoint@1 { |
| 153 | remote-endpoint = <&hdmi_mux_2>; |
| 154 | }; |
| 155 | |
| 156 | ipu2_di0_mipi: endpoint@2 { |
| 157 | }; |
| 158 | |
| 159 | ipu2_di0_lvds0: endpoint@3 { |
| 160 | remote-endpoint = <&lvds0_mux_2>; |
| 161 | }; |
| 162 | |
| 163 | ipu2_di0_lvds1: endpoint@4 { |
| 164 | remote-endpoint = <&lvds1_mux_2>; |
| 165 | }; |
| 166 | }; |
| 167 | |
| 168 | ipu2_di1: port@3 { |
| 169 | #address-cells = <1>; |
| 170 | #size-cells = <0>; |
| 171 | reg = <3>; |
| 172 | |
| 173 | ipu2_di1_hdmi: endpoint@1 { |
| 174 | remote-endpoint = <&hdmi_mux_3>; |
| 175 | }; |
| 176 | |
| 177 | ipu2_di1_mipi: endpoint@2 { |
| 178 | }; |
| 179 | |
| 180 | ipu2_di1_lvds0: endpoint@3 { |
| 181 | remote-endpoint = <&lvds0_mux_3>; |
| 182 | }; |
| 183 | |
| 184 | ipu2_di1_lvds1: endpoint@4 { |
| 185 | remote-endpoint = <&lvds1_mux_3>; |
| 186 | }; |
| 187 | }; |
| 188 | }; |
| 189 | }; |
| 190 | |
| 191 | display-subsystem { |
| 192 | compatible = "fsl,imx-display-subsystem"; |
| 193 | ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; |
| 194 | }; |
| 195 | }; |
| 196 | |
| 197 | &hdmi { |
| 198 | compatible = "fsl,imx6q-hdmi"; |
| 199 | |
| 200 | port@2 { |
| 201 | reg = <2>; |
| 202 | |
| 203 | hdmi_mux_2: endpoint { |
| 204 | remote-endpoint = <&ipu2_di0_hdmi>; |
| 205 | }; |
| 206 | }; |
| 207 | |
| 208 | port@3 { |
| 209 | reg = <3>; |
| 210 | |
| 211 | hdmi_mux_3: endpoint { |
| 212 | remote-endpoint = <&ipu2_di1_hdmi>; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 213 | }; |
| 214 | }; |
| 215 | }; |
Steffen Trumtrar | 41c0434 | 2013-03-28 16:23:35 +0100 | [diff] [blame] | 216 | |
| 217 | &ldb { |
| 218 | clocks = <&clks 33>, <&clks 34>, |
| 219 | <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>, |
| 220 | <&clks 135>, <&clks 136>; |
| 221 | clock-names = "di0_pll", "di1_pll", |
| 222 | "di0_sel", "di1_sel", "di2_sel", "di3_sel", |
| 223 | "di0", "di1"; |
| 224 | |
| 225 | lvds-channel@0 { |
Philipp Zabel | 4520e69 | 2014-03-05 10:21:01 +0100 | [diff] [blame^] | 226 | port@2 { |
| 227 | reg = <2>; |
| 228 | |
| 229 | lvds0_mux_2: endpoint { |
| 230 | remote-endpoint = <&ipu2_di0_lvds0>; |
| 231 | }; |
| 232 | }; |
| 233 | |
| 234 | port@3 { |
| 235 | reg = <3>; |
| 236 | |
| 237 | lvds0_mux_3: endpoint { |
| 238 | remote-endpoint = <&ipu2_di1_lvds0>; |
| 239 | }; |
| 240 | }; |
Steffen Trumtrar | 41c0434 | 2013-03-28 16:23:35 +0100 | [diff] [blame] | 241 | }; |
| 242 | |
| 243 | lvds-channel@1 { |
Philipp Zabel | 4520e69 | 2014-03-05 10:21:01 +0100 | [diff] [blame^] | 244 | port@2 { |
| 245 | reg = <2>; |
| 246 | |
| 247 | lvds1_mux_2: endpoint { |
| 248 | remote-endpoint = <&ipu2_di0_lvds1>; |
| 249 | }; |
| 250 | }; |
| 251 | |
| 252 | port@3 { |
| 253 | reg = <3>; |
| 254 | |
| 255 | lvds1_mux_3: endpoint { |
| 256 | remote-endpoint = <&ipu2_di1_lvds1>; |
| 257 | }; |
| 258 | }; |
Steffen Trumtrar | 41c0434 | 2013-03-28 16:23:35 +0100 | [diff] [blame] | 259 | }; |
| 260 | }; |
Russell King | 04cec1a | 2013-10-16 10:19:00 +0100 | [diff] [blame] | 261 | |
Philipp Zabel | 4520e69 | 2014-03-05 10:21:01 +0100 | [diff] [blame^] | 262 | &mipi_dsi { |
| 263 | port@2 { |
| 264 | reg = <2>; |
| 265 | |
| 266 | mipi_mux_2: endpoint { |
| 267 | remote-endpoint = <&ipu2_di0_mipi>; |
| 268 | }; |
| 269 | }; |
| 270 | |
| 271 | port@3 { |
| 272 | reg = <3>; |
| 273 | |
| 274 | mipi_mux_3: endpoint { |
| 275 | remote-endpoint = <&ipu2_di1_mipi>; |
| 276 | }; |
| 277 | }; |
Russell King | 04cec1a | 2013-10-16 10:19:00 +0100 | [diff] [blame] | 278 | }; |