Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1 | /* |
| 2 | * sata_mv.c - Marvell SATA support |
| 3 | * |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 4 | * Copyright 2005: EMC Corporation, all rights reserved. |
Jeff Garzik | e2b1be5 | 2005-11-18 14:04:23 -0500 | [diff] [blame] | 5 | * Copyright 2005 Red Hat, Inc. All rights reserved. |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 6 | * |
| 7 | * Please ALWAYS copy linux-ide@vger.kernel.org on emails. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | * |
| 22 | */ |
| 23 | |
Jeff Garzik | 4a05e20 | 2007-05-24 23:40:15 -0400 | [diff] [blame] | 24 | /* |
| 25 | sata_mv TODO list: |
| 26 | |
| 27 | 1) Needs a full errata audit for all chipsets. I implemented most |
| 28 | of the errata workarounds found in the Marvell vendor driver, but |
| 29 | I distinctly remember a couple workarounds (one related to PCI-X) |
| 30 | are still needed. |
| 31 | |
| 32 | 2) Convert to LibATA new EH. Required for hotplug, NCQ, and sane |
| 33 | probing/error handling in general. MUST HAVE. |
| 34 | |
| 35 | 3) Add hotplug support (easy, once new-EH support appears) |
| 36 | |
| 37 | 4) Add NCQ support (easy to intermediate, once new-EH support appears) |
| 38 | |
| 39 | 5) Investigate problems with PCI Message Signalled Interrupts (MSI). |
| 40 | |
| 41 | 6) Add port multiplier support (intermediate) |
| 42 | |
| 43 | 7) Test and verify 3.0 Gbps support |
| 44 | |
| 45 | 8) Develop a low-power-consumption strategy, and implement it. |
| 46 | |
| 47 | 9) [Experiment, low priority] See if ATAPI can be supported using |
| 48 | "unknown FIS" or "vendor-specific FIS" support, or something creative |
| 49 | like that. |
| 50 | |
| 51 | 10) [Experiment, low priority] Investigate interrupt coalescing. |
| 52 | Quite often, especially with PCI Message Signalled Interrupts (MSI), |
| 53 | the overhead reduced by interrupt mitigation is quite often not |
| 54 | worth the latency cost. |
| 55 | |
| 56 | 11) [Experiment, Marvell value added] Is it possible to use target |
| 57 | mode to cross-connect two Linux boxes with Marvell cards? If so, |
| 58 | creating LibATA target mode support would be very interesting. |
| 59 | |
| 60 | Target mode, for those without docs, is the ability to directly |
| 61 | connect two SATA controllers. |
| 62 | |
| 63 | 13) Verify that 7042 is fully supported. I only have a 6042. |
| 64 | |
| 65 | */ |
| 66 | |
| 67 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 68 | #include <linux/kernel.h> |
| 69 | #include <linux/module.h> |
| 70 | #include <linux/pci.h> |
| 71 | #include <linux/init.h> |
| 72 | #include <linux/blkdev.h> |
| 73 | #include <linux/delay.h> |
| 74 | #include <linux/interrupt.h> |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 75 | #include <linux/dma-mapping.h> |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 76 | #include <linux/device.h> |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 77 | #include <scsi/scsi_host.h> |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 78 | #include <scsi/scsi_cmnd.h> |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 79 | #include <linux/libata.h> |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 80 | |
| 81 | #define DRV_NAME "sata_mv" |
Jeff Garzik | 8bc3fc4 | 2007-05-21 20:26:38 -0400 | [diff] [blame] | 82 | #define DRV_VERSION "0.81" |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 83 | |
| 84 | enum { |
| 85 | /* BAR's are enumerated in terms of pci_resource_start() terms */ |
| 86 | MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ |
| 87 | MV_IO_BAR = 2, /* offset 0x18: IO space */ |
| 88 | MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ |
| 89 | |
| 90 | MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ |
| 91 | MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ |
| 92 | |
| 93 | MV_PCI_REG_BASE = 0, |
| 94 | MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ |
Mark Lord | 615ab95 | 2006-05-19 16:24:56 -0400 | [diff] [blame] | 95 | MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08), |
| 96 | MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88), |
| 97 | MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c), |
| 98 | MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc), |
| 99 | MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0), |
| 100 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 101 | MV_SATAHC0_REG_BASE = 0x20000, |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 102 | MV_FLASH_CTL = 0x1046c, |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 103 | MV_GPIO_PORT_CTL = 0x104f0, |
| 104 | MV_RESET_CFG = 0x180d8, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 105 | |
| 106 | MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, |
| 107 | MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, |
| 108 | MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ |
| 109 | MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, |
| 110 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 111 | MV_MAX_Q_DEPTH = 32, |
| 112 | MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, |
| 113 | |
| 114 | /* CRQB needs alignment on a 1KB boundary. Size == 1KB |
| 115 | * CRPB needs alignment on a 256B boundary. Size == 256B |
| 116 | * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB |
| 117 | * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B |
| 118 | */ |
| 119 | MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), |
| 120 | MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), |
| 121 | MV_MAX_SG_CT = 176, |
| 122 | MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), |
| 123 | MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ), |
| 124 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 125 | MV_PORTS_PER_HC = 4, |
| 126 | /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */ |
| 127 | MV_PORT_HC_SHIFT = 2, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 128 | /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 129 | MV_PORT_MASK = 3, |
| 130 | |
| 131 | /* Host Flags */ |
| 132 | MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ |
| 133 | MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 134 | MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
| 135 | ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO | |
| 136 | ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 137 | MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 138 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 139 | CRQB_FLAG_READ = (1 << 0), |
| 140 | CRQB_TAG_SHIFT = 1, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 141 | CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ |
| 142 | CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 143 | CRQB_CMD_ADDR_SHIFT = 8, |
| 144 | CRQB_CMD_CS = (0x2 << 11), |
| 145 | CRQB_CMD_LAST = (1 << 15), |
| 146 | |
| 147 | CRPB_FLAG_STATUS_SHIFT = 8, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 148 | CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ |
| 149 | CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 150 | |
| 151 | EPRD_FLAG_END_OF_TBL = (1 << 31), |
| 152 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 153 | /* PCI interface registers */ |
| 154 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 155 | PCI_COMMAND_OFS = 0xc00, |
| 156 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 157 | PCI_MAIN_CMD_STS_OFS = 0xd30, |
| 158 | STOP_PCI_MASTER = (1 << 2), |
| 159 | PCI_MASTER_EMPTY = (1 << 3), |
| 160 | GLOB_SFT_RST = (1 << 4), |
| 161 | |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 162 | MV_PCI_MODE = 0xd00, |
| 163 | MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, |
| 164 | MV_PCI_DISC_TIMER = 0xd04, |
| 165 | MV_PCI_MSI_TRIGGER = 0xc38, |
| 166 | MV_PCI_SERR_MASK = 0xc28, |
| 167 | MV_PCI_XBAR_TMOUT = 0x1d04, |
| 168 | MV_PCI_ERR_LOW_ADDRESS = 0x1d40, |
| 169 | MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, |
| 170 | MV_PCI_ERR_ATTRIBUTE = 0x1d48, |
| 171 | MV_PCI_ERR_COMMAND = 0x1d50, |
| 172 | |
| 173 | PCI_IRQ_CAUSE_OFS = 0x1d58, |
| 174 | PCI_IRQ_MASK_OFS = 0x1d5c, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 175 | PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ |
| 176 | |
| 177 | HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, |
| 178 | HC_MAIN_IRQ_MASK_OFS = 0x1d64, |
| 179 | PORT0_ERR = (1 << 0), /* shift by port # */ |
| 180 | PORT0_DONE = (1 << 1), /* shift by port # */ |
| 181 | HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ |
| 182 | HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ |
| 183 | PCI_ERR = (1 << 18), |
| 184 | TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */ |
| 185 | TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */ |
Jeff Garzik | fb621e2 | 2007-02-25 04:19:45 -0500 | [diff] [blame] | 186 | PORTS_0_3_COAL_DONE = (1 << 8), |
| 187 | PORTS_4_7_COAL_DONE = (1 << 17), |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 188 | PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */ |
| 189 | GPIO_INT = (1 << 22), |
| 190 | SELF_INT = (1 << 23), |
| 191 | TWSI_INT = (1 << 24), |
| 192 | HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ |
Jeff Garzik | fb621e2 | 2007-02-25 04:19:45 -0500 | [diff] [blame] | 193 | HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 194 | HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 195 | PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT | |
| 196 | HC_MAIN_RSVD), |
Jeff Garzik | fb621e2 | 2007-02-25 04:19:45 -0500 | [diff] [blame] | 197 | HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | |
| 198 | HC_MAIN_RSVD_5), |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 199 | |
| 200 | /* SATAHC registers */ |
| 201 | HC_CFG_OFS = 0, |
| 202 | |
| 203 | HC_IRQ_CAUSE_OFS = 0x14, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 204 | CRPB_DMA_DONE = (1 << 0), /* shift by port # */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 205 | HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */ |
| 206 | DEV_IRQ = (1 << 8), /* shift by port # */ |
| 207 | |
| 208 | /* Shadow block registers */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 209 | SHD_BLK_OFS = 0x100, |
| 210 | SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 211 | |
| 212 | /* SATA registers */ |
| 213 | SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ |
| 214 | SATA_ACTIVE_OFS = 0x350, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 215 | PHY_MODE3 = 0x310, |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 216 | PHY_MODE4 = 0x314, |
| 217 | PHY_MODE2 = 0x330, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 218 | MV5_PHY_MODE = 0x74, |
| 219 | MV5_LT_MODE = 0x30, |
| 220 | MV5_PHY_CTL = 0x0C, |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 221 | SATA_INTERFACE_CTL = 0x050, |
| 222 | |
| 223 | MV_M2_PREAMP_MASK = 0x7e0, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 224 | |
| 225 | /* Port registers */ |
| 226 | EDMA_CFG_OFS = 0, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 227 | EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */ |
| 228 | EDMA_CFG_NCQ = (1 << 5), |
| 229 | EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ |
| 230 | EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ |
| 231 | EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 232 | |
| 233 | EDMA_ERR_IRQ_CAUSE_OFS = 0x8, |
| 234 | EDMA_ERR_IRQ_MASK_OFS = 0xc, |
| 235 | EDMA_ERR_D_PAR = (1 << 0), |
| 236 | EDMA_ERR_PRD_PAR = (1 << 1), |
| 237 | EDMA_ERR_DEV = (1 << 2), |
| 238 | EDMA_ERR_DEV_DCON = (1 << 3), |
| 239 | EDMA_ERR_DEV_CON = (1 << 4), |
| 240 | EDMA_ERR_SERR = (1 << 5), |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 241 | EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ |
| 242 | EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 243 | EDMA_ERR_BIST_ASYNC = (1 << 8), |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 244 | EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 245 | EDMA_ERR_CRBQ_PAR = (1 << 9), |
| 246 | EDMA_ERR_CRPB_PAR = (1 << 10), |
| 247 | EDMA_ERR_INTRL_PAR = (1 << 11), |
| 248 | EDMA_ERR_IORDY = (1 << 12), |
| 249 | EDMA_ERR_LNK_CTRL_RX = (0xf << 13), |
| 250 | EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), |
| 251 | EDMA_ERR_LNK_DATA_RX = (0xf << 17), |
| 252 | EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), |
| 253 | EDMA_ERR_LNK_DATA_TX = (0x1f << 26), |
| 254 | EDMA_ERR_TRANS_PROTO = (1 << 31), |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 255 | EDMA_ERR_OVERRUN_5 = (1 << 5), |
| 256 | EDMA_ERR_UNDERRUN_5 = (1 << 6), |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 257 | EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 258 | EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR | |
| 259 | EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR | |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 260 | EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 261 | EDMA_ERR_LNK_DATA_RX | |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 262 | EDMA_ERR_LNK_DATA_TX | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 263 | EDMA_ERR_TRANS_PROTO), |
| 264 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 265 | EDMA_REQ_Q_BASE_HI_OFS = 0x10, |
| 266 | EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 267 | |
| 268 | EDMA_REQ_Q_OUT_PTR_OFS = 0x18, |
| 269 | EDMA_REQ_Q_PTR_SHIFT = 5, |
| 270 | |
| 271 | EDMA_RSP_Q_BASE_HI_OFS = 0x1c, |
| 272 | EDMA_RSP_Q_IN_PTR_OFS = 0x20, |
| 273 | EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 274 | EDMA_RSP_Q_PTR_SHIFT = 3, |
| 275 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 276 | EDMA_CMD_OFS = 0x28, |
| 277 | EDMA_EN = (1 << 0), |
| 278 | EDMA_DS = (1 << 1), |
| 279 | ATA_RST = (1 << 2), |
| 280 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 281 | EDMA_IORDY_TMOUT = 0x34, |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 282 | EDMA_ARB_CFG = 0x38, |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 283 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 284 | /* Host private flags (hp_flags) */ |
| 285 | MV_HP_FLAG_MSI = (1 << 0), |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 286 | MV_HP_ERRATA_50XXB0 = (1 << 1), |
| 287 | MV_HP_ERRATA_50XXB2 = (1 << 2), |
| 288 | MV_HP_ERRATA_60X1B2 = (1 << 3), |
| 289 | MV_HP_ERRATA_60X1C0 = (1 << 4), |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 290 | MV_HP_ERRATA_XX42A0 = (1 << 5), |
| 291 | MV_HP_50XX = (1 << 6), |
| 292 | MV_HP_GEN_IIE = (1 << 7), |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 293 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 294 | /* Port private flags (pp_flags) */ |
| 295 | MV_PP_FLAG_EDMA_EN = (1 << 0), |
| 296 | MV_PP_FLAG_EDMA_DS_ACT = (1 << 1), |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 297 | MV_PP_FLAG_HAD_A_RESET = (1 << 2), |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 298 | }; |
| 299 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 300 | #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX) |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 301 | #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0) |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 302 | #define IS_GEN_I(hpriv) IS_50XX(hpriv) |
| 303 | #define IS_GEN_II(hpriv) IS_60XX(hpriv) |
| 304 | #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 305 | |
Jeff Garzik | 095fec8 | 2005-11-12 09:50:49 -0500 | [diff] [blame] | 306 | enum { |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 307 | MV_DMA_BOUNDARY = 0xffffffffU, |
Jeff Garzik | 095fec8 | 2005-11-12 09:50:49 -0500 | [diff] [blame] | 308 | |
| 309 | EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, |
| 310 | |
| 311 | EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, |
| 312 | }; |
| 313 | |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 314 | enum chip_type { |
| 315 | chip_504x, |
| 316 | chip_508x, |
| 317 | chip_5080, |
| 318 | chip_604x, |
| 319 | chip_608x, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 320 | chip_6042, |
| 321 | chip_7042, |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 322 | }; |
| 323 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 324 | /* Command ReQuest Block: 32B */ |
| 325 | struct mv_crqb { |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 326 | __le32 sg_addr; |
| 327 | __le32 sg_addr_hi; |
| 328 | __le16 ctrl_flags; |
| 329 | __le16 ata_cmd[11]; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 330 | }; |
| 331 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 332 | struct mv_crqb_iie { |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 333 | __le32 addr; |
| 334 | __le32 addr_hi; |
| 335 | __le32 flags; |
| 336 | __le32 len; |
| 337 | __le32 ata_cmd[4]; |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 338 | }; |
| 339 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 340 | /* Command ResPonse Block: 8B */ |
| 341 | struct mv_crpb { |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 342 | __le16 id; |
| 343 | __le16 flags; |
| 344 | __le32 tmstmp; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 345 | }; |
| 346 | |
| 347 | /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ |
| 348 | struct mv_sg { |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 349 | __le32 addr; |
| 350 | __le32 flags_size; |
| 351 | __le32 addr_hi; |
| 352 | __le32 reserved; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 353 | }; |
| 354 | |
| 355 | struct mv_port_priv { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 356 | struct mv_crqb *crqb; |
| 357 | dma_addr_t crqb_dma; |
| 358 | struct mv_crpb *crpb; |
| 359 | dma_addr_t crpb_dma; |
| 360 | struct mv_sg *sg_tbl; |
| 361 | dma_addr_t sg_tbl_dma; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 362 | u32 pp_flags; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 363 | }; |
| 364 | |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 365 | struct mv_port_signal { |
| 366 | u32 amps; |
| 367 | u32 pre; |
| 368 | }; |
| 369 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 370 | struct mv_host_priv; |
| 371 | struct mv_hw_ops { |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 372 | void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 373 | unsigned int port); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 374 | void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); |
| 375 | void (*read_preamp)(struct mv_host_priv *hpriv, int idx, |
| 376 | void __iomem *mmio); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 377 | int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 378 | unsigned int n_hc); |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 379 | void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); |
| 380 | void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 381 | }; |
| 382 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 383 | struct mv_host_priv { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 384 | u32 hp_flags; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 385 | struct mv_port_signal signal[8]; |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 386 | const struct mv_hw_ops *ops; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 387 | }; |
| 388 | |
| 389 | static void mv_irq_clear(struct ata_port *ap); |
| 390 | static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in); |
| 391 | static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 392 | static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in); |
| 393 | static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 394 | static void mv_phy_reset(struct ata_port *ap); |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 395 | static void __mv_phy_reset(struct ata_port *ap, int can_sleep); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 396 | static int mv_port_start(struct ata_port *ap); |
| 397 | static void mv_port_stop(struct ata_port *ap); |
| 398 | static void mv_qc_prep(struct ata_queued_cmd *qc); |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 399 | static void mv_qc_prep_iie(struct ata_queued_cmd *qc); |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 400 | static unsigned int mv_qc_issue(struct ata_queued_cmd *qc); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 401 | static void mv_eng_timeout(struct ata_port *ap); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 402 | static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
| 403 | |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 404 | static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 405 | unsigned int port); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 406 | static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); |
| 407 | static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, |
| 408 | void __iomem *mmio); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 409 | static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 410 | unsigned int n_hc); |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 411 | static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); |
| 412 | static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 413 | |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 414 | static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 415 | unsigned int port); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 416 | static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); |
| 417 | static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, |
| 418 | void __iomem *mmio); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 419 | static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 420 | unsigned int n_hc); |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 421 | static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); |
| 422 | static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 423 | static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 424 | unsigned int port_no); |
| 425 | static void mv_stop_and_reset(struct ata_port *ap); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 426 | |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 427 | static struct scsi_host_template mv5_sht = { |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 428 | .module = THIS_MODULE, |
| 429 | .name = DRV_NAME, |
| 430 | .ioctl = ata_scsi_ioctl, |
| 431 | .queuecommand = ata_scsi_queuecmd, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 432 | .can_queue = ATA_DEF_QUEUE, |
| 433 | .this_id = ATA_SHT_THIS_ID, |
| 434 | .sg_tablesize = MV_MAX_SG_CT, |
| 435 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 436 | .emulated = ATA_SHT_EMULATED, |
| 437 | .use_clustering = 1, |
| 438 | .proc_name = DRV_NAME, |
| 439 | .dma_boundary = MV_DMA_BOUNDARY, |
| 440 | .slave_configure = ata_scsi_slave_config, |
| 441 | .slave_destroy = ata_scsi_slave_destroy, |
| 442 | .bios_param = ata_std_bios_param, |
| 443 | }; |
| 444 | |
| 445 | static struct scsi_host_template mv6_sht = { |
| 446 | .module = THIS_MODULE, |
| 447 | .name = DRV_NAME, |
| 448 | .ioctl = ata_scsi_ioctl, |
| 449 | .queuecommand = ata_scsi_queuecmd, |
| 450 | .can_queue = ATA_DEF_QUEUE, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 451 | .this_id = ATA_SHT_THIS_ID, |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 452 | .sg_tablesize = MV_MAX_SG_CT, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 453 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 454 | .emulated = ATA_SHT_EMULATED, |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 455 | .use_clustering = 1, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 456 | .proc_name = DRV_NAME, |
| 457 | .dma_boundary = MV_DMA_BOUNDARY, |
| 458 | .slave_configure = ata_scsi_slave_config, |
Tejun Heo | ccf68c3 | 2006-05-31 18:28:09 +0900 | [diff] [blame] | 459 | .slave_destroy = ata_scsi_slave_destroy, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 460 | .bios_param = ata_std_bios_param, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 461 | }; |
| 462 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 463 | static const struct ata_port_operations mv5_ops = { |
| 464 | .port_disable = ata_port_disable, |
| 465 | |
| 466 | .tf_load = ata_tf_load, |
| 467 | .tf_read = ata_tf_read, |
| 468 | .check_status = ata_check_status, |
| 469 | .exec_command = ata_exec_command, |
| 470 | .dev_select = ata_std_dev_select, |
| 471 | |
| 472 | .phy_reset = mv_phy_reset, |
Jeff Garzik | cffacd8 | 2007-03-09 09:46:47 -0500 | [diff] [blame] | 473 | .cable_detect = ata_cable_sata, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 474 | |
| 475 | .qc_prep = mv_qc_prep, |
| 476 | .qc_issue = mv_qc_issue, |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 477 | .data_xfer = ata_data_xfer, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 478 | |
| 479 | .eng_timeout = mv_eng_timeout, |
| 480 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 481 | .irq_clear = mv_irq_clear, |
Akira Iguchi | 246ce3b | 2007-01-26 16:27:58 +0900 | [diff] [blame] | 482 | .irq_on = ata_irq_on, |
| 483 | .irq_ack = ata_irq_ack, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 484 | |
| 485 | .scr_read = mv5_scr_read, |
| 486 | .scr_write = mv5_scr_write, |
| 487 | |
| 488 | .port_start = mv_port_start, |
| 489 | .port_stop = mv_port_stop, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 490 | }; |
| 491 | |
| 492 | static const struct ata_port_operations mv6_ops = { |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 493 | .port_disable = ata_port_disable, |
| 494 | |
| 495 | .tf_load = ata_tf_load, |
| 496 | .tf_read = ata_tf_read, |
| 497 | .check_status = ata_check_status, |
| 498 | .exec_command = ata_exec_command, |
| 499 | .dev_select = ata_std_dev_select, |
| 500 | |
| 501 | .phy_reset = mv_phy_reset, |
Jeff Garzik | cffacd8 | 2007-03-09 09:46:47 -0500 | [diff] [blame] | 502 | .cable_detect = ata_cable_sata, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 503 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 504 | .qc_prep = mv_qc_prep, |
| 505 | .qc_issue = mv_qc_issue, |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 506 | .data_xfer = ata_data_xfer, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 507 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 508 | .eng_timeout = mv_eng_timeout, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 509 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 510 | .irq_clear = mv_irq_clear, |
Akira Iguchi | 246ce3b | 2007-01-26 16:27:58 +0900 | [diff] [blame] | 511 | .irq_on = ata_irq_on, |
| 512 | .irq_ack = ata_irq_ack, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 513 | |
| 514 | .scr_read = mv_scr_read, |
| 515 | .scr_write = mv_scr_write, |
| 516 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 517 | .port_start = mv_port_start, |
| 518 | .port_stop = mv_port_stop, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 519 | }; |
| 520 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 521 | static const struct ata_port_operations mv_iie_ops = { |
| 522 | .port_disable = ata_port_disable, |
| 523 | |
| 524 | .tf_load = ata_tf_load, |
| 525 | .tf_read = ata_tf_read, |
| 526 | .check_status = ata_check_status, |
| 527 | .exec_command = ata_exec_command, |
| 528 | .dev_select = ata_std_dev_select, |
| 529 | |
| 530 | .phy_reset = mv_phy_reset, |
Jeff Garzik | cffacd8 | 2007-03-09 09:46:47 -0500 | [diff] [blame] | 531 | .cable_detect = ata_cable_sata, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 532 | |
| 533 | .qc_prep = mv_qc_prep_iie, |
| 534 | .qc_issue = mv_qc_issue, |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 535 | .data_xfer = ata_data_xfer, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 536 | |
| 537 | .eng_timeout = mv_eng_timeout, |
| 538 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 539 | .irq_clear = mv_irq_clear, |
Akira Iguchi | 246ce3b | 2007-01-26 16:27:58 +0900 | [diff] [blame] | 540 | .irq_on = ata_irq_on, |
| 541 | .irq_ack = ata_irq_ack, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 542 | |
| 543 | .scr_read = mv_scr_read, |
| 544 | .scr_write = mv_scr_write, |
| 545 | |
| 546 | .port_start = mv_port_start, |
| 547 | .port_stop = mv_port_stop, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 548 | }; |
| 549 | |
Arjan van de Ven | 98ac62d | 2005-11-28 10:06:23 +0100 | [diff] [blame] | 550 | static const struct ata_port_info mv_port_info[] = { |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 551 | { /* chip_504x */ |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 552 | .flags = MV_COMMON_FLAGS, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 553 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 554 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 555 | .port_ops = &mv5_ops, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 556 | }, |
| 557 | { /* chip_508x */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 558 | .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 559 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 560 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 561 | .port_ops = &mv5_ops, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 562 | }, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 563 | { /* chip_5080 */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 564 | .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 565 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 566 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 567 | .port_ops = &mv5_ops, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 568 | }, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 569 | { /* chip_604x */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 570 | .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 571 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 572 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 573 | .port_ops = &mv6_ops, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 574 | }, |
| 575 | { /* chip_608x */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 576 | .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | |
| 577 | MV_FLAG_DUAL_HC, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 578 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 579 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 580 | .port_ops = &mv6_ops, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 581 | }, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 582 | { /* chip_6042 */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 583 | .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 584 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 585 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 586 | .port_ops = &mv_iie_ops, |
| 587 | }, |
| 588 | { /* chip_7042 */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 589 | .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 590 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 591 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 592 | .port_ops = &mv_iie_ops, |
| 593 | }, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 594 | }; |
| 595 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 596 | static const struct pci_device_id mv_pci_tbl[] = { |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 597 | { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, |
| 598 | { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, |
| 599 | { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, |
| 600 | { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 601 | |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 602 | { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, |
| 603 | { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, |
| 604 | { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, |
| 605 | { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, |
| 606 | { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, |
Jeff Garzik | 2917953 | 2005-11-11 08:08:03 -0500 | [diff] [blame] | 607 | |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 608 | { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, |
| 609 | |
Florian Attenberger | d9f9c6b | 2007-07-02 17:09:29 +0200 | [diff] [blame] | 610 | /* Adaptec 1430SA */ |
| 611 | { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, |
| 612 | |
Olof Johansson | e93f09d | 2007-01-18 18:39:59 -0600 | [diff] [blame] | 613 | { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, |
| 614 | |
Morrison, Tom | 6a3d586 | 2007-03-06 02:38:10 -0800 | [diff] [blame] | 615 | /* add Marvell 7042 support */ |
| 616 | { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, |
| 617 | |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 618 | { } /* terminate list */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 619 | }; |
| 620 | |
| 621 | static struct pci_driver mv_pci_driver = { |
| 622 | .name = DRV_NAME, |
| 623 | .id_table = mv_pci_tbl, |
| 624 | .probe = mv_init_one, |
| 625 | .remove = ata_pci_remove_one, |
| 626 | }; |
| 627 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 628 | static const struct mv_hw_ops mv5xxx_ops = { |
| 629 | .phy_errata = mv5_phy_errata, |
| 630 | .enable_leds = mv5_enable_leds, |
| 631 | .read_preamp = mv5_read_preamp, |
| 632 | .reset_hc = mv5_reset_hc, |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 633 | .reset_flash = mv5_reset_flash, |
| 634 | .reset_bus = mv5_reset_bus, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 635 | }; |
| 636 | |
| 637 | static const struct mv_hw_ops mv6xxx_ops = { |
| 638 | .phy_errata = mv6_phy_errata, |
| 639 | .enable_leds = mv6_enable_leds, |
| 640 | .read_preamp = mv6_read_preamp, |
| 641 | .reset_hc = mv6_reset_hc, |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 642 | .reset_flash = mv6_reset_flash, |
| 643 | .reset_bus = mv_reset_pci_bus, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 644 | }; |
| 645 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 646 | /* |
Jeff Garzik | ddef9bb | 2006-02-02 16:17:06 -0500 | [diff] [blame] | 647 | * module options |
| 648 | */ |
| 649 | static int msi; /* Use PCI msi; either zero (off, default) or non-zero */ |
| 650 | |
| 651 | |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 652 | /* move to PCI layer or libata core? */ |
| 653 | static int pci_go_64(struct pci_dev *pdev) |
| 654 | { |
| 655 | int rc; |
| 656 | |
| 657 | if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { |
| 658 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); |
| 659 | if (rc) { |
| 660 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 661 | if (rc) { |
| 662 | dev_printk(KERN_ERR, &pdev->dev, |
| 663 | "64-bit DMA enable failed\n"); |
| 664 | return rc; |
| 665 | } |
| 666 | } |
| 667 | } else { |
| 668 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
| 669 | if (rc) { |
| 670 | dev_printk(KERN_ERR, &pdev->dev, |
| 671 | "32-bit DMA enable failed\n"); |
| 672 | return rc; |
| 673 | } |
| 674 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 675 | if (rc) { |
| 676 | dev_printk(KERN_ERR, &pdev->dev, |
| 677 | "32-bit consistent DMA enable failed\n"); |
| 678 | return rc; |
| 679 | } |
| 680 | } |
| 681 | |
| 682 | return rc; |
| 683 | } |
| 684 | |
Jeff Garzik | ddef9bb | 2006-02-02 16:17:06 -0500 | [diff] [blame] | 685 | /* |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 686 | * Functions |
| 687 | */ |
| 688 | |
| 689 | static inline void writelfl(unsigned long data, void __iomem *addr) |
| 690 | { |
| 691 | writel(data, addr); |
| 692 | (void) readl(addr); /* flush to avoid PCI posted write */ |
| 693 | } |
| 694 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 695 | static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) |
| 696 | { |
| 697 | return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); |
| 698 | } |
| 699 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 700 | static inline unsigned int mv_hc_from_port(unsigned int port) |
| 701 | { |
| 702 | return port >> MV_PORT_HC_SHIFT; |
| 703 | } |
| 704 | |
| 705 | static inline unsigned int mv_hardport_from_port(unsigned int port) |
| 706 | { |
| 707 | return port & MV_PORT_MASK; |
| 708 | } |
| 709 | |
| 710 | static inline void __iomem *mv_hc_base_from_port(void __iomem *base, |
| 711 | unsigned int port) |
| 712 | { |
| 713 | return mv_hc_base(base, mv_hc_from_port(port)); |
| 714 | } |
| 715 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 716 | static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) |
| 717 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 718 | return mv_hc_base_from_port(base, port) + |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 719 | MV_SATAHC_ARBTR_REG_SZ + |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 720 | (mv_hardport_from_port(port) * MV_PORT_REG_SZ); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 721 | } |
| 722 | |
| 723 | static inline void __iomem *mv_ap_base(struct ata_port *ap) |
| 724 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 725 | return mv_port_base(ap->host->iomap[MV_PRIMARY_BAR], ap->port_no); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 726 | } |
| 727 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 728 | static inline int mv_get_hc_count(unsigned long port_flags) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 729 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 730 | return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 731 | } |
| 732 | |
| 733 | static void mv_irq_clear(struct ata_port *ap) |
| 734 | { |
| 735 | } |
| 736 | |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 737 | static void mv_set_edma_ptrs(void __iomem *port_mmio, |
| 738 | struct mv_host_priv *hpriv, |
| 739 | struct mv_port_priv *pp) |
| 740 | { |
| 741 | /* |
| 742 | * initialize request queue |
| 743 | */ |
| 744 | WARN_ON(pp->crqb_dma & 0x3ff); |
| 745 | writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); |
| 746 | writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK, |
| 747 | port_mmio + EDMA_REQ_Q_IN_PTR_OFS); |
| 748 | |
| 749 | if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) |
| 750 | writelfl(pp->crqb_dma & 0xffffffff, |
| 751 | port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); |
| 752 | else |
| 753 | writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); |
| 754 | |
| 755 | /* |
| 756 | * initialize response queue |
| 757 | */ |
| 758 | WARN_ON(pp->crpb_dma & 0xff); |
| 759 | writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); |
| 760 | |
| 761 | if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) |
| 762 | writelfl(pp->crpb_dma & 0xffffffff, |
| 763 | port_mmio + EDMA_RSP_Q_IN_PTR_OFS); |
| 764 | else |
| 765 | writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); |
| 766 | |
| 767 | writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK, |
| 768 | port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); |
| 769 | |
| 770 | } |
| 771 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 772 | /** |
| 773 | * mv_start_dma - Enable eDMA engine |
| 774 | * @base: port base address |
| 775 | * @pp: port private data |
| 776 | * |
Tejun Heo | beec7db | 2006-02-11 19:11:13 +0900 | [diff] [blame] | 777 | * Verify the local cache of the eDMA state is accurate with a |
| 778 | * WARN_ON. |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 779 | * |
| 780 | * LOCKING: |
| 781 | * Inherited from caller. |
| 782 | */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 783 | static void mv_start_dma(void __iomem *base, struct mv_host_priv *hpriv, |
| 784 | struct mv_port_priv *pp) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 785 | { |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 786 | if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 787 | writelfl(EDMA_EN, base + EDMA_CMD_OFS); |
| 788 | pp->pp_flags |= MV_PP_FLAG_EDMA_EN; |
| 789 | } |
Tejun Heo | beec7db | 2006-02-11 19:11:13 +0900 | [diff] [blame] | 790 | WARN_ON(!(EDMA_EN & readl(base + EDMA_CMD_OFS))); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 791 | } |
| 792 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 793 | /** |
| 794 | * mv_stop_dma - Disable eDMA engine |
| 795 | * @ap: ATA channel to manipulate |
| 796 | * |
Tejun Heo | beec7db | 2006-02-11 19:11:13 +0900 | [diff] [blame] | 797 | * Verify the local cache of the eDMA state is accurate with a |
| 798 | * WARN_ON. |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 799 | * |
| 800 | * LOCKING: |
| 801 | * Inherited from caller. |
| 802 | */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 803 | static int mv_stop_dma(struct ata_port *ap) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 804 | { |
| 805 | void __iomem *port_mmio = mv_ap_base(ap); |
| 806 | struct mv_port_priv *pp = ap->private_data; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 807 | u32 reg; |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 808 | int i, err = 0; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 809 | |
Jeff Garzik | 4537deb | 2007-07-12 14:30:19 -0400 | [diff] [blame^] | 810 | if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 811 | /* Disable EDMA if active. The disable bit auto clears. |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 812 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 813 | writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); |
| 814 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 815 | } else { |
Tejun Heo | beec7db | 2006-02-11 19:11:13 +0900 | [diff] [blame] | 816 | WARN_ON(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)); |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 817 | } |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 818 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 819 | /* now properly wait for the eDMA to stop */ |
| 820 | for (i = 1000; i > 0; i--) { |
| 821 | reg = readl(port_mmio + EDMA_CMD_OFS); |
Jeff Garzik | 4537deb | 2007-07-12 14:30:19 -0400 | [diff] [blame^] | 822 | if (!(reg & EDMA_EN)) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 823 | break; |
Jeff Garzik | 4537deb | 2007-07-12 14:30:19 -0400 | [diff] [blame^] | 824 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 825 | udelay(100); |
| 826 | } |
| 827 | |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 828 | if (reg & EDMA_EN) { |
Tejun Heo | f15a1da | 2006-05-15 20:57:56 +0900 | [diff] [blame] | 829 | ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 830 | /* FIXME: Consider doing a reset here to recover */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 831 | err = -EIO; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 832 | } |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 833 | |
| 834 | return err; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 835 | } |
| 836 | |
Jeff Garzik | 8a70f8d | 2005-10-05 17:19:47 -0400 | [diff] [blame] | 837 | #ifdef ATA_DEBUG |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 838 | static void mv_dump_mem(void __iomem *start, unsigned bytes) |
| 839 | { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 840 | int b, w; |
| 841 | for (b = 0; b < bytes; ) { |
| 842 | DPRINTK("%p: ", start + b); |
| 843 | for (w = 0; b < bytes && w < 4; w++) { |
| 844 | printk("%08x ",readl(start + b)); |
| 845 | b += sizeof(u32); |
| 846 | } |
| 847 | printk("\n"); |
| 848 | } |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 849 | } |
Jeff Garzik | 8a70f8d | 2005-10-05 17:19:47 -0400 | [diff] [blame] | 850 | #endif |
| 851 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 852 | static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) |
| 853 | { |
| 854 | #ifdef ATA_DEBUG |
| 855 | int b, w; |
| 856 | u32 dw; |
| 857 | for (b = 0; b < bytes; ) { |
| 858 | DPRINTK("%02x: ", b); |
| 859 | for (w = 0; b < bytes && w < 4; w++) { |
| 860 | (void) pci_read_config_dword(pdev,b,&dw); |
| 861 | printk("%08x ",dw); |
| 862 | b += sizeof(u32); |
| 863 | } |
| 864 | printk("\n"); |
| 865 | } |
| 866 | #endif |
| 867 | } |
| 868 | static void mv_dump_all_regs(void __iomem *mmio_base, int port, |
| 869 | struct pci_dev *pdev) |
| 870 | { |
| 871 | #ifdef ATA_DEBUG |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 872 | void __iomem *hc_base = mv_hc_base(mmio_base, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 873 | port >> MV_PORT_HC_SHIFT); |
| 874 | void __iomem *port_base; |
| 875 | int start_port, num_ports, p, start_hc, num_hcs, hc; |
| 876 | |
| 877 | if (0 > port) { |
| 878 | start_hc = start_port = 0; |
| 879 | num_ports = 8; /* shld be benign for 4 port devs */ |
| 880 | num_hcs = 2; |
| 881 | } else { |
| 882 | start_hc = port >> MV_PORT_HC_SHIFT; |
| 883 | start_port = port; |
| 884 | num_ports = num_hcs = 1; |
| 885 | } |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 886 | DPRINTK("All registers for port(s) %u-%u:\n", start_port, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 887 | num_ports > 1 ? num_ports - 1 : start_port); |
| 888 | |
| 889 | if (NULL != pdev) { |
| 890 | DPRINTK("PCI config space regs:\n"); |
| 891 | mv_dump_pci_cfg(pdev, 0x68); |
| 892 | } |
| 893 | DPRINTK("PCI regs:\n"); |
| 894 | mv_dump_mem(mmio_base+0xc00, 0x3c); |
| 895 | mv_dump_mem(mmio_base+0xd00, 0x34); |
| 896 | mv_dump_mem(mmio_base+0xf00, 0x4); |
| 897 | mv_dump_mem(mmio_base+0x1d00, 0x6c); |
| 898 | for (hc = start_hc; hc < start_hc + num_hcs; hc++) { |
Dan Aloni | d220c37 | 2006-04-10 23:20:22 -0700 | [diff] [blame] | 899 | hc_base = mv_hc_base(mmio_base, hc); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 900 | DPRINTK("HC regs (HC %i):\n", hc); |
| 901 | mv_dump_mem(hc_base, 0x1c); |
| 902 | } |
| 903 | for (p = start_port; p < start_port + num_ports; p++) { |
| 904 | port_base = mv_port_base(mmio_base, p); |
| 905 | DPRINTK("EDMA regs (port %i):\n",p); |
| 906 | mv_dump_mem(port_base, 0x54); |
| 907 | DPRINTK("SATA regs (port %i):\n",p); |
| 908 | mv_dump_mem(port_base+0x300, 0x60); |
| 909 | } |
| 910 | #endif |
| 911 | } |
| 912 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 913 | static unsigned int mv_scr_offset(unsigned int sc_reg_in) |
| 914 | { |
| 915 | unsigned int ofs; |
| 916 | |
| 917 | switch (sc_reg_in) { |
| 918 | case SCR_STATUS: |
| 919 | case SCR_CONTROL: |
| 920 | case SCR_ERROR: |
| 921 | ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); |
| 922 | break; |
| 923 | case SCR_ACTIVE: |
| 924 | ofs = SATA_ACTIVE_OFS; /* active is not with the others */ |
| 925 | break; |
| 926 | default: |
| 927 | ofs = 0xffffffffU; |
| 928 | break; |
| 929 | } |
| 930 | return ofs; |
| 931 | } |
| 932 | |
| 933 | static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in) |
| 934 | { |
| 935 | unsigned int ofs = mv_scr_offset(sc_reg_in); |
| 936 | |
Jeff Garzik | 3517726 | 2007-02-24 21:26:42 -0500 | [diff] [blame] | 937 | if (0xffffffffU != ofs) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 938 | return readl(mv_ap_base(ap) + ofs); |
Jeff Garzik | 3517726 | 2007-02-24 21:26:42 -0500 | [diff] [blame] | 939 | else |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 940 | return (u32) ofs; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 941 | } |
| 942 | |
| 943 | static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) |
| 944 | { |
| 945 | unsigned int ofs = mv_scr_offset(sc_reg_in); |
| 946 | |
Jeff Garzik | 3517726 | 2007-02-24 21:26:42 -0500 | [diff] [blame] | 947 | if (0xffffffffU != ofs) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 948 | writelfl(val, mv_ap_base(ap) + ofs); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 949 | } |
| 950 | |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 951 | static void mv_edma_cfg(struct ata_port *ap, struct mv_host_priv *hpriv, |
| 952 | void __iomem *port_mmio) |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 953 | { |
| 954 | u32 cfg = readl(port_mmio + EDMA_CFG_OFS); |
| 955 | |
| 956 | /* set up non-NCQ EDMA configuration */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 957 | cfg &= ~(1 << 9); /* disable eQue */ |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 958 | |
Jeff Garzik | e728eab | 2007-02-25 02:53:41 -0500 | [diff] [blame] | 959 | if (IS_GEN_I(hpriv)) { |
| 960 | cfg &= ~0x1f; /* clear queue depth */ |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 961 | cfg |= (1 << 8); /* enab config burst size mask */ |
Jeff Garzik | e728eab | 2007-02-25 02:53:41 -0500 | [diff] [blame] | 962 | } |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 963 | |
Jeff Garzik | e728eab | 2007-02-25 02:53:41 -0500 | [diff] [blame] | 964 | else if (IS_GEN_II(hpriv)) { |
| 965 | cfg &= ~0x1f; /* clear queue depth */ |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 966 | cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; |
Jeff Garzik | e728eab | 2007-02-25 02:53:41 -0500 | [diff] [blame] | 967 | cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */ |
| 968 | } |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 969 | |
| 970 | else if (IS_GEN_IIE(hpriv)) { |
Jeff Garzik | e728eab | 2007-02-25 02:53:41 -0500 | [diff] [blame] | 971 | cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ |
| 972 | cfg |= (1 << 22); /* enab 4-entry host queue cache */ |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 973 | cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */ |
| 974 | cfg |= (1 << 18); /* enab early completion */ |
Jeff Garzik | e728eab | 2007-02-25 02:53:41 -0500 | [diff] [blame] | 975 | cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */ |
| 976 | cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */ |
Jeff Garzik | 4537deb | 2007-07-12 14:30:19 -0400 | [diff] [blame^] | 977 | cfg &= ~(EDMA_CFG_NCQ); /* clear NCQ */ |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 978 | } |
| 979 | |
| 980 | writelfl(cfg, port_mmio + EDMA_CFG_OFS); |
| 981 | } |
| 982 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 983 | /** |
| 984 | * mv_port_start - Port specific init/start routine. |
| 985 | * @ap: ATA channel to manipulate |
| 986 | * |
| 987 | * Allocate and point to DMA memory, init port private memory, |
| 988 | * zero indices. |
| 989 | * |
| 990 | * LOCKING: |
| 991 | * Inherited from caller. |
| 992 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 993 | static int mv_port_start(struct ata_port *ap) |
| 994 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 995 | struct device *dev = ap->host->dev; |
| 996 | struct mv_host_priv *hpriv = ap->host->private_data; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 997 | struct mv_port_priv *pp; |
| 998 | void __iomem *port_mmio = mv_ap_base(ap); |
| 999 | void *mem; |
| 1000 | dma_addr_t mem_dma; |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1001 | int rc; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1002 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1003 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 1004 | if (!pp) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1005 | return -ENOMEM; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1006 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1007 | mem = dmam_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma, |
| 1008 | GFP_KERNEL); |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 1009 | if (!mem) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1010 | return -ENOMEM; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1011 | memset(mem, 0, MV_PORT_PRIV_DMA_SZ); |
| 1012 | |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 1013 | rc = ata_pad_alloc(ap, dev); |
| 1014 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1015 | return rc; |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 1016 | |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 1017 | /* First item in chunk of DMA memory: |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1018 | * 32-slot command request table (CRQB), 32 bytes each in size |
| 1019 | */ |
| 1020 | pp->crqb = mem; |
| 1021 | pp->crqb_dma = mem_dma; |
| 1022 | mem += MV_CRQB_Q_SZ; |
| 1023 | mem_dma += MV_CRQB_Q_SZ; |
| 1024 | |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 1025 | /* Second item: |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1026 | * 32-slot command response table (CRPB), 8 bytes each in size |
| 1027 | */ |
| 1028 | pp->crpb = mem; |
| 1029 | pp->crpb_dma = mem_dma; |
| 1030 | mem += MV_CRPB_Q_SZ; |
| 1031 | mem_dma += MV_CRPB_Q_SZ; |
| 1032 | |
| 1033 | /* Third item: |
| 1034 | * Table of scatter-gather descriptors (ePRD), 16 bytes each |
| 1035 | */ |
| 1036 | pp->sg_tbl = mem; |
| 1037 | pp->sg_tbl_dma = mem_dma; |
| 1038 | |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 1039 | mv_edma_cfg(ap, hpriv, port_mmio); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1040 | |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 1041 | mv_set_edma_ptrs(port_mmio, hpriv, pp); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1042 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1043 | /* Don't turn on EDMA here...do it before DMA commands only. Else |
| 1044 | * we'll be unable to send non-data, PIO, etc due to restricted access |
| 1045 | * to shadow regs. |
| 1046 | */ |
| 1047 | ap->private_data = pp; |
| 1048 | return 0; |
| 1049 | } |
| 1050 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1051 | /** |
| 1052 | * mv_port_stop - Port specific cleanup/stop routine. |
| 1053 | * @ap: ATA channel to manipulate |
| 1054 | * |
| 1055 | * Stop DMA, cleanup port memory. |
| 1056 | * |
| 1057 | * LOCKING: |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1058 | * This routine uses the host lock to protect the DMA stop. |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1059 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1060 | static void mv_port_stop(struct ata_port *ap) |
| 1061 | { |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 1062 | unsigned long flags; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1063 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1064 | spin_lock_irqsave(&ap->host->lock, flags); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1065 | mv_stop_dma(ap); |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1066 | spin_unlock_irqrestore(&ap->host->lock, flags); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1067 | } |
| 1068 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1069 | /** |
| 1070 | * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries |
| 1071 | * @qc: queued command whose SG list to source from |
| 1072 | * |
| 1073 | * Populate the SG list and mark the last entry. |
| 1074 | * |
| 1075 | * LOCKING: |
| 1076 | * Inherited from caller. |
| 1077 | */ |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 1078 | static unsigned int mv_fill_sg(struct ata_queued_cmd *qc) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1079 | { |
| 1080 | struct mv_port_priv *pp = qc->ap->private_data; |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 1081 | unsigned int n_sg = 0; |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 1082 | struct scatterlist *sg; |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 1083 | struct mv_sg *mv_sg; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1084 | |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 1085 | mv_sg = pp->sg_tbl; |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 1086 | ata_for_each_sg(sg, qc) { |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 1087 | dma_addr_t addr = sg_dma_address(sg); |
| 1088 | u32 sg_len = sg_dma_len(sg); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1089 | |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 1090 | mv_sg->addr = cpu_to_le32(addr & 0xffffffff); |
| 1091 | mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); |
| 1092 | mv_sg->flags_size = cpu_to_le32(sg_len & 0xffff); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1093 | |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 1094 | if (ata_sg_is_last(sg, qc)) |
| 1095 | mv_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 1096 | |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 1097 | mv_sg++; |
| 1098 | n_sg++; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1099 | } |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 1100 | |
| 1101 | return n_sg; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1102 | } |
| 1103 | |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1104 | static inline unsigned mv_inc_q_index(unsigned index) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1105 | { |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1106 | return (index + 1) & MV_MAX_Q_DEPTH_MASK; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1107 | } |
| 1108 | |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 1109 | static inline void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1110 | { |
Mark Lord | 559eeda | 2006-05-19 16:40:15 -0400 | [diff] [blame] | 1111 | u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1112 | (last ? CRQB_CMD_LAST : 0); |
Mark Lord | 559eeda | 2006-05-19 16:40:15 -0400 | [diff] [blame] | 1113 | *cmdw = cpu_to_le16(tmp); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1114 | } |
| 1115 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1116 | /** |
| 1117 | * mv_qc_prep - Host specific command preparation. |
| 1118 | * @qc: queued command to prepare |
| 1119 | * |
| 1120 | * This routine simply redirects to the general purpose routine |
| 1121 | * if command is not DMA. Else, it handles prep of the CRQB |
| 1122 | * (command request block), does some sanity checking, and calls |
| 1123 | * the SG load routine. |
| 1124 | * |
| 1125 | * LOCKING: |
| 1126 | * Inherited from caller. |
| 1127 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1128 | static void mv_qc_prep(struct ata_queued_cmd *qc) |
| 1129 | { |
| 1130 | struct ata_port *ap = qc->ap; |
| 1131 | struct mv_port_priv *pp = ap->private_data; |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 1132 | __le16 *cw; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1133 | struct ata_taskfile *tf; |
| 1134 | u16 flags = 0; |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1135 | unsigned in_index; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1136 | |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 1137 | if (qc->tf.protocol != ATA_PROT_DMA) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1138 | return; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1139 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1140 | /* Fill in command request block |
| 1141 | */ |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1142 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1143 | flags |= CRQB_FLAG_READ; |
Tejun Heo | beec7db | 2006-02-11 19:11:13 +0900 | [diff] [blame] | 1144 | WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1145 | flags |= qc->tag << CRQB_TAG_SHIFT; |
Jeff Garzik | 4537deb | 2007-07-12 14:30:19 -0400 | [diff] [blame^] | 1146 | flags |= qc->tag << CRQB_IOID_SHIFT; /* 50xx appears to ignore this*/ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1147 | |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1148 | /* get current queue index from hardware */ |
| 1149 | in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS) |
| 1150 | >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1151 | |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1152 | pp->crqb[in_index].sg_addr = |
| 1153 | cpu_to_le32(pp->sg_tbl_dma & 0xffffffff); |
| 1154 | pp->crqb[in_index].sg_addr_hi = |
| 1155 | cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16); |
| 1156 | pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); |
| 1157 | |
| 1158 | cw = &pp->crqb[in_index].ata_cmd[0]; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1159 | tf = &qc->tf; |
| 1160 | |
| 1161 | /* Sadly, the CRQB cannot accomodate all registers--there are |
| 1162 | * only 11 bytes...so we must pick and choose required |
| 1163 | * registers based on the command. So, we drop feature and |
| 1164 | * hob_feature for [RW] DMA commands, but they are needed for |
| 1165 | * NCQ. NCQ will drop hob_nsect. |
| 1166 | */ |
| 1167 | switch (tf->command) { |
| 1168 | case ATA_CMD_READ: |
| 1169 | case ATA_CMD_READ_EXT: |
| 1170 | case ATA_CMD_WRITE: |
| 1171 | case ATA_CMD_WRITE_EXT: |
Jens Axboe | c15d85c | 2006-02-15 15:59:25 +0100 | [diff] [blame] | 1172 | case ATA_CMD_WRITE_FUA_EXT: |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1173 | mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); |
| 1174 | break; |
| 1175 | #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */ |
| 1176 | case ATA_CMD_FPDMA_READ: |
| 1177 | case ATA_CMD_FPDMA_WRITE: |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 1178 | mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1179 | mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); |
| 1180 | break; |
| 1181 | #endif /* FIXME: remove this line when NCQ added */ |
| 1182 | default: |
| 1183 | /* The only other commands EDMA supports in non-queued and |
| 1184 | * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none |
| 1185 | * of which are defined/used by Linux. If we get here, this |
| 1186 | * driver needs work. |
| 1187 | * |
| 1188 | * FIXME: modify libata to give qc_prep a return value and |
| 1189 | * return error here. |
| 1190 | */ |
| 1191 | BUG_ON(tf->command); |
| 1192 | break; |
| 1193 | } |
| 1194 | mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); |
| 1195 | mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); |
| 1196 | mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); |
| 1197 | mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); |
| 1198 | mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); |
| 1199 | mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); |
| 1200 | mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); |
| 1201 | mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); |
| 1202 | mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ |
| 1203 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1204 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1205 | return; |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1206 | mv_fill_sg(qc); |
| 1207 | } |
| 1208 | |
| 1209 | /** |
| 1210 | * mv_qc_prep_iie - Host specific command preparation. |
| 1211 | * @qc: queued command to prepare |
| 1212 | * |
| 1213 | * This routine simply redirects to the general purpose routine |
| 1214 | * if command is not DMA. Else, it handles prep of the CRQB |
| 1215 | * (command request block), does some sanity checking, and calls |
| 1216 | * the SG load routine. |
| 1217 | * |
| 1218 | * LOCKING: |
| 1219 | * Inherited from caller. |
| 1220 | */ |
| 1221 | static void mv_qc_prep_iie(struct ata_queued_cmd *qc) |
| 1222 | { |
| 1223 | struct ata_port *ap = qc->ap; |
| 1224 | struct mv_port_priv *pp = ap->private_data; |
| 1225 | struct mv_crqb_iie *crqb; |
| 1226 | struct ata_taskfile *tf; |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1227 | unsigned in_index; |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1228 | u32 flags = 0; |
| 1229 | |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 1230 | if (qc->tf.protocol != ATA_PROT_DMA) |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1231 | return; |
| 1232 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1233 | /* Fill in Gen IIE command request block |
| 1234 | */ |
| 1235 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) |
| 1236 | flags |= CRQB_FLAG_READ; |
| 1237 | |
Tejun Heo | beec7db | 2006-02-11 19:11:13 +0900 | [diff] [blame] | 1238 | WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1239 | flags |= qc->tag << CRQB_TAG_SHIFT; |
Jeff Garzik | 4537deb | 2007-07-12 14:30:19 -0400 | [diff] [blame^] | 1240 | flags |= qc->tag << CRQB_IOID_SHIFT; /* "I/O Id" is -really- |
| 1241 | what we use as our tag */ |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1242 | |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1243 | /* get current queue index from hardware */ |
| 1244 | in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS) |
| 1245 | >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; |
| 1246 | |
| 1247 | crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1248 | crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff); |
| 1249 | crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16); |
| 1250 | crqb->flags = cpu_to_le32(flags); |
| 1251 | |
| 1252 | tf = &qc->tf; |
| 1253 | crqb->ata_cmd[0] = cpu_to_le32( |
| 1254 | (tf->command << 16) | |
| 1255 | (tf->feature << 24) |
| 1256 | ); |
| 1257 | crqb->ata_cmd[1] = cpu_to_le32( |
| 1258 | (tf->lbal << 0) | |
| 1259 | (tf->lbam << 8) | |
| 1260 | (tf->lbah << 16) | |
| 1261 | (tf->device << 24) |
| 1262 | ); |
| 1263 | crqb->ata_cmd[2] = cpu_to_le32( |
| 1264 | (tf->hob_lbal << 0) | |
| 1265 | (tf->hob_lbam << 8) | |
| 1266 | (tf->hob_lbah << 16) | |
| 1267 | (tf->hob_feature << 24) |
| 1268 | ); |
| 1269 | crqb->ata_cmd[3] = cpu_to_le32( |
| 1270 | (tf->nsect << 0) | |
| 1271 | (tf->hob_nsect << 8) |
| 1272 | ); |
| 1273 | |
| 1274 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) |
| 1275 | return; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1276 | mv_fill_sg(qc); |
| 1277 | } |
| 1278 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1279 | /** |
| 1280 | * mv_qc_issue - Initiate a command to the host |
| 1281 | * @qc: queued command to start |
| 1282 | * |
| 1283 | * This routine simply redirects to the general purpose routine |
| 1284 | * if command is not DMA. Else, it sanity checks our local |
| 1285 | * caches of the request producer/consumer indices then enables |
| 1286 | * DMA and bumps the request producer index. |
| 1287 | * |
| 1288 | * LOCKING: |
| 1289 | * Inherited from caller. |
| 1290 | */ |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 1291 | static unsigned int mv_qc_issue(struct ata_queued_cmd *qc) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1292 | { |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 1293 | struct ata_port *ap = qc->ap; |
| 1294 | void __iomem *port_mmio = mv_ap_base(ap); |
| 1295 | struct mv_port_priv *pp = ap->private_data; |
| 1296 | struct mv_host_priv *hpriv = ap->host->private_data; |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1297 | unsigned in_index; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1298 | u32 in_ptr; |
| 1299 | |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 1300 | if (qc->tf.protocol != ATA_PROT_DMA) { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1301 | /* We're about to send a non-EDMA capable command to the |
| 1302 | * port. Turn off EDMA so there won't be problems accessing |
| 1303 | * shadow block, etc registers. |
| 1304 | */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 1305 | mv_stop_dma(ap); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1306 | return ata_qc_issue_prot(qc); |
| 1307 | } |
| 1308 | |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1309 | in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS); |
| 1310 | in_index = (in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1311 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1312 | /* until we do queuing, the queue should be empty at this point */ |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1313 | WARN_ON(in_index != ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) |
| 1314 | >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK)); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1315 | |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1316 | in_index = mv_inc_q_index(in_index); /* now incr producer index */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1317 | |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 1318 | mv_start_dma(port_mmio, hpriv, pp); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1319 | |
| 1320 | /* and write the request in pointer to kick the EDMA to life */ |
| 1321 | in_ptr &= EDMA_REQ_Q_BASE_LO_MASK; |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1322 | in_ptr |= in_index << EDMA_REQ_Q_PTR_SHIFT; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1323 | writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS); |
| 1324 | |
| 1325 | return 0; |
| 1326 | } |
| 1327 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1328 | /** |
| 1329 | * mv_get_crpb_status - get status from most recently completed cmd |
| 1330 | * @ap: ATA channel to manipulate |
| 1331 | * |
| 1332 | * This routine is for use when the port is in DMA mode, when it |
| 1333 | * will be using the CRPB (command response block) method of |
Tejun Heo | beec7db | 2006-02-11 19:11:13 +0900 | [diff] [blame] | 1334 | * returning command completion information. We check indices |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1335 | * are good, grab status, and bump the response consumer index to |
| 1336 | * prove that we're up to date. |
| 1337 | * |
| 1338 | * LOCKING: |
| 1339 | * Inherited from caller. |
| 1340 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1341 | static u8 mv_get_crpb_status(struct ata_port *ap) |
| 1342 | { |
| 1343 | void __iomem *port_mmio = mv_ap_base(ap); |
| 1344 | struct mv_port_priv *pp = ap->private_data; |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1345 | unsigned out_index; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1346 | u32 out_ptr; |
Mark Lord | 806a6e7 | 2006-03-21 21:11:53 -0500 | [diff] [blame] | 1347 | u8 ata_status; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1348 | |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1349 | out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); |
| 1350 | out_index = (out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1351 | |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1352 | ata_status = le16_to_cpu(pp->crpb[out_index].flags) |
| 1353 | >> CRPB_FLAG_STATUS_SHIFT; |
Mark Lord | 806a6e7 | 2006-03-21 21:11:53 -0500 | [diff] [blame] | 1354 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1355 | /* increment our consumer index... */ |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1356 | out_index = mv_inc_q_index(out_index); |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 1357 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1358 | /* and, until we do NCQ, there should only be 1 CRPB waiting */ |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1359 | WARN_ON(out_index != ((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) |
| 1360 | >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK)); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1361 | |
| 1362 | /* write out our inc'd consumer index so EDMA knows we're caught up */ |
| 1363 | out_ptr &= EDMA_RSP_Q_BASE_LO_MASK; |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1364 | out_ptr |= out_index << EDMA_RSP_Q_PTR_SHIFT; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1365 | writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); |
| 1366 | |
| 1367 | /* Return ATA status register for completed CRPB */ |
Mark Lord | 806a6e7 | 2006-03-21 21:11:53 -0500 | [diff] [blame] | 1368 | return ata_status; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1369 | } |
| 1370 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1371 | /** |
| 1372 | * mv_err_intr - Handle error interrupts on the port |
| 1373 | * @ap: ATA channel to manipulate |
Mark Lord | 9b358e3 | 2006-05-19 16:21:03 -0400 | [diff] [blame] | 1374 | * @reset_allowed: bool: 0 == don't trigger from reset here |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1375 | * |
| 1376 | * In most cases, just clear the interrupt and move on. However, |
| 1377 | * some cases require an eDMA reset, which is done right before |
| 1378 | * the COMRESET in mv_phy_reset(). The SERR case requires a |
| 1379 | * clear of pending errors in the SATA SERROR register. Finally, |
| 1380 | * if the port disabled DMA, update our cached copy to match. |
| 1381 | * |
| 1382 | * LOCKING: |
| 1383 | * Inherited from caller. |
| 1384 | */ |
Mark Lord | 9b358e3 | 2006-05-19 16:21:03 -0400 | [diff] [blame] | 1385 | static void mv_err_intr(struct ata_port *ap, int reset_allowed) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1386 | { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1387 | void __iomem *port_mmio = mv_ap_base(ap); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1388 | u32 edma_err_cause, serr = 0; |
| 1389 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1390 | edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); |
| 1391 | |
| 1392 | if (EDMA_ERR_SERR & edma_err_cause) { |
Tejun Heo | 81952c5 | 2006-05-15 20:57:47 +0900 | [diff] [blame] | 1393 | sata_scr_read(ap, SCR_ERROR, &serr); |
| 1394 | sata_scr_write_flush(ap, SCR_ERROR, serr); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1395 | } |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 1396 | if (EDMA_ERR_SELF_DIS & edma_err_cause) { |
| 1397 | struct mv_port_priv *pp = ap->private_data; |
| 1398 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
| 1399 | } |
| 1400 | DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x " |
Tejun Heo | 44877b4 | 2007-02-21 01:06:51 +0900 | [diff] [blame] | 1401 | "SERR: 0x%08x\n", ap->print_id, edma_err_cause, serr); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1402 | |
| 1403 | /* Clear EDMA now that SERR cleanup done */ |
| 1404 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); |
| 1405 | |
| 1406 | /* check for fatal here and recover if needed */ |
Mark Lord | 9b358e3 | 2006-05-19 16:21:03 -0400 | [diff] [blame] | 1407 | if (reset_allowed && (EDMA_ERR_FATAL & edma_err_cause)) |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1408 | mv_stop_and_reset(ap); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1409 | } |
| 1410 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1411 | /** |
| 1412 | * mv_host_intr - Handle all interrupts on the given host controller |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1413 | * @host: host specific structure |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1414 | * @relevant: port error bits relevant to this host controller |
| 1415 | * @hc: which host controller we're to look at |
| 1416 | * |
| 1417 | * Read then write clear the HC interrupt status then walk each |
| 1418 | * port connected to the HC and see if it needs servicing. Port |
| 1419 | * success ints are reported in the HC interrupt status reg, the |
| 1420 | * port error ints are reported in the higher level main |
| 1421 | * interrupt status register and thus are passed in via the |
| 1422 | * 'relevant' argument. |
| 1423 | * |
| 1424 | * LOCKING: |
| 1425 | * Inherited from caller. |
| 1426 | */ |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1427 | static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1428 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1429 | void __iomem *mmio = host->iomap[MV_PRIMARY_BAR]; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1430 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1431 | struct ata_queued_cmd *qc; |
| 1432 | u32 hc_irq_cause; |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 1433 | int port, port0; |
| 1434 | int shift, hard_port, handled; |
Jeff Garzik | a7dac44 | 2005-10-30 04:44:42 -0500 | [diff] [blame] | 1435 | unsigned int err_mask; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1436 | |
Jeff Garzik | 3517726 | 2007-02-24 21:26:42 -0500 | [diff] [blame] | 1437 | if (hc == 0) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1438 | port0 = 0; |
Jeff Garzik | 3517726 | 2007-02-24 21:26:42 -0500 | [diff] [blame] | 1439 | else |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1440 | port0 = MV_PORTS_PER_HC; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1441 | |
| 1442 | /* we'll need the HC success int register in most cases */ |
| 1443 | hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); |
Jeff Garzik | 3517726 | 2007-02-24 21:26:42 -0500 | [diff] [blame] | 1444 | if (hc_irq_cause) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1445 | writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1446 | |
| 1447 | VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n", |
| 1448 | hc,relevant,hc_irq_cause); |
| 1449 | |
| 1450 | for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) { |
Jeff Garzik | cd85f6e | 2006-03-20 19:49:54 -0500 | [diff] [blame] | 1451 | u8 ata_status = 0; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1452 | struct ata_port *ap = host->ports[port]; |
Mark Lord | 63af2a5 | 2006-03-29 09:50:31 -0500 | [diff] [blame] | 1453 | struct mv_port_priv *pp = ap->private_data; |
Jeff Garzik | 55d8ca4 | 2006-03-29 19:43:31 -0500 | [diff] [blame] | 1454 | |
Mark Lord | e857f14 | 2006-05-19 16:33:03 -0400 | [diff] [blame] | 1455 | hard_port = mv_hardport_from_port(port); /* range 0..3 */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1456 | handled = 0; /* ensure ata_status is set if handled++ */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1457 | |
Mark Lord | 63af2a5 | 2006-03-29 09:50:31 -0500 | [diff] [blame] | 1458 | /* Note that DEV_IRQ might happen spuriously during EDMA, |
Mark Lord | e857f14 | 2006-05-19 16:33:03 -0400 | [diff] [blame] | 1459 | * and should be ignored in such cases. |
| 1460 | * The cause of this is still under investigation. |
Jeff Garzik | 8190bdb | 2006-05-24 01:53:39 -0400 | [diff] [blame] | 1461 | */ |
Mark Lord | 63af2a5 | 2006-03-29 09:50:31 -0500 | [diff] [blame] | 1462 | if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { |
| 1463 | /* EDMA: check for response queue interrupt */ |
| 1464 | if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) { |
| 1465 | ata_status = mv_get_crpb_status(ap); |
| 1466 | handled = 1; |
| 1467 | } |
| 1468 | } else { |
| 1469 | /* PIO: check for device (drive) interrupt */ |
| 1470 | if ((DEV_IRQ << hard_port) & hc_irq_cause) { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1471 | ata_status = readb(ap->ioaddr.status_addr); |
Mark Lord | 63af2a5 | 2006-03-29 09:50:31 -0500 | [diff] [blame] | 1472 | handled = 1; |
Mark Lord | e857f14 | 2006-05-19 16:33:03 -0400 | [diff] [blame] | 1473 | /* ignore spurious intr if drive still BUSY */ |
| 1474 | if (ata_status & ATA_BUSY) { |
| 1475 | ata_status = 0; |
| 1476 | handled = 0; |
| 1477 | } |
Mark Lord | 63af2a5 | 2006-03-29 09:50:31 -0500 | [diff] [blame] | 1478 | } |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1479 | } |
| 1480 | |
Jeff Garzik | 029f546 | 2006-04-02 10:30:40 -0400 | [diff] [blame] | 1481 | if (ap && (ap->flags & ATA_FLAG_DISABLED)) |
Jeff Garzik | a2c91a8 | 2005-11-17 05:44:44 -0500 | [diff] [blame] | 1482 | continue; |
| 1483 | |
Jeff Garzik | a7dac44 | 2005-10-30 04:44:42 -0500 | [diff] [blame] | 1484 | err_mask = ac_err_mask(ata_status); |
| 1485 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1486 | shift = port << 1; /* (port * 2) */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1487 | if (port >= MV_PORTS_PER_HC) { |
| 1488 | shift++; /* skip bit 8 in the HC Main IRQ reg */ |
| 1489 | } |
| 1490 | if ((PORT0_ERR << shift) & relevant) { |
Mark Lord | 9b358e3 | 2006-05-19 16:21:03 -0400 | [diff] [blame] | 1491 | mv_err_intr(ap, 1); |
Jeff Garzik | a7dac44 | 2005-10-30 04:44:42 -0500 | [diff] [blame] | 1492 | err_mask |= AC_ERR_OTHER; |
Mark Lord | 63af2a5 | 2006-03-29 09:50:31 -0500 | [diff] [blame] | 1493 | handled = 1; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1494 | } |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 1495 | |
Mark Lord | 63af2a5 | 2006-03-29 09:50:31 -0500 | [diff] [blame] | 1496 | if (handled) { |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1497 | qc = ata_qc_from_tag(ap, ap->active_tag); |
Mark Lord | 63af2a5 | 2006-03-29 09:50:31 -0500 | [diff] [blame] | 1498 | if (qc && (qc->flags & ATA_QCFLAG_ACTIVE)) { |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1499 | VPRINTK("port %u IRQ found for qc, " |
| 1500 | "ata_status 0x%x\n", port,ata_status); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1501 | /* mark qc status appropriately */ |
Jeff Garzik | 701db69 | 2005-12-06 04:52:48 -0500 | [diff] [blame] | 1502 | if (!(qc->tf.flags & ATA_TFLAG_POLLING)) { |
Albert Lee | a22e2eb | 2005-12-05 15:38:02 +0800 | [diff] [blame] | 1503 | qc->err_mask |= err_mask; |
| 1504 | ata_qc_complete(qc); |
| 1505 | } |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1506 | } |
| 1507 | } |
| 1508 | } |
| 1509 | VPRINTK("EXIT\n"); |
| 1510 | } |
| 1511 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1512 | /** |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 1513 | * mv_interrupt - Main interrupt event handler |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1514 | * @irq: unused |
| 1515 | * @dev_instance: private data; in this case the host structure |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1516 | * |
| 1517 | * Read the read only register to determine if any host |
| 1518 | * controllers have pending interrupts. If so, call lower level |
| 1519 | * routine to handle. Also check for PCI errors which are only |
| 1520 | * reported here. |
| 1521 | * |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 1522 | * LOCKING: |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1523 | * This routine holds the host lock while processing pending |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1524 | * interrupts. |
| 1525 | */ |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1526 | static irqreturn_t mv_interrupt(int irq, void *dev_instance) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1527 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1528 | struct ata_host *host = dev_instance; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1529 | unsigned int hc, handled = 0, n_hcs; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1530 | void __iomem *mmio = host->iomap[MV_PRIMARY_BAR]; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1531 | u32 irq_stat; |
| 1532 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1533 | irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1534 | |
| 1535 | /* check the cases where we either have nothing pending or have read |
| 1536 | * a bogus register value which can indicate HW removal or PCI fault |
| 1537 | */ |
Jeff Garzik | 3517726 | 2007-02-24 21:26:42 -0500 | [diff] [blame] | 1538 | if (!irq_stat || (0xffffffffU == irq_stat)) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1539 | return IRQ_NONE; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1540 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1541 | n_hcs = mv_get_hc_count(host->ports[0]->flags); |
| 1542 | spin_lock(&host->lock); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1543 | |
| 1544 | for (hc = 0; hc < n_hcs; hc++) { |
| 1545 | u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT)); |
| 1546 | if (relevant) { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1547 | mv_host_intr(host, relevant, hc); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1548 | handled++; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1549 | } |
| 1550 | } |
Mark Lord | 615ab95 | 2006-05-19 16:24:56 -0400 | [diff] [blame] | 1551 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1552 | if (PCI_ERR & irq_stat) { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1553 | printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n", |
| 1554 | readl(mmio + PCI_IRQ_CAUSE_OFS)); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1555 | |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 1556 | DPRINTK("All regs @ PCI error\n"); |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1557 | mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1558 | |
| 1559 | writelfl(0, mmio + PCI_IRQ_CAUSE_OFS); |
| 1560 | handled++; |
| 1561 | } |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1562 | spin_unlock(&host->lock); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1563 | |
| 1564 | return IRQ_RETVAL(handled); |
| 1565 | } |
| 1566 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1567 | static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) |
| 1568 | { |
| 1569 | void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); |
| 1570 | unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; |
| 1571 | |
| 1572 | return hc_mmio + ofs; |
| 1573 | } |
| 1574 | |
| 1575 | static unsigned int mv5_scr_offset(unsigned int sc_reg_in) |
| 1576 | { |
| 1577 | unsigned int ofs; |
| 1578 | |
| 1579 | switch (sc_reg_in) { |
| 1580 | case SCR_STATUS: |
| 1581 | case SCR_ERROR: |
| 1582 | case SCR_CONTROL: |
| 1583 | ofs = sc_reg_in * sizeof(u32); |
| 1584 | break; |
| 1585 | default: |
| 1586 | ofs = 0xffffffffU; |
| 1587 | break; |
| 1588 | } |
| 1589 | return ofs; |
| 1590 | } |
| 1591 | |
| 1592 | static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in) |
| 1593 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1594 | void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR]; |
| 1595 | void __iomem *addr = mv5_phy_base(mmio, ap->port_no); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1596 | unsigned int ofs = mv5_scr_offset(sc_reg_in); |
| 1597 | |
| 1598 | if (ofs != 0xffffffffU) |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1599 | return readl(addr + ofs); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1600 | else |
| 1601 | return (u32) ofs; |
| 1602 | } |
| 1603 | |
| 1604 | static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) |
| 1605 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1606 | void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR]; |
| 1607 | void __iomem *addr = mv5_phy_base(mmio, ap->port_no); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1608 | unsigned int ofs = mv5_scr_offset(sc_reg_in); |
| 1609 | |
| 1610 | if (ofs != 0xffffffffU) |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1611 | writelfl(val, addr + ofs); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1612 | } |
| 1613 | |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 1614 | static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio) |
| 1615 | { |
| 1616 | u8 rev_id; |
| 1617 | int early_5080; |
| 1618 | |
| 1619 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); |
| 1620 | |
| 1621 | early_5080 = (pdev->device == 0x5080) && (rev_id == 0); |
| 1622 | |
| 1623 | if (!early_5080) { |
| 1624 | u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); |
| 1625 | tmp |= (1 << 0); |
| 1626 | writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); |
| 1627 | } |
| 1628 | |
| 1629 | mv_reset_pci_bus(pdev, mmio); |
| 1630 | } |
| 1631 | |
| 1632 | static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) |
| 1633 | { |
| 1634 | writel(0x0fcfffff, mmio + MV_FLASH_CTL); |
| 1635 | } |
| 1636 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1637 | static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1638 | void __iomem *mmio) |
| 1639 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1640 | void __iomem *phy_mmio = mv5_phy_base(mmio, idx); |
| 1641 | u32 tmp; |
| 1642 | |
| 1643 | tmp = readl(phy_mmio + MV5_PHY_MODE); |
| 1644 | |
| 1645 | hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ |
| 1646 | hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1647 | } |
| 1648 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1649 | static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1650 | { |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 1651 | u32 tmp; |
| 1652 | |
| 1653 | writel(0, mmio + MV_GPIO_PORT_CTL); |
| 1654 | |
| 1655 | /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ |
| 1656 | |
| 1657 | tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); |
| 1658 | tmp |= ~(1 << 0); |
| 1659 | writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1660 | } |
| 1661 | |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 1662 | static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 1663 | unsigned int port) |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1664 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1665 | void __iomem *phy_mmio = mv5_phy_base(mmio, port); |
| 1666 | const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); |
| 1667 | u32 tmp; |
| 1668 | int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); |
| 1669 | |
| 1670 | if (fix_apm_sq) { |
| 1671 | tmp = readl(phy_mmio + MV5_LT_MODE); |
| 1672 | tmp |= (1 << 19); |
| 1673 | writel(tmp, phy_mmio + MV5_LT_MODE); |
| 1674 | |
| 1675 | tmp = readl(phy_mmio + MV5_PHY_CTL); |
| 1676 | tmp &= ~0x3; |
| 1677 | tmp |= 0x1; |
| 1678 | writel(tmp, phy_mmio + MV5_PHY_CTL); |
| 1679 | } |
| 1680 | |
| 1681 | tmp = readl(phy_mmio + MV5_PHY_MODE); |
| 1682 | tmp &= ~mask; |
| 1683 | tmp |= hpriv->signal[port].pre; |
| 1684 | tmp |= hpriv->signal[port].amps; |
| 1685 | writel(tmp, phy_mmio + MV5_PHY_MODE); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1686 | } |
| 1687 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1688 | |
| 1689 | #undef ZERO |
| 1690 | #define ZERO(reg) writel(0, port_mmio + (reg)) |
| 1691 | static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 1692 | unsigned int port) |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1693 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1694 | void __iomem *port_mmio = mv_port_base(mmio, port); |
| 1695 | |
| 1696 | writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); |
| 1697 | |
| 1698 | mv_channel_reset(hpriv, mmio, port); |
| 1699 | |
| 1700 | ZERO(0x028); /* command */ |
| 1701 | writel(0x11f, port_mmio + EDMA_CFG_OFS); |
| 1702 | ZERO(0x004); /* timer */ |
| 1703 | ZERO(0x008); /* irq err cause */ |
| 1704 | ZERO(0x00c); /* irq err mask */ |
| 1705 | ZERO(0x010); /* rq bah */ |
| 1706 | ZERO(0x014); /* rq inp */ |
| 1707 | ZERO(0x018); /* rq outp */ |
| 1708 | ZERO(0x01c); /* respq bah */ |
| 1709 | ZERO(0x024); /* respq outp */ |
| 1710 | ZERO(0x020); /* respq inp */ |
| 1711 | ZERO(0x02c); /* test control */ |
| 1712 | writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); |
| 1713 | } |
| 1714 | #undef ZERO |
| 1715 | |
| 1716 | #define ZERO(reg) writel(0, hc_mmio + (reg)) |
| 1717 | static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 1718 | unsigned int hc) |
| 1719 | { |
| 1720 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
| 1721 | u32 tmp; |
| 1722 | |
| 1723 | ZERO(0x00c); |
| 1724 | ZERO(0x010); |
| 1725 | ZERO(0x014); |
| 1726 | ZERO(0x018); |
| 1727 | |
| 1728 | tmp = readl(hc_mmio + 0x20); |
| 1729 | tmp &= 0x1c1c1c1c; |
| 1730 | tmp |= 0x03030303; |
| 1731 | writel(tmp, hc_mmio + 0x20); |
| 1732 | } |
| 1733 | #undef ZERO |
| 1734 | |
| 1735 | static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 1736 | unsigned int n_hc) |
| 1737 | { |
| 1738 | unsigned int hc, port; |
| 1739 | |
| 1740 | for (hc = 0; hc < n_hc; hc++) { |
| 1741 | for (port = 0; port < MV_PORTS_PER_HC; port++) |
| 1742 | mv5_reset_hc_port(hpriv, mmio, |
| 1743 | (hc * MV_PORTS_PER_HC) + port); |
| 1744 | |
| 1745 | mv5_reset_one_hc(hpriv, mmio, hc); |
| 1746 | } |
| 1747 | |
| 1748 | return 0; |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1749 | } |
| 1750 | |
Jeff Garzik | 101ffae | 2005-11-12 22:17:49 -0500 | [diff] [blame] | 1751 | #undef ZERO |
| 1752 | #define ZERO(reg) writel(0, mmio + (reg)) |
| 1753 | static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio) |
| 1754 | { |
| 1755 | u32 tmp; |
| 1756 | |
| 1757 | tmp = readl(mmio + MV_PCI_MODE); |
| 1758 | tmp &= 0xff00ffff; |
| 1759 | writel(tmp, mmio + MV_PCI_MODE); |
| 1760 | |
| 1761 | ZERO(MV_PCI_DISC_TIMER); |
| 1762 | ZERO(MV_PCI_MSI_TRIGGER); |
| 1763 | writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); |
| 1764 | ZERO(HC_MAIN_IRQ_MASK_OFS); |
| 1765 | ZERO(MV_PCI_SERR_MASK); |
| 1766 | ZERO(PCI_IRQ_CAUSE_OFS); |
| 1767 | ZERO(PCI_IRQ_MASK_OFS); |
| 1768 | ZERO(MV_PCI_ERR_LOW_ADDRESS); |
| 1769 | ZERO(MV_PCI_ERR_HIGH_ADDRESS); |
| 1770 | ZERO(MV_PCI_ERR_ATTRIBUTE); |
| 1771 | ZERO(MV_PCI_ERR_COMMAND); |
| 1772 | } |
| 1773 | #undef ZERO |
| 1774 | |
| 1775 | static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) |
| 1776 | { |
| 1777 | u32 tmp; |
| 1778 | |
| 1779 | mv5_reset_flash(hpriv, mmio); |
| 1780 | |
| 1781 | tmp = readl(mmio + MV_GPIO_PORT_CTL); |
| 1782 | tmp &= 0x3; |
| 1783 | tmp |= (1 << 5) | (1 << 6); |
| 1784 | writel(tmp, mmio + MV_GPIO_PORT_CTL); |
| 1785 | } |
| 1786 | |
| 1787 | /** |
| 1788 | * mv6_reset_hc - Perform the 6xxx global soft reset |
| 1789 | * @mmio: base address of the HBA |
| 1790 | * |
| 1791 | * This routine only applies to 6xxx parts. |
| 1792 | * |
| 1793 | * LOCKING: |
| 1794 | * Inherited from caller. |
| 1795 | */ |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1796 | static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 1797 | unsigned int n_hc) |
Jeff Garzik | 101ffae | 2005-11-12 22:17:49 -0500 | [diff] [blame] | 1798 | { |
| 1799 | void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; |
| 1800 | int i, rc = 0; |
| 1801 | u32 t; |
| 1802 | |
| 1803 | /* Following procedure defined in PCI "main command and status |
| 1804 | * register" table. |
| 1805 | */ |
| 1806 | t = readl(reg); |
| 1807 | writel(t | STOP_PCI_MASTER, reg); |
| 1808 | |
| 1809 | for (i = 0; i < 1000; i++) { |
| 1810 | udelay(1); |
| 1811 | t = readl(reg); |
| 1812 | if (PCI_MASTER_EMPTY & t) { |
| 1813 | break; |
| 1814 | } |
| 1815 | } |
| 1816 | if (!(PCI_MASTER_EMPTY & t)) { |
| 1817 | printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); |
| 1818 | rc = 1; |
| 1819 | goto done; |
| 1820 | } |
| 1821 | |
| 1822 | /* set reset */ |
| 1823 | i = 5; |
| 1824 | do { |
| 1825 | writel(t | GLOB_SFT_RST, reg); |
| 1826 | t = readl(reg); |
| 1827 | udelay(1); |
| 1828 | } while (!(GLOB_SFT_RST & t) && (i-- > 0)); |
| 1829 | |
| 1830 | if (!(GLOB_SFT_RST & t)) { |
| 1831 | printk(KERN_ERR DRV_NAME ": can't set global reset\n"); |
| 1832 | rc = 1; |
| 1833 | goto done; |
| 1834 | } |
| 1835 | |
| 1836 | /* clear reset and *reenable the PCI master* (not mentioned in spec) */ |
| 1837 | i = 5; |
| 1838 | do { |
| 1839 | writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); |
| 1840 | t = readl(reg); |
| 1841 | udelay(1); |
| 1842 | } while ((GLOB_SFT_RST & t) && (i-- > 0)); |
| 1843 | |
| 1844 | if (GLOB_SFT_RST & t) { |
| 1845 | printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); |
| 1846 | rc = 1; |
| 1847 | } |
| 1848 | done: |
| 1849 | return rc; |
| 1850 | } |
| 1851 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1852 | static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1853 | void __iomem *mmio) |
| 1854 | { |
| 1855 | void __iomem *port_mmio; |
| 1856 | u32 tmp; |
| 1857 | |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1858 | tmp = readl(mmio + MV_RESET_CFG); |
| 1859 | if ((tmp & (1 << 0)) == 0) { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1860 | hpriv->signal[idx].amps = 0x7 << 8; |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1861 | hpriv->signal[idx].pre = 0x1 << 5; |
| 1862 | return; |
| 1863 | } |
| 1864 | |
| 1865 | port_mmio = mv_port_base(mmio, idx); |
| 1866 | tmp = readl(port_mmio + PHY_MODE2); |
| 1867 | |
| 1868 | hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ |
| 1869 | hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ |
| 1870 | } |
| 1871 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1872 | static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1873 | { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1874 | writel(0x00000060, mmio + MV_GPIO_PORT_CTL); |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1875 | } |
| 1876 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1877 | static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 1878 | unsigned int port) |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1879 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1880 | void __iomem *port_mmio = mv_port_base(mmio, port); |
| 1881 | |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1882 | u32 hp_flags = hpriv->hp_flags; |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1883 | int fix_phy_mode2 = |
| 1884 | hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1885 | int fix_phy_mode4 = |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1886 | hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); |
| 1887 | u32 m2, tmp; |
| 1888 | |
| 1889 | if (fix_phy_mode2) { |
| 1890 | m2 = readl(port_mmio + PHY_MODE2); |
| 1891 | m2 &= ~(1 << 16); |
| 1892 | m2 |= (1 << 31); |
| 1893 | writel(m2, port_mmio + PHY_MODE2); |
| 1894 | |
| 1895 | udelay(200); |
| 1896 | |
| 1897 | m2 = readl(port_mmio + PHY_MODE2); |
| 1898 | m2 &= ~((1 << 16) | (1 << 31)); |
| 1899 | writel(m2, port_mmio + PHY_MODE2); |
| 1900 | |
| 1901 | udelay(200); |
| 1902 | } |
| 1903 | |
| 1904 | /* who knows what this magic does */ |
| 1905 | tmp = readl(port_mmio + PHY_MODE3); |
| 1906 | tmp &= ~0x7F800000; |
| 1907 | tmp |= 0x2A800000; |
| 1908 | writel(tmp, port_mmio + PHY_MODE3); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1909 | |
| 1910 | if (fix_phy_mode4) { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1911 | u32 m4; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1912 | |
| 1913 | m4 = readl(port_mmio + PHY_MODE4); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1914 | |
| 1915 | if (hp_flags & MV_HP_ERRATA_60X1B2) |
| 1916 | tmp = readl(port_mmio + 0x310); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1917 | |
| 1918 | m4 = (m4 & ~(1 << 1)) | (1 << 0); |
| 1919 | |
| 1920 | writel(m4, port_mmio + PHY_MODE4); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1921 | |
| 1922 | if (hp_flags & MV_HP_ERRATA_60X1B2) |
| 1923 | writel(tmp, port_mmio + 0x310); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1924 | } |
| 1925 | |
| 1926 | /* Revert values of pre-emphasis and signal amps to the saved ones */ |
| 1927 | m2 = readl(port_mmio + PHY_MODE2); |
| 1928 | |
| 1929 | m2 &= ~MV_M2_PREAMP_MASK; |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 1930 | m2 |= hpriv->signal[port].amps; |
| 1931 | m2 |= hpriv->signal[port].pre; |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1932 | m2 &= ~(1 << 16); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1933 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1934 | /* according to mvSata 3.6.1, some IIE values are fixed */ |
| 1935 | if (IS_GEN_IIE(hpriv)) { |
| 1936 | m2 &= ~0xC30FF01F; |
| 1937 | m2 |= 0x0000900F; |
| 1938 | } |
| 1939 | |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1940 | writel(m2, port_mmio + PHY_MODE2); |
| 1941 | } |
| 1942 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1943 | static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 1944 | unsigned int port_no) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1945 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1946 | void __iomem *port_mmio = mv_port_base(mmio, port_no); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1947 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1948 | writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1949 | |
| 1950 | if (IS_60XX(hpriv)) { |
| 1951 | u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL); |
Mark Lord | eb46d68 | 2006-05-19 16:29:21 -0400 | [diff] [blame] | 1952 | ifctl |= (1 << 7); /* enable gen2i speed */ |
| 1953 | ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */ |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1954 | writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL); |
| 1955 | } |
| 1956 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1957 | udelay(25); /* allow reset propagation */ |
| 1958 | |
| 1959 | /* Spec never mentions clearing the bit. Marvell's driver does |
| 1960 | * clear the bit, however. |
| 1961 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1962 | writelfl(0, port_mmio + EDMA_CMD_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1963 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1964 | hpriv->ops->phy_errata(hpriv, mmio, port_no); |
| 1965 | |
| 1966 | if (IS_50XX(hpriv)) |
| 1967 | mdelay(1); |
| 1968 | } |
| 1969 | |
| 1970 | static void mv_stop_and_reset(struct ata_port *ap) |
| 1971 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1972 | struct mv_host_priv *hpriv = ap->host->private_data; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1973 | void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR]; |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1974 | |
| 1975 | mv_stop_dma(ap); |
| 1976 | |
| 1977 | mv_channel_reset(hpriv, mmio, ap->port_no); |
| 1978 | |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 1979 | __mv_phy_reset(ap, 0); |
| 1980 | } |
| 1981 | |
| 1982 | static inline void __msleep(unsigned int msec, int can_sleep) |
| 1983 | { |
| 1984 | if (can_sleep) |
| 1985 | msleep(msec); |
| 1986 | else |
| 1987 | mdelay(msec); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1988 | } |
| 1989 | |
| 1990 | /** |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 1991 | * __mv_phy_reset - Perform eDMA reset followed by COMRESET |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1992 | * @ap: ATA channel to manipulate |
| 1993 | * |
| 1994 | * Part of this is taken from __sata_phy_reset and modified to |
| 1995 | * not sleep since this routine gets called from interrupt level. |
| 1996 | * |
| 1997 | * LOCKING: |
| 1998 | * Inherited from caller. This is coded to safe to call at |
| 1999 | * interrupt level, i.e. it does not sleep. |
| 2000 | */ |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 2001 | static void __mv_phy_reset(struct ata_port *ap, int can_sleep) |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2002 | { |
| 2003 | struct mv_port_priv *pp = ap->private_data; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 2004 | struct mv_host_priv *hpriv = ap->host->private_data; |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2005 | void __iomem *port_mmio = mv_ap_base(ap); |
| 2006 | struct ata_taskfile tf; |
| 2007 | struct ata_device *dev = &ap->device[0]; |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 2008 | unsigned long deadline; |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 2009 | int retry = 5; |
| 2010 | u32 sstatus; |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2011 | |
| 2012 | VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2013 | |
Jeff Garzik | 095fec8 | 2005-11-12 09:50:49 -0500 | [diff] [blame] | 2014 | DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x " |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2015 | "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), |
| 2016 | mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2017 | |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 2018 | /* Issue COMRESET via SControl */ |
| 2019 | comreset_retry: |
Tejun Heo | 81952c5 | 2006-05-15 20:57:47 +0900 | [diff] [blame] | 2020 | sata_scr_write_flush(ap, SCR_CONTROL, 0x301); |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 2021 | __msleep(1, can_sleep); |
| 2022 | |
Tejun Heo | 81952c5 | 2006-05-15 20:57:47 +0900 | [diff] [blame] | 2023 | sata_scr_write_flush(ap, SCR_CONTROL, 0x300); |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 2024 | __msleep(20, can_sleep); |
| 2025 | |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 2026 | deadline = jiffies + msecs_to_jiffies(200); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2027 | do { |
Tejun Heo | 81952c5 | 2006-05-15 20:57:47 +0900 | [diff] [blame] | 2028 | sata_scr_read(ap, SCR_STATUS, &sstatus); |
Andres Salomon | 62f1d0e | 2006-09-11 08:51:05 -0400 | [diff] [blame] | 2029 | if (((sstatus & 0x3) == 3) || ((sstatus & 0x3) == 0)) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2030 | break; |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 2031 | |
| 2032 | __msleep(1, can_sleep); |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 2033 | } while (time_before(jiffies, deadline)); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2034 | |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 2035 | /* work around errata */ |
| 2036 | if (IS_60XX(hpriv) && |
| 2037 | (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) && |
| 2038 | (retry-- > 0)) |
| 2039 | goto comreset_retry; |
Jeff Garzik | 095fec8 | 2005-11-12 09:50:49 -0500 | [diff] [blame] | 2040 | |
| 2041 | DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x " |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2042 | "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), |
| 2043 | mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); |
| 2044 | |
Tejun Heo | 81952c5 | 2006-05-15 20:57:47 +0900 | [diff] [blame] | 2045 | if (ata_port_online(ap)) { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2046 | ata_port_probe(ap); |
| 2047 | } else { |
Tejun Heo | 81952c5 | 2006-05-15 20:57:47 +0900 | [diff] [blame] | 2048 | sata_scr_read(ap, SCR_STATUS, &sstatus); |
Tejun Heo | f15a1da | 2006-05-15 20:57:56 +0900 | [diff] [blame] | 2049 | ata_port_printk(ap, KERN_INFO, |
| 2050 | "no device found (phy stat %08x)\n", sstatus); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2051 | ata_port_disable(ap); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2052 | return; |
| 2053 | } |
| 2054 | |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 2055 | /* even after SStatus reflects that device is ready, |
| 2056 | * it seems to take a while for link to be fully |
| 2057 | * established (and thus Status no longer 0x80/0x7F), |
| 2058 | * so we poll a bit for that, here. |
| 2059 | */ |
| 2060 | retry = 20; |
| 2061 | while (1) { |
| 2062 | u8 drv_stat = ata_check_status(ap); |
| 2063 | if ((drv_stat != 0x80) && (drv_stat != 0x7f)) |
| 2064 | break; |
| 2065 | __msleep(500, can_sleep); |
| 2066 | if (retry-- <= 0) |
| 2067 | break; |
| 2068 | } |
| 2069 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2070 | tf.lbah = readb(ap->ioaddr.lbah_addr); |
| 2071 | tf.lbam = readb(ap->ioaddr.lbam_addr); |
| 2072 | tf.lbal = readb(ap->ioaddr.lbal_addr); |
| 2073 | tf.nsect = readb(ap->ioaddr.nsect_addr); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2074 | |
| 2075 | dev->class = ata_dev_classify(&tf); |
Tejun Heo | e1211e3 | 2006-04-01 01:38:18 +0900 | [diff] [blame] | 2076 | if (!ata_dev_enabled(dev)) { |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2077 | VPRINTK("Port disabled post-sig: No device present.\n"); |
| 2078 | ata_port_disable(ap); |
| 2079 | } |
Jeff Garzik | 095fec8 | 2005-11-12 09:50:49 -0500 | [diff] [blame] | 2080 | |
| 2081 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); |
| 2082 | |
| 2083 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
| 2084 | |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2085 | VPRINTK("EXIT\n"); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2086 | } |
| 2087 | |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 2088 | static void mv_phy_reset(struct ata_port *ap) |
| 2089 | { |
| 2090 | __mv_phy_reset(ap, 1); |
| 2091 | } |
| 2092 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2093 | /** |
| 2094 | * mv_eng_timeout - Routine called by libata when SCSI times out I/O |
| 2095 | * @ap: ATA channel to manipulate |
| 2096 | * |
| 2097 | * Intent is to clear all pending error conditions, reset the |
| 2098 | * chip/bus, fail the command, and move on. |
| 2099 | * |
| 2100 | * LOCKING: |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 2101 | * This routine holds the host lock while failing the command. |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2102 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2103 | static void mv_eng_timeout(struct ata_port *ap) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2104 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2105 | void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR]; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2106 | struct ata_queued_cmd *qc; |
Mark Lord | 2f9719b | 2006-06-07 12:53:29 -0400 | [diff] [blame] | 2107 | unsigned long flags; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2108 | |
Tejun Heo | f15a1da | 2006-05-15 20:57:56 +0900 | [diff] [blame] | 2109 | ata_port_printk(ap, KERN_ERR, "Entering mv_eng_timeout\n"); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2110 | DPRINTK("All regs @ start of eng_timeout\n"); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2111 | mv_dump_all_regs(mmio, ap->port_no, to_pci_dev(ap->host->dev)); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2112 | |
| 2113 | qc = ata_qc_from_tag(ap, ap->active_tag); |
| 2114 | printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n", |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2115 | mmio, ap, qc, qc->scsicmd, &qc->scsicmd->cmnd); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2116 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 2117 | spin_lock_irqsave(&ap->host->lock, flags); |
Mark Lord | 9b358e3 | 2006-05-19 16:21:03 -0400 | [diff] [blame] | 2118 | mv_err_intr(ap, 0); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2119 | mv_stop_and_reset(ap); |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 2120 | spin_unlock_irqrestore(&ap->host->lock, flags); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2121 | |
Mark Lord | 9b358e3 | 2006-05-19 16:21:03 -0400 | [diff] [blame] | 2122 | WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE)); |
| 2123 | if (qc->flags & ATA_QCFLAG_ACTIVE) { |
| 2124 | qc->err_mask |= AC_ERR_TIMEOUT; |
| 2125 | ata_eh_qc_complete(qc); |
| 2126 | } |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2127 | } |
| 2128 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2129 | /** |
| 2130 | * mv_port_init - Perform some early initialization on a single port. |
| 2131 | * @port: libata data structure storing shadow register addresses |
| 2132 | * @port_mmio: base address of the port |
| 2133 | * |
| 2134 | * Initialize shadow register mmio addresses, clear outstanding |
| 2135 | * interrupts on the port, and unmask interrupts for the future |
| 2136 | * start of the port. |
| 2137 | * |
| 2138 | * LOCKING: |
| 2139 | * Inherited from caller. |
| 2140 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2141 | static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) |
| 2142 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2143 | void __iomem *shd_base = port_mmio + SHD_BLK_OFS; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2144 | unsigned serr_ofs; |
| 2145 | |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 2146 | /* PIO related setup |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2147 | */ |
| 2148 | port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 2149 | port->error_addr = |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2150 | port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); |
| 2151 | port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); |
| 2152 | port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); |
| 2153 | port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); |
| 2154 | port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); |
| 2155 | port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 2156 | port->status_addr = |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2157 | port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); |
| 2158 | /* special case: control/altstatus doesn't have ATA_REG_ address */ |
| 2159 | port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; |
| 2160 | |
| 2161 | /* unused: */ |
Randy Dunlap | 8d9db2d | 2007-02-16 01:40:06 -0800 | [diff] [blame] | 2162 | port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2163 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2164 | /* Clear any currently outstanding port interrupt conditions */ |
| 2165 | serr_ofs = mv_scr_offset(SCR_ERROR); |
| 2166 | writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); |
| 2167 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); |
| 2168 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2169 | /* unmask all EDMA error interrupts */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2170 | writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2171 | |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 2172 | VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2173 | readl(port_mmio + EDMA_CFG_OFS), |
| 2174 | readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), |
| 2175 | readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2176 | } |
| 2177 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2178 | static int mv_chip_id(struct ata_host *host, unsigned int board_idx) |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2179 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2180 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 2181 | struct mv_host_priv *hpriv = host->private_data; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2182 | u8 rev_id; |
| 2183 | u32 hp_flags = hpriv->hp_flags; |
| 2184 | |
| 2185 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); |
| 2186 | |
| 2187 | switch(board_idx) { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2188 | case chip_5080: |
| 2189 | hpriv->ops = &mv5xxx_ops; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2190 | hp_flags |= MV_HP_50XX; |
| 2191 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2192 | switch (rev_id) { |
| 2193 | case 0x1: |
| 2194 | hp_flags |= MV_HP_ERRATA_50XXB0; |
| 2195 | break; |
| 2196 | case 0x3: |
| 2197 | hp_flags |= MV_HP_ERRATA_50XXB2; |
| 2198 | break; |
| 2199 | default: |
| 2200 | dev_printk(KERN_WARNING, &pdev->dev, |
| 2201 | "Applying 50XXB2 workarounds to unknown rev\n"); |
| 2202 | hp_flags |= MV_HP_ERRATA_50XXB2; |
| 2203 | break; |
| 2204 | } |
| 2205 | break; |
| 2206 | |
| 2207 | case chip_504x: |
| 2208 | case chip_508x: |
| 2209 | hpriv->ops = &mv5xxx_ops; |
| 2210 | hp_flags |= MV_HP_50XX; |
| 2211 | |
| 2212 | switch (rev_id) { |
| 2213 | case 0x0: |
| 2214 | hp_flags |= MV_HP_ERRATA_50XXB0; |
| 2215 | break; |
| 2216 | case 0x3: |
| 2217 | hp_flags |= MV_HP_ERRATA_50XXB2; |
| 2218 | break; |
| 2219 | default: |
| 2220 | dev_printk(KERN_WARNING, &pdev->dev, |
| 2221 | "Applying B2 workarounds to unknown rev\n"); |
| 2222 | hp_flags |= MV_HP_ERRATA_50XXB2; |
| 2223 | break; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2224 | } |
| 2225 | break; |
| 2226 | |
| 2227 | case chip_604x: |
| 2228 | case chip_608x: |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2229 | hpriv->ops = &mv6xxx_ops; |
| 2230 | |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2231 | switch (rev_id) { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2232 | case 0x7: |
| 2233 | hp_flags |= MV_HP_ERRATA_60X1B2; |
| 2234 | break; |
| 2235 | case 0x9: |
| 2236 | hp_flags |= MV_HP_ERRATA_60X1C0; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2237 | break; |
| 2238 | default: |
| 2239 | dev_printk(KERN_WARNING, &pdev->dev, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2240 | "Applying B2 workarounds to unknown rev\n"); |
| 2241 | hp_flags |= MV_HP_ERRATA_60X1B2; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2242 | break; |
| 2243 | } |
| 2244 | break; |
| 2245 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 2246 | case chip_7042: |
| 2247 | case chip_6042: |
| 2248 | hpriv->ops = &mv6xxx_ops; |
| 2249 | |
| 2250 | hp_flags |= MV_HP_GEN_IIE; |
| 2251 | |
| 2252 | switch (rev_id) { |
| 2253 | case 0x0: |
| 2254 | hp_flags |= MV_HP_ERRATA_XX42A0; |
| 2255 | break; |
| 2256 | case 0x1: |
| 2257 | hp_flags |= MV_HP_ERRATA_60X1C0; |
| 2258 | break; |
| 2259 | default: |
| 2260 | dev_printk(KERN_WARNING, &pdev->dev, |
| 2261 | "Applying 60X1C0 workarounds to unknown rev\n"); |
| 2262 | hp_flags |= MV_HP_ERRATA_60X1C0; |
| 2263 | break; |
| 2264 | } |
| 2265 | break; |
| 2266 | |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2267 | default: |
| 2268 | printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx); |
| 2269 | return 1; |
| 2270 | } |
| 2271 | |
| 2272 | hpriv->hp_flags = hp_flags; |
| 2273 | |
| 2274 | return 0; |
| 2275 | } |
| 2276 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2277 | /** |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2278 | * mv_init_host - Perform some early initialization of the host. |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2279 | * @host: ATA host to initialize |
| 2280 | * @board_idx: controller index |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2281 | * |
| 2282 | * If possible, do an early global reset of the host. Then do |
| 2283 | * our port init and clear/unmask all/relevant host interrupts. |
| 2284 | * |
| 2285 | * LOCKING: |
| 2286 | * Inherited from caller. |
| 2287 | */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2288 | static int mv_init_host(struct ata_host *host, unsigned int board_idx) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2289 | { |
| 2290 | int rc = 0, n_hc, port, hc; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2291 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 2292 | void __iomem *mmio = host->iomap[MV_PRIMARY_BAR]; |
| 2293 | struct mv_host_priv *hpriv = host->private_data; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2294 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2295 | /* global interrupt mask */ |
| 2296 | writel(0, mmio + HC_MAIN_IRQ_MASK_OFS); |
| 2297 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2298 | rc = mv_chip_id(host, board_idx); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2299 | if (rc) |
| 2300 | goto done; |
| 2301 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2302 | n_hc = mv_get_hc_count(host->ports[0]->flags); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2303 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2304 | for (port = 0; port < host->n_ports; port++) |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2305 | hpriv->ops->read_preamp(hpriv, port, mmio); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2306 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2307 | rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2308 | if (rc) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2309 | goto done; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2310 | |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 2311 | hpriv->ops->reset_flash(hpriv, mmio); |
| 2312 | hpriv->ops->reset_bus(pdev, mmio); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2313 | hpriv->ops->enable_leds(hpriv, mmio); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2314 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2315 | for (port = 0; port < host->n_ports; port++) { |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 2316 | if (IS_60XX(hpriv)) { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2317 | void __iomem *port_mmio = mv_port_base(mmio, port); |
| 2318 | |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 2319 | u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL); |
Mark Lord | eb46d68 | 2006-05-19 16:29:21 -0400 | [diff] [blame] | 2320 | ifctl |= (1 << 7); /* enable gen2i speed */ |
| 2321 | ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */ |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 2322 | writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL); |
| 2323 | } |
| 2324 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2325 | hpriv->ops->phy_errata(hpriv, mmio, port); |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 2326 | } |
| 2327 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2328 | for (port = 0; port < host->n_ports; port++) { |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 2329 | void __iomem *port_mmio = mv_port_base(mmio, port); |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2330 | mv_port_init(&host->ports[port]->ioaddr, port_mmio); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2331 | } |
| 2332 | |
| 2333 | for (hc = 0; hc < n_hc; hc++) { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2334 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
| 2335 | |
| 2336 | VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " |
| 2337 | "(before clear)=0x%08x\n", hc, |
| 2338 | readl(hc_mmio + HC_CFG_OFS), |
| 2339 | readl(hc_mmio + HC_IRQ_CAUSE_OFS)); |
| 2340 | |
| 2341 | /* Clear any currently outstanding hc interrupt conditions */ |
| 2342 | writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2343 | } |
| 2344 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2345 | /* Clear any currently outstanding host interrupt conditions */ |
| 2346 | writelfl(0, mmio + PCI_IRQ_CAUSE_OFS); |
| 2347 | |
| 2348 | /* and unmask interrupt generation for host regs */ |
| 2349 | writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS); |
Jeff Garzik | fb621e2 | 2007-02-25 04:19:45 -0500 | [diff] [blame] | 2350 | |
| 2351 | if (IS_50XX(hpriv)) |
| 2352 | writelfl(~HC_MAIN_MASKED_IRQS_5, mmio + HC_MAIN_IRQ_MASK_OFS); |
| 2353 | else |
| 2354 | writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2355 | |
| 2356 | VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x " |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 2357 | "PCI int cause/mask=0x%08x/0x%08x\n", |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2358 | readl(mmio + HC_MAIN_IRQ_CAUSE_OFS), |
| 2359 | readl(mmio + HC_MAIN_IRQ_MASK_OFS), |
| 2360 | readl(mmio + PCI_IRQ_CAUSE_OFS), |
| 2361 | readl(mmio + PCI_IRQ_MASK_OFS)); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2362 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2363 | done: |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2364 | return rc; |
| 2365 | } |
| 2366 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2367 | /** |
| 2368 | * mv_print_info - Dump key info to kernel log for perusal. |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2369 | * @host: ATA host to print info about |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2370 | * |
| 2371 | * FIXME: complete this. |
| 2372 | * |
| 2373 | * LOCKING: |
| 2374 | * Inherited from caller. |
| 2375 | */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2376 | static void mv_print_info(struct ata_host *host) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2377 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2378 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 2379 | struct mv_host_priv *hpriv = host->private_data; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2380 | u8 rev_id, scc; |
Jeff Garzik | c1e4fe7 | 2007-07-09 12:29:31 -0400 | [diff] [blame] | 2381 | const char *scc_s, *gen; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2382 | |
| 2383 | /* Use this to determine the HW stepping of the chip so we know |
| 2384 | * what errata to workaround |
| 2385 | */ |
| 2386 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); |
| 2387 | |
| 2388 | pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); |
| 2389 | if (scc == 0) |
| 2390 | scc_s = "SCSI"; |
| 2391 | else if (scc == 0x01) |
| 2392 | scc_s = "RAID"; |
| 2393 | else |
Jeff Garzik | c1e4fe7 | 2007-07-09 12:29:31 -0400 | [diff] [blame] | 2394 | scc_s = "?"; |
| 2395 | |
| 2396 | if (IS_GEN_I(hpriv)) |
| 2397 | gen = "I"; |
| 2398 | else if (IS_GEN_II(hpriv)) |
| 2399 | gen = "II"; |
| 2400 | else if (IS_GEN_IIE(hpriv)) |
| 2401 | gen = "IIE"; |
| 2402 | else |
| 2403 | gen = "?"; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2404 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2405 | dev_printk(KERN_INFO, &pdev->dev, |
Jeff Garzik | c1e4fe7 | 2007-07-09 12:29:31 -0400 | [diff] [blame] | 2406 | "Gen-%s %u slots %u ports %s mode IRQ via %s\n", |
| 2407 | gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2408 | scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); |
| 2409 | } |
| 2410 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2411 | /** |
| 2412 | * mv_init_one - handle a positive probe of a Marvell host |
| 2413 | * @pdev: PCI device found |
| 2414 | * @ent: PCI device ID entry for the matched host |
| 2415 | * |
| 2416 | * LOCKING: |
| 2417 | * Inherited from caller. |
| 2418 | */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2419 | static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
| 2420 | { |
| 2421 | static int printed_version = 0; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2422 | unsigned int board_idx = (unsigned int)ent->driver_data; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2423 | const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; |
| 2424 | struct ata_host *host; |
| 2425 | struct mv_host_priv *hpriv; |
| 2426 | int n_ports, rc; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2427 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2428 | if (!printed_version++) |
| 2429 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2430 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2431 | /* allocate host */ |
| 2432 | n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; |
| 2433 | |
| 2434 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); |
| 2435 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); |
| 2436 | if (!host || !hpriv) |
| 2437 | return -ENOMEM; |
| 2438 | host->private_data = hpriv; |
| 2439 | |
| 2440 | /* acquire resources */ |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2441 | rc = pcim_enable_device(pdev); |
| 2442 | if (rc) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2443 | return rc; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2444 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2445 | rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); |
| 2446 | if (rc == -EBUSY) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2447 | pcim_pin_device(pdev); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2448 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2449 | return rc; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2450 | host->iomap = pcim_iomap_table(pdev); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2451 | |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 2452 | rc = pci_go_64(pdev); |
| 2453 | if (rc) |
| 2454 | return rc; |
| 2455 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2456 | /* initialize adapter */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2457 | rc = mv_init_host(host, board_idx); |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2458 | if (rc) |
| 2459 | return rc; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2460 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2461 | /* Enable interrupts */ |
Tejun Heo | 6a59dcf | 2007-02-24 15:12:31 +0900 | [diff] [blame] | 2462 | if (msi && pci_enable_msi(pdev)) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2463 | pci_intx(pdev, 1); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2464 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2465 | mv_dump_pci_cfg(pdev, 0x68); |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2466 | mv_print_info(host); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2467 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2468 | pci_set_master(pdev); |
Jeff Garzik | 4537deb | 2007-07-12 14:30:19 -0400 | [diff] [blame^] | 2469 | pci_set_mwi(pdev); |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2470 | return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 2471 | IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2472 | } |
| 2473 | |
| 2474 | static int __init mv_init(void) |
| 2475 | { |
Pavel Roskin | b788719 | 2006-08-10 18:13:18 +0900 | [diff] [blame] | 2476 | return pci_register_driver(&mv_pci_driver); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2477 | } |
| 2478 | |
| 2479 | static void __exit mv_exit(void) |
| 2480 | { |
| 2481 | pci_unregister_driver(&mv_pci_driver); |
| 2482 | } |
| 2483 | |
| 2484 | MODULE_AUTHOR("Brett Russ"); |
| 2485 | MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); |
| 2486 | MODULE_LICENSE("GPL"); |
| 2487 | MODULE_DEVICE_TABLE(pci, mv_pci_tbl); |
| 2488 | MODULE_VERSION(DRV_VERSION); |
| 2489 | |
Jeff Garzik | ddef9bb | 2006-02-02 16:17:06 -0500 | [diff] [blame] | 2490 | module_param(msi, int, 0444); |
| 2491 | MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); |
| 2492 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2493 | module_init(mv_init); |
| 2494 | module_exit(mv_exit); |