Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/cpuidle34xx.c |
| 3 | * |
| 4 | * OMAP3 CPU IDLE Routines |
| 5 | * |
| 6 | * Copyright (C) 2008 Texas Instruments, Inc. |
| 7 | * Rajendra Nayak <rnayak@ti.com> |
| 8 | * |
| 9 | * Copyright (C) 2007 Texas Instruments, Inc. |
| 10 | * Karthik Dasu <karthik-dp@ti.com> |
| 11 | * |
| 12 | * Copyright (C) 2006 Nokia Corporation |
| 13 | * Tony Lindgren <tony@atomide.com> |
| 14 | * |
| 15 | * Copyright (C) 2005 Texas Instruments, Inc. |
| 16 | * Richard Woodruff <r-woodruff2@ti.com> |
| 17 | * |
| 18 | * Based on pm.c for omap2 |
| 19 | * |
| 20 | * This program is free software; you can redistribute it and/or modify |
| 21 | * it under the terms of the GNU General Public License version 2 as |
| 22 | * published by the Free Software Foundation. |
| 23 | */ |
| 24 | |
Tero Kristo | cf22854 | 2009-03-20 15:21:02 +0200 | [diff] [blame] | 25 | #include <linux/sched.h> |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 26 | #include <linux/cpuidle.h> |
| 27 | |
| 28 | #include <plat/prcm.h> |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 29 | #include <plat/irqs.h> |
Paul Walmsley | 72e06d0 | 2010-12-21 21:05:16 -0700 | [diff] [blame] | 30 | #include "powerdomain.h" |
Paul Walmsley | 1540f214 | 2010-12-21 21:05:15 -0700 | [diff] [blame] | 31 | #include "clockdomain.h" |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 32 | #include <plat/serial.h> |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 33 | |
Kevin Hilman | c98e223 | 2008-10-28 17:30:07 -0700 | [diff] [blame] | 34 | #include "pm.h" |
Paul Walmsley | 4814ced | 2010-10-08 11:40:20 -0600 | [diff] [blame] | 35 | #include "control.h" |
Kevin Hilman | c98e223 | 2008-10-28 17:30:07 -0700 | [diff] [blame] | 36 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 37 | #ifdef CONFIG_CPU_IDLE |
| 38 | |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 39 | /* |
| 40 | * The latencies/thresholds for various C states have |
| 41 | * to be configured from the respective board files. |
| 42 | * These are some default values (which might not provide |
| 43 | * the best power savings) used on boards which do not |
| 44 | * pass these details from the board file. |
| 45 | */ |
| 46 | static struct cpuidle_params cpuidle_params_table[] = { |
| 47 | /* C1 */ |
Jean Pihet | 866ba0e | 2011-05-09 12:02:13 +0200 | [diff] [blame] | 48 | {2 + 2, 5, 1}, |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 49 | /* C2 */ |
Jean Pihet | 866ba0e | 2011-05-09 12:02:13 +0200 | [diff] [blame] | 50 | {10 + 10, 30, 1}, |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 51 | /* C3 */ |
Jean Pihet | 866ba0e | 2011-05-09 12:02:13 +0200 | [diff] [blame] | 52 | {50 + 50, 300, 1}, |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 53 | /* C4 */ |
Jean Pihet | 866ba0e | 2011-05-09 12:02:13 +0200 | [diff] [blame] | 54 | {1500 + 1800, 4000, 1}, |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 55 | /* C5 */ |
Jean Pihet | 866ba0e | 2011-05-09 12:02:13 +0200 | [diff] [blame] | 56 | {2500 + 7500, 12000, 1}, |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 57 | /* C6 */ |
Jean Pihet | 866ba0e | 2011-05-09 12:02:13 +0200 | [diff] [blame] | 58 | {3000 + 8500, 15000, 1}, |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 59 | /* C7 */ |
Jean Pihet | 866ba0e | 2011-05-09 12:02:13 +0200 | [diff] [blame] | 60 | {10000 + 30000, 300000, 1}, |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 61 | }; |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 62 | #define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table) |
| 63 | |
| 64 | /* Mach specific information to be recorded in the C-state driver_data */ |
| 65 | struct omap3_idle_statedata { |
| 66 | u32 mpu_state; |
| 67 | u32 core_state; |
| 68 | u8 valid; |
| 69 | }; |
| 70 | struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES]; |
| 71 | |
| 72 | struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd; |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 73 | |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 74 | static int _cpuidle_allow_idle(struct powerdomain *pwrdm, |
| 75 | struct clockdomain *clkdm) |
| 76 | { |
Rajendra Nayak | 5cd1937 | 2011-02-25 16:06:48 -0700 | [diff] [blame] | 77 | clkdm_allow_idle(clkdm); |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 78 | return 0; |
| 79 | } |
| 80 | |
| 81 | static int _cpuidle_deny_idle(struct powerdomain *pwrdm, |
| 82 | struct clockdomain *clkdm) |
| 83 | { |
Rajendra Nayak | 5cd1937 | 2011-02-25 16:06:48 -0700 | [diff] [blame] | 84 | clkdm_deny_idle(clkdm); |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 85 | return 0; |
| 86 | } |
| 87 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 88 | /** |
| 89 | * omap3_enter_idle - Programs OMAP3 to enter the specified state |
| 90 | * @dev: cpuidle device |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 91 | * @drv: cpuidle driver |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 92 | * @index: the index of state to be entered |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 93 | * |
| 94 | * Called from the CPUidle framework to program the device to the |
| 95 | * specified target state selected by the governor. |
| 96 | */ |
| 97 | static int omap3_enter_idle(struct cpuidle_device *dev, |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 98 | struct cpuidle_driver *drv, |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 99 | int index) |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 100 | { |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 101 | struct omap3_idle_statedata *cx = |
Deepthi Dharwar | 4202735 | 2011-10-28 16:20:33 +0530 | [diff] [blame] | 102 | cpuidle_get_statedata(&dev->states_usage[index]); |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 103 | struct timespec ts_preidle, ts_postidle, ts_idle; |
Kevin Hilman | c98e223 | 2008-10-28 17:30:07 -0700 | [diff] [blame] | 104 | u32 mpu_state = cx->mpu_state, core_state = cx->core_state; |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 105 | int idle_time; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 106 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 107 | /* Used to keep track of the total time in idle */ |
| 108 | getnstimeofday(&ts_preidle); |
| 109 | |
| 110 | local_irq_disable(); |
| 111 | local_fiq_disable(); |
| 112 | |
Jouni Hogander | 7139178 | 2008-10-28 10:59:05 +0200 | [diff] [blame] | 113 | pwrdm_set_next_pwrst(mpu_pd, mpu_state); |
| 114 | pwrdm_set_next_pwrst(core_pd, core_state); |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 115 | |
Tero Kristo | cf22854 | 2009-03-20 15:21:02 +0200 | [diff] [blame] | 116 | if (omap_irq_pending() || need_resched()) |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 117 | goto return_sleep_time; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 118 | |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 119 | /* Deny idle for C1 */ |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 120 | if (index == 0) { |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 121 | pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle); |
| 122 | pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle); |
| 123 | } |
| 124 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 125 | /* Execute ARM wfi */ |
| 126 | omap_sram_idle(); |
| 127 | |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 128 | /* Re-allow idle for C1 */ |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 129 | if (index == 0) { |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 130 | pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle); |
| 131 | pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle); |
| 132 | } |
| 133 | |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 134 | return_sleep_time: |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 135 | getnstimeofday(&ts_postidle); |
| 136 | ts_idle = timespec_sub(ts_postidle, ts_preidle); |
| 137 | |
| 138 | local_irq_enable(); |
| 139 | local_fiq_enable(); |
| 140 | |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 141 | idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \ |
| 142 | USEC_PER_SEC; |
| 143 | |
| 144 | /* Update cpuidle counters */ |
| 145 | dev->last_residency = idle_time; |
| 146 | |
| 147 | return index; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 148 | } |
| 149 | |
| 150 | /** |
Jean Pihet | 0490891 | 2011-05-09 12:02:16 +0200 | [diff] [blame] | 151 | * next_valid_state - Find next valid C-state |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 152 | * @dev: cpuidle device |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 153 | * @drv: cpuidle driver |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 154 | * @index: Index of currently selected c-state |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 155 | * |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 156 | * If the state corresponding to index is valid, index is returned back |
| 157 | * to the caller. Else, this function searches for a lower c-state which is |
| 158 | * still valid (as defined in omap3_power_states[]) and returns its index. |
Jean Pihet | 0490891 | 2011-05-09 12:02:16 +0200 | [diff] [blame] | 159 | * |
| 160 | * A state is valid if the 'valid' field is enabled and |
| 161 | * if it satisfies the enable_off_mode condition. |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 162 | */ |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 163 | static int next_valid_state(struct cpuidle_device *dev, |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 164 | struct cpuidle_driver *drv, |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 165 | int index) |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 166 | { |
Deepthi Dharwar | 4202735 | 2011-10-28 16:20:33 +0530 | [diff] [blame] | 167 | struct cpuidle_state_usage *curr_usage = &dev->states_usage[index]; |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 168 | struct cpuidle_state *curr = &drv->states[index]; |
Deepthi Dharwar | 4202735 | 2011-10-28 16:20:33 +0530 | [diff] [blame] | 169 | struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage); |
Jean Pihet | 0490891 | 2011-05-09 12:02:16 +0200 | [diff] [blame] | 170 | u32 mpu_deepest_state = PWRDM_POWER_RET; |
| 171 | u32 core_deepest_state = PWRDM_POWER_RET; |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 172 | int next_index = -1; |
Jean Pihet | 0490891 | 2011-05-09 12:02:16 +0200 | [diff] [blame] | 173 | |
| 174 | if (enable_off_mode) { |
| 175 | mpu_deepest_state = PWRDM_POWER_OFF; |
| 176 | /* |
| 177 | * Erratum i583: valable for ES rev < Es1.2 on 3630. |
| 178 | * CORE OFF mode is not supported in a stable form, restrict |
| 179 | * instead the CORE state to RET. |
| 180 | */ |
| 181 | if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) |
| 182 | core_deepest_state = PWRDM_POWER_OFF; |
| 183 | } |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 184 | |
| 185 | /* Check if current state is valid */ |
Jean Pihet | 0490891 | 2011-05-09 12:02:16 +0200 | [diff] [blame] | 186 | if ((cx->valid) && |
| 187 | (cx->mpu_state >= mpu_deepest_state) && |
| 188 | (cx->core_state >= core_deepest_state)) { |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 189 | return index; |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 190 | } else { |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 191 | int idx = OMAP3_NUM_STATES - 1; |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 192 | |
Jean Pihet | c6cd91d | 2011-05-09 12:02:15 +0200 | [diff] [blame] | 193 | /* Reach the current state starting at highest C-state */ |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 194 | for (; idx >= 0; idx--) { |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 195 | if (&drv->states[idx] == curr) { |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 196 | next_index = idx; |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 197 | break; |
| 198 | } |
| 199 | } |
| 200 | |
Jean Pihet | c6cd91d | 2011-05-09 12:02:15 +0200 | [diff] [blame] | 201 | /* Should never hit this condition */ |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 202 | WARN_ON(next_index == -1); |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 203 | |
| 204 | /* |
| 205 | * Drop to next valid state. |
| 206 | * Start search from the next (lower) state. |
| 207 | */ |
| 208 | idx--; |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 209 | for (; idx >= 0; idx--) { |
Deepthi Dharwar | 4202735 | 2011-10-28 16:20:33 +0530 | [diff] [blame] | 210 | cx = cpuidle_get_statedata(&dev->states_usage[idx]); |
Jean Pihet | 0490891 | 2011-05-09 12:02:16 +0200 | [diff] [blame] | 211 | if ((cx->valid) && |
| 212 | (cx->mpu_state >= mpu_deepest_state) && |
| 213 | (cx->core_state >= core_deepest_state)) { |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 214 | next_index = idx; |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 215 | break; |
| 216 | } |
| 217 | } |
| 218 | /* |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 219 | * C1 is always valid. |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 220 | * So, no need to check for 'next_index == -1' outside |
| 221 | * this loop. |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 222 | */ |
| 223 | } |
| 224 | |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 225 | return next_index; |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 226 | } |
| 227 | |
| 228 | /** |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 229 | * omap3_enter_idle_bm - Checks for any bus activity |
| 230 | * @dev: cpuidle device |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 231 | * @drv: cpuidle driver |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 232 | * @index: array index of target state to be programmed |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 233 | * |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 234 | * This function checks for any pending activity and then programs |
| 235 | * the device to the specified or a safer state. |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 236 | */ |
| 237 | static int omap3_enter_idle_bm(struct cpuidle_device *dev, |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 238 | struct cpuidle_driver *drv, |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 239 | int index) |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 240 | { |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 241 | int new_state_idx; |
Jean Pihet | c6cd91d | 2011-05-09 12:02:15 +0200 | [diff] [blame] | 242 | u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state; |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 243 | struct omap3_idle_statedata *cx; |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 244 | int ret; |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 245 | |
Jean Pihet | c6cd91d | 2011-05-09 12:02:15 +0200 | [diff] [blame] | 246 | if (!omap3_can_sleep()) { |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 247 | new_state_idx = drv->safe_state_index; |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 248 | goto select_state; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 249 | } |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 250 | |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 251 | /* |
| 252 | * Prevent idle completely if CAM is active. |
| 253 | * CAM does not have wakeup capability in OMAP3. |
| 254 | */ |
| 255 | cam_state = pwrdm_read_pwrst(cam_pd); |
| 256 | if (cam_state == PWRDM_POWER_ON) { |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 257 | new_state_idx = drv->safe_state_index; |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 258 | goto select_state; |
| 259 | } |
| 260 | |
| 261 | /* |
Jean Pihet | c6cd91d | 2011-05-09 12:02:15 +0200 | [diff] [blame] | 262 | * FIXME: we currently manage device-specific idle states |
| 263 | * for PER and CORE in combination with CPU-specific |
| 264 | * idle states. This is wrong, and device-specific |
| 265 | * idle management needs to be separated out into |
| 266 | * its own code. |
| 267 | */ |
| 268 | |
| 269 | /* |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 270 | * Prevent PER off if CORE is not in retention or off as this |
| 271 | * would disable PER wakeups completely. |
| 272 | */ |
Deepthi Dharwar | 4202735 | 2011-10-28 16:20:33 +0530 | [diff] [blame] | 273 | cx = cpuidle_get_statedata(&dev->states_usage[index]); |
Jean Pihet | c6cd91d | 2011-05-09 12:02:15 +0200 | [diff] [blame] | 274 | core_next_state = cx->core_state; |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 275 | per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd); |
| 276 | if ((per_next_state == PWRDM_POWER_OFF) && |
Kevin Hilman | 65707fb | 2010-10-01 08:35:47 -0700 | [diff] [blame] | 277 | (core_next_state > PWRDM_POWER_RET)) |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 278 | per_next_state = PWRDM_POWER_RET; |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 279 | |
| 280 | /* Are we changing PER target state? */ |
| 281 | if (per_next_state != per_saved_state) |
| 282 | pwrdm_set_next_pwrst(per_pd, per_next_state); |
| 283 | |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 284 | new_state_idx = next_valid_state(dev, drv, index); |
Jean Pihet | c6cd91d | 2011-05-09 12:02:15 +0200 | [diff] [blame] | 285 | |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 286 | select_state: |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 287 | ret = omap3_enter_idle(dev, drv, new_state_idx); |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 288 | |
| 289 | /* Restore original PER state if it was modified */ |
| 290 | if (per_next_state != per_saved_state) |
| 291 | pwrdm_set_next_pwrst(per_pd, per_saved_state); |
| 292 | |
| 293 | return ret; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 294 | } |
| 295 | |
| 296 | DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); |
| 297 | |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 298 | void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params) |
| 299 | { |
| 300 | int i; |
| 301 | |
| 302 | if (!cpuidle_board_params) |
| 303 | return; |
| 304 | |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 305 | for (i = 0; i < OMAP3_NUM_STATES; i++) { |
| 306 | cpuidle_params_table[i].valid = cpuidle_board_params[i].valid; |
Jean Pihet | 866ba0e | 2011-05-09 12:02:13 +0200 | [diff] [blame] | 307 | cpuidle_params_table[i].exit_latency = |
| 308 | cpuidle_board_params[i].exit_latency; |
| 309 | cpuidle_params_table[i].target_residency = |
| 310 | cpuidle_board_params[i].target_residency; |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 311 | } |
| 312 | return; |
| 313 | } |
| 314 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 315 | struct cpuidle_driver omap3_idle_driver = { |
| 316 | .name = "omap3_idle", |
| 317 | .owner = THIS_MODULE, |
| 318 | }; |
| 319 | |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 320 | /* Helper to fill the C-state common data*/ |
| 321 | static inline void _fill_cstate(struct cpuidle_driver *drv, |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 322 | int idx, const char *descr) |
| 323 | { |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 324 | struct cpuidle_state *state = &drv->states[idx]; |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 325 | |
| 326 | state->exit_latency = cpuidle_params_table[idx].exit_latency; |
| 327 | state->target_residency = cpuidle_params_table[idx].target_residency; |
| 328 | state->flags = CPUIDLE_FLAG_TIME_VALID; |
| 329 | state->enter = omap3_enter_idle_bm; |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 330 | sprintf(state->name, "C%d", idx + 1); |
| 331 | strncpy(state->desc, descr, CPUIDLE_DESC_LEN); |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 332 | |
| 333 | } |
| 334 | |
| 335 | /* Helper to register the driver_data */ |
| 336 | static inline struct omap3_idle_statedata *_fill_cstate_usage( |
| 337 | struct cpuidle_device *dev, |
| 338 | int idx) |
| 339 | { |
| 340 | struct omap3_idle_statedata *cx = &omap3_idle_data[idx]; |
| 341 | struct cpuidle_state_usage *state_usage = &dev->states_usage[idx]; |
| 342 | |
| 343 | cx->valid = cpuidle_params_table[idx].valid; |
Deepthi Dharwar | 4202735 | 2011-10-28 16:20:33 +0530 | [diff] [blame] | 344 | cpuidle_set_statedata(state_usage, cx); |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 345 | |
| 346 | return cx; |
| 347 | } |
| 348 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 349 | /** |
| 350 | * omap3_idle_init - Init routine for OMAP3 idle |
| 351 | * |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 352 | * Registers the OMAP3 specific cpuidle driver to the cpuidle |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 353 | * framework with the valid set of states. |
| 354 | */ |
Kalle Jokiniemi | 0343371 | 2008-09-26 11:04:20 +0300 | [diff] [blame] | 355 | int __init omap3_idle_init(void) |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 356 | { |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 357 | struct cpuidle_device *dev; |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 358 | struct cpuidle_driver *drv = &omap3_idle_driver; |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 359 | struct omap3_idle_statedata *cx; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 360 | |
| 361 | mpu_pd = pwrdm_lookup("mpu_pwrdm"); |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 362 | core_pd = pwrdm_lookup("core_pwrdm"); |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 363 | per_pd = pwrdm_lookup("per_pwrdm"); |
| 364 | cam_pd = pwrdm_lookup("cam_pwrdm"); |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 365 | |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 366 | |
| 367 | drv->safe_state_index = -1; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 368 | dev = &per_cpu(omap3_idle_dev, smp_processor_id()); |
| 369 | |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 370 | /* C1 . MPU WFI + Core active */ |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 371 | _fill_cstate(drv, 0, "MPU ON + CORE ON"); |
| 372 | (&drv->states[0])->enter = omap3_enter_idle; |
| 373 | drv->safe_state_index = 0; |
| 374 | cx = _fill_cstate_usage(dev, 0); |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 375 | cx->valid = 1; /* C1 is always valid */ |
| 376 | cx->mpu_state = PWRDM_POWER_ON; |
| 377 | cx->core_state = PWRDM_POWER_ON; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 378 | |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 379 | /* C2 . MPU WFI + Core inactive */ |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 380 | _fill_cstate(drv, 1, "MPU ON + CORE ON"); |
| 381 | cx = _fill_cstate_usage(dev, 1); |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 382 | cx->mpu_state = PWRDM_POWER_ON; |
| 383 | cx->core_state = PWRDM_POWER_ON; |
| 384 | |
| 385 | /* C3 . MPU CSWR + Core inactive */ |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 386 | _fill_cstate(drv, 2, "MPU RET + CORE ON"); |
| 387 | cx = _fill_cstate_usage(dev, 2); |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 388 | cx->mpu_state = PWRDM_POWER_RET; |
| 389 | cx->core_state = PWRDM_POWER_ON; |
| 390 | |
| 391 | /* C4 . MPU OFF + Core inactive */ |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 392 | _fill_cstate(drv, 3, "MPU OFF + CORE ON"); |
| 393 | cx = _fill_cstate_usage(dev, 3); |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 394 | cx->mpu_state = PWRDM_POWER_OFF; |
| 395 | cx->core_state = PWRDM_POWER_ON; |
| 396 | |
| 397 | /* C5 . MPU RET + Core RET */ |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 398 | _fill_cstate(drv, 4, "MPU RET + CORE RET"); |
| 399 | cx = _fill_cstate_usage(dev, 4); |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 400 | cx->mpu_state = PWRDM_POWER_RET; |
| 401 | cx->core_state = PWRDM_POWER_RET; |
| 402 | |
| 403 | /* C6 . MPU OFF + Core RET */ |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 404 | _fill_cstate(drv, 5, "MPU OFF + CORE RET"); |
| 405 | cx = _fill_cstate_usage(dev, 5); |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 406 | cx->mpu_state = PWRDM_POWER_OFF; |
| 407 | cx->core_state = PWRDM_POWER_RET; |
| 408 | |
| 409 | /* C7 . MPU OFF + Core OFF */ |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 410 | _fill_cstate(drv, 6, "MPU OFF + CORE OFF"); |
| 411 | cx = _fill_cstate_usage(dev, 6); |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 412 | /* |
| 413 | * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot |
| 414 | * enable OFF mode in a stable form for previous revisions. |
| 415 | * We disable C7 state as a result. |
| 416 | */ |
| 417 | if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) { |
| 418 | cx->valid = 0; |
| 419 | pr_warn("%s: core off state C7 disabled due to i583\n", |
| 420 | __func__); |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 421 | } |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 422 | cx->mpu_state = PWRDM_POWER_OFF; |
| 423 | cx->core_state = PWRDM_POWER_OFF; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 424 | |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame^] | 425 | drv->state_count = OMAP3_NUM_STATES; |
| 426 | cpuidle_register_driver(&omap3_idle_driver); |
| 427 | |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 428 | dev->state_count = OMAP3_NUM_STATES; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 429 | if (cpuidle_register_device(dev)) { |
| 430 | printk(KERN_ERR "%s: CPUidle register device failed\n", |
| 431 | __func__); |
| 432 | return -EIO; |
| 433 | } |
| 434 | |
| 435 | return 0; |
| 436 | } |
Kalle Jokiniemi | 0343371 | 2008-09-26 11:04:20 +0300 | [diff] [blame] | 437 | #else |
| 438 | int __init omap3_idle_init(void) |
| 439 | { |
| 440 | return 0; |
| 441 | } |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 442 | #endif /* CONFIG_CPU_IDLE */ |