Clarence Ip | aac9f33 | 2016-08-31 15:46:35 -0400 | [diff] [blame] | 1 | /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 12 | |
| 13 | #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ |
| 14 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 15 | #include <linux/debugfs.h> |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 16 | #include <uapi/drm/sde_drm.h> |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 17 | |
| 18 | #include "msm_prop.h" |
| 19 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 20 | #include "sde_kms.h" |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 21 | #include "sde_fence.h" |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 22 | #include "sde_formats.h" |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 23 | #include "sde_hw_sspp.h" |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 24 | #include "sde_trace.h" |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 25 | #include "sde_crtc.h" |
Lloyd Atkinson | 8772e20 | 2016-09-26 17:52:16 -0400 | [diff] [blame] | 26 | #include "sde_vbif.h" |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 27 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 28 | #define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\ |
| 29 | (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) |
| 30 | |
| 31 | #define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\ |
| 32 | (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) |
| 33 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 34 | #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) |
| 35 | #define PHASE_STEP_SHIFT 21 |
| 36 | #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) |
| 37 | #define PHASE_RESIDUAL 15 |
| 38 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 39 | #define SHARP_STRENGTH_DEFAULT 32 |
| 40 | #define SHARP_EDGE_THR_DEFAULT 112 |
| 41 | #define SHARP_SMOOTH_THR_DEFAULT 8 |
| 42 | #define SHARP_NOISE_THR_DEFAULT 2 |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 43 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 44 | #define SDE_NAME_SIZE 12 |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 45 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 46 | #define SDE_PLANE_COLOR_FILL_FLAG BIT(31) |
| 47 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 48 | /* dirty bits for update function */ |
| 49 | #define SDE_PLANE_DIRTY_RECTS 0x1 |
| 50 | #define SDE_PLANE_DIRTY_FORMAT 0x2 |
| 51 | #define SDE_PLANE_DIRTY_SHARPEN 0x4 |
| 52 | #define SDE_PLANE_DIRTY_ALL 0xFFFFFFFF |
| 53 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 54 | /** |
| 55 | * enum sde_plane_qos - Different qos configurations for each pipe |
| 56 | * |
| 57 | * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe. |
| 58 | * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe. |
| 59 | * this configuration is mutually exclusive from VBLANK_CTRL. |
| 60 | * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe. |
| 61 | */ |
| 62 | enum sde_plane_qos { |
| 63 | SDE_PLANE_QOS_VBLANK_CTRL = BIT(0), |
| 64 | SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1), |
| 65 | SDE_PLANE_QOS_PANIC_CTRL = BIT(2), |
| 66 | }; |
| 67 | |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 68 | /* |
| 69 | * struct sde_plane - local sde plane structure |
| 70 | * @csc_cfg: Decoded user configuration for csc |
| 71 | * @csc_usr_ptr: Points to csc_cfg if valid user config available |
| 72 | * @csc_ptr: Points to sde_csc_cfg structure to use for current |
| 73 | */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 74 | struct sde_plane { |
| 75 | struct drm_plane base; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 76 | |
| 77 | int mmu_id; |
| 78 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 79 | struct mutex lock; |
| 80 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 81 | enum sde_sspp pipe; |
| 82 | uint32_t features; /* capabilities from catalog */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 83 | uint32_t nformats; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 84 | uint32_t formats[64]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 85 | |
| 86 | struct sde_hw_pipe *pipe_hw; |
| 87 | struct sde_hw_pipe_cfg pipe_cfg; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 88 | struct sde_hw_sharp_cfg sharp_cfg; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 89 | struct sde_hw_scaler3_cfg scaler3_cfg; |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 90 | struct sde_hw_pipe_qos_cfg pipe_qos_cfg; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 91 | uint32_t color_fill; |
| 92 | bool is_error; |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 93 | bool is_rt_pipe; |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 94 | |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 95 | struct sde_hw_pixel_ext pixel_ext; |
| 96 | bool pixel_ext_usr; |
| 97 | |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 98 | struct sde_csc_cfg csc_cfg; |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 99 | struct sde_csc_cfg *csc_usr_ptr; |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 100 | struct sde_csc_cfg *csc_ptr; |
| 101 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 102 | const struct sde_sspp_sub_blks *pipe_sblk; |
| 103 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 104 | char pipe_name[SDE_NAME_SIZE]; |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 105 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 106 | struct msm_property_info property_info; |
| 107 | struct msm_property_data property_data[PLANE_PROP_COUNT]; |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 108 | struct drm_property_blob *blob_info; |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 109 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 110 | /* debugfs related stuff */ |
| 111 | struct dentry *debugfs_root; |
| 112 | struct sde_debugfs_regset32 debugfs_src; |
| 113 | struct sde_debugfs_regset32 debugfs_scaler; |
| 114 | struct sde_debugfs_regset32 debugfs_csc; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 115 | }; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 116 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 117 | #define to_sde_plane(x) container_of(x, struct sde_plane, base) |
| 118 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 119 | static bool sde_plane_enabled(struct drm_plane_state *state) |
| 120 | { |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 121 | return state && state->fb && state->crtc; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 122 | } |
| 123 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 124 | /** |
| 125 | * _sde_plane_calc_fill_level - calculate fill level of the given source format |
| 126 | * @plane: Pointer to drm plane |
| 127 | * @fmt: Pointer to source buffer format |
| 128 | * @src_wdith: width of source buffer |
| 129 | * Return: fill level corresponding to the source buffer/format or 0 if error |
| 130 | */ |
| 131 | static inline int _sde_plane_calc_fill_level(struct drm_plane *plane, |
| 132 | const struct sde_format *fmt, u32 src_width) |
| 133 | { |
| 134 | struct sde_plane *psde; |
| 135 | u32 fixed_buff_size; |
| 136 | u32 total_fl; |
| 137 | |
| 138 | if (!plane || !fmt) { |
| 139 | SDE_ERROR("invalid arguments\n"); |
| 140 | return 0; |
| 141 | } |
| 142 | |
| 143 | psde = to_sde_plane(plane); |
| 144 | fixed_buff_size = psde->pipe_sblk->pixel_ram_size; |
| 145 | |
| 146 | if (fmt->fetch_planes == SDE_PLANE_PSEUDO_PLANAR) { |
| 147 | if (fmt->chroma_sample == SDE_CHROMA_420) { |
| 148 | /* NV12 */ |
| 149 | total_fl = (fixed_buff_size / 2) / |
| 150 | ((src_width + 32) * fmt->bpp); |
| 151 | } else { |
| 152 | /* non NV12 */ |
| 153 | total_fl = (fixed_buff_size) / |
| 154 | ((src_width + 32) * fmt->bpp); |
| 155 | } |
| 156 | } else { |
| 157 | total_fl = (fixed_buff_size * 2) / |
| 158 | ((src_width + 32) * fmt->bpp); |
| 159 | } |
| 160 | |
| 161 | SDE_DEBUG("plane%u: pnum:%d fmt:%x w:%u fl:%u\n", |
| 162 | plane->base.id, psde->pipe - SSPP_VIG0, |
| 163 | fmt->base.pixel_format, src_width, total_fl); |
| 164 | |
| 165 | return total_fl; |
| 166 | } |
| 167 | |
| 168 | /** |
| 169 | * _sde_plane_get_qos_lut_linear - get linear LUT mapping |
| 170 | * @total_fl: fill level |
| 171 | * Return: LUT setting corresponding to the fill level |
| 172 | */ |
| 173 | static inline u32 _sde_plane_get_qos_lut_linear(u32 total_fl) |
| 174 | { |
| 175 | u32 qos_lut; |
| 176 | |
| 177 | if (total_fl <= 4) |
| 178 | qos_lut = 0x1B; |
| 179 | else if (total_fl <= 5) |
| 180 | qos_lut = 0x5B; |
| 181 | else if (total_fl <= 6) |
| 182 | qos_lut = 0x15B; |
| 183 | else if (total_fl <= 7) |
| 184 | qos_lut = 0x55B; |
| 185 | else if (total_fl <= 8) |
| 186 | qos_lut = 0x155B; |
| 187 | else if (total_fl <= 9) |
| 188 | qos_lut = 0x555B; |
| 189 | else if (total_fl <= 10) |
| 190 | qos_lut = 0x1555B; |
| 191 | else if (total_fl <= 11) |
| 192 | qos_lut = 0x5555B; |
| 193 | else if (total_fl <= 12) |
| 194 | qos_lut = 0x15555B; |
| 195 | else |
| 196 | qos_lut = 0x55555B; |
| 197 | |
| 198 | return qos_lut; |
| 199 | } |
| 200 | |
| 201 | /** |
| 202 | * _sde_plane_get_qos_lut_macrotile - get macrotile LUT mapping |
| 203 | * @total_fl: fill level |
| 204 | * Return: LUT setting corresponding to the fill level |
| 205 | */ |
| 206 | static inline u32 _sde_plane_get_qos_lut_macrotile(u32 total_fl) |
| 207 | { |
| 208 | u32 qos_lut; |
| 209 | |
| 210 | if (total_fl <= 10) |
| 211 | qos_lut = 0x1AAff; |
| 212 | else if (total_fl <= 11) |
| 213 | qos_lut = 0x5AAFF; |
| 214 | else if (total_fl <= 12) |
| 215 | qos_lut = 0x15AAFF; |
| 216 | else |
| 217 | qos_lut = 0x55AAFF; |
| 218 | |
| 219 | return qos_lut; |
| 220 | } |
| 221 | |
| 222 | /** |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 223 | * _sde_plane_set_qos_lut - set QoS LUT of the given plane |
| 224 | * @plane: Pointer to drm plane |
| 225 | * @fb: Pointer to framebuffer associated with the given plane |
| 226 | */ |
| 227 | static void _sde_plane_set_qos_lut(struct drm_plane *plane, |
| 228 | struct drm_framebuffer *fb) |
| 229 | { |
| 230 | struct sde_plane *psde; |
| 231 | const struct sde_format *fmt = NULL; |
| 232 | u32 qos_lut; |
| 233 | u32 total_fl = 0; |
| 234 | |
| 235 | if (!plane || !fb) { |
| 236 | SDE_ERROR("invalid arguments plane %d fb %d\n", |
| 237 | plane != 0, fb != 0); |
| 238 | return; |
| 239 | } |
| 240 | |
| 241 | psde = to_sde_plane(plane); |
| 242 | |
| 243 | if (!psde->pipe_hw || !psde->pipe_sblk) { |
| 244 | SDE_ERROR("invalid arguments\n"); |
| 245 | return; |
| 246 | } else if (!psde->pipe_hw->ops.setup_creq_lut) { |
| 247 | return; |
| 248 | } |
| 249 | |
| 250 | if (!psde->is_rt_pipe) { |
| 251 | qos_lut = psde->pipe_sblk->creq_lut_nrt; |
| 252 | } else { |
| 253 | fmt = sde_get_sde_format_ext( |
| 254 | fb->pixel_format, |
| 255 | fb->modifier, |
| 256 | drm_format_num_planes(fb->pixel_format)); |
| 257 | total_fl = _sde_plane_calc_fill_level(plane, fmt, |
| 258 | psde->pipe_cfg.src_rect.w); |
| 259 | |
| 260 | if (SDE_FORMAT_IS_LINEAR(fmt)) |
| 261 | qos_lut = _sde_plane_get_qos_lut_linear(total_fl); |
| 262 | else |
| 263 | qos_lut = _sde_plane_get_qos_lut_macrotile(total_fl); |
| 264 | } |
| 265 | |
| 266 | psde->pipe_qos_cfg.creq_lut = qos_lut; |
| 267 | |
| 268 | trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0, |
| 269 | (fmt) ? fmt->base.pixel_format : 0, |
| 270 | psde->is_rt_pipe, total_fl, qos_lut, |
| 271 | (fmt) ? SDE_FORMAT_IS_LINEAR(fmt) : 0); |
| 272 | |
| 273 | SDE_DEBUG("plane%u: pnum:%d fmt:%x rt:%d fl:%u lut:0x%x\n", |
| 274 | plane->base.id, |
| 275 | psde->pipe - SSPP_VIG0, |
| 276 | (fmt) ? fmt->base.pixel_format : 0, |
| 277 | psde->is_rt_pipe, total_fl, qos_lut); |
| 278 | |
| 279 | psde->pipe_hw->ops.setup_creq_lut(psde->pipe_hw, &psde->pipe_qos_cfg); |
| 280 | } |
| 281 | |
| 282 | /** |
| 283 | * _sde_plane_set_panic_lut - set danger/safe LUT of the given plane |
| 284 | * @plane: Pointer to drm plane |
| 285 | * @fb: Pointer to framebuffer associated with the given plane |
| 286 | */ |
| 287 | static void _sde_plane_set_danger_lut(struct drm_plane *plane, |
| 288 | struct drm_framebuffer *fb) |
| 289 | { |
| 290 | struct sde_plane *psde; |
| 291 | const struct sde_format *fmt = NULL; |
| 292 | u32 danger_lut, safe_lut; |
| 293 | |
| 294 | if (!plane || !fb) { |
| 295 | SDE_ERROR("invalid arguments\n"); |
| 296 | return; |
| 297 | } |
| 298 | |
| 299 | psde = to_sde_plane(plane); |
| 300 | |
| 301 | if (!psde->pipe_hw || !psde->pipe_sblk) { |
| 302 | SDE_ERROR("invalid arguments\n"); |
| 303 | return; |
| 304 | } else if (!psde->pipe_hw->ops.setup_danger_safe_lut) { |
| 305 | return; |
| 306 | } |
| 307 | |
| 308 | if (!psde->is_rt_pipe) { |
| 309 | danger_lut = psde->pipe_sblk->danger_lut_nrt; |
| 310 | safe_lut = psde->pipe_sblk->safe_lut_nrt; |
| 311 | } else { |
| 312 | fmt = sde_get_sde_format_ext( |
| 313 | fb->pixel_format, |
| 314 | fb->modifier, |
| 315 | drm_format_num_planes(fb->pixel_format)); |
| 316 | |
| 317 | if (SDE_FORMAT_IS_LINEAR(fmt)) { |
| 318 | danger_lut = psde->pipe_sblk->danger_lut_linear; |
| 319 | safe_lut = psde->pipe_sblk->safe_lut_linear; |
| 320 | } else { |
| 321 | danger_lut = psde->pipe_sblk->danger_lut_tile; |
| 322 | safe_lut = psde->pipe_sblk->safe_lut_tile; |
| 323 | } |
| 324 | } |
| 325 | |
| 326 | psde->pipe_qos_cfg.danger_lut = danger_lut; |
| 327 | psde->pipe_qos_cfg.safe_lut = safe_lut; |
| 328 | |
| 329 | trace_sde_perf_set_danger_luts(psde->pipe - SSPP_VIG0, |
| 330 | (fmt) ? fmt->base.pixel_format : 0, |
| 331 | (fmt) ? fmt->fetch_mode : 0, |
| 332 | psde->pipe_qos_cfg.danger_lut, |
| 333 | psde->pipe_qos_cfg.safe_lut); |
| 334 | |
| 335 | SDE_DEBUG("plane%u: pnum:%d fmt:%x mode:%d luts[0x%x, 0x%x]\n", |
| 336 | plane->base.id, |
| 337 | psde->pipe - SSPP_VIG0, |
| 338 | fmt ? fmt->base.pixel_format : 0, |
| 339 | fmt ? fmt->fetch_mode : -1, |
| 340 | psde->pipe_qos_cfg.danger_lut, |
| 341 | psde->pipe_qos_cfg.safe_lut); |
| 342 | |
| 343 | psde->pipe_hw->ops.setup_danger_safe_lut(psde->pipe_hw, |
| 344 | &psde->pipe_qos_cfg); |
| 345 | } |
| 346 | |
| 347 | /** |
| 348 | * _sde_plane_set_qos_ctrl - set QoS control of the given plane |
| 349 | * @plane: Pointer to drm plane |
| 350 | * @enable: true to enable QoS control |
| 351 | * @flags: QoS control mode (enum sde_plane_qos) |
| 352 | */ |
| 353 | static void _sde_plane_set_qos_ctrl(struct drm_plane *plane, |
| 354 | bool enable, u32 flags) |
| 355 | { |
| 356 | struct sde_plane *psde; |
| 357 | |
| 358 | if (!plane) { |
| 359 | SDE_ERROR("invalid arguments\n"); |
| 360 | return; |
| 361 | } |
| 362 | |
| 363 | psde = to_sde_plane(plane); |
| 364 | |
| 365 | if (!psde->pipe_hw || !psde->pipe_sblk) { |
| 366 | SDE_ERROR("invalid arguments\n"); |
| 367 | return; |
| 368 | } else if (!psde->pipe_hw->ops.setup_qos_ctrl) { |
| 369 | return; |
| 370 | } |
| 371 | |
| 372 | if (flags & SDE_PLANE_QOS_VBLANK_CTRL) { |
| 373 | psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank; |
| 374 | psde->pipe_qos_cfg.danger_vblank = |
| 375 | psde->pipe_sblk->danger_vblank; |
| 376 | psde->pipe_qos_cfg.vblank_en = enable; |
| 377 | } |
| 378 | |
| 379 | if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) { |
| 380 | /* this feature overrules previous VBLANK_CTRL */ |
| 381 | psde->pipe_qos_cfg.vblank_en = false; |
| 382 | psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */ |
| 383 | } |
| 384 | |
| 385 | if (flags & SDE_PLANE_QOS_PANIC_CTRL) |
| 386 | psde->pipe_qos_cfg.danger_safe_en = enable; |
| 387 | |
| 388 | if (!psde->is_rt_pipe) { |
| 389 | psde->pipe_qos_cfg.vblank_en = false; |
| 390 | psde->pipe_qos_cfg.danger_safe_en = false; |
| 391 | } |
| 392 | |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 393 | SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n", |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 394 | plane->base.id, |
| 395 | psde->pipe - SSPP_VIG0, |
| 396 | psde->pipe_qos_cfg.danger_safe_en, |
| 397 | psde->pipe_qos_cfg.vblank_en, |
| 398 | psde->pipe_qos_cfg.creq_vblank, |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 399 | psde->pipe_qos_cfg.danger_vblank, |
| 400 | psde->is_rt_pipe); |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 401 | |
| 402 | psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw, |
| 403 | &psde->pipe_qos_cfg); |
| 404 | } |
| 405 | |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 406 | /** |
| 407 | * _sde_plane_set_ot_limit - set OT limit for the given plane |
| 408 | * @plane: Pointer to drm plane |
| 409 | * @crtc: Pointer to drm crtc |
| 410 | */ |
| 411 | static void _sde_plane_set_ot_limit(struct drm_plane *plane, |
| 412 | struct drm_crtc *crtc) |
| 413 | { |
| 414 | struct sde_plane *psde; |
| 415 | struct sde_vbif_set_ot_params ot_params; |
| 416 | struct msm_drm_private *priv; |
| 417 | struct sde_kms *sde_kms; |
| 418 | |
| 419 | if (!plane || !plane->dev || !crtc) { |
| 420 | SDE_ERROR("invalid arguments plane %d crtc %d\n", |
| 421 | plane != 0, crtc != 0); |
| 422 | return; |
| 423 | } |
| 424 | |
| 425 | priv = plane->dev->dev_private; |
| 426 | if (!priv || !priv->kms) { |
| 427 | SDE_ERROR("invalid KMS reference\n"); |
| 428 | return; |
| 429 | } |
| 430 | |
| 431 | sde_kms = to_sde_kms(priv->kms); |
| 432 | psde = to_sde_plane(plane); |
| 433 | if (!psde->pipe_hw) { |
| 434 | SDE_ERROR("invalid pipe reference\n"); |
| 435 | return; |
| 436 | } |
| 437 | |
| 438 | memset(&ot_params, 0, sizeof(ot_params)); |
| 439 | ot_params.xin_id = psde->pipe_hw->cap->xin_id; |
| 440 | ot_params.num = psde->pipe_hw->idx - SSPP_NONE; |
| 441 | ot_params.width = psde->pipe_cfg.src_rect.w; |
| 442 | ot_params.height = psde->pipe_cfg.src_rect.h; |
| 443 | ot_params.is_wfd = !psde->is_rt_pipe; |
| 444 | ot_params.frame_rate = crtc->mode.vrefresh; |
| 445 | ot_params.vbif_idx = VBIF_RT; |
| 446 | ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl; |
| 447 | ot_params.rd = true; |
| 448 | |
| 449 | sde_vbif_set_ot_limit(sde_kms, &ot_params); |
| 450 | } |
| 451 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 452 | /* helper to update a state's input fence pointer from the property */ |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 453 | static void _sde_plane_set_input_fence(struct sde_plane *psde, |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 454 | struct sde_plane_state *pstate, uint64_t fd) |
| 455 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 456 | if (!psde || !pstate) { |
| 457 | SDE_ERROR("invalid arg(s), plane %d state %d\n", |
| 458 | psde != 0, pstate != 0); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 459 | return; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 460 | } |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 461 | |
| 462 | /* clear previous reference */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 463 | if (pstate->input_fence) |
| 464 | sde_sync_put(pstate->input_fence); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 465 | |
| 466 | /* get fence pointer for later */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 467 | pstate->input_fence = sde_sync_get(fd); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 468 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 469 | SDE_DEBUG_PLANE(psde, "0x%llX\n", fd); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 470 | } |
| 471 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 472 | int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms) |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 473 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 474 | struct sde_plane *psde; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 475 | struct sde_plane_state *pstate; |
Clarence Ip | 78a04ed | 2016-10-04 15:57:45 -0400 | [diff] [blame] | 476 | uint32_t prefix; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 477 | void *input_fence; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 478 | int ret = -EINVAL; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 479 | |
| 480 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 481 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 482 | } else if (!plane->state) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 483 | SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n"); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 484 | } else { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 485 | psde = to_sde_plane(plane); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 486 | pstate = to_sde_plane_state(plane->state); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 487 | input_fence = pstate->input_fence; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 488 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 489 | if (input_fence) { |
Clarence Ip | 78a04ed | 2016-10-04 15:57:45 -0400 | [diff] [blame] | 490 | prefix = sde_sync_get_name_prefix(input_fence); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 491 | ret = sde_sync_wait(input_fence, wait_ms); |
Clarence Ip | 78a04ed | 2016-10-04 15:57:45 -0400 | [diff] [blame] | 492 | |
| 493 | MSM_EVT(plane->dev, |
| 494 | plane->base.id, |
| 495 | (uint64_t)-ret << (sizeof(uint32_t) * CHAR_BIT) |
| 496 | | prefix); |
| 497 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 498 | switch (ret) { |
| 499 | case 0: |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 500 | SDE_DEBUG_PLANE(psde, "signaled\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 501 | break; |
| 502 | case -ETIME: |
Clarence Ip | 78a04ed | 2016-10-04 15:57:45 -0400 | [diff] [blame] | 503 | SDE_ERROR_PLANE(psde, "%ums timeout on %08X\n", |
| 504 | wait_ms, prefix); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 505 | psde->is_error = true; |
| 506 | break; |
| 507 | default: |
Clarence Ip | 78a04ed | 2016-10-04 15:57:45 -0400 | [diff] [blame] | 508 | SDE_ERROR_PLANE(psde, "error %d on %08X\n", |
| 509 | ret, prefix); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 510 | psde->is_error = true; |
| 511 | break; |
| 512 | } |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 513 | } else { |
| 514 | ret = 0; |
| 515 | } |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 516 | } |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 517 | return ret; |
| 518 | } |
| 519 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 520 | static inline void _sde_plane_set_scanout(struct drm_plane *plane, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 521 | struct sde_plane_state *pstate, |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 522 | struct sde_hw_pipe_cfg *pipe_cfg, |
| 523 | struct drm_framebuffer *fb) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 524 | { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 525 | struct sde_plane *psde; |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 526 | int ret; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 527 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 528 | if (!plane || !pstate || !pipe_cfg || !fb) { |
| 529 | SDE_ERROR( |
| 530 | "invalid arg(s), plane %d state %d cfg %d fb %d\n", |
| 531 | plane != 0, pstate != 0, pipe_cfg != 0, fb != 0); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 532 | return; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 533 | } |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 534 | |
| 535 | psde = to_sde_plane(plane); |
Clarence Ip | b6eb236 | 2016-09-08 16:18:13 -0400 | [diff] [blame] | 536 | if (!psde->pipe_hw) { |
| 537 | SDE_ERROR_PLANE(psde, "invalid pipe_hw\n"); |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 538 | return; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 539 | } |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 540 | |
Clarence Ip | b6eb236 | 2016-09-08 16:18:13 -0400 | [diff] [blame] | 541 | ret = sde_format_populate_layout(psde->mmu_id, fb, &pipe_cfg->layout); |
| 542 | if (ret == -EAGAIN) |
| 543 | SDE_DEBUG_PLANE(psde, "not updating same src addrs\n"); |
| 544 | else if (ret) |
| 545 | SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret); |
| 546 | else if (psde->pipe_hw->ops.setup_sourceaddress) |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 547 | psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 548 | } |
| 549 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 550 | static void _sde_plane_setup_scaler3(struct sde_plane *psde, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 551 | uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, |
| 552 | struct sde_hw_scaler3_cfg *scale_cfg, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 553 | const struct sde_format *fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 554 | uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) |
| 555 | { |
| 556 | } |
| 557 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 558 | /** |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 559 | * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 560 | * @psde: Pointer to SDE plane object |
| 561 | * @src: Source size |
| 562 | * @dst: Destination size |
| 563 | * @phase_steps: Pointer to output array for phase steps |
| 564 | * @filter: Pointer to output array for filter type |
| 565 | * @fmt: Pointer to format definition |
| 566 | * @chroma_subsampling: Subsampling amount for chroma channel |
| 567 | * |
| 568 | * Returns: 0 on success |
| 569 | */ |
| 570 | static int _sde_plane_setup_scaler2(struct sde_plane *psde, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 571 | uint32_t src, uint32_t dst, uint32_t *phase_steps, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 572 | enum sde_hw_filter *filter, const struct sde_format *fmt, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 573 | uint32_t chroma_subsampling) |
| 574 | { |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 575 | if (!psde || !phase_steps || !filter || !fmt) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 576 | SDE_ERROR( |
| 577 | "invalid arg(s), plane %d phase %d filter %d fmt %d\n", |
| 578 | psde != 0, phase_steps != 0, filter != 0, fmt != 0); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 579 | return -EINVAL; |
| 580 | } |
| 581 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 582 | /* calculate phase steps, leave init phase as zero */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 583 | phase_steps[SDE_SSPP_COMP_0] = |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 584 | mult_frac(1 << PHASE_STEP_SHIFT, src, dst); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 585 | phase_steps[SDE_SSPP_COMP_1_2] = |
| 586 | phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling; |
| 587 | phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2]; |
| 588 | phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 589 | |
| 590 | /* calculate scaler config, if necessary */ |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 591 | if (SDE_FORMAT_IS_YUV(fmt) || src != dst) { |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 592 | filter[SDE_SSPP_COMP_3] = |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 593 | (src <= dst) ? SDE_SCALE_FILTER_BIL : |
| 594 | SDE_SCALE_FILTER_PCMN; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 595 | |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 596 | if (SDE_FORMAT_IS_YUV(fmt)) { |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 597 | filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 598 | filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3]; |
| 599 | } else { |
| 600 | filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3]; |
| 601 | filter[SDE_SSPP_COMP_1_2] = |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 602 | SDE_SCALE_FILTER_NEAREST; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 603 | } |
| 604 | } else { |
| 605 | /* disable scaler */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 606 | filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX; |
| 607 | filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX; |
| 608 | filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 609 | } |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 610 | return 0; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 611 | } |
| 612 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 613 | /** |
| 614 | * _sde_plane_setup_pixel_ext - determine default pixel extension values |
| 615 | * @psde: Pointer to SDE plane object |
| 616 | * @src: Source size |
| 617 | * @dst: Destination size |
| 618 | * @decimated_src: Source size after decimation, if any |
| 619 | * @phase_steps: Pointer to output array for phase steps |
| 620 | * @out_src: Output array for pixel extension values |
| 621 | * @out_edge1: Output array for pixel extension first edge |
| 622 | * @out_edge2: Output array for pixel extension second edge |
| 623 | * @filter: Pointer to array for filter type |
| 624 | * @fmt: Pointer to format definition |
| 625 | * @chroma_subsampling: Subsampling amount for chroma channel |
| 626 | * @post_compare: Whether to chroma subsampled source size for comparisions |
| 627 | */ |
| 628 | static void _sde_plane_setup_pixel_ext(struct sde_plane *psde, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 629 | uint32_t src, uint32_t dst, uint32_t decimated_src, |
| 630 | uint32_t *phase_steps, uint32_t *out_src, int *out_edge1, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 631 | int *out_edge2, enum sde_hw_filter *filter, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 632 | const struct sde_format *fmt, uint32_t chroma_subsampling, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 633 | bool post_compare) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 634 | { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 635 | int64_t edge1, edge2, caf; |
| 636 | uint32_t src_work; |
| 637 | int i, tmp; |
| 638 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 639 | if (psde && phase_steps && out_src && out_edge1 && |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 640 | out_edge2 && filter && fmt) { |
| 641 | /* handle CAF for YUV formats */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 642 | if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 643 | caf = PHASE_STEP_UNIT_SCALE; |
| 644 | else |
| 645 | caf = 0; |
| 646 | |
| 647 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 648 | src_work = decimated_src; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 649 | if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 650 | src_work /= chroma_subsampling; |
| 651 | if (post_compare) |
| 652 | src = src_work; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 653 | if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 654 | /* unity */ |
| 655 | edge1 = 0; |
| 656 | edge2 = 0; |
| 657 | } else if (dst >= src) { |
| 658 | /* upscale */ |
| 659 | edge1 = (1 << PHASE_RESIDUAL); |
| 660 | edge1 -= caf; |
| 661 | edge2 = (1 << PHASE_RESIDUAL); |
| 662 | edge2 += (dst - 1) * *(phase_steps + i); |
| 663 | edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE; |
| 664 | edge2 += caf; |
| 665 | edge2 = -(edge2); |
| 666 | } else { |
| 667 | /* downscale */ |
| 668 | edge1 = 0; |
| 669 | edge2 = (dst - 1) * *(phase_steps + i); |
| 670 | edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE; |
| 671 | edge2 += *(phase_steps + i); |
| 672 | edge2 = -(edge2); |
| 673 | } |
| 674 | |
| 675 | /* only enable CAF for luma plane */ |
| 676 | caf = 0; |
| 677 | |
| 678 | /* populate output arrays */ |
| 679 | *(out_src + i) = src_work; |
| 680 | |
| 681 | /* edge updates taken from __pxl_extn_helper */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 682 | if (edge1 >= 0) { |
| 683 | tmp = (uint32_t)edge1; |
| 684 | tmp >>= PHASE_STEP_SHIFT; |
| 685 | *(out_edge1 + i) = -tmp; |
| 686 | } else { |
| 687 | tmp = (uint32_t)(-edge1); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 688 | *(out_edge1 + i) = |
| 689 | (tmp + PHASE_STEP_UNIT_SCALE - 1) >> |
| 690 | PHASE_STEP_SHIFT; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 691 | } |
| 692 | if (edge2 >= 0) { |
| 693 | tmp = (uint32_t)edge2; |
| 694 | tmp >>= PHASE_STEP_SHIFT; |
| 695 | *(out_edge2 + i) = -tmp; |
| 696 | } else { |
| 697 | tmp = (uint32_t)(-edge2); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 698 | *(out_edge2 + i) = |
| 699 | (tmp + PHASE_STEP_UNIT_SCALE - 1) >> |
| 700 | PHASE_STEP_SHIFT; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 701 | } |
| 702 | } |
| 703 | } |
| 704 | } |
| 705 | |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 706 | static inline void _sde_plane_setup_csc(struct sde_plane *psde) |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 707 | { |
| 708 | static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = { |
| 709 | { |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 710 | /* S15.16 format */ |
| 711 | 0x00012A00, 0x00000000, 0x00019880, |
| 712 | 0x00012A00, 0xFFFF9B80, 0xFFFF3000, |
| 713 | 0x00012A00, 0x00020480, 0x00000000, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 714 | }, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 715 | /* signed bias */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 716 | { 0xfff0, 0xff80, 0xff80,}, |
| 717 | { 0x0, 0x0, 0x0,}, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 718 | /* unsigned clamp */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 719 | { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,}, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 720 | { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,}, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 721 | }; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 722 | |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 723 | if (!psde) { |
| 724 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 725 | return; |
| 726 | } |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 727 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 728 | /* revert to kernel default if override not available */ |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 729 | if (psde->csc_usr_ptr) |
| 730 | psde->csc_ptr = psde->csc_usr_ptr; |
| 731 | else |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 732 | psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L; |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 733 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 734 | SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n", |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 735 | psde->csc_ptr->csc_mv[0], |
| 736 | psde->csc_ptr->csc_mv[1], |
| 737 | psde->csc_ptr->csc_mv[2]); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 738 | } |
| 739 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 740 | static void _sde_plane_setup_scaler(struct sde_plane *psde, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 741 | const struct sde_format *fmt, |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 742 | struct sde_plane_state *pstate) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 743 | { |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 744 | struct sde_hw_pixel_ext *pe; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 745 | uint32_t chroma_subsmpl_h, chroma_subsmpl_v; |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 746 | uint32_t tmp, i; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 747 | |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 748 | if (!psde || !fmt) { |
| 749 | SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n", |
| 750 | psde != 0, fmt != 0, pstate != 0); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 751 | return; |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 752 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 753 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 754 | pe = &(psde->pixel_ext); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 755 | |
Clarence Ip | dedbba9 | 2016-09-27 17:43:10 -0400 | [diff] [blame] | 756 | psde->pipe_cfg.horz_decimation = |
| 757 | sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE); |
| 758 | psde->pipe_cfg.vert_decimation = |
| 759 | sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE); |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 760 | |
| 761 | /* don't chroma subsample if decimating */ |
| 762 | chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 763 | drm_format_horz_chroma_subsampling(fmt->base.pixel_format); |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 764 | chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 765 | drm_format_vert_chroma_subsampling(fmt->base.pixel_format); |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 766 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 767 | /* update scaler */ |
| 768 | if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) { |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 769 | if (!psde->pixel_ext_usr) { |
| 770 | /* calculate default config for QSEED3 */ |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 771 | _sde_plane_setup_scaler3(psde, |
| 772 | psde->pipe_cfg.src_rect.w, |
| 773 | psde->pipe_cfg.src_rect.h, |
| 774 | psde->pipe_cfg.dst_rect.w, |
| 775 | psde->pipe_cfg.dst_rect.h, |
| 776 | &psde->scaler3_cfg, fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 777 | chroma_subsmpl_h, chroma_subsmpl_v); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 778 | } |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 779 | } else if (!psde->pixel_ext_usr) { |
| 780 | /* calculate default configuration for QSEED2 */ |
| 781 | memset(pe, 0, sizeof(struct sde_hw_pixel_ext)); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 782 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 783 | SDE_DEBUG_PLANE(psde, "default config\n"); |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 784 | _sde_plane_setup_scaler2(psde, |
| 785 | psde->pipe_cfg.src_rect.w, |
| 786 | psde->pipe_cfg.dst_rect.w, |
| 787 | pe->phase_step_x, |
| 788 | pe->horz_filter, fmt, chroma_subsmpl_h); |
| 789 | _sde_plane_setup_scaler2(psde, |
| 790 | psde->pipe_cfg.src_rect.h, |
| 791 | psde->pipe_cfg.dst_rect.h, |
| 792 | pe->phase_step_y, |
| 793 | pe->vert_filter, fmt, chroma_subsmpl_v); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 794 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 795 | /* calculate left/right/top/bottom pixel extensions */ |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 796 | tmp = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 797 | psde->pipe_cfg.horz_decimation); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 798 | if (SDE_FORMAT_IS_YUV(fmt)) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 799 | tmp &= ~0x1; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 800 | _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w, |
| 801 | psde->pipe_cfg.dst_rect.w, tmp, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 802 | pe->phase_step_x, |
| 803 | pe->roi_w, |
| 804 | pe->num_ext_pxls_left, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 805 | pe->num_ext_pxls_right, pe->horz_filter, fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 806 | chroma_subsmpl_h, 0); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 807 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 808 | tmp = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 809 | psde->pipe_cfg.vert_decimation); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 810 | _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h, |
| 811 | psde->pipe_cfg.dst_rect.h, tmp, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 812 | pe->phase_step_y, |
| 813 | pe->roi_h, |
| 814 | pe->num_ext_pxls_top, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 815 | pe->num_ext_pxls_btm, pe->vert_filter, fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 816 | chroma_subsmpl_v, 1); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 817 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 818 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 819 | if (pe->num_ext_pxls_left[i] >= 0) |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 820 | pe->left_rpt[i] = pe->num_ext_pxls_left[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 821 | else |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 822 | pe->left_ftch[i] = pe->num_ext_pxls_left[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 823 | |
| 824 | if (pe->num_ext_pxls_right[i] >= 0) |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 825 | pe->right_rpt[i] = pe->num_ext_pxls_right[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 826 | else |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 827 | pe->right_ftch[i] = pe->num_ext_pxls_right[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 828 | |
| 829 | if (pe->num_ext_pxls_top[i] >= 0) |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 830 | pe->top_rpt[i] = pe->num_ext_pxls_top[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 831 | else |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 832 | pe->top_ftch[i] = pe->num_ext_pxls_top[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 833 | |
| 834 | if (pe->num_ext_pxls_btm[i] >= 0) |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 835 | pe->btm_rpt[i] = pe->num_ext_pxls_btm[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 836 | else |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 837 | pe->btm_ftch[i] = pe->num_ext_pxls_btm[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 838 | } |
| 839 | } |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 840 | } |
| 841 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 842 | /** |
| 843 | * _sde_plane_color_fill - enables color fill on plane |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 844 | * @psde: Pointer to SDE plane object |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 845 | * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red |
| 846 | * @alpha: 8-bit fill alpha value, 255 selects 100% alpha |
| 847 | * Returns: 0 on success |
| 848 | */ |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 849 | static int _sde_plane_color_fill(struct sde_plane *psde, |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 850 | uint32_t color, uint32_t alpha) |
| 851 | { |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 852 | const struct sde_format *fmt; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 853 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 854 | if (!psde) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 855 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 856 | return -EINVAL; |
| 857 | } |
| 858 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 859 | if (!psde->pipe_hw) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 860 | SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n"); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 861 | return -EINVAL; |
| 862 | } |
| 863 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 864 | SDE_DEBUG_PLANE(psde, "\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 865 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 866 | /* |
| 867 | * select fill format to match user property expectation, |
| 868 | * h/w only supports RGB variants |
| 869 | */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 870 | fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 871 | |
| 872 | /* update sspp */ |
| 873 | if (fmt && psde->pipe_hw->ops.setup_solidfill) { |
| 874 | psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw, |
| 875 | (color & 0xFFFFFF) | ((alpha & 0xFF) << 24)); |
| 876 | |
| 877 | /* override scaler/decimation if solid fill */ |
| 878 | psde->pipe_cfg.src_rect.x = 0; |
| 879 | psde->pipe_cfg.src_rect.y = 0; |
| 880 | psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w; |
| 881 | psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h; |
| 882 | |
| 883 | _sde_plane_setup_scaler(psde, fmt, 0); |
| 884 | |
| 885 | if (psde->pipe_hw->ops.setup_format) |
| 886 | psde->pipe_hw->ops.setup_format(psde->pipe_hw, |
| 887 | fmt, SDE_SSPP_SOLID_FILL); |
| 888 | |
| 889 | if (psde->pipe_hw->ops.setup_rects) |
| 890 | psde->pipe_hw->ops.setup_rects(psde->pipe_hw, |
| 891 | &psde->pipe_cfg, &psde->pixel_ext); |
| 892 | } |
| 893 | |
| 894 | return 0; |
| 895 | } |
| 896 | |
| 897 | static int _sde_plane_mode_set(struct drm_plane *plane, |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 898 | struct drm_plane_state *state) |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 899 | { |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 900 | uint32_t nplanes, src_flags; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 901 | struct sde_plane *psde; |
| 902 | struct sde_plane_state *pstate; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 903 | const struct sde_format *fmt; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 904 | struct drm_crtc *crtc; |
| 905 | struct drm_framebuffer *fb; |
| 906 | struct sde_rect src, dst; |
| 907 | bool q16_data = true; |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 908 | int idx; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 909 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 910 | if (!plane) { |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 911 | SDE_ERROR("invalid plane\n"); |
| 912 | return -EINVAL; |
| 913 | } else if (!plane->state) { |
| 914 | SDE_ERROR("invalid plane state\n"); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 915 | return -EINVAL; |
| 916 | } |
| 917 | |
| 918 | psde = to_sde_plane(plane); |
| 919 | pstate = to_sde_plane_state(plane->state); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 920 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 921 | crtc = state->crtc; |
| 922 | fb = state->fb; |
| 923 | if (!crtc || !fb) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 924 | SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n", |
| 925 | crtc != 0, fb != 0); |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 926 | return -EINVAL; |
| 927 | } |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 928 | fmt = to_sde_format(msm_framebuffer_format(fb)); |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 929 | nplanes = fmt->num_planes; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 930 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 931 | /* determine what needs to be refreshed */ |
| 932 | while ((idx = msm_property_pop_dirty(&psde->property_info)) >= 0) { |
| 933 | switch (idx) { |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 934 | case PLANE_PROP_SCALER_V1: |
Clarence Ip | dedbba9 | 2016-09-27 17:43:10 -0400 | [diff] [blame] | 935 | case PLANE_PROP_H_DECIMATE: |
| 936 | case PLANE_PROP_V_DECIMATE: |
| 937 | case PLANE_PROP_SRC_CONFIG: |
| 938 | case PLANE_PROP_ZPOS: |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 939 | pstate->dirty |= SDE_PLANE_DIRTY_RECTS; |
| 940 | break; |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 941 | case PLANE_PROP_CSC_V1: |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 942 | pstate->dirty |= SDE_PLANE_DIRTY_FORMAT; |
| 943 | break; |
| 944 | case PLANE_PROP_COLOR_FILL: |
| 945 | /* potentially need to refresh everything */ |
| 946 | pstate->dirty = SDE_PLANE_DIRTY_ALL; |
| 947 | break; |
| 948 | case PLANE_PROP_ROTATION: |
| 949 | pstate->dirty |= SDE_PLANE_DIRTY_FORMAT; |
| 950 | break; |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 951 | case PLANE_PROP_INFO: |
| 952 | case PLANE_PROP_ALPHA: |
| 953 | case PLANE_PROP_INPUT_FENCE: |
| 954 | case PLANE_PROP_BLEND_OP: |
| 955 | /* no special action required */ |
| 956 | break; |
| 957 | default: |
| 958 | /* unknown property, refresh everything */ |
| 959 | pstate->dirty |= SDE_PLANE_DIRTY_ALL; |
| 960 | SDE_ERROR("executing full mode set, prp_idx %d\n", idx); |
| 961 | break; |
| 962 | } |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 963 | } |
| 964 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 965 | if (pstate->dirty & SDE_PLANE_DIRTY_RECTS) |
| 966 | memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg)); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 967 | |
| 968 | _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb); |
| 969 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 970 | /* early out if nothing dirty */ |
| 971 | if (!pstate->dirty) |
| 972 | return 0; |
| 973 | pstate->pending = true; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 974 | |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 975 | psde->is_rt_pipe = sde_crtc_is_rt(crtc); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 976 | _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL); |
| 977 | |
| 978 | /* update roi config */ |
| 979 | if (pstate->dirty & SDE_PLANE_DIRTY_RECTS) { |
| 980 | POPULATE_RECT(&src, state->src_x, state->src_y, |
| 981 | state->src_w, state->src_h, q16_data); |
| 982 | POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, |
| 983 | state->crtc_w, state->crtc_h, !q16_data); |
| 984 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 985 | SDE_DEBUG_PLANE(psde, |
| 986 | "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %s ubwc %d\n", |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 987 | fb->base.id, src.x, src.y, src.w, src.h, |
| 988 | crtc->base.id, dst.x, dst.y, dst.w, dst.h, |
| 989 | drm_get_format_name(fmt->base.pixel_format), |
| 990 | SDE_FORMAT_IS_UBWC(fmt)); |
| 991 | |
| 992 | if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) & |
| 993 | BIT(SDE_DRM_DEINTERLACE)) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 994 | SDE_DEBUG_PLANE(psde, "deinterlace\n"); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 995 | for (idx = 0; idx < SDE_MAX_PLANES; ++idx) |
| 996 | psde->pipe_cfg.layout.plane_pitch[idx] <<= 1; |
| 997 | src.h /= 2; |
| 998 | src.y = DIV_ROUND_UP(src.y, 2); |
| 999 | src.y &= ~0x1; |
| 1000 | } |
| 1001 | |
| 1002 | psde->pipe_cfg.src_rect = src; |
| 1003 | psde->pipe_cfg.dst_rect = dst; |
| 1004 | |
| 1005 | /* check for color fill */ |
| 1006 | psde->color_fill = (uint32_t)sde_plane_get_property(pstate, |
| 1007 | PLANE_PROP_COLOR_FILL); |
| 1008 | if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) { |
| 1009 | /* skip remaining processing on color fill */ |
| 1010 | pstate->dirty = 0x0; |
| 1011 | } else if (psde->pipe_hw->ops.setup_rects) { |
| 1012 | _sde_plane_setup_scaler(psde, fmt, pstate); |
| 1013 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1014 | psde->pipe_hw->ops.setup_rects(psde->pipe_hw, |
| 1015 | &psde->pipe_cfg, &psde->pixel_ext); |
| 1016 | } |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1017 | } |
| 1018 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1019 | if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT) && |
| 1020 | psde->pipe_hw->ops.setup_format) { |
| 1021 | src_flags = 0x0; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1022 | SDE_DEBUG_PLANE(psde, "rotation 0x%llX\n", |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1023 | sde_plane_get_property(pstate, PLANE_PROP_ROTATION)); |
| 1024 | if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) & |
| 1025 | BIT(DRM_REFLECT_X)) |
| 1026 | src_flags |= SDE_SSPP_FLIP_LR; |
| 1027 | if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) & |
| 1028 | BIT(DRM_REFLECT_Y)) |
| 1029 | src_flags |= SDE_SSPP_FLIP_UD; |
| 1030 | |
| 1031 | /* update format */ |
| 1032 | psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt, src_flags); |
| 1033 | |
| 1034 | /* update csc */ |
| 1035 | if (SDE_FORMAT_IS_YUV(fmt)) |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1036 | _sde_plane_setup_csc(psde); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1037 | else |
| 1038 | psde->csc_ptr = 0; |
| 1039 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1040 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1041 | /* update sharpening */ |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1042 | if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) && |
| 1043 | psde->pipe_hw->ops.setup_sharpening) { |
| 1044 | psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT; |
| 1045 | psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT; |
| 1046 | psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT; |
| 1047 | psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1048 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1049 | psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw, |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1050 | &psde->sharp_cfg); |
| 1051 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1052 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 1053 | _sde_plane_set_qos_lut(plane, fb); |
| 1054 | _sde_plane_set_danger_lut(plane, fb); |
| 1055 | |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 1056 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 1057 | _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL); |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 1058 | _sde_plane_set_ot_limit(plane, crtc); |
| 1059 | } |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 1060 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1061 | /* clear dirty */ |
| 1062 | pstate->dirty = 0x0; |
| 1063 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1064 | return 0; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1065 | } |
| 1066 | |
| 1067 | static int sde_plane_prepare_fb(struct drm_plane *plane, |
| 1068 | const struct drm_plane_state *new_state) |
| 1069 | { |
| 1070 | struct drm_framebuffer *fb = new_state->fb; |
| 1071 | struct sde_plane *psde = to_sde_plane(plane); |
| 1072 | |
| 1073 | if (!new_state->fb) |
| 1074 | return 0; |
| 1075 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1076 | SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1077 | return msm_framebuffer_prepare(fb, psde->mmu_id); |
| 1078 | } |
| 1079 | |
| 1080 | static void sde_plane_cleanup_fb(struct drm_plane *plane, |
| 1081 | const struct drm_plane_state *old_state) |
| 1082 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1083 | struct drm_framebuffer *fb = old_state ? old_state->fb : NULL; |
| 1084 | struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1085 | |
| 1086 | if (!fb) |
| 1087 | return; |
| 1088 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1089 | SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1090 | msm_framebuffer_cleanup(fb, psde->mmu_id); |
| 1091 | } |
| 1092 | |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1093 | static void _sde_plane_atomic_check_mode_changed(struct sde_plane *psde, |
| 1094 | struct drm_plane_state *state, |
| 1095 | struct drm_plane_state *old_state) |
| 1096 | { |
| 1097 | struct sde_plane_state *pstate = to_sde_plane_state(state); |
| 1098 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1099 | /* no need to check it again */ |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1100 | if (pstate->dirty == SDE_PLANE_DIRTY_ALL) |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1101 | return; |
| 1102 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1103 | if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state) |
| 1104 | || psde->is_error) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1105 | SDE_DEBUG_PLANE(psde, |
| 1106 | "enabling/disabling full modeset required\n"); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1107 | pstate->dirty |= SDE_PLANE_DIRTY_ALL; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1108 | } else if (to_sde_plane_state(old_state)->pending) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1109 | SDE_DEBUG_PLANE(psde, "still pending\n"); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1110 | pstate->dirty |= SDE_PLANE_DIRTY_ALL; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1111 | } else if (state->src_w != old_state->src_w || |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1112 | state->src_h != old_state->src_h || |
| 1113 | state->src_x != old_state->src_x || |
| 1114 | state->src_y != old_state->src_y) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1115 | SDE_DEBUG_PLANE(psde, "src rect updated\n"); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1116 | pstate->dirty |= SDE_PLANE_DIRTY_RECTS; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1117 | } else if (state->crtc_w != old_state->crtc_w || |
| 1118 | state->crtc_h != old_state->crtc_h || |
| 1119 | state->crtc_x != old_state->crtc_x || |
| 1120 | state->crtc_y != old_state->crtc_y) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1121 | SDE_DEBUG_PLANE(psde, "crtc rect updated\n"); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1122 | pstate->dirty |= SDE_PLANE_DIRTY_RECTS; |
| 1123 | } |
| 1124 | |
| 1125 | if (!state->fb || !old_state->fb) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1126 | SDE_DEBUG_PLANE(psde, "can't compare fb handles\n"); |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1127 | } else if (state->fb->pixel_format != old_state->fb->pixel_format) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1128 | SDE_DEBUG_PLANE(psde, "format change\n"); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1129 | pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1130 | } else { |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1131 | uint64_t *new_mods = state->fb->modifier; |
| 1132 | uint64_t *old_mods = old_state->fb->modifier; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1133 | uint32_t *new_pitches = state->fb->pitches; |
| 1134 | uint32_t *old_pitches = old_state->fb->pitches; |
| 1135 | uint32_t *new_offset = state->fb->offsets; |
| 1136 | uint32_t *old_offset = old_state->fb->offsets; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1137 | int i; |
| 1138 | |
| 1139 | for (i = 0; i < ARRAY_SIZE(state->fb->modifier); i++) { |
| 1140 | if (new_mods[i] != old_mods[i]) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1141 | SDE_DEBUG_PLANE(psde, |
| 1142 | "format modifiers change\"\ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1143 | plane:%d new_mode:%llu old_mode:%llu\n", |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1144 | i, new_mods[i], old_mods[i]); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1145 | pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | |
| 1146 | SDE_PLANE_DIRTY_RECTS; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1147 | break; |
| 1148 | } |
| 1149 | } |
Lloyd Atkinson | 3ab9ef7 | 2016-07-14 17:42:41 -0400 | [diff] [blame] | 1150 | for (i = 0; i < ARRAY_SIZE(state->fb->pitches); i++) { |
| 1151 | if (new_pitches[i] != old_pitches[i]) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1152 | SDE_DEBUG_PLANE(psde, |
| 1153 | "pitches change plane:%d\"\ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1154 | old_pitches:%u new_pitches:%u\n", |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1155 | i, old_pitches[i], new_pitches[i]); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1156 | pstate->dirty |= SDE_PLANE_DIRTY_RECTS; |
Lloyd Atkinson | 3ab9ef7 | 2016-07-14 17:42:41 -0400 | [diff] [blame] | 1157 | break; |
| 1158 | } |
| 1159 | } |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1160 | for (i = 0; i < ARRAY_SIZE(state->fb->offsets); i++) { |
| 1161 | if (new_offset[i] != old_offset[i]) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1162 | SDE_DEBUG_PLANE(psde, |
| 1163 | "offset change plane:%d\"\ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1164 | old_offset:%u new_offset:%u\n", |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1165 | i, old_offset[i], new_offset[i]); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1166 | pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | |
| 1167 | SDE_PLANE_DIRTY_RECTS; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1168 | break; |
| 1169 | } |
| 1170 | } |
Lloyd Atkinson | 3ab9ef7 | 2016-07-14 17:42:41 -0400 | [diff] [blame] | 1171 | } |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1172 | } |
| 1173 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1174 | static int sde_plane_atomic_check(struct drm_plane *plane, |
| 1175 | struct drm_plane_state *state) |
| 1176 | { |
Clarence Ip | dedbba9 | 2016-09-27 17:43:10 -0400 | [diff] [blame] | 1177 | int ret = 0; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1178 | struct sde_plane *psde; |
| 1179 | struct sde_plane_state *pstate; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 1180 | const struct sde_format *fmt; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1181 | struct sde_rect src, dst; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1182 | uint32_t deci_w, deci_h, src_deci_w, src_deci_h; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1183 | uint32_t max_upscale, max_downscale, min_src_size, max_linewidth; |
| 1184 | bool q16_data = true; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1185 | |
| 1186 | if (!plane || !state) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1187 | SDE_ERROR("invalid arg(s), plane %d state %d\n", |
| 1188 | plane != 0, state != 0); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1189 | ret = -EINVAL; |
| 1190 | goto exit; |
| 1191 | } |
| 1192 | |
| 1193 | psde = to_sde_plane(plane); |
| 1194 | pstate = to_sde_plane_state(state); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1195 | |
| 1196 | if (!psde->pipe_sblk) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1197 | SDE_ERROR_PLANE(psde, "invalid catalog\n"); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1198 | ret = -EINVAL; |
| 1199 | goto exit; |
| 1200 | } |
| 1201 | |
Clarence Ip | dedbba9 | 2016-09-27 17:43:10 -0400 | [diff] [blame] | 1202 | deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE); |
| 1203 | deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1204 | |
| 1205 | /* src values are in Q16 fixed point, convert to integer */ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1206 | POPULATE_RECT(&src, state->src_x, state->src_y, state->src_w, |
| 1207 | state->src_h, q16_data); |
| 1208 | POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w, |
| 1209 | state->crtc_h, !q16_data); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1210 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1211 | src_deci_w = DECIMATED_DIMENSION(src.w, deci_w); |
| 1212 | src_deci_h = DECIMATED_DIMENSION(src.h, deci_h); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1213 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1214 | max_upscale = psde->pipe_sblk->maxupscale; |
| 1215 | max_downscale = psde->pipe_sblk->maxdwnscale; |
| 1216 | max_linewidth = psde->pipe_sblk->maxlinewidth; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1217 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1218 | SDE_DEBUG_PLANE(psde, "check %d -> %d\n", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1219 | sde_plane_enabled(plane->state), sde_plane_enabled(state)); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1220 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1221 | if (!sde_plane_enabled(state)) |
| 1222 | goto modeset_update; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1223 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1224 | fmt = to_sde_format(msm_framebuffer_format(state->fb)); |
| 1225 | |
| 1226 | min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1; |
| 1227 | |
| 1228 | if (SDE_FORMAT_IS_YUV(fmt) && |
| 1229 | (!(psde->features & SDE_SSPP_SCALER) || |
| 1230 | !(psde->features & BIT(SDE_SSPP_CSC)))) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1231 | SDE_ERROR_PLANE(psde, |
| 1232 | "plane doesn't have scaler/csc for yuv\n"); |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1233 | ret = -EINVAL; |
| 1234 | |
| 1235 | /* check src bounds */ |
| 1236 | } else if (state->fb->width > MAX_IMG_WIDTH || |
| 1237 | state->fb->height > MAX_IMG_HEIGHT || |
| 1238 | src.w < min_src_size || src.h < min_src_size || |
| 1239 | CHECK_LAYER_BOUNDS(src.x, src.w, state->fb->width) || |
| 1240 | CHECK_LAYER_BOUNDS(src.y, src.h, state->fb->height)) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1241 | SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1242 | src.x, src.y, src.w, src.h); |
| 1243 | ret = -E2BIG; |
| 1244 | |
| 1245 | /* valid yuv image */ |
| 1246 | } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) || |
| 1247 | (src.w & 0x1) || (src.h & 0x1))) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1248 | SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1249 | src.x, src.y, src.w, src.h); |
| 1250 | ret = -EINVAL; |
| 1251 | |
| 1252 | /* min dst support */ |
| 1253 | } else if (dst.w < 0x1 || dst.h < 0x1) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1254 | SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1255 | dst.x, dst.y, dst.w, dst.h); |
| 1256 | ret = -EINVAL; |
| 1257 | |
| 1258 | /* decimation validation */ |
| 1259 | } else if (deci_w || deci_h) { |
| 1260 | if ((deci_w > psde->pipe_sblk->maxhdeciexp) || |
| 1261 | (deci_h > psde->pipe_sblk->maxvdeciexp)) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1262 | SDE_ERROR_PLANE(psde, |
| 1263 | "too much decimation requested\n"); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1264 | ret = -EINVAL; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1265 | } else if (fmt->fetch_mode != SDE_FETCH_LINEAR) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1266 | SDE_ERROR_PLANE(psde, |
| 1267 | "decimation requires linear fetch\n"); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1268 | ret = -EINVAL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1269 | } |
| 1270 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1271 | } else if (!(psde->features & SDE_SSPP_SCALER) && |
| 1272 | ((src.w != dst.w) || (src.h != dst.h))) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1273 | SDE_ERROR_PLANE(psde, |
| 1274 | "pipe doesn't support scaling %ux%u->%ux%u\n", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1275 | src.w, src.h, dst.w, dst.h); |
| 1276 | ret = -EINVAL; |
| 1277 | |
| 1278 | /* check decimated source width */ |
| 1279 | } else if (src_deci_w > max_linewidth) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1280 | SDE_ERROR_PLANE(psde, |
| 1281 | "invalid src w:%u, deci w:%u, line w:%u\n", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1282 | src.w, src_deci_w, max_linewidth); |
| 1283 | ret = -E2BIG; |
| 1284 | |
| 1285 | /* check max scaler capability */ |
| 1286 | } else if (((src_deci_w * max_upscale) < dst.w) || |
| 1287 | ((src_deci_h * max_upscale) < dst.h) || |
| 1288 | ((dst.w * max_downscale) < src_deci_w) || |
| 1289 | ((dst.h * max_downscale) < src_deci_h)) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1290 | SDE_ERROR_PLANE(psde, |
| 1291 | "too much scaling requested %ux%u->%ux%u\n", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1292 | src_deci_w, src_deci_h, dst.w, dst.h); |
| 1293 | ret = -E2BIG; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1294 | } |
| 1295 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1296 | modeset_update: |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1297 | if (!ret) |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1298 | _sde_plane_atomic_check_mode_changed(psde, state, plane->state); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1299 | exit: |
| 1300 | return ret; |
| 1301 | } |
| 1302 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1303 | /** |
| 1304 | * sde_plane_flush - final plane operations before commit flush |
| 1305 | * @plane: Pointer to drm plane structure |
| 1306 | */ |
| 1307 | void sde_plane_flush(struct drm_plane *plane) |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1308 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1309 | struct sde_plane *psde; |
| 1310 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1311 | if (!plane) { |
| 1312 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1313 | return; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1314 | } |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1315 | |
| 1316 | psde = to_sde_plane(plane); |
| 1317 | |
| 1318 | /* |
| 1319 | * These updates have to be done immediately before the plane flush |
| 1320 | * timing, and may not be moved to the atomic_update/mode_set functions. |
| 1321 | */ |
| 1322 | if (psde->is_error) |
| 1323 | /* force white frame with 0% alpha pipe output on error */ |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1324 | _sde_plane_color_fill(psde, 0xFFFFFF, 0x0); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1325 | else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) |
| 1326 | /* force 100% alpha */ |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1327 | _sde_plane_color_fill(psde, psde->color_fill, 0xFF); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1328 | else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc) |
| 1329 | psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr); |
| 1330 | |
| 1331 | /* flag h/w flush complete */ |
| 1332 | if (plane->state) |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1333 | to_sde_plane_state(plane->state)->pending = false; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1334 | } |
| 1335 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1336 | static void sde_plane_atomic_update(struct drm_plane *plane, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1337 | struct drm_plane_state *old_state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1338 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1339 | struct sde_plane *psde; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1340 | struct drm_plane_state *state; |
| 1341 | struct sde_plane_state *pstate; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1342 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1343 | if (!plane) { |
| 1344 | SDE_ERROR("invalid plane\n"); |
| 1345 | return; |
| 1346 | } else if (!plane->state) { |
| 1347 | SDE_ERROR("invalid plane state\n"); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1348 | return; |
| 1349 | } |
| 1350 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1351 | psde = to_sde_plane(plane); |
| 1352 | psde->is_error = false; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1353 | state = plane->state; |
| 1354 | pstate = to_sde_plane_state(state); |
| 1355 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1356 | SDE_DEBUG_PLANE(psde, "\n"); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1357 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1358 | if (!sde_plane_enabled(state)) { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1359 | pstate->pending = true; |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1360 | } else { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1361 | int ret; |
| 1362 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1363 | ret = _sde_plane_mode_set(plane, state); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1364 | /* atomic_check should have ensured that this doesn't fail */ |
| 1365 | WARN_ON(ret < 0); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1366 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1367 | } |
| 1368 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1369 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1370 | /* helper to install properties which are common to planes and crtcs */ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1371 | static void _sde_plane_install_properties(struct drm_plane *plane, |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 1372 | struct sde_mdss_cfg *catalog) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1373 | { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1374 | static const struct drm_prop_enum_list e_blend_op[] = { |
| 1375 | {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"}, |
| 1376 | {SDE_DRM_BLEND_OP_OPAQUE, "opaque"}, |
| 1377 | {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"}, |
| 1378 | {SDE_DRM_BLEND_OP_COVERAGE, "coverage"} |
| 1379 | }; |
| 1380 | static const struct drm_prop_enum_list e_src_config[] = { |
| 1381 | {SDE_DRM_DEINTERLACE, "deinterlace"} |
| 1382 | }; |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1383 | const struct sde_format_extended *format_list; |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1384 | struct sde_kms_info *info; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1385 | struct sde_plane *psde = to_sde_plane(plane); |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 1386 | int zpos_max = 255; |
| 1387 | int zpos_def = 0; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1388 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1389 | if (!plane || !psde) { |
| 1390 | SDE_ERROR("invalid plane\n"); |
| 1391 | return; |
| 1392 | } else if (!psde->pipe_hw || !psde->pipe_sblk) { |
| 1393 | SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n", |
| 1394 | psde->pipe_hw != 0, psde->pipe_sblk != 0); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1395 | return; |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 1396 | } else if (!catalog) { |
| 1397 | SDE_ERROR("invalid catalog\n"); |
| 1398 | return; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1399 | } |
| 1400 | |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 1401 | if (sde_is_custom_client()) { |
| 1402 | if (catalog->mixer_count && catalog->mixer) |
| 1403 | zpos_max = catalog->mixer[0].sblk->maxblendstages; |
| 1404 | } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) { |
| 1405 | /* reserve zpos == 0 for primary planes */ |
| 1406 | zpos_def = drm_plane_index(plane) + 1; |
| 1407 | } |
| 1408 | |
| 1409 | msm_property_install_range(&psde->property_info, "zpos", |
| 1410 | 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1411 | |
Lloyd Atkinson | 38ad8c9 | 2016-07-06 10:39:32 -0400 | [diff] [blame] | 1412 | msm_property_install_range(&psde->property_info, "alpha", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1413 | 0x0, 0, 255, 255, PLANE_PROP_ALPHA); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1414 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1415 | /* linux default file descriptor range on each process */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1416 | msm_property_install_range(&psde->property_info, "input_fence", |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1417 | 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1418 | |
Clarence Ip | dedbba9 | 2016-09-27 17:43:10 -0400 | [diff] [blame] | 1419 | if (psde->pipe_sblk->maxhdeciexp) { |
| 1420 | msm_property_install_range(&psde->property_info, "h_decimate", |
| 1421 | 0x0, 0, psde->pipe_sblk->maxhdeciexp, 0, |
| 1422 | PLANE_PROP_H_DECIMATE); |
| 1423 | } |
| 1424 | |
| 1425 | if (psde->pipe_sblk->maxvdeciexp) { |
| 1426 | msm_property_install_range(&psde->property_info, "v_decimate", |
| 1427 | 0x0, 0, psde->pipe_sblk->maxvdeciexp, 0, |
| 1428 | PLANE_PROP_V_DECIMATE); |
| 1429 | } |
| 1430 | |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1431 | if (psde->features & SDE_SSPP_SCALER) { |
| 1432 | msm_property_install_volatile_range(&psde->property_info, |
| 1433 | "scaler_v1", 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V1); |
| 1434 | } |
| 1435 | |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1436 | if (psde->features & BIT(SDE_SSPP_CSC)) { |
| 1437 | msm_property_install_volatile_range(&psde->property_info, |
| 1438 | "csc_v1", 0x0, 0, ~0, 0, PLANE_PROP_CSC_V1); |
| 1439 | } |
| 1440 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1441 | /* standard properties */ |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1442 | msm_property_install_rotation(&psde->property_info, |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1443 | BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y), PLANE_PROP_ROTATION); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1444 | |
Lloyd Atkinson | 38ad8c9 | 2016-07-06 10:39:32 -0400 | [diff] [blame] | 1445 | msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0, |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1446 | e_blend_op, ARRAY_SIZE(e_blend_op), PLANE_PROP_BLEND_OP); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1447 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1448 | msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1, |
| 1449 | e_src_config, ARRAY_SIZE(e_src_config), PLANE_PROP_SRC_CONFIG); |
| 1450 | |
| 1451 | if (psde->pipe_hw->ops.setup_solidfill) |
| 1452 | msm_property_install_range(&psde->property_info, "color_fill", |
| 1453 | 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL); |
| 1454 | |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1455 | info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL); |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1456 | if (!info) { |
| 1457 | SDE_ERROR("failed to allocate info memory\n"); |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1458 | return; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1459 | } |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1460 | |
| 1461 | msm_property_install_blob(&psde->property_info, "capabilities", |
| 1462 | DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO); |
| 1463 | sde_kms_info_reset(info); |
| 1464 | |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1465 | format_list = psde->pipe_sblk->format_list; |
| 1466 | if (format_list) { |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1467 | sde_kms_info_start(info, "pixel_formats"); |
| 1468 | while (format_list->fourcc_format) { |
| 1469 | sde_kms_info_append_format(info, |
| 1470 | format_list->fourcc_format, |
| 1471 | format_list->modifier); |
| 1472 | ++format_list; |
| 1473 | } |
| 1474 | sde_kms_info_stop(info); |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1475 | } |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1476 | |
| 1477 | sde_kms_info_add_keyint(info, "max_linewidth", |
| 1478 | psde->pipe_sblk->maxlinewidth); |
| 1479 | sde_kms_info_add_keyint(info, "max_upscale", |
| 1480 | psde->pipe_sblk->maxupscale); |
| 1481 | sde_kms_info_add_keyint(info, "max_downscale", |
| 1482 | psde->pipe_sblk->maxdwnscale); |
| 1483 | sde_kms_info_add_keyint(info, "max_horizontal_deci", |
| 1484 | psde->pipe_sblk->maxhdeciexp); |
| 1485 | sde_kms_info_add_keyint(info, "max_vertical_deci", |
| 1486 | psde->pipe_sblk->maxvdeciexp); |
| 1487 | msm_property_set_blob(&psde->property_info, &psde->blob_info, |
| 1488 | info->data, info->len, PLANE_PROP_INFO); |
| 1489 | |
| 1490 | kfree(info); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1491 | } |
| 1492 | |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1493 | static inline void _sde_plane_set_csc_v1(struct sde_plane *psde, void *usr_ptr) |
| 1494 | { |
| 1495 | struct sde_drm_csc_v1 csc_v1; |
| 1496 | int i; |
| 1497 | |
| 1498 | if (!psde) { |
| 1499 | SDE_ERROR("invalid plane\n"); |
| 1500 | return; |
| 1501 | } |
| 1502 | |
| 1503 | psde->csc_usr_ptr = NULL; |
| 1504 | if (!usr_ptr) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1505 | SDE_DEBUG_PLANE(psde, "csc data removed\n"); |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1506 | return; |
| 1507 | } |
| 1508 | |
| 1509 | if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1510 | SDE_ERROR_PLANE(psde, "failed to copy csc data\n"); |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1511 | return; |
| 1512 | } |
| 1513 | |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1514 | /* populate from user space */ |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1515 | for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i) |
| 1516 | psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16; |
| 1517 | for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) { |
| 1518 | psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i]; |
| 1519 | psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i]; |
| 1520 | } |
| 1521 | for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) { |
| 1522 | psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i]; |
| 1523 | psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i]; |
| 1524 | } |
| 1525 | psde->csc_usr_ptr = &psde->csc_cfg; |
| 1526 | } |
| 1527 | |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1528 | static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde, void *usr) |
| 1529 | { |
| 1530 | struct sde_drm_scaler_v1 scale_v1; |
| 1531 | struct sde_hw_pixel_ext *pe; |
| 1532 | int i; |
| 1533 | |
| 1534 | if (!psde) { |
| 1535 | SDE_ERROR("invalid plane\n"); |
| 1536 | return; |
| 1537 | } |
| 1538 | |
| 1539 | psde->pixel_ext_usr = false; |
| 1540 | if (!usr) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1541 | SDE_DEBUG_PLANE(psde, "scale data removed\n"); |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1542 | return; |
| 1543 | } |
| 1544 | |
| 1545 | if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1546 | SDE_ERROR_PLANE(psde, "failed to copy scale data\n"); |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1547 | return; |
| 1548 | } |
| 1549 | |
| 1550 | /* populate from user space */ |
| 1551 | pe = &(psde->pixel_ext); |
| 1552 | memset(pe, 0, sizeof(struct sde_hw_pixel_ext)); |
| 1553 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 1554 | pe->init_phase_x[i] = scale_v1.init_phase_x[i]; |
| 1555 | pe->phase_step_x[i] = scale_v1.phase_step_x[i]; |
| 1556 | pe->init_phase_y[i] = scale_v1.init_phase_y[i]; |
| 1557 | pe->phase_step_y[i] = scale_v1.phase_step_y[i]; |
| 1558 | |
| 1559 | pe->horz_filter[i] = scale_v1.horz_filter[i]; |
| 1560 | pe->vert_filter[i] = scale_v1.vert_filter[i]; |
| 1561 | } |
| 1562 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 1563 | pe->num_ext_pxls_left[i] = scale_v1.lr.num_pxls_start[i]; |
| 1564 | pe->num_ext_pxls_right[i] = scale_v1.lr.num_pxls_end[i]; |
| 1565 | pe->left_ftch[i] = scale_v1.lr.ftch_start[i]; |
| 1566 | pe->right_ftch[i] = scale_v1.lr.ftch_end[i]; |
| 1567 | pe->left_rpt[i] = scale_v1.lr.rpt_start[i]; |
| 1568 | pe->right_rpt[i] = scale_v1.lr.rpt_end[i]; |
| 1569 | pe->roi_w[i] = scale_v1.lr.roi[i]; |
| 1570 | |
| 1571 | pe->num_ext_pxls_top[i] = scale_v1.tb.num_pxls_start[i]; |
| 1572 | pe->num_ext_pxls_btm[i] = scale_v1.tb.num_pxls_end[i]; |
| 1573 | pe->top_ftch[i] = scale_v1.tb.ftch_start[i]; |
| 1574 | pe->btm_ftch[i] = scale_v1.tb.ftch_end[i]; |
| 1575 | pe->top_rpt[i] = scale_v1.tb.rpt_start[i]; |
| 1576 | pe->btm_rpt[i] = scale_v1.tb.rpt_end[i]; |
| 1577 | pe->roi_h[i] = scale_v1.tb.roi[i]; |
| 1578 | } |
| 1579 | psde->pixel_ext_usr = true; |
| 1580 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1581 | SDE_DEBUG_PLANE(psde, "user property data copied\n"); |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1582 | } |
| 1583 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1584 | static int sde_plane_atomic_set_property(struct drm_plane *plane, |
| 1585 | struct drm_plane_state *state, struct drm_property *property, |
| 1586 | uint64_t val) |
| 1587 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1588 | struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1589 | struct sde_plane_state *pstate; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1590 | int idx, ret = -EINVAL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1591 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1592 | SDE_DEBUG_PLANE(psde, "\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1593 | |
| 1594 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1595 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1596 | } else if (!state) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1597 | SDE_ERROR_PLANE(psde, "invalid state\n"); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1598 | } else { |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1599 | pstate = to_sde_plane_state(state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1600 | ret = msm_property_atomic_set(&psde->property_info, |
| 1601 | pstate->property_values, pstate->property_blobs, |
| 1602 | property, val); |
| 1603 | if (!ret) { |
| 1604 | idx = msm_property_index(&psde->property_info, |
| 1605 | property); |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1606 | switch (idx) { |
| 1607 | case PLANE_PROP_INPUT_FENCE: |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1608 | _sde_plane_set_input_fence(psde, pstate, val); |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1609 | break; |
| 1610 | case PLANE_PROP_CSC_V1: |
| 1611 | _sde_plane_set_csc_v1(psde, (void *)val); |
| 1612 | break; |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 1613 | case PLANE_PROP_SCALER_V1: |
| 1614 | _sde_plane_set_scaler_v1(psde, (void *)val); |
| 1615 | break; |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 1616 | default: |
| 1617 | /* nothing to do */ |
| 1618 | break; |
| 1619 | } |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1620 | } |
| 1621 | } |
| 1622 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1623 | return ret; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1624 | } |
| 1625 | |
| 1626 | static int sde_plane_set_property(struct drm_plane *plane, |
| 1627 | struct drm_property *property, uint64_t val) |
| 1628 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1629 | SDE_DEBUG("\n"); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1630 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1631 | return sde_plane_atomic_set_property(plane, |
| 1632 | plane->state, property, val); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1633 | } |
| 1634 | |
| 1635 | static int sde_plane_atomic_get_property(struct drm_plane *plane, |
| 1636 | const struct drm_plane_state *state, |
| 1637 | struct drm_property *property, uint64_t *val) |
| 1638 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1639 | struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1640 | struct sde_plane_state *pstate; |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1641 | int ret = -EINVAL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1642 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1643 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1644 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1645 | } else if (!state) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1646 | SDE_ERROR("invalid state\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1647 | } else { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1648 | SDE_DEBUG_PLANE(psde, "\n"); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1649 | pstate = to_sde_plane_state(state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1650 | ret = msm_property_atomic_get(&psde->property_info, |
| 1651 | pstate->property_values, pstate->property_blobs, |
| 1652 | property, val); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1653 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1654 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1655 | return ret; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1656 | } |
| 1657 | |
| 1658 | static void sde_plane_destroy(struct drm_plane *plane) |
| 1659 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1660 | struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1661 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1662 | SDE_DEBUG_PLANE(psde, "\n"); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1663 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1664 | if (psde) { |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 1665 | _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL); |
| 1666 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1667 | debugfs_remove_recursive(psde->debugfs_root); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1668 | |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1669 | if (psde->blob_info) |
| 1670 | drm_property_unreference_blob(psde->blob_info); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1671 | msm_property_destroy(&psde->property_info); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1672 | mutex_destroy(&psde->lock); |
| 1673 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1674 | drm_plane_helper_disable(plane); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1675 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1676 | /* this will destroy the states as well */ |
| 1677 | drm_plane_cleanup(plane); |
| 1678 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1679 | if (psde->pipe_hw) |
| 1680 | sde_hw_sspp_destroy(psde->pipe_hw); |
| 1681 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1682 | kfree(psde); |
| 1683 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1684 | } |
| 1685 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1686 | static void sde_plane_destroy_state(struct drm_plane *plane, |
| 1687 | struct drm_plane_state *state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1688 | { |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1689 | struct sde_plane *psde; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1690 | struct sde_plane_state *pstate; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1691 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1692 | if (!plane || !state) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1693 | SDE_ERROR("invalid arg(s), plane %d state %d\n", |
| 1694 | plane != 0, state != 0); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1695 | return; |
| 1696 | } |
| 1697 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1698 | psde = to_sde_plane(plane); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1699 | pstate = to_sde_plane_state(state); |
| 1700 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1701 | SDE_DEBUG_PLANE(psde, "\n"); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1702 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1703 | /* remove ref count for frame buffers */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1704 | if (state->fb) |
| 1705 | drm_framebuffer_unreference(state->fb); |
| 1706 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1707 | /* remove ref count for fence */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1708 | if (pstate->input_fence) |
| 1709 | sde_sync_put(pstate->input_fence); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1710 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1711 | /* destroy value helper */ |
| 1712 | msm_property_destroy_state(&psde->property_info, pstate, |
| 1713 | pstate->property_values, pstate->property_blobs); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1714 | } |
| 1715 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1716 | static struct drm_plane_state * |
| 1717 | sde_plane_duplicate_state(struct drm_plane *plane) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1718 | { |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1719 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1720 | struct sde_plane_state *pstate; |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1721 | struct sde_plane_state *old_state; |
Clarence Ip | 17e908b | 2016-09-29 15:58:00 -0400 | [diff] [blame] | 1722 | uint64_t input_fence_default; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1723 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1724 | if (!plane) { |
| 1725 | SDE_ERROR("invalid plane\n"); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1726 | return NULL; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1727 | } else if (!plane->state) { |
| 1728 | SDE_ERROR("invalid plane state\n"); |
| 1729 | return NULL; |
| 1730 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1731 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1732 | old_state = to_sde_plane_state(plane->state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1733 | psde = to_sde_plane(plane); |
| 1734 | pstate = msm_property_alloc_state(&psde->property_info); |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1735 | if (!pstate) { |
| 1736 | SDE_ERROR_PLANE(psde, "failed to allocate state\n"); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1737 | return NULL; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1738 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1739 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1740 | SDE_DEBUG_PLANE(psde, "\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1741 | |
| 1742 | /* duplicate value helper */ |
| 1743 | msm_property_duplicate_state(&psde->property_info, old_state, pstate, |
| 1744 | pstate->property_values, pstate->property_blobs); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1745 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1746 | /* add ref count for frame buffer */ |
| 1747 | if (pstate->base.fb) |
| 1748 | drm_framebuffer_reference(pstate->base.fb); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1749 | |
Clarence Ip | 17e908b | 2016-09-29 15:58:00 -0400 | [diff] [blame] | 1750 | /* clear out any input fence */ |
| 1751 | pstate->input_fence = 0; |
| 1752 | input_fence_default = msm_property_get_default( |
| 1753 | &psde->property_info, PLANE_PROP_INPUT_FENCE); |
| 1754 | msm_property_set_property(&psde->property_info, pstate->property_values, |
| 1755 | PLANE_PROP_INPUT_FENCE, input_fence_default); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1756 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1757 | pstate->dirty = 0x0; |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1758 | pstate->pending = false; |
| 1759 | |
| 1760 | return &pstate->base; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1761 | } |
| 1762 | |
| 1763 | static void sde_plane_reset(struct drm_plane *plane) |
| 1764 | { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1765 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1766 | struct sde_plane_state *pstate; |
| 1767 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1768 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1769 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1770 | return; |
| 1771 | } |
| 1772 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1773 | psde = to_sde_plane(plane); |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1774 | SDE_DEBUG_PLANE(psde, "\n"); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1775 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1776 | /* remove previous state, if present */ |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1777 | if (plane->state) { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1778 | sde_plane_destroy_state(plane, plane->state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1779 | plane->state = 0; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1780 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1781 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1782 | pstate = msm_property_alloc_state(&psde->property_info); |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1783 | if (!pstate) { |
| 1784 | SDE_ERROR_PLANE(psde, "failed to allocate state\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1785 | return; |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1786 | } |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1787 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1788 | /* reset value helper */ |
| 1789 | msm_property_reset_state(&psde->property_info, pstate, |
| 1790 | pstate->property_values, pstate->property_blobs); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1791 | |
| 1792 | pstate->base.plane = plane; |
| 1793 | |
| 1794 | plane->state = &pstate->base; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1795 | } |
| 1796 | |
| 1797 | static const struct drm_plane_funcs sde_plane_funcs = { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1798 | .update_plane = drm_atomic_helper_update_plane, |
| 1799 | .disable_plane = drm_atomic_helper_disable_plane, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1800 | .destroy = sde_plane_destroy, |
| 1801 | .set_property = sde_plane_set_property, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1802 | .atomic_set_property = sde_plane_atomic_set_property, |
| 1803 | .atomic_get_property = sde_plane_atomic_get_property, |
| 1804 | .reset = sde_plane_reset, |
| 1805 | .atomic_duplicate_state = sde_plane_duplicate_state, |
| 1806 | .atomic_destroy_state = sde_plane_destroy_state, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1807 | }; |
| 1808 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1809 | static const struct drm_plane_helper_funcs sde_plane_helper_funcs = { |
| 1810 | .prepare_fb = sde_plane_prepare_fb, |
| 1811 | .cleanup_fb = sde_plane_cleanup_fb, |
| 1812 | .atomic_check = sde_plane_atomic_check, |
| 1813 | .atomic_update = sde_plane_atomic_update, |
| 1814 | }; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1815 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1816 | enum sde_sspp sde_plane_pipe(struct drm_plane *plane) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1817 | { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1818 | return plane ? to_sde_plane(plane)->pipe : SSPP_NONE; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1819 | } |
| 1820 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1821 | static void _sde_plane_init_debugfs(struct sde_plane *psde, struct sde_kms *kms) |
| 1822 | { |
| 1823 | const struct sde_sspp_sub_blks *sblk = 0; |
| 1824 | const struct sde_sspp_cfg *cfg = 0; |
| 1825 | |
| 1826 | if (psde && psde->pipe_hw) |
| 1827 | cfg = psde->pipe_hw->cap; |
| 1828 | if (cfg) |
| 1829 | sblk = cfg->sblk; |
| 1830 | |
| 1831 | if (kms && sblk) { |
| 1832 | /* create overall sub-directory for the pipe */ |
| 1833 | psde->debugfs_root = |
| 1834 | debugfs_create_dir(psde->pipe_name, |
| 1835 | sde_debugfs_get_root(kms)); |
| 1836 | if (psde->debugfs_root) { |
| 1837 | /* don't error check these */ |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1838 | debugfs_create_x32("features", 0644, |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1839 | psde->debugfs_root, &psde->features); |
| 1840 | |
| 1841 | /* add register dump support */ |
| 1842 | sde_debugfs_setup_regset32(&psde->debugfs_src, |
| 1843 | sblk->src_blk.base + cfg->base, |
| 1844 | sblk->src_blk.len, |
Clarence Ip | aac9f33 | 2016-08-31 15:46:35 -0400 | [diff] [blame] | 1845 | kms); |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1846 | sde_debugfs_create_regset32("src_blk", 0444, |
| 1847 | psde->debugfs_root, &psde->debugfs_src); |
| 1848 | |
| 1849 | sde_debugfs_setup_regset32(&psde->debugfs_scaler, |
| 1850 | sblk->scaler_blk.base + cfg->base, |
| 1851 | sblk->scaler_blk.len, |
Clarence Ip | aac9f33 | 2016-08-31 15:46:35 -0400 | [diff] [blame] | 1852 | kms); |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1853 | sde_debugfs_create_regset32("scaler_blk", 0444, |
| 1854 | psde->debugfs_root, |
| 1855 | &psde->debugfs_scaler); |
| 1856 | |
| 1857 | sde_debugfs_setup_regset32(&psde->debugfs_csc, |
| 1858 | sblk->csc_blk.base + cfg->base, |
| 1859 | sblk->csc_blk.len, |
Clarence Ip | aac9f33 | 2016-08-31 15:46:35 -0400 | [diff] [blame] | 1860 | kms); |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1861 | sde_debugfs_create_regset32("csc_blk", 0444, |
| 1862 | psde->debugfs_root, &psde->debugfs_csc); |
| 1863 | } |
| 1864 | } |
| 1865 | } |
| 1866 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1867 | /* initialize plane */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1868 | struct drm_plane *sde_plane_init(struct drm_device *dev, |
Clarence Ip | 2bbf7b3 | 2016-09-23 15:07:16 -0400 | [diff] [blame] | 1869 | uint32_t pipe, bool primary_plane, |
| 1870 | unsigned long possible_crtcs) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1871 | { |
| 1872 | struct drm_plane *plane = NULL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1873 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1874 | struct msm_drm_private *priv; |
| 1875 | struct sde_kms *kms; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1876 | enum drm_plane_type type; |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 1877 | int ret = -EINVAL; |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1878 | |
| 1879 | if (!dev) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1880 | SDE_ERROR("[%u]device is NULL\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1881 | goto exit; |
| 1882 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1883 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1884 | priv = dev->dev_private; |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 1885 | if (!priv) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1886 | SDE_ERROR("[%u]private data is NULL\n", pipe); |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 1887 | goto exit; |
| 1888 | } |
| 1889 | |
| 1890 | if (!priv->kms) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1891 | SDE_ERROR("[%u]invalid KMS reference\n", pipe); |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 1892 | goto exit; |
| 1893 | } |
| 1894 | kms = to_sde_kms(priv->kms); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1895 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1896 | if (!kms->catalog) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1897 | SDE_ERROR("[%u]invalid catalog reference\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1898 | goto exit; |
| 1899 | } |
| 1900 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1901 | /* create and zero local structure */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1902 | psde = kzalloc(sizeof(*psde), GFP_KERNEL); |
| 1903 | if (!psde) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1904 | SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1905 | ret = -ENOMEM; |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1906 | goto exit; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1907 | } |
| 1908 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1909 | /* cache local stuff for later */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1910 | plane = &psde->base; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1911 | psde->pipe = pipe; |
Alan Kwong | 112a84f | 2016-05-24 20:49:21 -0400 | [diff] [blame] | 1912 | psde->mmu_id = kms->mmu_id[MSM_SMMU_DOMAIN_UNSECURE]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1913 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1914 | /* initialize underlying h/w driver */ |
| 1915 | psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog); |
| 1916 | if (IS_ERR(psde->pipe_hw)) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1917 | SDE_ERROR("[%u]SSPP init failed\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1918 | ret = PTR_ERR(psde->pipe_hw); |
| 1919 | goto clean_plane; |
| 1920 | } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1921 | SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1922 | goto clean_sspp; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1923 | } |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1924 | |
| 1925 | /* cache features mask for later */ |
| 1926 | psde->features = psde->pipe_hw->cap->features; |
| 1927 | psde->pipe_sblk = psde->pipe_hw->cap->sblk; |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1928 | if (!psde->pipe_sblk) { |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1929 | SDE_ERROR("[%u]invalid sblk\n", pipe); |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1930 | goto clean_sspp; |
| 1931 | } |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1932 | |
| 1933 | /* add plane to DRM framework */ |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1934 | psde->nformats = sde_populate_formats(psde->pipe_sblk->format_list, |
| 1935 | psde->formats, |
| 1936 | 0, |
| 1937 | ARRAY_SIZE(psde->formats)); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1938 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1939 | if (!psde->nformats) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1940 | SDE_ERROR("[%u]no valid formats for plane\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1941 | goto clean_sspp; |
| 1942 | } |
| 1943 | |
| 1944 | if (psde->features & BIT(SDE_SSPP_CURSOR)) |
| 1945 | type = DRM_PLANE_TYPE_CURSOR; |
| 1946 | else if (primary_plane) |
| 1947 | type = DRM_PLANE_TYPE_PRIMARY; |
| 1948 | else |
| 1949 | type = DRM_PLANE_TYPE_OVERLAY; |
Clarence Ip | 2bbf7b3 | 2016-09-23 15:07:16 -0400 | [diff] [blame] | 1950 | ret = drm_universal_plane_init(dev, plane, possible_crtcs, |
| 1951 | &sde_plane_funcs, psde->formats, psde->nformats, type); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1952 | if (ret) |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1953 | goto clean_sspp; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1954 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1955 | /* success! finalize initialization */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1956 | drm_plane_helper_add(plane, &sde_plane_helper_funcs); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1957 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1958 | msm_property_init(&psde->property_info, &plane->base, dev, |
| 1959 | priv->plane_property, psde->property_data, |
| 1960 | PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT, |
| 1961 | sizeof(struct sde_plane_state)); |
| 1962 | |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 1963 | _sde_plane_install_properties(plane, kms->catalog); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1964 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1965 | /* save user friendly pipe name for later */ |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1966 | snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id); |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1967 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1968 | mutex_init(&psde->lock); |
| 1969 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1970 | _sde_plane_init_debugfs(psde, kms); |
| 1971 | |
Clarence Ip | 13a8cf4 | 2016-09-29 17:27:47 -0400 | [diff] [blame] | 1972 | DRM_INFO("%s created for pipe %u\n", psde->pipe_name, pipe); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1973 | return plane; |
| 1974 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1975 | clean_sspp: |
| 1976 | if (psde && psde->pipe_hw) |
| 1977 | sde_hw_sspp_destroy(psde->pipe_hw); |
| 1978 | clean_plane: |
| 1979 | kfree(psde); |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 1980 | exit: |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1981 | return ERR_PTR(ret); |
| 1982 | } |