Clarence Ip | aac9f33 | 2016-08-31 15:46:35 -0400 | [diff] [blame^] | 1 | /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 12 | |
| 13 | #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ |
| 14 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 15 | #include <linux/debugfs.h> |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 16 | #include <uapi/drm/sde_drm.h> |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 17 | |
| 18 | #include "msm_prop.h" |
| 19 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 20 | #include "sde_kms.h" |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 21 | #include "sde_fence.h" |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 22 | #include "sde_formats.h" |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 23 | #include "sde_hw_sspp.h" |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 24 | #include "sde_trace.h" |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 25 | #include "sde_crtc.h" |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 26 | |
| 27 | #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) |
| 28 | #define PHASE_STEP_SHIFT 21 |
| 29 | #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) |
| 30 | #define PHASE_RESIDUAL 15 |
| 31 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 32 | #define SHARP_STRENGTH_DEFAULT 32 |
| 33 | #define SHARP_EDGE_THR_DEFAULT 112 |
| 34 | #define SHARP_SMOOTH_THR_DEFAULT 8 |
| 35 | #define SHARP_NOISE_THR_DEFAULT 2 |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 36 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 37 | #define SDE_NAME_SIZE 12 |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 38 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 39 | #define SDE_PLANE_COLOR_FILL_FLAG BIT(31) |
| 40 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 41 | /* dirty bits for update function */ |
| 42 | #define SDE_PLANE_DIRTY_RECTS 0x1 |
| 43 | #define SDE_PLANE_DIRTY_FORMAT 0x2 |
| 44 | #define SDE_PLANE_DIRTY_SHARPEN 0x4 |
| 45 | #define SDE_PLANE_DIRTY_ALL 0xFFFFFFFF |
| 46 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 47 | /** |
| 48 | * enum sde_plane_qos - Different qos configurations for each pipe |
| 49 | * |
| 50 | * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe. |
| 51 | * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe. |
| 52 | * this configuration is mutually exclusive from VBLANK_CTRL. |
| 53 | * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe. |
| 54 | */ |
| 55 | enum sde_plane_qos { |
| 56 | SDE_PLANE_QOS_VBLANK_CTRL = BIT(0), |
| 57 | SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1), |
| 58 | SDE_PLANE_QOS_PANIC_CTRL = BIT(2), |
| 59 | }; |
| 60 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 61 | struct sde_plane { |
| 62 | struct drm_plane base; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 63 | |
| 64 | int mmu_id; |
| 65 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 66 | struct mutex lock; |
| 67 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 68 | enum sde_sspp pipe; |
| 69 | uint32_t features; /* capabilities from catalog */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 70 | uint32_t nformats; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 71 | uint32_t formats[64]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 72 | |
| 73 | struct sde_hw_pipe *pipe_hw; |
| 74 | struct sde_hw_pipe_cfg pipe_cfg; |
| 75 | struct sde_hw_pixel_ext pixel_ext; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 76 | struct sde_hw_sharp_cfg sharp_cfg; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 77 | struct sde_hw_scaler3_cfg scaler3_cfg; |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 78 | struct sde_hw_pipe_qos_cfg pipe_qos_cfg; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 79 | uint32_t color_fill; |
| 80 | bool is_error; |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 81 | bool is_rt_pipe; |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 82 | |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 83 | struct sde_csc_cfg csc_cfg; |
| 84 | struct sde_csc_cfg *csc_ptr; |
| 85 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 86 | const struct sde_sspp_sub_blks *pipe_sblk; |
| 87 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 88 | char pipe_name[SDE_NAME_SIZE]; |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 89 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 90 | struct msm_property_info property_info; |
| 91 | struct msm_property_data property_data[PLANE_PROP_COUNT]; |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 92 | struct drm_property_blob *blob_info; |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 93 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 94 | /* debugfs related stuff */ |
| 95 | struct dentry *debugfs_root; |
| 96 | struct sde_debugfs_regset32 debugfs_src; |
| 97 | struct sde_debugfs_regset32 debugfs_scaler; |
| 98 | struct sde_debugfs_regset32 debugfs_csc; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 99 | }; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 100 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 101 | #define to_sde_plane(x) container_of(x, struct sde_plane, base) |
| 102 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 103 | static bool sde_plane_enabled(struct drm_plane_state *state) |
| 104 | { |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 105 | return state && state->fb && state->crtc; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 106 | } |
| 107 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 108 | /** |
| 109 | * _sde_plane_calc_fill_level - calculate fill level of the given source format |
| 110 | * @plane: Pointer to drm plane |
| 111 | * @fmt: Pointer to source buffer format |
| 112 | * @src_wdith: width of source buffer |
| 113 | * Return: fill level corresponding to the source buffer/format or 0 if error |
| 114 | */ |
| 115 | static inline int _sde_plane_calc_fill_level(struct drm_plane *plane, |
| 116 | const struct sde_format *fmt, u32 src_width) |
| 117 | { |
| 118 | struct sde_plane *psde; |
| 119 | u32 fixed_buff_size; |
| 120 | u32 total_fl; |
| 121 | |
| 122 | if (!plane || !fmt) { |
| 123 | SDE_ERROR("invalid arguments\n"); |
| 124 | return 0; |
| 125 | } |
| 126 | |
| 127 | psde = to_sde_plane(plane); |
| 128 | fixed_buff_size = psde->pipe_sblk->pixel_ram_size; |
| 129 | |
| 130 | if (fmt->fetch_planes == SDE_PLANE_PSEUDO_PLANAR) { |
| 131 | if (fmt->chroma_sample == SDE_CHROMA_420) { |
| 132 | /* NV12 */ |
| 133 | total_fl = (fixed_buff_size / 2) / |
| 134 | ((src_width + 32) * fmt->bpp); |
| 135 | } else { |
| 136 | /* non NV12 */ |
| 137 | total_fl = (fixed_buff_size) / |
| 138 | ((src_width + 32) * fmt->bpp); |
| 139 | } |
| 140 | } else { |
| 141 | total_fl = (fixed_buff_size * 2) / |
| 142 | ((src_width + 32) * fmt->bpp); |
| 143 | } |
| 144 | |
| 145 | SDE_DEBUG("plane%u: pnum:%d fmt:%x w:%u fl:%u\n", |
| 146 | plane->base.id, psde->pipe - SSPP_VIG0, |
| 147 | fmt->base.pixel_format, src_width, total_fl); |
| 148 | |
| 149 | return total_fl; |
| 150 | } |
| 151 | |
| 152 | /** |
| 153 | * _sde_plane_get_qos_lut_linear - get linear LUT mapping |
| 154 | * @total_fl: fill level |
| 155 | * Return: LUT setting corresponding to the fill level |
| 156 | */ |
| 157 | static inline u32 _sde_plane_get_qos_lut_linear(u32 total_fl) |
| 158 | { |
| 159 | u32 qos_lut; |
| 160 | |
| 161 | if (total_fl <= 4) |
| 162 | qos_lut = 0x1B; |
| 163 | else if (total_fl <= 5) |
| 164 | qos_lut = 0x5B; |
| 165 | else if (total_fl <= 6) |
| 166 | qos_lut = 0x15B; |
| 167 | else if (total_fl <= 7) |
| 168 | qos_lut = 0x55B; |
| 169 | else if (total_fl <= 8) |
| 170 | qos_lut = 0x155B; |
| 171 | else if (total_fl <= 9) |
| 172 | qos_lut = 0x555B; |
| 173 | else if (total_fl <= 10) |
| 174 | qos_lut = 0x1555B; |
| 175 | else if (total_fl <= 11) |
| 176 | qos_lut = 0x5555B; |
| 177 | else if (total_fl <= 12) |
| 178 | qos_lut = 0x15555B; |
| 179 | else |
| 180 | qos_lut = 0x55555B; |
| 181 | |
| 182 | return qos_lut; |
| 183 | } |
| 184 | |
| 185 | /** |
| 186 | * _sde_plane_get_qos_lut_macrotile - get macrotile LUT mapping |
| 187 | * @total_fl: fill level |
| 188 | * Return: LUT setting corresponding to the fill level |
| 189 | */ |
| 190 | static inline u32 _sde_plane_get_qos_lut_macrotile(u32 total_fl) |
| 191 | { |
| 192 | u32 qos_lut; |
| 193 | |
| 194 | if (total_fl <= 10) |
| 195 | qos_lut = 0x1AAff; |
| 196 | else if (total_fl <= 11) |
| 197 | qos_lut = 0x5AAFF; |
| 198 | else if (total_fl <= 12) |
| 199 | qos_lut = 0x15AAFF; |
| 200 | else |
| 201 | qos_lut = 0x55AAFF; |
| 202 | |
| 203 | return qos_lut; |
| 204 | } |
| 205 | |
| 206 | /** |
| 207 | * _sde_plane_is_rt_pipe - check if the given plane requires real-time QoS |
| 208 | * @plane: Pointer to drm plane |
| 209 | * @crtc: Pointer to drm crtc associated with the given plane |
| 210 | */ |
| 211 | static bool _sde_plane_is_rt_pipe(struct drm_plane *plane, |
| 212 | struct drm_crtc *crtc) |
| 213 | { |
| 214 | struct sde_plane *psde = to_sde_plane(plane); |
| 215 | struct drm_connector *connector; |
| 216 | bool is_rt = false; |
| 217 | |
| 218 | /* check if this plane has a physical connector interface */ |
| 219 | drm_for_each_connector(connector, plane->dev) |
| 220 | if (connector->state && |
| 221 | (connector->state->crtc == crtc) && |
| 222 | (connector->connector_type |
| 223 | != DRM_MODE_CONNECTOR_VIRTUAL)) { |
| 224 | is_rt = true; |
| 225 | break; |
| 226 | } |
| 227 | |
| 228 | SDE_DEBUG("plane%u: pnum:%d rt:%d\n", |
| 229 | plane->base.id, psde->pipe - SSPP_VIG0, is_rt); |
| 230 | |
| 231 | return is_rt; |
| 232 | } |
| 233 | |
| 234 | /** |
| 235 | * _sde_plane_set_qos_lut - set QoS LUT of the given plane |
| 236 | * @plane: Pointer to drm plane |
| 237 | * @fb: Pointer to framebuffer associated with the given plane |
| 238 | */ |
| 239 | static void _sde_plane_set_qos_lut(struct drm_plane *plane, |
| 240 | struct drm_framebuffer *fb) |
| 241 | { |
| 242 | struct sde_plane *psde; |
| 243 | const struct sde_format *fmt = NULL; |
| 244 | u32 qos_lut; |
| 245 | u32 total_fl = 0; |
| 246 | |
| 247 | if (!plane || !fb) { |
| 248 | SDE_ERROR("invalid arguments plane %d fb %d\n", |
| 249 | plane != 0, fb != 0); |
| 250 | return; |
| 251 | } |
| 252 | |
| 253 | psde = to_sde_plane(plane); |
| 254 | |
| 255 | if (!psde->pipe_hw || !psde->pipe_sblk) { |
| 256 | SDE_ERROR("invalid arguments\n"); |
| 257 | return; |
| 258 | } else if (!psde->pipe_hw->ops.setup_creq_lut) { |
| 259 | return; |
| 260 | } |
| 261 | |
| 262 | if (!psde->is_rt_pipe) { |
| 263 | qos_lut = psde->pipe_sblk->creq_lut_nrt; |
| 264 | } else { |
| 265 | fmt = sde_get_sde_format_ext( |
| 266 | fb->pixel_format, |
| 267 | fb->modifier, |
| 268 | drm_format_num_planes(fb->pixel_format)); |
| 269 | total_fl = _sde_plane_calc_fill_level(plane, fmt, |
| 270 | psde->pipe_cfg.src_rect.w); |
| 271 | |
| 272 | if (SDE_FORMAT_IS_LINEAR(fmt)) |
| 273 | qos_lut = _sde_plane_get_qos_lut_linear(total_fl); |
| 274 | else |
| 275 | qos_lut = _sde_plane_get_qos_lut_macrotile(total_fl); |
| 276 | } |
| 277 | |
| 278 | psde->pipe_qos_cfg.creq_lut = qos_lut; |
| 279 | |
| 280 | trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0, |
| 281 | (fmt) ? fmt->base.pixel_format : 0, |
| 282 | psde->is_rt_pipe, total_fl, qos_lut, |
| 283 | (fmt) ? SDE_FORMAT_IS_LINEAR(fmt) : 0); |
| 284 | |
| 285 | SDE_DEBUG("plane%u: pnum:%d fmt:%x rt:%d fl:%u lut:0x%x\n", |
| 286 | plane->base.id, |
| 287 | psde->pipe - SSPP_VIG0, |
| 288 | (fmt) ? fmt->base.pixel_format : 0, |
| 289 | psde->is_rt_pipe, total_fl, qos_lut); |
| 290 | |
| 291 | psde->pipe_hw->ops.setup_creq_lut(psde->pipe_hw, &psde->pipe_qos_cfg); |
| 292 | } |
| 293 | |
| 294 | /** |
| 295 | * _sde_plane_set_panic_lut - set danger/safe LUT of the given plane |
| 296 | * @plane: Pointer to drm plane |
| 297 | * @fb: Pointer to framebuffer associated with the given plane |
| 298 | */ |
| 299 | static void _sde_plane_set_danger_lut(struct drm_plane *plane, |
| 300 | struct drm_framebuffer *fb) |
| 301 | { |
| 302 | struct sde_plane *psde; |
| 303 | const struct sde_format *fmt = NULL; |
| 304 | u32 danger_lut, safe_lut; |
| 305 | |
| 306 | if (!plane || !fb) { |
| 307 | SDE_ERROR("invalid arguments\n"); |
| 308 | return; |
| 309 | } |
| 310 | |
| 311 | psde = to_sde_plane(plane); |
| 312 | |
| 313 | if (!psde->pipe_hw || !psde->pipe_sblk) { |
| 314 | SDE_ERROR("invalid arguments\n"); |
| 315 | return; |
| 316 | } else if (!psde->pipe_hw->ops.setup_danger_safe_lut) { |
| 317 | return; |
| 318 | } |
| 319 | |
| 320 | if (!psde->is_rt_pipe) { |
| 321 | danger_lut = psde->pipe_sblk->danger_lut_nrt; |
| 322 | safe_lut = psde->pipe_sblk->safe_lut_nrt; |
| 323 | } else { |
| 324 | fmt = sde_get_sde_format_ext( |
| 325 | fb->pixel_format, |
| 326 | fb->modifier, |
| 327 | drm_format_num_planes(fb->pixel_format)); |
| 328 | |
| 329 | if (SDE_FORMAT_IS_LINEAR(fmt)) { |
| 330 | danger_lut = psde->pipe_sblk->danger_lut_linear; |
| 331 | safe_lut = psde->pipe_sblk->safe_lut_linear; |
| 332 | } else { |
| 333 | danger_lut = psde->pipe_sblk->danger_lut_tile; |
| 334 | safe_lut = psde->pipe_sblk->safe_lut_tile; |
| 335 | } |
| 336 | } |
| 337 | |
| 338 | psde->pipe_qos_cfg.danger_lut = danger_lut; |
| 339 | psde->pipe_qos_cfg.safe_lut = safe_lut; |
| 340 | |
| 341 | trace_sde_perf_set_danger_luts(psde->pipe - SSPP_VIG0, |
| 342 | (fmt) ? fmt->base.pixel_format : 0, |
| 343 | (fmt) ? fmt->fetch_mode : 0, |
| 344 | psde->pipe_qos_cfg.danger_lut, |
| 345 | psde->pipe_qos_cfg.safe_lut); |
| 346 | |
| 347 | SDE_DEBUG("plane%u: pnum:%d fmt:%x mode:%d luts[0x%x, 0x%x]\n", |
| 348 | plane->base.id, |
| 349 | psde->pipe - SSPP_VIG0, |
| 350 | fmt ? fmt->base.pixel_format : 0, |
| 351 | fmt ? fmt->fetch_mode : -1, |
| 352 | psde->pipe_qos_cfg.danger_lut, |
| 353 | psde->pipe_qos_cfg.safe_lut); |
| 354 | |
| 355 | psde->pipe_hw->ops.setup_danger_safe_lut(psde->pipe_hw, |
| 356 | &psde->pipe_qos_cfg); |
| 357 | } |
| 358 | |
| 359 | /** |
| 360 | * _sde_plane_set_qos_ctrl - set QoS control of the given plane |
| 361 | * @plane: Pointer to drm plane |
| 362 | * @enable: true to enable QoS control |
| 363 | * @flags: QoS control mode (enum sde_plane_qos) |
| 364 | */ |
| 365 | static void _sde_plane_set_qos_ctrl(struct drm_plane *plane, |
| 366 | bool enable, u32 flags) |
| 367 | { |
| 368 | struct sde_plane *psde; |
| 369 | |
| 370 | if (!plane) { |
| 371 | SDE_ERROR("invalid arguments\n"); |
| 372 | return; |
| 373 | } |
| 374 | |
| 375 | psde = to_sde_plane(plane); |
| 376 | |
| 377 | if (!psde->pipe_hw || !psde->pipe_sblk) { |
| 378 | SDE_ERROR("invalid arguments\n"); |
| 379 | return; |
| 380 | } else if (!psde->pipe_hw->ops.setup_qos_ctrl) { |
| 381 | return; |
| 382 | } |
| 383 | |
| 384 | if (flags & SDE_PLANE_QOS_VBLANK_CTRL) { |
| 385 | psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank; |
| 386 | psde->pipe_qos_cfg.danger_vblank = |
| 387 | psde->pipe_sblk->danger_vblank; |
| 388 | psde->pipe_qos_cfg.vblank_en = enable; |
| 389 | } |
| 390 | |
| 391 | if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) { |
| 392 | /* this feature overrules previous VBLANK_CTRL */ |
| 393 | psde->pipe_qos_cfg.vblank_en = false; |
| 394 | psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */ |
| 395 | } |
| 396 | |
| 397 | if (flags & SDE_PLANE_QOS_PANIC_CTRL) |
| 398 | psde->pipe_qos_cfg.danger_safe_en = enable; |
| 399 | |
| 400 | if (!psde->is_rt_pipe) { |
| 401 | psde->pipe_qos_cfg.vblank_en = false; |
| 402 | psde->pipe_qos_cfg.danger_safe_en = false; |
| 403 | } |
| 404 | |
| 405 | SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x]\n", |
| 406 | plane->base.id, |
| 407 | psde->pipe - SSPP_VIG0, |
| 408 | psde->pipe_qos_cfg.danger_safe_en, |
| 409 | psde->pipe_qos_cfg.vblank_en, |
| 410 | psde->pipe_qos_cfg.creq_vblank, |
| 411 | psde->pipe_qos_cfg.danger_vblank); |
| 412 | |
| 413 | psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw, |
| 414 | &psde->pipe_qos_cfg); |
| 415 | } |
| 416 | |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 417 | /** |
| 418 | * _sde_plane_set_ot_limit - set OT limit for the given plane |
| 419 | * @plane: Pointer to drm plane |
| 420 | * @crtc: Pointer to drm crtc |
| 421 | */ |
| 422 | static void _sde_plane_set_ot_limit(struct drm_plane *plane, |
| 423 | struct drm_crtc *crtc) |
| 424 | { |
| 425 | struct sde_plane *psde; |
| 426 | struct sde_vbif_set_ot_params ot_params; |
| 427 | struct msm_drm_private *priv; |
| 428 | struct sde_kms *sde_kms; |
| 429 | |
| 430 | if (!plane || !plane->dev || !crtc) { |
| 431 | SDE_ERROR("invalid arguments plane %d crtc %d\n", |
| 432 | plane != 0, crtc != 0); |
| 433 | return; |
| 434 | } |
| 435 | |
| 436 | priv = plane->dev->dev_private; |
| 437 | if (!priv || !priv->kms) { |
| 438 | SDE_ERROR("invalid KMS reference\n"); |
| 439 | return; |
| 440 | } |
| 441 | |
| 442 | sde_kms = to_sde_kms(priv->kms); |
| 443 | psde = to_sde_plane(plane); |
| 444 | if (!psde->pipe_hw) { |
| 445 | SDE_ERROR("invalid pipe reference\n"); |
| 446 | return; |
| 447 | } |
| 448 | |
| 449 | memset(&ot_params, 0, sizeof(ot_params)); |
| 450 | ot_params.xin_id = psde->pipe_hw->cap->xin_id; |
| 451 | ot_params.num = psde->pipe_hw->idx - SSPP_NONE; |
| 452 | ot_params.width = psde->pipe_cfg.src_rect.w; |
| 453 | ot_params.height = psde->pipe_cfg.src_rect.h; |
| 454 | ot_params.is_wfd = !psde->is_rt_pipe; |
| 455 | ot_params.frame_rate = crtc->mode.vrefresh; |
| 456 | ot_params.vbif_idx = VBIF_RT; |
| 457 | ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl; |
| 458 | ot_params.rd = true; |
| 459 | |
| 460 | sde_vbif_set_ot_limit(sde_kms, &ot_params); |
| 461 | } |
| 462 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 463 | /* helper to update a state's input fence pointer from the property */ |
| 464 | static void _sde_plane_set_input_fence(struct drm_plane *plane, |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 465 | struct sde_plane_state *pstate, uint64_t fd) |
| 466 | { |
| 467 | if (!plane || !pstate) |
| 468 | return; |
| 469 | |
| 470 | /* clear previous reference */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 471 | if (pstate->input_fence) |
| 472 | sde_sync_put(pstate->input_fence); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 473 | |
| 474 | /* get fence pointer for later */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 475 | pstate->input_fence = sde_sync_get(fd); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 476 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 477 | SDE_DEBUG("0x%llX\n", fd); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 478 | } |
| 479 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 480 | int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms) |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 481 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 482 | struct sde_plane *psde; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 483 | struct sde_plane_state *pstate; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 484 | void *input_fence; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 485 | int ret = -EINVAL; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 486 | |
| 487 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 488 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 489 | } else if (!plane->state) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 490 | SDE_ERROR("invalid plane state\n"); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 491 | } else { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 492 | psde = to_sde_plane(plane); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 493 | pstate = to_sde_plane_state(plane->state); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 494 | input_fence = pstate->input_fence; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 495 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 496 | if (input_fence) { |
| 497 | ret = sde_sync_wait(input_fence, wait_ms); |
| 498 | switch (ret) { |
| 499 | case 0: |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 500 | SDE_DEBUG("%s signaled\n", psde->pipe_name); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 501 | break; |
| 502 | case -ETIME: |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 503 | SDE_ERROR("timeout on %s, %ums\n", |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 504 | psde->pipe_name, wait_ms); |
| 505 | psde->is_error = true; |
| 506 | break; |
| 507 | default: |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 508 | SDE_ERROR("error on %s, %d\n", |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 509 | psde->pipe_name, ret); |
| 510 | psde->is_error = true; |
| 511 | break; |
| 512 | } |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 513 | } else { |
| 514 | ret = 0; |
| 515 | } |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 516 | } |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 517 | return ret; |
| 518 | } |
| 519 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 520 | static inline void _sde_plane_set_scanout(struct drm_plane *plane, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 521 | struct sde_plane_state *pstate, |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 522 | struct sde_hw_pipe_cfg *pipe_cfg, |
| 523 | struct drm_framebuffer *fb) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 524 | { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 525 | struct sde_plane *psde; |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 526 | int ret; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 527 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 528 | if (!plane || !pstate || !pipe_cfg || !fb) |
| 529 | return; |
| 530 | |
| 531 | psde = to_sde_plane(plane); |
| 532 | |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 533 | ret = sde_format_populate_layout(psde->mmu_id, fb, &pipe_cfg->layout); |
| 534 | if (ret) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 535 | SDE_ERROR("failed to get format layout, error: %d\n", ret); |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 536 | return; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 537 | } |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 538 | |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 539 | if (psde->pipe_hw && psde->pipe_hw->ops.setup_sourceaddress) |
| 540 | psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 541 | } |
| 542 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 543 | static void _sde_plane_setup_scaler3(struct sde_plane *psde, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 544 | uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, |
| 545 | struct sde_hw_scaler3_cfg *scale_cfg, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 546 | const struct sde_format *fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 547 | uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) |
| 548 | { |
| 549 | } |
| 550 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 551 | /** |
| 552 | * _sde_plane_setup_scaler2(): Determine default scaler phase steps/filter type |
| 553 | * @psde: Pointer to SDE plane object |
| 554 | * @src: Source size |
| 555 | * @dst: Destination size |
| 556 | * @phase_steps: Pointer to output array for phase steps |
| 557 | * @filter: Pointer to output array for filter type |
| 558 | * @fmt: Pointer to format definition |
| 559 | * @chroma_subsampling: Subsampling amount for chroma channel |
| 560 | * |
| 561 | * Returns: 0 on success |
| 562 | */ |
| 563 | static int _sde_plane_setup_scaler2(struct sde_plane *psde, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 564 | uint32_t src, uint32_t dst, uint32_t *phase_steps, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 565 | enum sde_hw_filter *filter, const struct sde_format *fmt, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 566 | uint32_t chroma_subsampling) |
| 567 | { |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 568 | if (!psde || !phase_steps || !filter || !fmt) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 569 | SDE_ERROR("invalid arguments\n"); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 570 | return -EINVAL; |
| 571 | } |
| 572 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 573 | /* calculate phase steps, leave init phase as zero */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 574 | phase_steps[SDE_SSPP_COMP_0] = |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 575 | mult_frac(1 << PHASE_STEP_SHIFT, src, dst); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 576 | phase_steps[SDE_SSPP_COMP_1_2] = |
| 577 | phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling; |
| 578 | phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2]; |
| 579 | phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 580 | |
| 581 | /* calculate scaler config, if necessary */ |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 582 | if (SDE_FORMAT_IS_YUV(fmt) || src != dst) { |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 583 | filter[SDE_SSPP_COMP_3] = |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 584 | (src <= dst) ? SDE_SCALE_FILTER_BIL : |
| 585 | SDE_SCALE_FILTER_PCMN; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 586 | |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 587 | if (SDE_FORMAT_IS_YUV(fmt)) { |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 588 | filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 589 | filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3]; |
| 590 | } else { |
| 591 | filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3]; |
| 592 | filter[SDE_SSPP_COMP_1_2] = |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 593 | SDE_SCALE_FILTER_NEAREST; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 594 | } |
| 595 | } else { |
| 596 | /* disable scaler */ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 597 | SDE_DEBUG("disable scaler\n"); |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 598 | filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX; |
| 599 | filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX; |
| 600 | filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 601 | } |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 602 | return 0; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 603 | } |
| 604 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 605 | /** |
| 606 | * _sde_plane_setup_pixel_ext - determine default pixel extension values |
| 607 | * @psde: Pointer to SDE plane object |
| 608 | * @src: Source size |
| 609 | * @dst: Destination size |
| 610 | * @decimated_src: Source size after decimation, if any |
| 611 | * @phase_steps: Pointer to output array for phase steps |
| 612 | * @out_src: Output array for pixel extension values |
| 613 | * @out_edge1: Output array for pixel extension first edge |
| 614 | * @out_edge2: Output array for pixel extension second edge |
| 615 | * @filter: Pointer to array for filter type |
| 616 | * @fmt: Pointer to format definition |
| 617 | * @chroma_subsampling: Subsampling amount for chroma channel |
| 618 | * @post_compare: Whether to chroma subsampled source size for comparisions |
| 619 | */ |
| 620 | static void _sde_plane_setup_pixel_ext(struct sde_plane *psde, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 621 | uint32_t src, uint32_t dst, uint32_t decimated_src, |
| 622 | uint32_t *phase_steps, uint32_t *out_src, int *out_edge1, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 623 | int *out_edge2, enum sde_hw_filter *filter, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 624 | const struct sde_format *fmt, uint32_t chroma_subsampling, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 625 | bool post_compare) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 626 | { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 627 | int64_t edge1, edge2, caf; |
| 628 | uint32_t src_work; |
| 629 | int i, tmp; |
| 630 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 631 | if (psde && phase_steps && out_src && out_edge1 && |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 632 | out_edge2 && filter && fmt) { |
| 633 | /* handle CAF for YUV formats */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 634 | if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 635 | caf = PHASE_STEP_UNIT_SCALE; |
| 636 | else |
| 637 | caf = 0; |
| 638 | |
| 639 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 640 | src_work = decimated_src; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 641 | if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 642 | src_work /= chroma_subsampling; |
| 643 | if (post_compare) |
| 644 | src = src_work; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 645 | if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 646 | /* unity */ |
| 647 | edge1 = 0; |
| 648 | edge2 = 0; |
| 649 | } else if (dst >= src) { |
| 650 | /* upscale */ |
| 651 | edge1 = (1 << PHASE_RESIDUAL); |
| 652 | edge1 -= caf; |
| 653 | edge2 = (1 << PHASE_RESIDUAL); |
| 654 | edge2 += (dst - 1) * *(phase_steps + i); |
| 655 | edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE; |
| 656 | edge2 += caf; |
| 657 | edge2 = -(edge2); |
| 658 | } else { |
| 659 | /* downscale */ |
| 660 | edge1 = 0; |
| 661 | edge2 = (dst - 1) * *(phase_steps + i); |
| 662 | edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE; |
| 663 | edge2 += *(phase_steps + i); |
| 664 | edge2 = -(edge2); |
| 665 | } |
| 666 | |
| 667 | /* only enable CAF for luma plane */ |
| 668 | caf = 0; |
| 669 | |
| 670 | /* populate output arrays */ |
| 671 | *(out_src + i) = src_work; |
| 672 | |
| 673 | /* edge updates taken from __pxl_extn_helper */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 674 | if (edge1 >= 0) { |
| 675 | tmp = (uint32_t)edge1; |
| 676 | tmp >>= PHASE_STEP_SHIFT; |
| 677 | *(out_edge1 + i) = -tmp; |
| 678 | } else { |
| 679 | tmp = (uint32_t)(-edge1); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 680 | *(out_edge1 + i) = |
| 681 | (tmp + PHASE_STEP_UNIT_SCALE - 1) >> |
| 682 | PHASE_STEP_SHIFT; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 683 | } |
| 684 | if (edge2 >= 0) { |
| 685 | tmp = (uint32_t)edge2; |
| 686 | tmp >>= PHASE_STEP_SHIFT; |
| 687 | *(out_edge2 + i) = -tmp; |
| 688 | } else { |
| 689 | tmp = (uint32_t)(-edge2); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 690 | *(out_edge2 + i) = |
| 691 | (tmp + PHASE_STEP_UNIT_SCALE - 1) >> |
| 692 | PHASE_STEP_SHIFT; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 693 | } |
| 694 | } |
| 695 | } |
| 696 | } |
| 697 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 698 | /** |
| 699 | * _sde_plane_verify_blob - verify incoming blob is big enough to contain |
| 700 | * sub-structure |
| 701 | * @blob_ptr: Pointer to start of incoming blob data |
| 702 | * @blob_size: Size of incoming blob data, in bytes |
| 703 | * @sub_ptr: Pointer to start of desired sub-structure |
| 704 | * @sub_size: Required size of sub-structure, in bytes |
| 705 | */ |
| 706 | static int _sde_plane_verify_blob(void *blob_ptr, |
| 707 | size_t blob_size, |
| 708 | void *sub_ptr, |
| 709 | size_t sub_size) |
| 710 | { |
| 711 | /* |
| 712 | * Use the blob size provided by drm to check if there are enough |
| 713 | * bytes from the start of versioned sub-structures to the end of |
| 714 | * blob data: |
| 715 | * |
| 716 | * e.g., |
| 717 | * blob_ptr --> struct blob_data { |
| 718 | * uint32_t version; |
| 719 | * sub_ptr --> struct blob_data_v1 v1; |
| 720 | * sub_ptr + sub_size --> struct blob_stuff more_stuff; |
| 721 | * blob_ptr + blob_size --> }; |
| 722 | * |
| 723 | * It's important to check the actual number of bytes from the start |
| 724 | * of the sub-structure to the end of the blob data, and not just rely |
| 725 | * on something like, |
| 726 | * |
| 727 | * sizeof(blob) - sizeof(blob->version) >= sizeof(sub-struct) |
| 728 | * |
| 729 | * This is because the start of the sub-structure can vary based on |
| 730 | * how the compiler pads the overall structure. |
| 731 | */ |
| 732 | if (blob_ptr && sub_ptr) |
| 733 | /* return zero if end of blob >= end of sub-struct */ |
| 734 | return ((unsigned char *)blob_ptr + blob_size) < |
| 735 | ((unsigned char *)sub_ptr + sub_size); |
| 736 | return -EINVAL; |
| 737 | } |
| 738 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 739 | static void _sde_plane_setup_csc(struct sde_plane *psde, |
| 740 | struct sde_plane_state *pstate, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 741 | const struct sde_format *fmt) |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 742 | { |
| 743 | static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = { |
| 744 | { |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 745 | /* S15.16 format */ |
| 746 | 0x00012A00, 0x00000000, 0x00019880, |
| 747 | 0x00012A00, 0xFFFF9B80, 0xFFFF3000, |
| 748 | 0x00012A00, 0x00020480, 0x00000000, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 749 | }, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 750 | /* signed bias */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 751 | { 0xfff0, 0xff80, 0xff80,}, |
| 752 | { 0x0, 0x0, 0x0,}, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 753 | /* unsigned clamp */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 754 | { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,}, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 755 | { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,}, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 756 | }; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 757 | static const struct sde_csc_cfg sde_csc_NOP = { |
| 758 | { |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 759 | /* identity matrix, S15.16 format */ |
| 760 | 0x10000, 0x00000, 0x00000, |
| 761 | 0x00000, 0x10000, 0x00000, |
| 762 | 0x00000, 0x00000, 0x10000, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 763 | }, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 764 | /* signed bias */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 765 | { 0x0, 0x0, 0x0,}, |
| 766 | { 0x0, 0x0, 0x0,}, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 767 | /* unsigned clamp */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 768 | { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff,}, |
| 769 | { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff,}, |
| 770 | }; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 771 | struct sde_drm_csc *csc = NULL; |
| 772 | size_t csc_size = 0; |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 773 | int i; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 774 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 775 | if (!psde || !pstate || !fmt) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 776 | SDE_ERROR("invalid arguments\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 777 | return; |
| 778 | } |
| 779 | if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_csc) |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 780 | return; |
| 781 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 782 | /* check for user space override */ |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 783 | psde->csc_ptr = NULL; |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 784 | csc = msm_property_get_blob(&psde->property_info, |
| 785 | pstate->property_blobs, |
| 786 | &csc_size, |
| 787 | PLANE_PROP_CSC); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 788 | if (csc) { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 789 | /* user space override */ |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 790 | memcpy(&psde->csc_cfg, |
| 791 | &sde_csc_NOP, |
| 792 | sizeof(struct sde_csc_cfg)); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 793 | switch (csc->version) { |
| 794 | case SDE_DRM_CSC_V1: |
| 795 | if (!_sde_plane_verify_blob(csc, |
| 796 | csc_size, |
| 797 | &csc->v1, |
| 798 | sizeof(struct sde_drm_csc_v1))) { |
| 799 | for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i) |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 800 | psde->csc_cfg.csc_mv[i] = |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 801 | csc->v1.ctm_coeff[i] >> 16; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 802 | for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) { |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 803 | psde->csc_cfg.csc_pre_bv[i] = |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 804 | csc->v1.pre_bias[i]; |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 805 | psde->csc_cfg.csc_post_bv[i] = |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 806 | csc->v1.post_bias[i]; |
| 807 | } |
| 808 | for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) { |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 809 | psde->csc_cfg.csc_pre_lv[i] = |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 810 | csc->v1.pre_clamp[i]; |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 811 | psde->csc_cfg.csc_post_lv[i] = |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 812 | csc->v1.post_clamp[i]; |
| 813 | } |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 814 | psde->csc_ptr = &psde->csc_cfg; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 815 | } |
| 816 | break; |
| 817 | default: |
| 818 | break; |
| 819 | } |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 820 | if (!psde->csc_ptr) |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 821 | SDE_ERROR("invalid csc blob, v%lld\n", csc->version); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 822 | } |
| 823 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 824 | /* revert to kernel default if override not available */ |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 825 | if (psde->csc_ptr) |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 826 | SDE_DEBUG("user blob override for csc\n"); |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 827 | else if (SDE_FORMAT_IS_YUV(fmt)) |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 828 | psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 829 | } |
| 830 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 831 | static void _sde_plane_setup_scaler(struct sde_plane *psde, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 832 | const struct sde_format *fmt, |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 833 | struct sde_plane_state *pstate) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 834 | { |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 835 | struct sde_hw_pixel_ext *pe = NULL; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 836 | struct sde_drm_scaler *sc_u = NULL; |
| 837 | struct sde_drm_scaler_v1 *sc_u1 = NULL; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 838 | size_t sc_u_size = 0; |
| 839 | uint32_t chroma_subsmpl_h, chroma_subsmpl_v; |
| 840 | uint32_t tmp; |
| 841 | int i; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 842 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 843 | if (!psde || !fmt) |
| 844 | return; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 845 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 846 | pe = &(psde->pixel_ext); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 847 | memset(pe, 0, sizeof(struct sde_hw_pixel_ext)); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 848 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 849 | /* get scaler config from user space */ |
Clarence Ip | c3ffec1 | 2016-07-18 19:07:24 -0400 | [diff] [blame] | 850 | if (pstate) |
| 851 | sc_u = msm_property_get_blob(&psde->property_info, |
| 852 | pstate->property_blobs, |
| 853 | &sc_u_size, |
| 854 | PLANE_PROP_SCALER); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 855 | if (sc_u) { |
| 856 | switch (sc_u->version) { |
| 857 | case SDE_DRM_SCALER_V1: |
| 858 | if (!_sde_plane_verify_blob(sc_u, |
| 859 | sc_u_size, |
| 860 | &sc_u->v1, |
| 861 | sizeof(*sc_u1))) |
| 862 | sc_u1 = &sc_u->v1; |
| 863 | break; |
| 864 | default: |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 865 | SDE_DEBUG("unrecognized scaler blob v%lld\n", |
| 866 | sc_u->version); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 867 | break; |
| 868 | } |
| 869 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 870 | |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 871 | /* decimation */ |
| 872 | if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_DECIMATE)) { |
| 873 | psde->pipe_cfg.horz_decimation = sc_u1->horz_decimate; |
| 874 | psde->pipe_cfg.vert_decimation = sc_u1->vert_decimate; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 875 | } else { |
| 876 | psde->pipe_cfg.horz_decimation = 0; |
| 877 | psde->pipe_cfg.vert_decimation = 0; |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 878 | } |
| 879 | |
| 880 | /* don't chroma subsample if decimating */ |
| 881 | chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 882 | drm_format_horz_chroma_subsampling(fmt->base.pixel_format); |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 883 | chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 884 | drm_format_vert_chroma_subsampling(fmt->base.pixel_format); |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 885 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 886 | /* update scaler */ |
| 887 | if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) { |
| 888 | if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_SCALER_3)) |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 889 | SDE_DEBUG("SCALER3 blob detected\n"); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 890 | else |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 891 | _sde_plane_setup_scaler3(psde, |
| 892 | psde->pipe_cfg.src_rect.w, |
| 893 | psde->pipe_cfg.src_rect.h, |
| 894 | psde->pipe_cfg.dst_rect.w, |
| 895 | psde->pipe_cfg.dst_rect.h, |
| 896 | &psde->scaler3_cfg, fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 897 | chroma_subsmpl_h, chroma_subsmpl_v); |
| 898 | } else { |
| 899 | /* always calculate basic scaler config */ |
| 900 | if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_SCALER_2)) { |
| 901 | /* populate from user space */ |
| 902 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 903 | pe->init_phase_x[i] = sc_u1->init_phase_x[i]; |
| 904 | pe->phase_step_x[i] = sc_u1->phase_step_x[i]; |
| 905 | pe->init_phase_y[i] = sc_u1->init_phase_y[i]; |
| 906 | pe->phase_step_y[i] = sc_u1->phase_step_y[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 907 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 908 | pe->horz_filter[i] = sc_u1->horz_filter[i]; |
| 909 | pe->vert_filter[i] = sc_u1->vert_filter[i]; |
| 910 | } |
| 911 | } else { |
| 912 | /* calculate phase steps */ |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 913 | _sde_plane_setup_scaler2(psde, |
| 914 | psde->pipe_cfg.src_rect.w, |
| 915 | psde->pipe_cfg.dst_rect.w, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 916 | pe->phase_step_x, |
| 917 | pe->horz_filter, fmt, chroma_subsmpl_h); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 918 | _sde_plane_setup_scaler2(psde, |
| 919 | psde->pipe_cfg.src_rect.h, |
| 920 | psde->pipe_cfg.dst_rect.h, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 921 | pe->phase_step_y, |
| 922 | pe->vert_filter, fmt, chroma_subsmpl_v); |
| 923 | } |
| 924 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 925 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 926 | /* update pixel extensions */ |
| 927 | if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_PIX_EXT)) { |
| 928 | /* populate from user space */ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 929 | SDE_DEBUG("pixel ext blob detected\n"); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 930 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 931 | pe->num_ext_pxls_left[i] = sc_u1->lr.num_pxls_start[i]; |
| 932 | pe->num_ext_pxls_right[i] = sc_u1->lr.num_pxls_end[i]; |
| 933 | pe->left_ftch[i] = sc_u1->lr.ftch_start[i]; |
| 934 | pe->right_ftch[i] = sc_u1->lr.ftch_end[i]; |
| 935 | pe->left_rpt[i] = sc_u1->lr.rpt_start[i]; |
| 936 | pe->right_rpt[i] = sc_u1->lr.rpt_end[i]; |
| 937 | pe->roi_w[i] = sc_u1->lr.roi[i]; |
| 938 | |
| 939 | pe->num_ext_pxls_top[i] = sc_u1->tb.num_pxls_start[i]; |
| 940 | pe->num_ext_pxls_btm[i] = sc_u1->tb.num_pxls_end[i]; |
| 941 | pe->top_ftch[i] = sc_u1->tb.ftch_start[i]; |
| 942 | pe->btm_ftch[i] = sc_u1->tb.ftch_end[i]; |
| 943 | pe->top_rpt[i] = sc_u1->tb.rpt_start[i]; |
| 944 | pe->btm_rpt[i] = sc_u1->tb.rpt_end[i]; |
| 945 | pe->roi_h[i] = sc_u1->tb.roi[i]; |
| 946 | } |
| 947 | } else { |
| 948 | /* calculate left/right/top/bottom pixel extensions */ |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 949 | tmp = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 950 | psde->pipe_cfg.horz_decimation); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 951 | if (SDE_FORMAT_IS_YUV(fmt)) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 952 | tmp &= ~0x1; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 953 | _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w, |
| 954 | psde->pipe_cfg.dst_rect.w, tmp, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 955 | pe->phase_step_x, |
| 956 | pe->roi_w, |
| 957 | pe->num_ext_pxls_left, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 958 | pe->num_ext_pxls_right, pe->horz_filter, fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 959 | chroma_subsmpl_h, 0); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 960 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 961 | tmp = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 962 | psde->pipe_cfg.vert_decimation); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 963 | _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h, |
| 964 | psde->pipe_cfg.dst_rect.h, tmp, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 965 | pe->phase_step_y, |
| 966 | pe->roi_h, |
| 967 | pe->num_ext_pxls_top, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 968 | pe->num_ext_pxls_btm, pe->vert_filter, fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 969 | chroma_subsmpl_v, 1); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 970 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 971 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 972 | if (pe->num_ext_pxls_left[i] >= 0) |
| 973 | pe->left_rpt[i] = |
| 974 | pe->num_ext_pxls_left[i]; |
| 975 | else |
| 976 | pe->left_ftch[i] = |
| 977 | pe->num_ext_pxls_left[i]; |
| 978 | |
| 979 | if (pe->num_ext_pxls_right[i] >= 0) |
| 980 | pe->right_rpt[i] = |
| 981 | pe->num_ext_pxls_right[i]; |
| 982 | else |
| 983 | pe->right_ftch[i] = |
| 984 | pe->num_ext_pxls_right[i]; |
| 985 | |
| 986 | if (pe->num_ext_pxls_top[i] >= 0) |
| 987 | pe->top_rpt[i] = |
| 988 | pe->num_ext_pxls_top[i]; |
| 989 | else |
| 990 | pe->top_ftch[i] = |
| 991 | pe->num_ext_pxls_top[i]; |
| 992 | |
| 993 | if (pe->num_ext_pxls_btm[i] >= 0) |
| 994 | pe->btm_rpt[i] = |
| 995 | pe->num_ext_pxls_btm[i]; |
| 996 | else |
| 997 | pe->btm_ftch[i] = |
| 998 | pe->num_ext_pxls_btm[i]; |
| 999 | } |
| 1000 | } |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1001 | } |
| 1002 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1003 | /** |
| 1004 | * _sde_plane_color_fill - enables color fill on plane |
| 1005 | * @plane: Pointer to DRM plane object |
| 1006 | * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red |
| 1007 | * @alpha: 8-bit fill alpha value, 255 selects 100% alpha |
| 1008 | * Returns: 0 on success |
| 1009 | */ |
| 1010 | static int _sde_plane_color_fill(struct drm_plane *plane, |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1011 | uint32_t color, uint32_t alpha) |
| 1012 | { |
| 1013 | struct sde_plane *psde; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 1014 | const struct sde_format *fmt; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1015 | |
| 1016 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1017 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1018 | return -EINVAL; |
| 1019 | } |
| 1020 | |
| 1021 | psde = to_sde_plane(plane); |
| 1022 | if (!psde->pipe_hw) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1023 | SDE_ERROR("invalid plane h/w pointer\n"); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1024 | return -EINVAL; |
| 1025 | } |
| 1026 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1027 | DBG(""); |
| 1028 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1029 | /* |
| 1030 | * select fill format to match user property expectation, |
| 1031 | * h/w only supports RGB variants |
| 1032 | */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 1033 | fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1034 | |
| 1035 | /* update sspp */ |
| 1036 | if (fmt && psde->pipe_hw->ops.setup_solidfill) { |
| 1037 | psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw, |
| 1038 | (color & 0xFFFFFF) | ((alpha & 0xFF) << 24)); |
| 1039 | |
| 1040 | /* override scaler/decimation if solid fill */ |
| 1041 | psde->pipe_cfg.src_rect.x = 0; |
| 1042 | psde->pipe_cfg.src_rect.y = 0; |
| 1043 | psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w; |
| 1044 | psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h; |
| 1045 | |
| 1046 | _sde_plane_setup_scaler(psde, fmt, 0); |
| 1047 | |
| 1048 | if (psde->pipe_hw->ops.setup_format) |
| 1049 | psde->pipe_hw->ops.setup_format(psde->pipe_hw, |
| 1050 | fmt, SDE_SSPP_SOLID_FILL); |
| 1051 | |
| 1052 | if (psde->pipe_hw->ops.setup_rects) |
| 1053 | psde->pipe_hw->ops.setup_rects(psde->pipe_hw, |
| 1054 | &psde->pipe_cfg, &psde->pixel_ext); |
| 1055 | } |
| 1056 | |
| 1057 | return 0; |
| 1058 | } |
| 1059 | |
| 1060 | static int _sde_plane_mode_set(struct drm_plane *plane, |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1061 | struct drm_plane_state *state) |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1062 | { |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1063 | uint32_t nplanes, src_flags, zpos, split_w; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1064 | struct sde_plane *psde; |
| 1065 | struct sde_plane_state *pstate; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 1066 | const struct sde_format *fmt; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1067 | struct drm_crtc *crtc; |
| 1068 | struct drm_framebuffer *fb; |
| 1069 | struct sde_rect src, dst; |
| 1070 | bool q16_data = true; |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1071 | int idx; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1072 | |
| 1073 | if (!plane || !plane->state) { |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1074 | SDE_ERROR("invalid plane\n"); |
| 1075 | return -EINVAL; |
| 1076 | } else if (!plane->state) { |
| 1077 | SDE_ERROR("invalid plane state\n"); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1078 | return -EINVAL; |
| 1079 | } |
| 1080 | |
| 1081 | psde = to_sde_plane(plane); |
| 1082 | pstate = to_sde_plane_state(plane->state); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1083 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1084 | crtc = state->crtc; |
| 1085 | fb = state->fb; |
| 1086 | if (!crtc || !fb) { |
| 1087 | SDE_ERROR("invalid crtc/fb\n"); |
| 1088 | return -EINVAL; |
| 1089 | } |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 1090 | fmt = to_sde_format(msm_framebuffer_format(fb)); |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1091 | nplanes = fmt->num_planes; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1092 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1093 | /* determine what needs to be refreshed */ |
| 1094 | while ((idx = msm_property_pop_dirty(&psde->property_info)) >= 0) { |
| 1095 | switch (idx) { |
| 1096 | case PLANE_PROP_SCALER: |
| 1097 | pstate->dirty |= SDE_PLANE_DIRTY_RECTS; |
| 1098 | break; |
| 1099 | case PLANE_PROP_CSC: |
| 1100 | pstate->dirty |= SDE_PLANE_DIRTY_FORMAT; |
| 1101 | break; |
| 1102 | case PLANE_PROP_COLOR_FILL: |
| 1103 | /* potentially need to refresh everything */ |
| 1104 | pstate->dirty = SDE_PLANE_DIRTY_ALL; |
| 1105 | break; |
| 1106 | case PLANE_PROP_ROTATION: |
| 1107 | pstate->dirty |= SDE_PLANE_DIRTY_FORMAT; |
| 1108 | break; |
| 1109 | case PLANE_PROP_SRC_CONFIG: |
| 1110 | case PLANE_PROP_ZPOS: |
| 1111 | pstate->dirty |= SDE_PLANE_DIRTY_RECTS; |
| 1112 | break; |
| 1113 | case PLANE_PROP_INFO: |
| 1114 | case PLANE_PROP_ALPHA: |
| 1115 | case PLANE_PROP_INPUT_FENCE: |
| 1116 | case PLANE_PROP_BLEND_OP: |
| 1117 | /* no special action required */ |
| 1118 | break; |
| 1119 | default: |
| 1120 | /* unknown property, refresh everything */ |
| 1121 | pstate->dirty |= SDE_PLANE_DIRTY_ALL; |
| 1122 | SDE_ERROR("executing full mode set, prp_idx %d\n", idx); |
| 1123 | break; |
| 1124 | } |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1125 | } |
| 1126 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1127 | if (pstate->dirty & SDE_PLANE_DIRTY_RECTS) |
| 1128 | memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg)); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1129 | |
| 1130 | _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb); |
| 1131 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1132 | /* early out if nothing dirty */ |
| 1133 | if (!pstate->dirty) |
| 1134 | return 0; |
| 1135 | pstate->pending = true; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1136 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1137 | psde->is_rt_pipe = _sde_plane_is_rt_pipe(plane, crtc); |
| 1138 | _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL); |
| 1139 | |
| 1140 | /* update roi config */ |
| 1141 | if (pstate->dirty & SDE_PLANE_DIRTY_RECTS) { |
| 1142 | POPULATE_RECT(&src, state->src_x, state->src_y, |
| 1143 | state->src_w, state->src_h, q16_data); |
| 1144 | POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, |
| 1145 | state->crtc_w, state->crtc_h, !q16_data); |
| 1146 | |
| 1147 | SDE_DEBUG( |
| 1148 | "%s:FB[%u] %u,%u,%u,%u -> crtc%u %d,%d,%u,%u, %s ubwc %d\n", |
| 1149 | psde->pipe_name, |
| 1150 | fb->base.id, src.x, src.y, src.w, src.h, |
| 1151 | crtc->base.id, dst.x, dst.y, dst.w, dst.h, |
| 1152 | drm_get_format_name(fmt->base.pixel_format), |
| 1153 | SDE_FORMAT_IS_UBWC(fmt)); |
| 1154 | |
| 1155 | if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) & |
| 1156 | BIT(SDE_DRM_DEINTERLACE)) { |
| 1157 | SDE_DEBUG("deinterlace\n"); |
| 1158 | for (idx = 0; idx < SDE_MAX_PLANES; ++idx) |
| 1159 | psde->pipe_cfg.layout.plane_pitch[idx] <<= 1; |
| 1160 | src.h /= 2; |
| 1161 | src.y = DIV_ROUND_UP(src.y, 2); |
| 1162 | src.y &= ~0x1; |
| 1163 | } |
| 1164 | |
| 1165 | psde->pipe_cfg.src_rect = src; |
| 1166 | psde->pipe_cfg.dst_rect = dst; |
| 1167 | |
| 1168 | /* check for color fill */ |
| 1169 | psde->color_fill = (uint32_t)sde_plane_get_property(pstate, |
| 1170 | PLANE_PROP_COLOR_FILL); |
| 1171 | if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) { |
| 1172 | /* skip remaining processing on color fill */ |
| 1173 | pstate->dirty = 0x0; |
| 1174 | } else if (psde->pipe_hw->ops.setup_rects) { |
| 1175 | _sde_plane_setup_scaler(psde, fmt, pstate); |
| 1176 | |
| 1177 | /* base layer source split needs update */ |
| 1178 | zpos = sde_plane_get_property(pstate, PLANE_PROP_ZPOS); |
| 1179 | if (zpos == SDE_STAGE_BASE) { |
| 1180 | split_w = get_crtc_split_width(crtc); |
| 1181 | if (psde->pipe_cfg.dst_rect.x >= split_w) |
| 1182 | psde->pipe_cfg.dst_rect.x -= split_w; |
| 1183 | } |
| 1184 | psde->pipe_hw->ops.setup_rects(psde->pipe_hw, |
| 1185 | &psde->pipe_cfg, &psde->pixel_ext); |
| 1186 | } |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1187 | } |
| 1188 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1189 | if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT) && |
| 1190 | psde->pipe_hw->ops.setup_format) { |
| 1191 | src_flags = 0x0; |
| 1192 | SDE_DEBUG("rotation 0x%llX\n", |
| 1193 | sde_plane_get_property(pstate, PLANE_PROP_ROTATION)); |
| 1194 | if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) & |
| 1195 | BIT(DRM_REFLECT_X)) |
| 1196 | src_flags |= SDE_SSPP_FLIP_LR; |
| 1197 | if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) & |
| 1198 | BIT(DRM_REFLECT_Y)) |
| 1199 | src_flags |= SDE_SSPP_FLIP_UD; |
| 1200 | |
| 1201 | /* update format */ |
| 1202 | psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt, src_flags); |
| 1203 | |
| 1204 | /* update csc */ |
| 1205 | if (SDE_FORMAT_IS_YUV(fmt)) |
| 1206 | _sde_plane_setup_csc(psde, pstate, fmt); |
| 1207 | else |
| 1208 | psde->csc_ptr = 0; |
| 1209 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1210 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1211 | /* update sharpening */ |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1212 | if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) && |
| 1213 | psde->pipe_hw->ops.setup_sharpening) { |
| 1214 | psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT; |
| 1215 | psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT; |
| 1216 | psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT; |
| 1217 | psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1218 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1219 | psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw, |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1220 | &psde->sharp_cfg); |
| 1221 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1222 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 1223 | _sde_plane_set_qos_lut(plane, fb); |
| 1224 | _sde_plane_set_danger_lut(plane, fb); |
| 1225 | |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 1226 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 1227 | _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL); |
Alan Kwong | 5d324e4 | 2016-07-28 22:56:18 -0400 | [diff] [blame] | 1228 | _sde_plane_set_ot_limit(plane, crtc); |
| 1229 | } |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 1230 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1231 | /* clear dirty */ |
| 1232 | pstate->dirty = 0x0; |
| 1233 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1234 | return 0; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1235 | } |
| 1236 | |
| 1237 | static int sde_plane_prepare_fb(struct drm_plane *plane, |
| 1238 | const struct drm_plane_state *new_state) |
| 1239 | { |
| 1240 | struct drm_framebuffer *fb = new_state->fb; |
| 1241 | struct sde_plane *psde = to_sde_plane(plane); |
| 1242 | |
| 1243 | if (!new_state->fb) |
| 1244 | return 0; |
| 1245 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1246 | SDE_DEBUG("%s: FB[%u]\n", psde->pipe_name, fb->base.id); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1247 | return msm_framebuffer_prepare(fb, psde->mmu_id); |
| 1248 | } |
| 1249 | |
| 1250 | static void sde_plane_cleanup_fb(struct drm_plane *plane, |
| 1251 | const struct drm_plane_state *old_state) |
| 1252 | { |
| 1253 | struct drm_framebuffer *fb = old_state->fb; |
| 1254 | struct sde_plane *psde = to_sde_plane(plane); |
| 1255 | |
| 1256 | if (!fb) |
| 1257 | return; |
| 1258 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1259 | SDE_DEBUG("%s: FB[%u]\n", psde->pipe_name, fb->base.id); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1260 | msm_framebuffer_cleanup(fb, psde->mmu_id); |
| 1261 | } |
| 1262 | |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1263 | static void _sde_plane_atomic_check_mode_changed(struct sde_plane *psde, |
| 1264 | struct drm_plane_state *state, |
| 1265 | struct drm_plane_state *old_state) |
| 1266 | { |
| 1267 | struct sde_plane_state *pstate = to_sde_plane_state(state); |
| 1268 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1269 | /* no need to check it again */ |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1270 | if (pstate->dirty == SDE_PLANE_DIRTY_ALL) |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1271 | return; |
| 1272 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1273 | if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state) |
| 1274 | || psde->is_error) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1275 | SDE_DEBUG("%s: pipe enabling/disabling full modeset required\n", |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1276 | psde->pipe_name); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1277 | pstate->dirty |= SDE_PLANE_DIRTY_ALL; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1278 | } else if (to_sde_plane_state(old_state)->pending) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1279 | SDE_DEBUG("%s: still pending\n", psde->pipe_name); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1280 | pstate->dirty |= SDE_PLANE_DIRTY_ALL; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1281 | } else if (state->src_w != old_state->src_w || |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1282 | state->src_h != old_state->src_h || |
| 1283 | state->src_x != old_state->src_x || |
| 1284 | state->src_y != old_state->src_y) { |
| 1285 | SDE_DEBUG("%s: src rect updated\n", psde->pipe_name); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1286 | pstate->dirty |= SDE_PLANE_DIRTY_RECTS; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1287 | } else if (state->crtc_w != old_state->crtc_w || |
| 1288 | state->crtc_h != old_state->crtc_h || |
| 1289 | state->crtc_x != old_state->crtc_x || |
| 1290 | state->crtc_y != old_state->crtc_y) { |
| 1291 | SDE_DEBUG("%s: crtc rect updated\n", psde->pipe_name); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1292 | pstate->dirty |= SDE_PLANE_DIRTY_RECTS; |
| 1293 | } |
| 1294 | |
| 1295 | if (!state->fb || !old_state->fb) { |
| 1296 | SDE_DEBUG("%s: can't compare fb handles\n", psde->pipe_name); |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1297 | } else if (state->fb->pixel_format != old_state->fb->pixel_format) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1298 | SDE_DEBUG("%s: format change!\n", psde->pipe_name); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1299 | pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1300 | } else { |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1301 | uint64_t *new_mods = state->fb->modifier; |
| 1302 | uint64_t *old_mods = old_state->fb->modifier; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1303 | uint32_t *new_pitches = state->fb->pitches; |
| 1304 | uint32_t *old_pitches = old_state->fb->pitches; |
| 1305 | uint32_t *new_offset = state->fb->offsets; |
| 1306 | uint32_t *old_offset = old_state->fb->offsets; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1307 | int i; |
| 1308 | |
| 1309 | for (i = 0; i < ARRAY_SIZE(state->fb->modifier); i++) { |
| 1310 | if (new_mods[i] != old_mods[i]) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1311 | SDE_DEBUG("%s: format modifiers change\"\ |
| 1312 | plane:%d new_mode:%llu old_mode:%llu\n", |
| 1313 | psde->pipe_name, i, new_mods[i], |
| 1314 | old_mods[i]); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1315 | pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | |
| 1316 | SDE_PLANE_DIRTY_RECTS; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1317 | break; |
| 1318 | } |
| 1319 | } |
Lloyd Atkinson | 3ab9ef7 | 2016-07-14 17:42:41 -0400 | [diff] [blame] | 1320 | for (i = 0; i < ARRAY_SIZE(state->fb->pitches); i++) { |
| 1321 | if (new_pitches[i] != old_pitches[i]) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1322 | SDE_DEBUG("%s: pitches change plane:%d\"\ |
| 1323 | old_pitches:%u new_pitches:%u\n", |
Lloyd Atkinson | 3ab9ef7 | 2016-07-14 17:42:41 -0400 | [diff] [blame] | 1324 | psde->pipe_name, i, old_pitches[i], |
| 1325 | new_pitches[i]); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1326 | pstate->dirty |= SDE_PLANE_DIRTY_RECTS; |
Lloyd Atkinson | 3ab9ef7 | 2016-07-14 17:42:41 -0400 | [diff] [blame] | 1327 | break; |
| 1328 | } |
| 1329 | } |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1330 | for (i = 0; i < ARRAY_SIZE(state->fb->offsets); i++) { |
| 1331 | if (new_offset[i] != old_offset[i]) { |
| 1332 | SDE_DEBUG("%s: offset change plane:%d\"\ |
| 1333 | old_offset:%u new_offset:%u\n", |
| 1334 | psde->pipe_name, i, old_offset[i], |
| 1335 | new_offset[i]); |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1336 | pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | |
| 1337 | SDE_PLANE_DIRTY_RECTS; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1338 | break; |
| 1339 | } |
| 1340 | } |
Lloyd Atkinson | 3ab9ef7 | 2016-07-14 17:42:41 -0400 | [diff] [blame] | 1341 | } |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1342 | } |
| 1343 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1344 | static bool __get_scale_data(struct sde_plane *psde, |
| 1345 | struct sde_plane_state *pstate, struct sde_drm_scaler *sc_u, |
| 1346 | size_t *sc_u_size) |
| 1347 | { |
| 1348 | bool valid_flag = false; |
| 1349 | |
| 1350 | sc_u = msm_property_get_blob(&psde->property_info, |
| 1351 | pstate->property_blobs, |
| 1352 | sc_u_size, |
| 1353 | PLANE_PROP_SCALER); |
| 1354 | if (sc_u) { |
| 1355 | switch (sc_u->version) { |
| 1356 | case SDE_DRM_SCALER_V1: |
| 1357 | if (!_sde_plane_verify_blob(sc_u, *sc_u_size, |
| 1358 | &sc_u->v1, sizeof(struct sde_drm_scaler_v1))) |
| 1359 | valid_flag = true; |
| 1360 | break; |
| 1361 | default: |
| 1362 | SDE_DEBUG("unrecognized scaler blob v%lld\n", |
| 1363 | sc_u->version); |
| 1364 | break; |
| 1365 | } |
| 1366 | } |
| 1367 | |
| 1368 | return valid_flag; |
| 1369 | } |
| 1370 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1371 | static int sde_plane_atomic_check(struct drm_plane *plane, |
| 1372 | struct drm_plane_state *state) |
| 1373 | { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1374 | int ret = 0, valid_scale_data; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1375 | struct sde_plane *psde; |
| 1376 | struct sde_plane_state *pstate; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 1377 | const struct sde_format *fmt; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1378 | size_t sc_u_size = 0; |
| 1379 | struct sde_drm_scaler *sc_u = NULL; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1380 | struct sde_rect src, dst; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1381 | uint32_t deci_w, deci_h, src_deci_w, src_deci_h; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1382 | uint32_t max_upscale, max_downscale, min_src_size, max_linewidth; |
| 1383 | bool q16_data = true; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1384 | |
| 1385 | if (!plane || !state) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1386 | SDE_ERROR("invalid plane/state\n"); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1387 | ret = -EINVAL; |
| 1388 | goto exit; |
| 1389 | } |
| 1390 | |
| 1391 | psde = to_sde_plane(plane); |
| 1392 | pstate = to_sde_plane_state(state); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1393 | |
| 1394 | if (!psde->pipe_sblk) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1395 | SDE_ERROR("invalid plane catalog\n"); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1396 | ret = -EINVAL; |
| 1397 | goto exit; |
| 1398 | } |
| 1399 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1400 | valid_scale_data = __get_scale_data(psde, pstate, sc_u, &sc_u_size); |
| 1401 | deci_w = valid_scale_data && sc_u ? sc_u->v1.horz_decimate : 0; |
| 1402 | deci_h = valid_scale_data && sc_u ? sc_u->v1.vert_decimate : 0; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1403 | |
| 1404 | /* src values are in Q16 fixed point, convert to integer */ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1405 | POPULATE_RECT(&src, state->src_x, state->src_y, state->src_w, |
| 1406 | state->src_h, q16_data); |
| 1407 | POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w, |
| 1408 | state->crtc_h, !q16_data); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1409 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1410 | src_deci_w = DECIMATED_DIMENSION(src.w, deci_w); |
| 1411 | src_deci_h = DECIMATED_DIMENSION(src.h, deci_h); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1412 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1413 | max_upscale = psde->pipe_sblk->maxupscale; |
| 1414 | max_downscale = psde->pipe_sblk->maxdwnscale; |
| 1415 | max_linewidth = psde->pipe_sblk->maxlinewidth; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1416 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1417 | SDE_DEBUG("%s: check (%d -> %d)\n", psde->pipe_name, |
| 1418 | sde_plane_enabled(plane->state), sde_plane_enabled(state)); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1419 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1420 | if (!sde_plane_enabled(state)) |
| 1421 | goto modeset_update; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1422 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1423 | fmt = to_sde_format(msm_framebuffer_format(state->fb)); |
| 1424 | |
| 1425 | min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1; |
| 1426 | |
| 1427 | if (SDE_FORMAT_IS_YUV(fmt) && |
| 1428 | (!(psde->features & SDE_SSPP_SCALER) || |
| 1429 | !(psde->features & BIT(SDE_SSPP_CSC)))) { |
| 1430 | SDE_ERROR("plane doesn't have scaler/csc capability for yuv\n"); |
| 1431 | ret = -EINVAL; |
| 1432 | |
| 1433 | /* check src bounds */ |
| 1434 | } else if (state->fb->width > MAX_IMG_WIDTH || |
| 1435 | state->fb->height > MAX_IMG_HEIGHT || |
| 1436 | src.w < min_src_size || src.h < min_src_size || |
| 1437 | CHECK_LAYER_BOUNDS(src.x, src.w, state->fb->width) || |
| 1438 | CHECK_LAYER_BOUNDS(src.y, src.h, state->fb->height)) { |
| 1439 | SDE_ERROR("invalid source (%u, %u) -> (%u, %u)\n", |
| 1440 | src.x, src.y, src.w, src.h); |
| 1441 | ret = -E2BIG; |
| 1442 | |
| 1443 | /* valid yuv image */ |
| 1444 | } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) || |
| 1445 | (src.w & 0x1) || (src.h & 0x1))) { |
| 1446 | SDE_ERROR("invalid yuv source (%u, %u) -> (%u, %u)\n", |
| 1447 | src.x, src.y, src.w, src.h); |
| 1448 | ret = -EINVAL; |
| 1449 | |
| 1450 | /* min dst support */ |
| 1451 | } else if (dst.w < 0x1 || dst.h < 0x1) { |
| 1452 | SDE_ERROR("invalid dest rect (%u, %u) -> (%u, %u)\n", |
| 1453 | dst.x, dst.y, dst.w, dst.h); |
| 1454 | ret = -EINVAL; |
| 1455 | |
| 1456 | /* decimation validation */ |
| 1457 | } else if (deci_w || deci_h) { |
| 1458 | if ((deci_w > psde->pipe_sblk->maxhdeciexp) || |
| 1459 | (deci_h > psde->pipe_sblk->maxvdeciexp)) { |
| 1460 | SDE_ERROR("too much decimation requested\n"); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1461 | ret = -EINVAL; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1462 | } else if (fmt->fetch_mode != SDE_FETCH_LINEAR) { |
| 1463 | SDE_ERROR("decimation requires linear fetch\n"); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1464 | ret = -EINVAL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1465 | } |
| 1466 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1467 | } else if (!(psde->features & SDE_SSPP_SCALER) && |
| 1468 | ((src.w != dst.w) || (src.h != dst.h))) { |
| 1469 | SDE_ERROR("pipe doesn't support scaling %ux%u->%ux%u\n", |
| 1470 | src.w, src.h, dst.w, dst.h); |
| 1471 | ret = -EINVAL; |
| 1472 | |
| 1473 | /* check decimated source width */ |
| 1474 | } else if (src_deci_w > max_linewidth) { |
| 1475 | SDE_ERROR("invalid source width:%u, deci wid:%u, line wid:%u\n", |
| 1476 | src.w, src_deci_w, max_linewidth); |
| 1477 | ret = -E2BIG; |
| 1478 | |
| 1479 | /* check max scaler capability */ |
| 1480 | } else if (((src_deci_w * max_upscale) < dst.w) || |
| 1481 | ((src_deci_h * max_upscale) < dst.h) || |
| 1482 | ((dst.w * max_downscale) < src_deci_w) || |
| 1483 | ((dst.h * max_downscale) < src_deci_h)) { |
| 1484 | SDE_ERROR("too much scaling requested %ux%u -> %ux%u\n", |
| 1485 | src_deci_w, src_deci_h, dst.w, dst.h); |
| 1486 | ret = -E2BIG; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1487 | } |
| 1488 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1489 | modeset_update: |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1490 | if (!ret) |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1491 | _sde_plane_atomic_check_mode_changed(psde, state, plane->state); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1492 | exit: |
| 1493 | return ret; |
| 1494 | } |
| 1495 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1496 | /** |
| 1497 | * sde_plane_flush - final plane operations before commit flush |
| 1498 | * @plane: Pointer to drm plane structure |
| 1499 | */ |
| 1500 | void sde_plane_flush(struct drm_plane *plane) |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1501 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1502 | struct sde_plane *psde; |
| 1503 | |
| 1504 | if (!plane) |
| 1505 | return; |
| 1506 | |
| 1507 | psde = to_sde_plane(plane); |
| 1508 | |
| 1509 | /* |
| 1510 | * These updates have to be done immediately before the plane flush |
| 1511 | * timing, and may not be moved to the atomic_update/mode_set functions. |
| 1512 | */ |
| 1513 | if (psde->is_error) |
| 1514 | /* force white frame with 0% alpha pipe output on error */ |
| 1515 | _sde_plane_color_fill(plane, 0xFFFFFF, 0x0); |
| 1516 | else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) |
| 1517 | /* force 100% alpha */ |
| 1518 | _sde_plane_color_fill(plane, psde->color_fill, 0xFF); |
| 1519 | else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc) |
| 1520 | psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr); |
| 1521 | |
| 1522 | /* flag h/w flush complete */ |
| 1523 | if (plane->state) |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1524 | to_sde_plane_state(plane->state)->pending = false; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1525 | } |
| 1526 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1527 | static void sde_plane_atomic_update(struct drm_plane *plane, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1528 | struct drm_plane_state *old_state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1529 | { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1530 | struct sde_plane *sde_plane; |
| 1531 | struct drm_plane_state *state; |
| 1532 | struct sde_plane_state *pstate; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1533 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1534 | if (!plane || !plane->state) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1535 | SDE_ERROR("invalid plane/state\n"); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1536 | return; |
| 1537 | } |
| 1538 | |
| 1539 | sde_plane = to_sde_plane(plane); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1540 | sde_plane->is_error = false; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1541 | state = plane->state; |
| 1542 | pstate = to_sde_plane_state(state); |
| 1543 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1544 | SDE_DEBUG("%s: update\n", sde_plane->pipe_name); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1545 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1546 | if (!sde_plane_enabled(state)) { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1547 | pstate->pending = true; |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1548 | } else { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1549 | int ret; |
| 1550 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1551 | ret = _sde_plane_mode_set(plane, state); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1552 | /* atomic_check should have ensured that this doesn't fail */ |
| 1553 | WARN_ON(ret < 0); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1554 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1555 | } |
| 1556 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1557 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1558 | /* helper to install properties which are common to planes and crtcs */ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1559 | static void _sde_plane_install_properties(struct drm_plane *plane, |
| 1560 | u32 max_blendstages) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1561 | { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1562 | static const struct drm_prop_enum_list e_blend_op[] = { |
| 1563 | {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"}, |
| 1564 | {SDE_DRM_BLEND_OP_OPAQUE, "opaque"}, |
| 1565 | {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"}, |
| 1566 | {SDE_DRM_BLEND_OP_COVERAGE, "coverage"} |
| 1567 | }; |
| 1568 | static const struct drm_prop_enum_list e_src_config[] = { |
| 1569 | {SDE_DRM_DEINTERLACE, "deinterlace"} |
| 1570 | }; |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1571 | const struct sde_format_extended *format_list; |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1572 | struct sde_kms_info *info; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1573 | struct sde_plane *psde = to_sde_plane(plane); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1574 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1575 | if (!plane || !psde || !psde->pipe_hw || !psde->pipe_sblk) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1576 | SDE_ERROR("Invalid argument(s)\n"); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1577 | return; |
| 1578 | } |
| 1579 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1580 | msm_property_install_range(&psde->property_info, "zpos", 0x0, 0, |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1581 | max_blendstages, SDE_STAGE_BASE, PLANE_PROP_ZPOS); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1582 | |
Lloyd Atkinson | 38ad8c9 | 2016-07-06 10:39:32 -0400 | [diff] [blame] | 1583 | msm_property_install_range(&psde->property_info, "alpha", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1584 | 0x0, 0, 255, 255, PLANE_PROP_ALPHA); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1585 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1586 | /* linux default file descriptor range on each process */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1587 | msm_property_install_range(&psde->property_info, "input_fence", |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1588 | 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1589 | |
| 1590 | /* standard properties */ |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1591 | msm_property_install_rotation(&psde->property_info, |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1592 | BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y), PLANE_PROP_ROTATION); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1593 | |
Lloyd Atkinson | 38ad8c9 | 2016-07-06 10:39:32 -0400 | [diff] [blame] | 1594 | msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0, |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1595 | e_blend_op, ARRAY_SIZE(e_blend_op), PLANE_PROP_BLEND_OP); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1596 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1597 | msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1, |
| 1598 | e_src_config, ARRAY_SIZE(e_src_config), PLANE_PROP_SRC_CONFIG); |
| 1599 | |
| 1600 | if (psde->pipe_hw->ops.setup_solidfill) |
| 1601 | msm_property_install_range(&psde->property_info, "color_fill", |
| 1602 | 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL); |
| 1603 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1604 | if (psde->features & SDE_SSPP_SCALER) |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1605 | msm_property_install_blob(&psde->property_info, "scaler", 0, |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1606 | PLANE_PROP_SCALER); |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1607 | |
| 1608 | if (psde->features & BIT(SDE_SSPP_CSC)) |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1609 | msm_property_install_blob(&psde->property_info, "csc", 0, |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1610 | PLANE_PROP_CSC); |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1611 | |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1612 | info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL); |
| 1613 | if (!info) |
| 1614 | return; |
| 1615 | |
| 1616 | msm_property_install_blob(&psde->property_info, "capabilities", |
| 1617 | DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO); |
| 1618 | sde_kms_info_reset(info); |
| 1619 | |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1620 | format_list = psde->pipe_sblk->format_list; |
| 1621 | if (format_list) { |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1622 | sde_kms_info_start(info, "pixel_formats"); |
| 1623 | while (format_list->fourcc_format) { |
| 1624 | sde_kms_info_append_format(info, |
| 1625 | format_list->fourcc_format, |
| 1626 | format_list->modifier); |
| 1627 | ++format_list; |
| 1628 | } |
| 1629 | sde_kms_info_stop(info); |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1630 | } |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1631 | |
| 1632 | sde_kms_info_add_keyint(info, "max_linewidth", |
| 1633 | psde->pipe_sblk->maxlinewidth); |
| 1634 | sde_kms_info_add_keyint(info, "max_upscale", |
| 1635 | psde->pipe_sblk->maxupscale); |
| 1636 | sde_kms_info_add_keyint(info, "max_downscale", |
| 1637 | psde->pipe_sblk->maxdwnscale); |
| 1638 | sde_kms_info_add_keyint(info, "max_horizontal_deci", |
| 1639 | psde->pipe_sblk->maxhdeciexp); |
| 1640 | sde_kms_info_add_keyint(info, "max_vertical_deci", |
| 1641 | psde->pipe_sblk->maxvdeciexp); |
| 1642 | msm_property_set_blob(&psde->property_info, &psde->blob_info, |
| 1643 | info->data, info->len, PLANE_PROP_INFO); |
| 1644 | |
| 1645 | kfree(info); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1646 | } |
| 1647 | |
| 1648 | static int sde_plane_atomic_set_property(struct drm_plane *plane, |
| 1649 | struct drm_plane_state *state, struct drm_property *property, |
| 1650 | uint64_t val) |
| 1651 | { |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1652 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1653 | struct sde_plane_state *pstate; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1654 | int idx, ret = -EINVAL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1655 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1656 | DBG(""); |
| 1657 | |
| 1658 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1659 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1660 | } else if (!state) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1661 | SDE_ERROR("invalid state\n"); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1662 | } else { |
| 1663 | psde = to_sde_plane(plane); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1664 | pstate = to_sde_plane_state(state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1665 | ret = msm_property_atomic_set(&psde->property_info, |
| 1666 | pstate->property_values, pstate->property_blobs, |
| 1667 | property, val); |
| 1668 | if (!ret) { |
| 1669 | idx = msm_property_index(&psde->property_info, |
| 1670 | property); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1671 | if (idx == PLANE_PROP_INPUT_FENCE) |
| 1672 | _sde_plane_set_input_fence(plane, pstate, val); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1673 | } |
| 1674 | } |
| 1675 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1676 | return ret; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1677 | } |
| 1678 | |
| 1679 | static int sde_plane_set_property(struct drm_plane *plane, |
| 1680 | struct drm_property *property, uint64_t val) |
| 1681 | { |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1682 | DBG(""); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1683 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1684 | return sde_plane_atomic_set_property(plane, |
| 1685 | plane->state, property, val); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1686 | } |
| 1687 | |
| 1688 | static int sde_plane_atomic_get_property(struct drm_plane *plane, |
| 1689 | const struct drm_plane_state *state, |
| 1690 | struct drm_property *property, uint64_t *val) |
| 1691 | { |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1692 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1693 | struct sde_plane_state *pstate; |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1694 | int ret = -EINVAL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1695 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1696 | DBG(""); |
| 1697 | |
| 1698 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1699 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1700 | } else if (!state) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1701 | SDE_ERROR("invalid state\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1702 | } else { |
| 1703 | psde = to_sde_plane(plane); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1704 | pstate = to_sde_plane_state(state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1705 | ret = msm_property_atomic_get(&psde->property_info, |
| 1706 | pstate->property_values, pstate->property_blobs, |
| 1707 | property, val); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1708 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1709 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1710 | return ret; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1711 | } |
| 1712 | |
| 1713 | static void sde_plane_destroy(struct drm_plane *plane) |
| 1714 | { |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1715 | struct sde_plane *psde; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1716 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1717 | DBG(""); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1718 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1719 | if (plane) { |
| 1720 | psde = to_sde_plane(plane); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1721 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 1722 | _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL); |
| 1723 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1724 | debugfs_remove_recursive(psde->debugfs_root); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1725 | |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1726 | if (psde->blob_info) |
| 1727 | drm_property_unreference_blob(psde->blob_info); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1728 | msm_property_destroy(&psde->property_info); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1729 | mutex_destroy(&psde->lock); |
| 1730 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1731 | drm_plane_helper_disable(plane); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1732 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1733 | /* this will destroy the states as well */ |
| 1734 | drm_plane_cleanup(plane); |
| 1735 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1736 | if (psde->pipe_hw) |
| 1737 | sde_hw_sspp_destroy(psde->pipe_hw); |
| 1738 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1739 | kfree(psde); |
| 1740 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1741 | } |
| 1742 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1743 | static void sde_plane_destroy_state(struct drm_plane *plane, |
| 1744 | struct drm_plane_state *state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1745 | { |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1746 | struct sde_plane *psde; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1747 | struct sde_plane_state *pstate; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1748 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1749 | if (!plane || !state) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1750 | SDE_ERROR("invalid plane/state\n"); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1751 | return; |
| 1752 | } |
| 1753 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1754 | psde = to_sde_plane(plane); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1755 | pstate = to_sde_plane_state(state); |
| 1756 | |
| 1757 | DBG(""); |
| 1758 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1759 | /* remove ref count for frame buffers */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1760 | if (state->fb) |
| 1761 | drm_framebuffer_unreference(state->fb); |
| 1762 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1763 | /* remove ref count for fence */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1764 | if (pstate->input_fence) |
| 1765 | sde_sync_put(pstate->input_fence); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1766 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1767 | /* destroy value helper */ |
| 1768 | msm_property_destroy_state(&psde->property_info, pstate, |
| 1769 | pstate->property_values, pstate->property_blobs); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1770 | } |
| 1771 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1772 | static struct drm_plane_state * |
| 1773 | sde_plane_duplicate_state(struct drm_plane *plane) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1774 | { |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1775 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1776 | struct sde_plane_state *pstate; |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1777 | struct sde_plane_state *old_state; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1778 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1779 | if (!plane || !plane->state) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1780 | return NULL; |
| 1781 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1782 | old_state = to_sde_plane_state(plane->state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1783 | psde = to_sde_plane(plane); |
| 1784 | pstate = msm_property_alloc_state(&psde->property_info); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1785 | if (!pstate) |
| 1786 | return NULL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1787 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1788 | DBG(""); |
| 1789 | |
| 1790 | /* duplicate value helper */ |
| 1791 | msm_property_duplicate_state(&psde->property_info, old_state, pstate, |
| 1792 | pstate->property_values, pstate->property_blobs); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1793 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1794 | /* add ref count for frame buffer */ |
| 1795 | if (pstate->base.fb) |
| 1796 | drm_framebuffer_reference(pstate->base.fb); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1797 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1798 | /* add ref count for fence */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1799 | if (pstate->input_fence) { |
| 1800 | pstate->input_fence = 0; |
| 1801 | _sde_plane_set_input_fence(plane, pstate, pstate-> |
| 1802 | property_values[PLANE_PROP_INPUT_FENCE]); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1803 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1804 | |
Clarence Ip | 282dad6 | 2016-09-27 17:07:35 -0400 | [diff] [blame] | 1805 | pstate->dirty = 0x0; |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1806 | pstate->pending = false; |
| 1807 | |
| 1808 | return &pstate->base; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1809 | } |
| 1810 | |
| 1811 | static void sde_plane_reset(struct drm_plane *plane) |
| 1812 | { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1813 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1814 | struct sde_plane_state *pstate; |
| 1815 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1816 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1817 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1818 | return; |
| 1819 | } |
| 1820 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1821 | psde = to_sde_plane(plane); |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1822 | SDE_DEBUG("%s\n", psde->pipe_name); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1823 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1824 | /* remove previous state, if present */ |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1825 | if (plane->state) { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1826 | sde_plane_destroy_state(plane, plane->state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1827 | plane->state = 0; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1828 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1829 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1830 | pstate = msm_property_alloc_state(&psde->property_info); |
| 1831 | if (!pstate) |
| 1832 | return; |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1833 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1834 | /* reset value helper */ |
| 1835 | msm_property_reset_state(&psde->property_info, pstate, |
| 1836 | pstate->property_values, pstate->property_blobs); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1837 | |
| 1838 | pstate->base.plane = plane; |
| 1839 | |
| 1840 | plane->state = &pstate->base; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1841 | } |
| 1842 | |
| 1843 | static const struct drm_plane_funcs sde_plane_funcs = { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1844 | .update_plane = drm_atomic_helper_update_plane, |
| 1845 | .disable_plane = drm_atomic_helper_disable_plane, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1846 | .destroy = sde_plane_destroy, |
| 1847 | .set_property = sde_plane_set_property, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1848 | .atomic_set_property = sde_plane_atomic_set_property, |
| 1849 | .atomic_get_property = sde_plane_atomic_get_property, |
| 1850 | .reset = sde_plane_reset, |
| 1851 | .atomic_duplicate_state = sde_plane_duplicate_state, |
| 1852 | .atomic_destroy_state = sde_plane_destroy_state, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1853 | }; |
| 1854 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1855 | static const struct drm_plane_helper_funcs sde_plane_helper_funcs = { |
| 1856 | .prepare_fb = sde_plane_prepare_fb, |
| 1857 | .cleanup_fb = sde_plane_cleanup_fb, |
| 1858 | .atomic_check = sde_plane_atomic_check, |
| 1859 | .atomic_update = sde_plane_atomic_update, |
| 1860 | }; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1861 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1862 | enum sde_sspp sde_plane_pipe(struct drm_plane *plane) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1863 | { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1864 | struct sde_plane *sde_plane = to_sde_plane(plane); |
| 1865 | |
| 1866 | return sde_plane->pipe; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1867 | } |
| 1868 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1869 | static void _sde_plane_init_debugfs(struct sde_plane *psde, struct sde_kms *kms) |
| 1870 | { |
| 1871 | const struct sde_sspp_sub_blks *sblk = 0; |
| 1872 | const struct sde_sspp_cfg *cfg = 0; |
| 1873 | |
| 1874 | if (psde && psde->pipe_hw) |
| 1875 | cfg = psde->pipe_hw->cap; |
| 1876 | if (cfg) |
| 1877 | sblk = cfg->sblk; |
| 1878 | |
| 1879 | if (kms && sblk) { |
| 1880 | /* create overall sub-directory for the pipe */ |
| 1881 | psde->debugfs_root = |
| 1882 | debugfs_create_dir(psde->pipe_name, |
| 1883 | sde_debugfs_get_root(kms)); |
| 1884 | if (psde->debugfs_root) { |
| 1885 | /* don't error check these */ |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1886 | debugfs_create_x32("features", 0644, |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1887 | psde->debugfs_root, &psde->features); |
| 1888 | |
| 1889 | /* add register dump support */ |
| 1890 | sde_debugfs_setup_regset32(&psde->debugfs_src, |
| 1891 | sblk->src_blk.base + cfg->base, |
| 1892 | sblk->src_blk.len, |
Clarence Ip | aac9f33 | 2016-08-31 15:46:35 -0400 | [diff] [blame^] | 1893 | kms); |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1894 | sde_debugfs_create_regset32("src_blk", 0444, |
| 1895 | psde->debugfs_root, &psde->debugfs_src); |
| 1896 | |
| 1897 | sde_debugfs_setup_regset32(&psde->debugfs_scaler, |
| 1898 | sblk->scaler_blk.base + cfg->base, |
| 1899 | sblk->scaler_blk.len, |
Clarence Ip | aac9f33 | 2016-08-31 15:46:35 -0400 | [diff] [blame^] | 1900 | kms); |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1901 | sde_debugfs_create_regset32("scaler_blk", 0444, |
| 1902 | psde->debugfs_root, |
| 1903 | &psde->debugfs_scaler); |
| 1904 | |
| 1905 | sde_debugfs_setup_regset32(&psde->debugfs_csc, |
| 1906 | sblk->csc_blk.base + cfg->base, |
| 1907 | sblk->csc_blk.len, |
Clarence Ip | aac9f33 | 2016-08-31 15:46:35 -0400 | [diff] [blame^] | 1908 | kms); |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1909 | sde_debugfs_create_regset32("csc_blk", 0444, |
| 1910 | psde->debugfs_root, &psde->debugfs_csc); |
| 1911 | } |
| 1912 | } |
| 1913 | } |
| 1914 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1915 | /* initialize plane */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1916 | struct drm_plane *sde_plane_init(struct drm_device *dev, |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1917 | uint32_t pipe, bool primary_plane) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1918 | { |
| 1919 | struct drm_plane *plane = NULL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1920 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1921 | struct msm_drm_private *priv; |
| 1922 | struct sde_kms *kms; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1923 | enum drm_plane_type type; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1924 | int ret = -EINVAL, max_blendstages = 255; |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1925 | |
| 1926 | if (!dev) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1927 | SDE_ERROR("[%u]device is NULL\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1928 | goto exit; |
| 1929 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1930 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1931 | priv = dev->dev_private; |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 1932 | if (!priv) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1933 | SDE_ERROR("[%u]private data is NULL\n", pipe); |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 1934 | goto exit; |
| 1935 | } |
| 1936 | |
| 1937 | if (!priv->kms) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1938 | SDE_ERROR("[%u]invalid KMS reference\n", pipe); |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 1939 | goto exit; |
| 1940 | } |
| 1941 | kms = to_sde_kms(priv->kms); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1942 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1943 | if (!kms->catalog) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1944 | SDE_ERROR("[%u]invalid catalog reference\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1945 | goto exit; |
| 1946 | } |
| 1947 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1948 | /* create and zero local structure */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1949 | psde = kzalloc(sizeof(*psde), GFP_KERNEL); |
| 1950 | if (!psde) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1951 | SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1952 | ret = -ENOMEM; |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1953 | goto exit; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1954 | } |
| 1955 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1956 | /* cache local stuff for later */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1957 | plane = &psde->base; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1958 | psde->pipe = pipe; |
Alan Kwong | 112a84f | 2016-05-24 20:49:21 -0400 | [diff] [blame] | 1959 | psde->mmu_id = kms->mmu_id[MSM_SMMU_DOMAIN_UNSECURE]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1960 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1961 | /* initialize underlying h/w driver */ |
| 1962 | psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog); |
| 1963 | if (IS_ERR(psde->pipe_hw)) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1964 | SDE_ERROR("[%u]SSPP init failed\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1965 | ret = PTR_ERR(psde->pipe_hw); |
| 1966 | goto clean_plane; |
| 1967 | } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1968 | SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1969 | goto clean_sspp; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1970 | } |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1971 | |
| 1972 | /* cache features mask for later */ |
| 1973 | psde->features = psde->pipe_hw->cap->features; |
| 1974 | psde->pipe_sblk = psde->pipe_hw->cap->sblk; |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1975 | if (!psde->pipe_sblk) { |
| 1976 | SDE_ERROR("invalid sblk on pipe %d\n", pipe); |
| 1977 | goto clean_sspp; |
| 1978 | } |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1979 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1980 | if (kms->catalog && kms->catalog->mixer_count && kms->catalog->mixer) |
| 1981 | max_blendstages = kms->catalog->mixer[0].sblk->maxblendstages; |
| 1982 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1983 | /* add plane to DRM framework */ |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1984 | psde->nformats = sde_populate_formats(psde->pipe_sblk->format_list, |
| 1985 | psde->formats, |
| 1986 | 0, |
| 1987 | ARRAY_SIZE(psde->formats)); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1988 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1989 | if (!psde->nformats) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1990 | SDE_ERROR("[%u]no valid formats for plane\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1991 | goto clean_sspp; |
| 1992 | } |
| 1993 | |
| 1994 | if (psde->features & BIT(SDE_SSPP_CURSOR)) |
| 1995 | type = DRM_PLANE_TYPE_CURSOR; |
| 1996 | else if (primary_plane) |
| 1997 | type = DRM_PLANE_TYPE_PRIMARY; |
| 1998 | else |
| 1999 | type = DRM_PLANE_TYPE_OVERLAY; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2000 | ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs, |
| 2001 | psde->formats, psde->nformats, |
| 2002 | type); |
| 2003 | if (ret) |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2004 | goto clean_sspp; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2005 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2006 | /* success! finalize initialization */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2007 | drm_plane_helper_add(plane, &sde_plane_helper_funcs); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2008 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 2009 | msm_property_init(&psde->property_info, &plane->base, dev, |
| 2010 | priv->plane_property, psde->property_data, |
| 2011 | PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT, |
| 2012 | sizeof(struct sde_plane_state)); |
| 2013 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 2014 | _sde_plane_install_properties(plane, max_blendstages); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 2015 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2016 | /* save user friendly pipe name for later */ |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 2017 | snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id); |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2018 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 2019 | mutex_init(&psde->lock); |
| 2020 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 2021 | _sde_plane_init_debugfs(psde, kms); |
| 2022 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 2023 | DRM_INFO("[%u]successfully created %s\n", pipe, psde->pipe_name); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2024 | return plane; |
| 2025 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 2026 | clean_sspp: |
| 2027 | if (psde && psde->pipe_hw) |
| 2028 | sde_hw_sspp_destroy(psde->pipe_hw); |
| 2029 | clean_plane: |
| 2030 | kfree(psde); |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 2031 | exit: |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2032 | return ERR_PTR(ret); |
| 2033 | } |