Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1 | /* |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 2 | * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
Deepak Katragadda | 9abd794 | 2017-06-13 14:20:09 -0700 | [diff] [blame] | 14 | #define pr_fmt(fmt) "clk: %s: " fmt, __func__ |
| 15 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 16 | #include <linux/kernel.h> |
| 17 | #include <linux/bitops.h> |
| 18 | #include <linux/err.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/of.h> |
| 22 | #include <linux/of_device.h> |
| 23 | #include <linux/clk.h> |
| 24 | #include <linux/clk-provider.h> |
| 25 | #include <linux/regmap.h> |
| 26 | #include <linux/reset-controller.h> |
| 27 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 28 | #include <dt-bindings/clock/qcom,gcc-sdm845.h> |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 29 | |
| 30 | #include "common.h" |
| 31 | #include "clk-regmap.h" |
| 32 | #include "clk-pll.h" |
| 33 | #include "clk-rcg.h" |
| 34 | #include "clk-branch.h" |
| 35 | #include "reset.h" |
| 36 | #include "clk-alpha-pll.h" |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 37 | #include "vdd-level-sdm845.h" |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 38 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 39 | #define GCC_MMSS_MISC 0x09FFC |
| 40 | #define GCC_GPU_MISC 0x71028 |
| 41 | |
| 42 | #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } |
| 43 | |
| 44 | static DEFINE_VDD_REGULATORS(vdd_cx, VDD_CX_NUM, 1, vdd_corner); |
| 45 | static DEFINE_VDD_REGULATORS(vdd_cx_ao, VDD_CX_NUM, 1, vdd_corner); |
| 46 | |
| 47 | enum { |
| 48 | P_BI_TCXO, |
| 49 | P_AUD_REF_CLK, |
| 50 | P_CORE_BI_PLL_TEST_SE, |
| 51 | P_GPLL0_OUT_EVEN, |
| 52 | P_GPLL0_OUT_MAIN, |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 53 | P_GPLL1_OUT_MAIN, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 54 | P_GPLL4_OUT_MAIN, |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 55 | P_GPLL6_OUT_MAIN, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 56 | P_SLEEP_CLK, |
| 57 | }; |
| 58 | |
| 59 | static const struct parent_map gcc_parent_map_0[] = { |
| 60 | { P_BI_TCXO, 0 }, |
| 61 | { P_GPLL0_OUT_MAIN, 1 }, |
| 62 | { P_GPLL0_OUT_EVEN, 6 }, |
| 63 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 64 | }; |
| 65 | |
| 66 | static const char * const gcc_parent_names_0[] = { |
| 67 | "bi_tcxo", |
| 68 | "gpll0", |
| 69 | "gpll0_out_even", |
| 70 | "core_bi_pll_test_se", |
| 71 | }; |
| 72 | |
| 73 | static const struct parent_map gcc_parent_map_1[] = { |
| 74 | { P_BI_TCXO, 0 }, |
| 75 | { P_GPLL0_OUT_MAIN, 1 }, |
| 76 | { P_SLEEP_CLK, 5 }, |
| 77 | { P_GPLL0_OUT_EVEN, 6 }, |
| 78 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 79 | }; |
| 80 | |
| 81 | static const char * const gcc_parent_names_1[] = { |
| 82 | "bi_tcxo", |
| 83 | "gpll0", |
| 84 | "core_pi_sleep_clk", |
| 85 | "gpll0_out_even", |
| 86 | "core_bi_pll_test_se", |
| 87 | }; |
| 88 | |
| 89 | static const struct parent_map gcc_parent_map_2[] = { |
| 90 | { P_BI_TCXO, 0 }, |
| 91 | { P_SLEEP_CLK, 5 }, |
| 92 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 93 | }; |
| 94 | |
| 95 | static const char * const gcc_parent_names_2[] = { |
| 96 | "bi_tcxo", |
| 97 | "core_pi_sleep_clk", |
| 98 | "core_bi_pll_test_se", |
| 99 | }; |
| 100 | |
| 101 | static const struct parent_map gcc_parent_map_3[] = { |
| 102 | { P_BI_TCXO, 0 }, |
| 103 | { P_GPLL0_OUT_MAIN, 1 }, |
| 104 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 105 | }; |
| 106 | |
| 107 | static const char * const gcc_parent_names_3[] = { |
| 108 | "bi_tcxo", |
| 109 | "gpll0", |
| 110 | "core_bi_pll_test_se", |
| 111 | }; |
| 112 | |
| 113 | static const struct parent_map gcc_parent_map_4[] = { |
| 114 | { P_BI_TCXO, 0 }, |
| 115 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 116 | }; |
| 117 | |
| 118 | static const char * const gcc_parent_names_4[] = { |
| 119 | "bi_tcxo", |
| 120 | "core_bi_pll_test_se", |
| 121 | }; |
| 122 | |
| 123 | static const struct parent_map gcc_parent_map_5[] = { |
| 124 | { P_BI_TCXO, 0 }, |
| 125 | { P_GPLL0_OUT_MAIN, 1 }, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 126 | { P_GPLL4_OUT_MAIN, 5 }, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 127 | { P_GPLL0_OUT_EVEN, 6 }, |
| 128 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 129 | }; |
| 130 | |
| 131 | static const char * const gcc_parent_names_5[] = { |
| 132 | "bi_tcxo", |
| 133 | "gpll0", |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 134 | "gpll4", |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 135 | "gpll0_out_even", |
| 136 | "core_bi_pll_test_se", |
| 137 | }; |
| 138 | |
| 139 | static const struct parent_map gcc_parent_map_6[] = { |
| 140 | { P_BI_TCXO, 0 }, |
| 141 | { P_GPLL0_OUT_MAIN, 1 }, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 142 | { P_AUD_REF_CLK, 2 }, |
| 143 | { P_GPLL0_OUT_EVEN, 6 }, |
| 144 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 145 | }; |
| 146 | |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 147 | static const char * const gcc_parent_names_6[] = { |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 148 | "bi_tcxo", |
| 149 | "gpll0", |
| 150 | "aud_ref_clk", |
| 151 | "gpll0_out_even", |
| 152 | "core_bi_pll_test_se", |
| 153 | }; |
| 154 | |
Deepak Katragadda | 3760e05 | 2017-04-20 13:41:32 -0700 | [diff] [blame] | 155 | static const char * const gcc_parent_names_7[] = { |
| 156 | "bi_tcxo_ao", |
| 157 | "gpll0", |
| 158 | "gpll0_out_even", |
| 159 | "core_bi_pll_test_se", |
| 160 | }; |
| 161 | |
Deepak Katragadda | 050c202 | 2017-05-05 09:50:43 -0700 | [diff] [blame] | 162 | static const char * const gcc_parent_names_8[] = { |
| 163 | "bi_tcxo_ao", |
| 164 | "gpll0", |
| 165 | "core_bi_pll_test_se", |
| 166 | }; |
| 167 | |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 168 | static const struct parent_map gcc_parent_map_9[] = { |
| 169 | { P_BI_TCXO, 0 }, |
| 170 | { P_GPLL0_OUT_MAIN, 1 }, |
| 171 | { P_GPLL1_OUT_MAIN, 4 }, |
| 172 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 173 | }; |
| 174 | |
| 175 | static const char * const gcc_parent_names_9[] = { |
| 176 | "bi_tcxo", |
| 177 | "gpll0", |
| 178 | "gpll1", |
| 179 | "core_bi_pll_test_se", |
| 180 | }; |
| 181 | |
Deepak Katragadda | f56802e | 2017-07-14 13:39:03 -0700 | [diff] [blame] | 182 | static const struct parent_map gcc_parent_map_10[] = { |
| 183 | { P_BI_TCXO, 0 }, |
| 184 | { P_GPLL0_OUT_MAIN, 1 }, |
| 185 | { P_GPLL4_OUT_MAIN, 5 }, |
| 186 | { P_GPLL0_OUT_EVEN, 6 }, |
| 187 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 188 | }; |
| 189 | |
| 190 | static const char * const gcc_parent_names_10[] = { |
| 191 | "bi_tcxo", |
| 192 | "gpll0", |
| 193 | "gpll4", |
| 194 | "gpll0_out_even", |
| 195 | "core_bi_pll_test_se", |
| 196 | }; |
| 197 | |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 198 | static const struct parent_map gcc_parent_map_7[] = { |
| 199 | { P_BI_TCXO, 0 }, |
| 200 | { P_GPLL0_OUT_MAIN, 1 }, |
| 201 | { P_GPLL6_OUT_MAIN, 2 }, |
| 202 | { P_GPLL0_OUT_EVEN, 6 }, |
| 203 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 204 | }; |
| 205 | |
| 206 | static const char * const gcc_parent_names_11[] = { |
| 207 | "bi_tcxo", |
| 208 | "gpll0", |
| 209 | "gpll6", |
| 210 | "gpll0_out_even", |
| 211 | "core_bi_pll_test_se", |
| 212 | }; |
| 213 | |
Deepak Katragadda | d075ba3 | 2017-04-06 13:45:47 -0700 | [diff] [blame] | 214 | static struct clk_dummy measure_only_snoc_clk = { |
| 215 | .rrate = 1000, |
| 216 | .hw.init = &(struct clk_init_data){ |
| 217 | .name = "measure_only_snoc_clk", |
| 218 | .ops = &clk_dummy_ops, |
| 219 | }, |
| 220 | }; |
| 221 | |
| 222 | static struct clk_dummy measure_only_cnoc_clk = { |
| 223 | .rrate = 1000, |
| 224 | .hw.init = &(struct clk_init_data){ |
| 225 | .name = "measure_only_cnoc_clk", |
| 226 | .ops = &clk_dummy_ops, |
| 227 | }, |
| 228 | }; |
| 229 | |
| 230 | static struct clk_dummy measure_only_bimc_clk = { |
| 231 | .rrate = 1000, |
| 232 | .hw.init = &(struct clk_init_data){ |
| 233 | .name = "measure_only_bimc_clk", |
| 234 | .ops = &clk_dummy_ops, |
| 235 | }, |
| 236 | }; |
| 237 | |
| 238 | static struct clk_dummy measure_only_ipa_2x_clk = { |
| 239 | .rrate = 1000, |
| 240 | .hw.init = &(struct clk_init_data){ |
| 241 | .name = "measure_only_ipa_2x_clk", |
| 242 | .ops = &clk_dummy_ops, |
| 243 | }, |
| 244 | }; |
| 245 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 246 | static struct pll_vco fabia_vco[] = { |
Deepak Katragadda | 47e084f | 2017-06-06 15:08:26 -0700 | [diff] [blame] | 247 | { 249600000, 2000000000, 0 }, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 248 | { 125000000, 1000000000, 1 }, |
| 249 | }; |
| 250 | |
| 251 | static struct clk_alpha_pll gpll0 = { |
| 252 | .offset = 0x0, |
| 253 | .vco_table = fabia_vco, |
| 254 | .num_vco = ARRAY_SIZE(fabia_vco), |
| 255 | .type = FABIA_PLL, |
| 256 | .clkr = { |
| 257 | .enable_reg = 0x52000, |
| 258 | .enable_mask = BIT(0), |
| 259 | .hw.init = &(struct clk_init_data){ |
| 260 | .name = "gpll0", |
| 261 | .parent_names = (const char *[]){ "bi_tcxo" }, |
| 262 | .num_parents = 1, |
| 263 | .ops = &clk_fabia_fixed_pll_ops, |
Deepak Katragadda | d04d2ca | 2017-03-30 11:03:20 -0700 | [diff] [blame] | 264 | VDD_CX_FMAX_MAP4( |
| 265 | MIN, 615000000, |
| 266 | LOW, 1066000000, |
| 267 | LOW_L1, 1600000000, |
| 268 | NOMINAL, 2000000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 269 | }, |
| 270 | }, |
| 271 | }; |
| 272 | |
Deepak Katragadda | f56802e | 2017-07-14 13:39:03 -0700 | [diff] [blame] | 273 | static struct clk_alpha_pll gpll4 = { |
| 274 | .offset = 0x76000, |
| 275 | .vco_table = fabia_vco, |
| 276 | .num_vco = ARRAY_SIZE(fabia_vco), |
| 277 | .type = FABIA_PLL, |
| 278 | .clkr = { |
| 279 | .enable_reg = 0x52000, |
| 280 | .enable_mask = BIT(4), |
| 281 | .hw.init = &(struct clk_init_data){ |
| 282 | .name = "gpll4", |
| 283 | .parent_names = (const char *[]){ "bi_tcxo" }, |
| 284 | .num_parents = 1, |
| 285 | .ops = &clk_fabia_fixed_pll_ops, |
| 286 | VDD_CX_FMAX_MAP4( |
| 287 | MIN, 615000000, |
| 288 | LOW, 1066000000, |
| 289 | LOW_L1, 1600000000, |
| 290 | NOMINAL, 2000000000), |
| 291 | }, |
| 292 | }, |
| 293 | }; |
| 294 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 295 | static const struct clk_div_table post_div_table_fabia_even[] = { |
| 296 | { 0x0, 1 }, |
| 297 | { 0x1, 2 }, |
| 298 | { 0x3, 4 }, |
| 299 | { 0x7, 8 }, |
Stephen Boyd | 9e3b0a3 | 2017-03-07 05:30:31 -0800 | [diff] [blame] | 300 | { } |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 301 | }; |
| 302 | |
| 303 | static struct clk_alpha_pll_postdiv gpll0_out_even = { |
| 304 | .offset = 0x0, |
| 305 | .post_div_shift = 8, |
| 306 | .post_div_table = post_div_table_fabia_even, |
| 307 | .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), |
| 308 | .width = 4, |
| 309 | .clkr.hw.init = &(struct clk_init_data){ |
| 310 | .name = "gpll0_out_even", |
| 311 | .parent_names = (const char *[]){ "gpll0" }, |
| 312 | .num_parents = 1, |
| 313 | .ops = &clk_generic_pll_postdiv_ops, |
| 314 | }, |
| 315 | }; |
| 316 | |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 317 | static struct clk_alpha_pll gpll6 = { |
| 318 | .offset = 0x13000, |
| 319 | .vco_table = fabia_vco, |
| 320 | .num_vco = ARRAY_SIZE(fabia_vco), |
| 321 | .type = FABIA_PLL, |
| 322 | .clkr = { |
| 323 | .enable_reg = 0x52000, |
| 324 | .enable_mask = BIT(6), |
| 325 | .hw.init = &(struct clk_init_data){ |
| 326 | .name = "gpll6", |
| 327 | .parent_names = (const char *[]){ "bi_tcxo" }, |
| 328 | .num_parents = 1, |
| 329 | .ops = &clk_fabia_fixed_pll_ops, |
| 330 | VDD_CX_FMAX_MAP4( |
| 331 | MIN, 615000000, |
| 332 | LOW, 1066000000, |
| 333 | LOW_L1, 1600000000, |
| 334 | NOMINAL, 2000000000), |
| 335 | }, |
| 336 | }, |
| 337 | }; |
| 338 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 339 | static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { |
| 340 | F(19200000, P_BI_TCXO, 1, 0, 0), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 341 | { } |
| 342 | }; |
| 343 | |
| 344 | static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { |
| 345 | .cmd_rcgr = 0x48014, |
| 346 | .mnd_width = 0, |
| 347 | .hid_width = 5, |
| 348 | .parent_map = gcc_parent_map_0, |
| 349 | .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, |
| 350 | .clkr.hw.init = &(struct clk_init_data){ |
| 351 | .name = "gcc_cpuss_ahb_clk_src", |
Deepak Katragadda | 3760e05 | 2017-04-20 13:41:32 -0700 | [diff] [blame] | 352 | .parent_names = gcc_parent_names_7, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 353 | .num_parents = 4, |
| 354 | .flags = CLK_SET_RATE_PARENT, |
| 355 | .ops = &clk_rcg2_ops, |
| 356 | VDD_CX_FMAX_MAP3_AO( |
| 357 | MIN, 19200000, |
| 358 | LOW, 50000000, |
| 359 | NOMINAL, 100000000), |
| 360 | }, |
| 361 | }; |
| 362 | |
| 363 | static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = { |
| 364 | F(19200000, P_BI_TCXO, 1, 0, 0), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 365 | { } |
| 366 | }; |
| 367 | |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 368 | static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src_sdm670[] = { |
| 369 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 370 | F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), |
| 371 | { } |
| 372 | }; |
| 373 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 374 | static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = { |
| 375 | .cmd_rcgr = 0x4815c, |
| 376 | .mnd_width = 0, |
| 377 | .hid_width = 5, |
| 378 | .parent_map = gcc_parent_map_3, |
| 379 | .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, |
| 380 | .clkr.hw.init = &(struct clk_init_data){ |
| 381 | .name = "gcc_cpuss_rbcpr_clk_src", |
Deepak Katragadda | 050c202 | 2017-05-05 09:50:43 -0700 | [diff] [blame] | 382 | .parent_names = gcc_parent_names_8, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 383 | .num_parents = 3, |
| 384 | .flags = CLK_SET_RATE_PARENT, |
| 385 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 050c202 | 2017-05-05 09:50:43 -0700 | [diff] [blame] | 386 | VDD_CX_FMAX_MAP1_AO( |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 387 | MIN, 19200000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 388 | }, |
| 389 | }; |
| 390 | |
| 391 | static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { |
Deepak Katragadda | bae7106 | 2017-05-22 14:37:11 -0700 | [diff] [blame] | 392 | F(19200000, P_BI_TCXO, 1, 0, 0), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 393 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), |
| 394 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), |
| 395 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 396 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), |
| 397 | { } |
| 398 | }; |
| 399 | |
| 400 | static struct clk_rcg2 gcc_gp1_clk_src = { |
| 401 | .cmd_rcgr = 0x64004, |
| 402 | .mnd_width = 8, |
| 403 | .hid_width = 5, |
| 404 | .parent_map = gcc_parent_map_1, |
| 405 | .freq_tbl = ftbl_gcc_gp1_clk_src, |
| 406 | .clkr.hw.init = &(struct clk_init_data){ |
| 407 | .name = "gcc_gp1_clk_src", |
| 408 | .parent_names = gcc_parent_names_1, |
| 409 | .num_parents = 5, |
| 410 | .flags = CLK_SET_RATE_PARENT, |
| 411 | .ops = &clk_rcg2_ops, |
| 412 | VDD_CX_FMAX_MAP4( |
| 413 | MIN, 19200000, |
| 414 | LOWER, 50000000, |
| 415 | LOW, 100000000, |
| 416 | NOMINAL, 200000000), |
| 417 | }, |
| 418 | }; |
| 419 | |
| 420 | static struct clk_rcg2 gcc_gp2_clk_src = { |
| 421 | .cmd_rcgr = 0x65004, |
| 422 | .mnd_width = 8, |
| 423 | .hid_width = 5, |
| 424 | .parent_map = gcc_parent_map_1, |
| 425 | .freq_tbl = ftbl_gcc_gp1_clk_src, |
| 426 | .clkr.hw.init = &(struct clk_init_data){ |
| 427 | .name = "gcc_gp2_clk_src", |
| 428 | .parent_names = gcc_parent_names_1, |
| 429 | .num_parents = 5, |
| 430 | .flags = CLK_SET_RATE_PARENT, |
| 431 | .ops = &clk_rcg2_ops, |
| 432 | VDD_CX_FMAX_MAP4( |
| 433 | MIN, 19200000, |
| 434 | LOWER, 50000000, |
| 435 | LOW, 100000000, |
| 436 | NOMINAL, 200000000), |
| 437 | }, |
| 438 | }; |
| 439 | |
| 440 | static struct clk_rcg2 gcc_gp3_clk_src = { |
| 441 | .cmd_rcgr = 0x66004, |
| 442 | .mnd_width = 8, |
| 443 | .hid_width = 5, |
| 444 | .parent_map = gcc_parent_map_1, |
| 445 | .freq_tbl = ftbl_gcc_gp1_clk_src, |
| 446 | .clkr.hw.init = &(struct clk_init_data){ |
| 447 | .name = "gcc_gp3_clk_src", |
| 448 | .parent_names = gcc_parent_names_1, |
| 449 | .num_parents = 5, |
| 450 | .flags = CLK_SET_RATE_PARENT, |
| 451 | .ops = &clk_rcg2_ops, |
| 452 | VDD_CX_FMAX_MAP4( |
| 453 | MIN, 19200000, |
| 454 | LOWER, 50000000, |
| 455 | LOW, 100000000, |
| 456 | NOMINAL, 200000000), |
| 457 | }, |
| 458 | }; |
| 459 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 460 | static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { |
| 461 | F(9600000, P_BI_TCXO, 2, 0, 0), |
| 462 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 463 | { } |
| 464 | }; |
| 465 | |
| 466 | static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { |
| 467 | .cmd_rcgr = 0x6b028, |
| 468 | .mnd_width = 16, |
| 469 | .hid_width = 5, |
| 470 | .parent_map = gcc_parent_map_2, |
| 471 | .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, |
| 472 | .clkr.hw.init = &(struct clk_init_data){ |
| 473 | .name = "gcc_pcie_0_aux_clk_src", |
| 474 | .parent_names = gcc_parent_names_2, |
| 475 | .num_parents = 3, |
| 476 | .flags = CLK_SET_RATE_PARENT, |
| 477 | .ops = &clk_rcg2_ops, |
| 478 | VDD_CX_FMAX_MAP2( |
| 479 | MIN, 9600000, |
| 480 | LOW, 19200000), |
| 481 | }, |
| 482 | }; |
| 483 | |
| 484 | static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { |
| 485 | .cmd_rcgr = 0x8d028, |
| 486 | .mnd_width = 16, |
| 487 | .hid_width = 5, |
| 488 | .parent_map = gcc_parent_map_2, |
| 489 | .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, |
| 490 | .clkr.hw.init = &(struct clk_init_data){ |
| 491 | .name = "gcc_pcie_1_aux_clk_src", |
| 492 | .parent_names = gcc_parent_names_2, |
| 493 | .num_parents = 3, |
| 494 | .flags = CLK_SET_RATE_PARENT, |
| 495 | .ops = &clk_rcg2_ops, |
| 496 | VDD_CX_FMAX_MAP2( |
| 497 | MIN, 9600000, |
| 498 | LOW, 19200000), |
| 499 | }, |
| 500 | }; |
| 501 | |
| 502 | static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { |
| 503 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 504 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 505 | { } |
| 506 | }; |
| 507 | |
| 508 | static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { |
| 509 | .cmd_rcgr = 0x6f014, |
| 510 | .mnd_width = 0, |
| 511 | .hid_width = 5, |
| 512 | .parent_map = gcc_parent_map_0, |
| 513 | .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, |
| 514 | .clkr.hw.init = &(struct clk_init_data){ |
| 515 | .name = "gcc_pcie_phy_refgen_clk_src", |
| 516 | .parent_names = gcc_parent_names_0, |
| 517 | .num_parents = 4, |
| 518 | .flags = CLK_SET_RATE_PARENT, |
| 519 | .ops = &clk_rcg2_ops, |
| 520 | VDD_CX_FMAX_MAP2( |
| 521 | MIN, 19200000, |
| 522 | LOW, 100000000), |
| 523 | }, |
| 524 | }; |
| 525 | |
| 526 | static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { |
Deepak Katragadda | bae7106 | 2017-05-22 14:37:11 -0700 | [diff] [blame] | 527 | F(9600000, P_BI_TCXO, 2, 0, 0), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 528 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 529 | F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), |
| 530 | { } |
| 531 | }; |
| 532 | |
| 533 | static struct clk_rcg2 gcc_pdm2_clk_src = { |
| 534 | .cmd_rcgr = 0x33010, |
| 535 | .mnd_width = 0, |
| 536 | .hid_width = 5, |
| 537 | .parent_map = gcc_parent_map_0, |
| 538 | .freq_tbl = ftbl_gcc_pdm2_clk_src, |
| 539 | .clkr.hw.init = &(struct clk_init_data){ |
| 540 | .name = "gcc_pdm2_clk_src", |
| 541 | .parent_names = gcc_parent_names_0, |
| 542 | .num_parents = 4, |
| 543 | .flags = CLK_SET_RATE_PARENT, |
| 544 | .ops = &clk_rcg2_ops, |
| 545 | VDD_CX_FMAX_MAP3( |
| 546 | MIN, 9600000, |
| 547 | LOWER, 19200000, |
| 548 | LOW, 60000000), |
| 549 | }, |
| 550 | }; |
| 551 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 552 | static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 553 | F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), |
| 554 | F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 555 | F(19200000, P_BI_TCXO, 1, 0, 0), |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 556 | F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), |
| 557 | F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), |
Deepak Katragadda | f56802e | 2017-07-14 13:39:03 -0700 | [diff] [blame] | 558 | F(38400000, P_GPLL0_OUT_EVEN, 1, 16, 125), |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 559 | F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), |
| 560 | F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), |
| 561 | F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), |
| 562 | F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), |
| 563 | F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 564 | { } |
| 565 | }; |
| 566 | |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 567 | static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2[] = { |
| 568 | F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), |
| 569 | F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), |
| 570 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 571 | F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), |
| 572 | F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), |
| 573 | F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), |
| 574 | F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), |
| 575 | F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), |
| 576 | F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), |
| 577 | F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), |
| 578 | F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), |
| 579 | F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), |
| 580 | F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), |
| 581 | F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), |
| 582 | F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75), |
| 583 | { } |
| 584 | }; |
| 585 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 586 | static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { |
| 587 | .cmd_rcgr = 0x17034, |
| 588 | .mnd_width = 16, |
| 589 | .hid_width = 5, |
| 590 | .parent_map = gcc_parent_map_0, |
| 591 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 592 | .enable_safe_config = true, |
| 593 | .clkr.hw.init = &(struct clk_init_data){ |
| 594 | .name = "gcc_qupv3_wrap0_s0_clk_src", |
| 595 | .parent_names = gcc_parent_names_0, |
| 596 | .num_parents = 4, |
| 597 | .flags = CLK_SET_RATE_PARENT, |
| 598 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 599 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 600 | MIN, 19200000, |
| 601 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 602 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 603 | }, |
| 604 | }; |
| 605 | |
| 606 | static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { |
| 607 | .cmd_rcgr = 0x17164, |
| 608 | .mnd_width = 16, |
| 609 | .hid_width = 5, |
| 610 | .parent_map = gcc_parent_map_0, |
| 611 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 612 | .enable_safe_config = true, |
| 613 | .clkr.hw.init = &(struct clk_init_data){ |
| 614 | .name = "gcc_qupv3_wrap0_s1_clk_src", |
| 615 | .parent_names = gcc_parent_names_0, |
| 616 | .num_parents = 4, |
| 617 | .flags = CLK_SET_RATE_PARENT, |
| 618 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 619 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 620 | MIN, 19200000, |
| 621 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 622 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 623 | }, |
| 624 | }; |
| 625 | |
| 626 | static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { |
| 627 | .cmd_rcgr = 0x17294, |
| 628 | .mnd_width = 16, |
| 629 | .hid_width = 5, |
| 630 | .parent_map = gcc_parent_map_0, |
| 631 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 632 | .enable_safe_config = true, |
| 633 | .clkr.hw.init = &(struct clk_init_data){ |
| 634 | .name = "gcc_qupv3_wrap0_s2_clk_src", |
| 635 | .parent_names = gcc_parent_names_0, |
| 636 | .num_parents = 4, |
| 637 | .flags = CLK_SET_RATE_PARENT, |
| 638 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 639 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 640 | MIN, 19200000, |
| 641 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 642 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 643 | }, |
| 644 | }; |
| 645 | |
| 646 | static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { |
| 647 | .cmd_rcgr = 0x173c4, |
| 648 | .mnd_width = 16, |
| 649 | .hid_width = 5, |
| 650 | .parent_map = gcc_parent_map_0, |
| 651 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 652 | .enable_safe_config = true, |
| 653 | .clkr.hw.init = &(struct clk_init_data){ |
| 654 | .name = "gcc_qupv3_wrap0_s3_clk_src", |
| 655 | .parent_names = gcc_parent_names_0, |
| 656 | .num_parents = 4, |
| 657 | .flags = CLK_SET_RATE_PARENT, |
| 658 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 659 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 660 | MIN, 19200000, |
| 661 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 662 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 663 | }, |
| 664 | }; |
| 665 | |
| 666 | static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { |
| 667 | .cmd_rcgr = 0x174f4, |
| 668 | .mnd_width = 16, |
| 669 | .hid_width = 5, |
| 670 | .parent_map = gcc_parent_map_0, |
| 671 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 672 | .enable_safe_config = true, |
| 673 | .clkr.hw.init = &(struct clk_init_data){ |
| 674 | .name = "gcc_qupv3_wrap0_s4_clk_src", |
| 675 | .parent_names = gcc_parent_names_0, |
| 676 | .num_parents = 4, |
| 677 | .flags = CLK_SET_RATE_PARENT, |
| 678 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 679 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 680 | MIN, 19200000, |
| 681 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 682 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 683 | }, |
| 684 | }; |
| 685 | |
| 686 | static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { |
| 687 | .cmd_rcgr = 0x17624, |
| 688 | .mnd_width = 16, |
| 689 | .hid_width = 5, |
| 690 | .parent_map = gcc_parent_map_0, |
| 691 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 692 | .enable_safe_config = true, |
| 693 | .clkr.hw.init = &(struct clk_init_data){ |
| 694 | .name = "gcc_qupv3_wrap0_s5_clk_src", |
| 695 | .parent_names = gcc_parent_names_0, |
| 696 | .num_parents = 4, |
| 697 | .flags = CLK_SET_RATE_PARENT, |
| 698 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 699 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 700 | MIN, 19200000, |
| 701 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 702 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 703 | }, |
| 704 | }; |
| 705 | |
| 706 | static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { |
| 707 | .cmd_rcgr = 0x17754, |
| 708 | .mnd_width = 16, |
| 709 | .hid_width = 5, |
| 710 | .parent_map = gcc_parent_map_0, |
| 711 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 712 | .enable_safe_config = true, |
| 713 | .clkr.hw.init = &(struct clk_init_data){ |
| 714 | .name = "gcc_qupv3_wrap0_s6_clk_src", |
| 715 | .parent_names = gcc_parent_names_0, |
| 716 | .num_parents = 4, |
| 717 | .flags = CLK_SET_RATE_PARENT, |
| 718 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 719 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 720 | MIN, 19200000, |
| 721 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 722 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 723 | }, |
| 724 | }; |
| 725 | |
| 726 | static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { |
| 727 | .cmd_rcgr = 0x17884, |
| 728 | .mnd_width = 16, |
| 729 | .hid_width = 5, |
| 730 | .parent_map = gcc_parent_map_0, |
| 731 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 732 | .enable_safe_config = true, |
| 733 | .clkr.hw.init = &(struct clk_init_data){ |
| 734 | .name = "gcc_qupv3_wrap0_s7_clk_src", |
| 735 | .parent_names = gcc_parent_names_0, |
| 736 | .num_parents = 4, |
| 737 | .flags = CLK_SET_RATE_PARENT, |
| 738 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 739 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 740 | MIN, 19200000, |
| 741 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 742 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 743 | }, |
| 744 | }; |
| 745 | |
| 746 | static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { |
| 747 | .cmd_rcgr = 0x18018, |
| 748 | .mnd_width = 16, |
| 749 | .hid_width = 5, |
| 750 | .parent_map = gcc_parent_map_0, |
| 751 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 752 | .enable_safe_config = true, |
| 753 | .clkr.hw.init = &(struct clk_init_data){ |
| 754 | .name = "gcc_qupv3_wrap1_s0_clk_src", |
| 755 | .parent_names = gcc_parent_names_0, |
| 756 | .num_parents = 4, |
| 757 | .flags = CLK_SET_RATE_PARENT, |
| 758 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 759 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 760 | MIN, 19200000, |
| 761 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 762 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 763 | }, |
| 764 | }; |
| 765 | |
| 766 | static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { |
| 767 | .cmd_rcgr = 0x18148, |
| 768 | .mnd_width = 16, |
| 769 | .hid_width = 5, |
| 770 | .parent_map = gcc_parent_map_0, |
| 771 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 772 | .enable_safe_config = true, |
| 773 | .clkr.hw.init = &(struct clk_init_data){ |
| 774 | .name = "gcc_qupv3_wrap1_s1_clk_src", |
| 775 | .parent_names = gcc_parent_names_0, |
| 776 | .num_parents = 4, |
| 777 | .flags = CLK_SET_RATE_PARENT, |
| 778 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 779 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 780 | MIN, 19200000, |
| 781 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 782 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 783 | }, |
| 784 | }; |
| 785 | |
| 786 | static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { |
| 787 | .cmd_rcgr = 0x18278, |
| 788 | .mnd_width = 16, |
| 789 | .hid_width = 5, |
| 790 | .parent_map = gcc_parent_map_0, |
| 791 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 792 | .enable_safe_config = true, |
| 793 | .clkr.hw.init = &(struct clk_init_data){ |
| 794 | .name = "gcc_qupv3_wrap1_s2_clk_src", |
| 795 | .parent_names = gcc_parent_names_0, |
| 796 | .num_parents = 4, |
| 797 | .flags = CLK_SET_RATE_PARENT, |
| 798 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 799 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 800 | MIN, 19200000, |
| 801 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 802 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 803 | }, |
| 804 | }; |
| 805 | |
| 806 | static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { |
| 807 | .cmd_rcgr = 0x183a8, |
| 808 | .mnd_width = 16, |
| 809 | .hid_width = 5, |
| 810 | .parent_map = gcc_parent_map_0, |
| 811 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 812 | .enable_safe_config = true, |
| 813 | .clkr.hw.init = &(struct clk_init_data){ |
| 814 | .name = "gcc_qupv3_wrap1_s3_clk_src", |
| 815 | .parent_names = gcc_parent_names_0, |
| 816 | .num_parents = 4, |
| 817 | .flags = CLK_SET_RATE_PARENT, |
| 818 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 819 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 820 | MIN, 19200000, |
| 821 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 822 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 823 | }, |
| 824 | }; |
| 825 | |
| 826 | static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { |
| 827 | .cmd_rcgr = 0x184d8, |
| 828 | .mnd_width = 16, |
| 829 | .hid_width = 5, |
| 830 | .parent_map = gcc_parent_map_0, |
| 831 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 832 | .enable_safe_config = true, |
| 833 | .clkr.hw.init = &(struct clk_init_data){ |
| 834 | .name = "gcc_qupv3_wrap1_s4_clk_src", |
| 835 | .parent_names = gcc_parent_names_0, |
| 836 | .num_parents = 4, |
| 837 | .flags = CLK_SET_RATE_PARENT, |
| 838 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 839 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 840 | MIN, 19200000, |
| 841 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 842 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 843 | }, |
| 844 | }; |
| 845 | |
| 846 | static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { |
| 847 | .cmd_rcgr = 0x18608, |
| 848 | .mnd_width = 16, |
| 849 | .hid_width = 5, |
| 850 | .parent_map = gcc_parent_map_0, |
| 851 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 852 | .enable_safe_config = true, |
| 853 | .clkr.hw.init = &(struct clk_init_data){ |
| 854 | .name = "gcc_qupv3_wrap1_s5_clk_src", |
| 855 | .parent_names = gcc_parent_names_0, |
| 856 | .num_parents = 4, |
| 857 | .flags = CLK_SET_RATE_PARENT, |
| 858 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 859 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 860 | MIN, 19200000, |
| 861 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 862 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 863 | }, |
| 864 | }; |
| 865 | |
| 866 | static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { |
| 867 | .cmd_rcgr = 0x18738, |
| 868 | .mnd_width = 16, |
| 869 | .hid_width = 5, |
| 870 | .parent_map = gcc_parent_map_0, |
| 871 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 872 | .enable_safe_config = true, |
| 873 | .clkr.hw.init = &(struct clk_init_data){ |
| 874 | .name = "gcc_qupv3_wrap1_s6_clk_src", |
| 875 | .parent_names = gcc_parent_names_0, |
| 876 | .num_parents = 4, |
| 877 | .flags = CLK_SET_RATE_PARENT, |
| 878 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 879 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 880 | MIN, 19200000, |
| 881 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 882 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 883 | }, |
| 884 | }; |
| 885 | |
| 886 | static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { |
| 887 | .cmd_rcgr = 0x18868, |
| 888 | .mnd_width = 16, |
| 889 | .hid_width = 5, |
| 890 | .parent_map = gcc_parent_map_0, |
| 891 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 892 | .enable_safe_config = true, |
| 893 | .clkr.hw.init = &(struct clk_init_data){ |
| 894 | .name = "gcc_qupv3_wrap1_s7_clk_src", |
| 895 | .parent_names = gcc_parent_names_0, |
| 896 | .num_parents = 4, |
| 897 | .flags = CLK_SET_RATE_PARENT, |
| 898 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 899 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 900 | MIN, 19200000, |
| 901 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 902 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 903 | }, |
| 904 | }; |
| 905 | |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 906 | static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { |
| 907 | F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), |
| 908 | F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), |
| 909 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), |
| 910 | F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), |
| 911 | { } |
| 912 | }; |
| 913 | |
| 914 | static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { |
| 915 | .cmd_rcgr = 0x26010, |
| 916 | .mnd_width = 8, |
| 917 | .hid_width = 5, |
| 918 | .parent_map = gcc_parent_map_0, |
| 919 | .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, |
| 920 | .enable_safe_config = true, |
| 921 | .clkr.hw.init = &(struct clk_init_data){ |
| 922 | .name = "gcc_sdcc1_ice_core_clk_src", |
| 923 | .parent_names = gcc_parent_names_0, |
| 924 | .num_parents = 4, |
| 925 | .flags = CLK_SET_RATE_PARENT, |
| 926 | .ops = &clk_rcg2_ops, |
| 927 | VDD_CX_FMAX_MAP3( |
| 928 | MIN, 75000000, |
| 929 | LOW, 150000000, |
| 930 | NOMINAL, 300000000), |
| 931 | }, |
| 932 | }; |
| 933 | |
| 934 | static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { |
| 935 | F(144000, P_BI_TCXO, 16, 3, 25), |
| 936 | F(400000, P_BI_TCXO, 12, 1, 4), |
| 937 | F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), |
| 938 | F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), |
| 939 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), |
| 940 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 941 | F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), |
| 942 | F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), |
| 943 | { } |
| 944 | }; |
| 945 | |
| 946 | static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { |
| 947 | .cmd_rcgr = 0x26028, |
| 948 | .mnd_width = 8, |
| 949 | .hid_width = 5, |
| 950 | .parent_map = gcc_parent_map_7, |
| 951 | .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, |
| 952 | .enable_safe_config = true, |
| 953 | .clkr.hw.init = &(struct clk_init_data){ |
| 954 | .name = "gcc_sdcc1_apps_clk_src", |
| 955 | .parent_names = gcc_parent_names_11, |
| 956 | .num_parents = 5, |
| 957 | .flags = CLK_SET_RATE_PARENT, |
| 958 | .ops = &clk_rcg2_ops, |
| 959 | VDD_CX_FMAX_MAP4( |
| 960 | MIN, 19200000, |
| 961 | LOWER, 50000000, |
| 962 | LOW, 100000000, |
| 963 | NOMINAL, 384000000), |
| 964 | }, |
| 965 | }; |
| 966 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 967 | static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { |
Deepak Katragadda | 5d08d67 | 2017-04-18 09:38:30 -0700 | [diff] [blame] | 968 | F(400000, P_BI_TCXO, 12, 1, 4), |
Deepak Katragadda | bae7106 | 2017-05-22 14:37:11 -0700 | [diff] [blame] | 969 | F(9600000, P_BI_TCXO, 2, 0, 0), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 970 | F(19200000, P_BI_TCXO, 1, 0, 0), |
Deepak Katragadda | 47e084f | 2017-06-06 15:08:26 -0700 | [diff] [blame] | 971 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), |
| 972 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 973 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
Deepak Katragadda | f56802e | 2017-07-14 13:39:03 -0700 | [diff] [blame] | 974 | F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0), |
| 975 | { } |
| 976 | }; |
| 977 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 978 | static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { |
| 979 | .cmd_rcgr = 0x1400c, |
| 980 | .mnd_width = 8, |
| 981 | .hid_width = 5, |
Deepak Katragadda | f56802e | 2017-07-14 13:39:03 -0700 | [diff] [blame] | 982 | .parent_map = gcc_parent_map_10, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 983 | .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, |
| 984 | .enable_safe_config = true, |
| 985 | .clkr.hw.init = &(struct clk_init_data){ |
| 986 | .name = "gcc_sdcc2_apps_clk_src", |
Deepak Katragadda | f56802e | 2017-07-14 13:39:03 -0700 | [diff] [blame] | 987 | .parent_names = gcc_parent_names_10, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 988 | .num_parents = 5, |
| 989 | .flags = CLK_SET_RATE_PARENT, |
| 990 | .ops = &clk_rcg2_ops, |
| 991 | VDD_CX_FMAX_MAP4( |
| 992 | MIN, 9600000, |
| 993 | LOWER, 19200000, |
| 994 | LOW, 100000000, |
Deepak Katragadda | f56802e | 2017-07-14 13:39:03 -0700 | [diff] [blame] | 995 | LOW_L1, 201500000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 996 | }, |
| 997 | }; |
| 998 | |
| 999 | static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { |
Deepak Katragadda | 5d08d67 | 2017-04-18 09:38:30 -0700 | [diff] [blame] | 1000 | F(400000, P_BI_TCXO, 12, 1, 4), |
Deepak Katragadda | bae7106 | 2017-05-22 14:37:11 -0700 | [diff] [blame] | 1001 | F(9600000, P_BI_TCXO, 2, 0, 0), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1002 | F(19200000, P_BI_TCXO, 1, 0, 0), |
Deepak Katragadda | 5d08d67 | 2017-04-18 09:38:30 -0700 | [diff] [blame] | 1003 | F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1004 | F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), |
| 1005 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 1006 | { } |
| 1007 | }; |
| 1008 | |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 1009 | static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src_sdm670[] = { |
| 1010 | F(400000, P_BI_TCXO, 12, 1, 4), |
| 1011 | F(9600000, P_BI_TCXO, 2, 0, 0), |
| 1012 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 1013 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), |
| 1014 | F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), |
| 1015 | F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), |
| 1016 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 1017 | { } |
| 1018 | }; |
| 1019 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1020 | static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { |
| 1021 | .cmd_rcgr = 0x1600c, |
| 1022 | .mnd_width = 8, |
| 1023 | .hid_width = 5, |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 1024 | .parent_map = gcc_parent_map_0, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1025 | .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 1026 | .enable_safe_config = true, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1027 | .clkr.hw.init = &(struct clk_init_data){ |
| 1028 | .name = "gcc_sdcc4_apps_clk_src", |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 1029 | .parent_names = gcc_parent_names_0, |
| 1030 | .num_parents = 4, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1031 | .flags = CLK_SET_RATE_PARENT, |
| 1032 | .ops = &clk_rcg2_ops, |
| 1033 | VDD_CX_FMAX_MAP4( |
| 1034 | MIN, 9600000, |
| 1035 | LOWER, 19200000, |
| 1036 | LOW, 50000000, |
| 1037 | NOMINAL, 100000000), |
| 1038 | }, |
| 1039 | }; |
| 1040 | |
| 1041 | static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = { |
| 1042 | F(105495, P_BI_TCXO, 2, 1, 91), |
| 1043 | { } |
| 1044 | }; |
| 1045 | |
| 1046 | static struct clk_rcg2 gcc_tsif_ref_clk_src = { |
| 1047 | .cmd_rcgr = 0x36010, |
| 1048 | .mnd_width = 8, |
| 1049 | .hid_width = 5, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 1050 | .parent_map = gcc_parent_map_6, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1051 | .freq_tbl = ftbl_gcc_tsif_ref_clk_src, |
| 1052 | .clkr.hw.init = &(struct clk_init_data){ |
| 1053 | .name = "gcc_tsif_ref_clk_src", |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 1054 | .parent_names = gcc_parent_names_6, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1055 | .num_parents = 5, |
| 1056 | .flags = CLK_SET_RATE_PARENT, |
| 1057 | .ops = &clk_rcg2_ops, |
| 1058 | VDD_CX_FMAX_MAP1( |
| 1059 | MIN, 105495), |
| 1060 | }, |
| 1061 | }; |
| 1062 | |
Deepak Katragadda | bae7106 | 2017-05-22 14:37:11 -0700 | [diff] [blame] | 1063 | static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { |
| 1064 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), |
| 1065 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), |
| 1066 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 1067 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), |
| 1068 | { } |
| 1069 | }; |
| 1070 | |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 1071 | static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src_sdm845_v2[] = { |
| 1072 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), |
| 1073 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), |
| 1074 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 1075 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), |
| 1076 | F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), |
| 1077 | { } |
| 1078 | }; |
| 1079 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1080 | static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { |
| 1081 | .cmd_rcgr = 0x7501c, |
| 1082 | .mnd_width = 8, |
| 1083 | .hid_width = 5, |
| 1084 | .parent_map = gcc_parent_map_0, |
Deepak Katragadda | bae7106 | 2017-05-22 14:37:11 -0700 | [diff] [blame] | 1085 | .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 1086 | .flags = FORCE_ENABLE_RCG, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1087 | .clkr.hw.init = &(struct clk_init_data){ |
| 1088 | .name = "gcc_ufs_card_axi_clk_src", |
| 1089 | .parent_names = gcc_parent_names_0, |
| 1090 | .num_parents = 4, |
| 1091 | .flags = CLK_SET_RATE_PARENT, |
| 1092 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 1093 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1094 | MIN, 50000000, |
| 1095 | LOW, 100000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 1096 | NOMINAL, 200000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1097 | }, |
| 1098 | }; |
| 1099 | |
| 1100 | static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { |
| 1101 | F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), |
| 1102 | F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), |
| 1103 | F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), |
| 1104 | F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), |
| 1105 | { } |
| 1106 | }; |
| 1107 | |
| 1108 | static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { |
| 1109 | .cmd_rcgr = 0x7505c, |
| 1110 | .mnd_width = 0, |
| 1111 | .hid_width = 5, |
| 1112 | .parent_map = gcc_parent_map_0, |
| 1113 | .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 1114 | .flags = FORCE_ENABLE_RCG, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1115 | .clkr.hw.init = &(struct clk_init_data){ |
| 1116 | .name = "gcc_ufs_card_ice_core_clk_src", |
| 1117 | .parent_names = gcc_parent_names_0, |
| 1118 | .num_parents = 4, |
| 1119 | .flags = CLK_SET_RATE_PARENT, |
| 1120 | .ops = &clk_rcg2_ops, |
| 1121 | VDD_CX_FMAX_MAP3( |
| 1122 | MIN, 75000000, |
| 1123 | LOW, 150000000, |
| 1124 | NOMINAL, 300000000), |
| 1125 | }, |
| 1126 | }; |
| 1127 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1128 | static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { |
| 1129 | .cmd_rcgr = 0x75090, |
| 1130 | .mnd_width = 0, |
| 1131 | .hid_width = 5, |
| 1132 | .parent_map = gcc_parent_map_4, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 1133 | .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 1134 | .flags = FORCE_ENABLE_RCG, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1135 | .clkr.hw.init = &(struct clk_init_data){ |
| 1136 | .name = "gcc_ufs_card_phy_aux_clk_src", |
| 1137 | .parent_names = gcc_parent_names_4, |
| 1138 | .num_parents = 2, |
| 1139 | .flags = CLK_SET_RATE_PARENT, |
| 1140 | .ops = &clk_rcg2_ops, |
| 1141 | VDD_CX_FMAX_MAP1( |
| 1142 | MIN, 19200000), |
| 1143 | }, |
| 1144 | }; |
| 1145 | |
| 1146 | static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = { |
| 1147 | F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), |
| 1148 | F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), |
| 1149 | F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), |
| 1150 | { } |
| 1151 | }; |
| 1152 | |
| 1153 | static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { |
| 1154 | .cmd_rcgr = 0x75074, |
| 1155 | .mnd_width = 0, |
| 1156 | .hid_width = 5, |
| 1157 | .parent_map = gcc_parent_map_0, |
| 1158 | .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 1159 | .flags = FORCE_ENABLE_RCG, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1160 | .clkr.hw.init = &(struct clk_init_data){ |
| 1161 | .name = "gcc_ufs_card_unipro_core_clk_src", |
| 1162 | .parent_names = gcc_parent_names_0, |
| 1163 | .num_parents = 4, |
| 1164 | .flags = CLK_SET_RATE_PARENT, |
| 1165 | .ops = &clk_rcg2_ops, |
| 1166 | VDD_CX_FMAX_MAP3( |
| 1167 | MIN, 37500000, |
| 1168 | LOW, 75000000, |
| 1169 | NOMINAL, 150000000), |
| 1170 | }, |
| 1171 | }; |
| 1172 | |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 1173 | static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { |
| 1174 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), |
| 1175 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), |
| 1176 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 1177 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), |
| 1178 | F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), |
| 1179 | { } |
| 1180 | }; |
| 1181 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1182 | static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { |
| 1183 | .cmd_rcgr = 0x7701c, |
| 1184 | .mnd_width = 8, |
| 1185 | .hid_width = 5, |
| 1186 | .parent_map = gcc_parent_map_0, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 1187 | .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 1188 | .flags = FORCE_ENABLE_RCG, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1189 | .clkr.hw.init = &(struct clk_init_data){ |
| 1190 | .name = "gcc_ufs_phy_axi_clk_src", |
| 1191 | .parent_names = gcc_parent_names_0, |
| 1192 | .num_parents = 4, |
| 1193 | .flags = CLK_SET_RATE_PARENT, |
| 1194 | .ops = &clk_rcg2_ops, |
| 1195 | VDD_CX_FMAX_MAP4( |
| 1196 | MIN, 50000000, |
| 1197 | LOW, 100000000, |
| 1198 | NOMINAL, 200000000, |
| 1199 | HIGH, 240000000), |
| 1200 | }, |
| 1201 | }; |
| 1202 | |
| 1203 | static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { |
| 1204 | .cmd_rcgr = 0x7705c, |
| 1205 | .mnd_width = 0, |
| 1206 | .hid_width = 5, |
| 1207 | .parent_map = gcc_parent_map_0, |
| 1208 | .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 1209 | .flags = FORCE_ENABLE_RCG, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1210 | .clkr.hw.init = &(struct clk_init_data){ |
| 1211 | .name = "gcc_ufs_phy_ice_core_clk_src", |
| 1212 | .parent_names = gcc_parent_names_0, |
| 1213 | .num_parents = 4, |
| 1214 | .flags = CLK_SET_RATE_PARENT, |
| 1215 | .ops = &clk_rcg2_ops, |
| 1216 | VDD_CX_FMAX_MAP3( |
| 1217 | MIN, 75000000, |
| 1218 | LOW, 150000000, |
| 1219 | NOMINAL, 300000000), |
| 1220 | }, |
| 1221 | }; |
| 1222 | |
| 1223 | static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { |
| 1224 | .cmd_rcgr = 0x77090, |
| 1225 | .mnd_width = 0, |
| 1226 | .hid_width = 5, |
| 1227 | .parent_map = gcc_parent_map_4, |
| 1228 | .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 1229 | .flags = FORCE_ENABLE_RCG, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1230 | .clkr.hw.init = &(struct clk_init_data){ |
| 1231 | .name = "gcc_ufs_phy_phy_aux_clk_src", |
| 1232 | .parent_names = gcc_parent_names_4, |
| 1233 | .num_parents = 2, |
| 1234 | .flags = CLK_SET_RATE_PARENT, |
| 1235 | .ops = &clk_rcg2_ops, |
| 1236 | VDD_CX_FMAX_MAP1( |
| 1237 | MIN, 19200000), |
| 1238 | }, |
| 1239 | }; |
| 1240 | |
| 1241 | static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { |
| 1242 | .cmd_rcgr = 0x77074, |
| 1243 | .mnd_width = 0, |
| 1244 | .hid_width = 5, |
| 1245 | .parent_map = gcc_parent_map_0, |
| 1246 | .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 1247 | .flags = FORCE_ENABLE_RCG, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1248 | .clkr.hw.init = &(struct clk_init_data){ |
| 1249 | .name = "gcc_ufs_phy_unipro_core_clk_src", |
| 1250 | .parent_names = gcc_parent_names_0, |
| 1251 | .num_parents = 4, |
| 1252 | .flags = CLK_SET_RATE_PARENT, |
| 1253 | .ops = &clk_rcg2_ops, |
| 1254 | VDD_CX_FMAX_MAP3( |
| 1255 | MIN, 37500000, |
| 1256 | LOW, 75000000, |
| 1257 | NOMINAL, 150000000), |
| 1258 | }, |
| 1259 | }; |
| 1260 | |
| 1261 | static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { |
| 1262 | F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), |
| 1263 | F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), |
| 1264 | F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), |
| 1265 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), |
| 1266 | F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), |
| 1267 | { } |
| 1268 | }; |
| 1269 | |
| 1270 | static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { |
| 1271 | .cmd_rcgr = 0xf018, |
| 1272 | .mnd_width = 8, |
| 1273 | .hid_width = 5, |
| 1274 | .parent_map = gcc_parent_map_0, |
| 1275 | .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, |
| 1276 | .enable_safe_config = true, |
| 1277 | .clkr.hw.init = &(struct clk_init_data){ |
| 1278 | .name = "gcc_usb30_prim_master_clk_src", |
| 1279 | .parent_names = gcc_parent_names_0, |
| 1280 | .num_parents = 4, |
| 1281 | .flags = CLK_SET_RATE_PARENT, |
| 1282 | .ops = &clk_rcg2_ops, |
| 1283 | VDD_CX_FMAX_MAP5( |
| 1284 | MIN, 33333333, |
| 1285 | LOWER, 66666667, |
| 1286 | LOW, 133333333, |
| 1287 | NOMINAL, 200000000, |
| 1288 | HIGH, 240000000), |
| 1289 | }, |
| 1290 | }; |
| 1291 | |
| 1292 | static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { |
Deepak Katragadda | bae7106 | 2017-05-22 14:37:11 -0700 | [diff] [blame] | 1293 | F(19200000, P_BI_TCXO, 1, 0, 0), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1294 | F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), |
| 1295 | F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0), |
| 1296 | F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), |
| 1297 | { } |
| 1298 | }; |
| 1299 | |
| 1300 | static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { |
| 1301 | .cmd_rcgr = 0xf030, |
| 1302 | .mnd_width = 0, |
| 1303 | .hid_width = 5, |
| 1304 | .parent_map = gcc_parent_map_0, |
| 1305 | .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, |
| 1306 | .enable_safe_config = true, |
| 1307 | .clkr.hw.init = &(struct clk_init_data){ |
| 1308 | .name = "gcc_usb30_prim_mock_utmi_clk_src", |
| 1309 | .parent_names = gcc_parent_names_0, |
| 1310 | .num_parents = 4, |
| 1311 | .flags = CLK_SET_RATE_PARENT, |
| 1312 | .ops = &clk_rcg2_ops, |
| 1313 | VDD_CX_FMAX_MAP3( |
| 1314 | MIN, 19200000, |
| 1315 | LOWER, 40000000, |
| 1316 | LOW, 60000000), |
| 1317 | }, |
| 1318 | }; |
| 1319 | |
| 1320 | static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { |
| 1321 | .cmd_rcgr = 0x10018, |
| 1322 | .mnd_width = 8, |
| 1323 | .hid_width = 5, |
| 1324 | .parent_map = gcc_parent_map_0, |
| 1325 | .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, |
| 1326 | .clkr.hw.init = &(struct clk_init_data){ |
| 1327 | .name = "gcc_usb30_sec_master_clk_src", |
| 1328 | .parent_names = gcc_parent_names_0, |
| 1329 | .num_parents = 4, |
| 1330 | .flags = CLK_SET_RATE_PARENT, |
| 1331 | .ops = &clk_rcg2_ops, |
| 1332 | VDD_CX_FMAX_MAP5( |
| 1333 | MIN, 33333333, |
| 1334 | LOWER, 66666667, |
| 1335 | LOW, 133333333, |
| 1336 | NOMINAL, 200000000, |
| 1337 | HIGH, 240000000), |
| 1338 | }, |
| 1339 | }; |
| 1340 | |
| 1341 | static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { |
| 1342 | .cmd_rcgr = 0x10030, |
| 1343 | .mnd_width = 0, |
| 1344 | .hid_width = 5, |
| 1345 | .parent_map = gcc_parent_map_0, |
| 1346 | .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, |
| 1347 | .clkr.hw.init = &(struct clk_init_data){ |
| 1348 | .name = "gcc_usb30_sec_mock_utmi_clk_src", |
| 1349 | .parent_names = gcc_parent_names_0, |
| 1350 | .num_parents = 4, |
| 1351 | .flags = CLK_SET_RATE_PARENT, |
| 1352 | .ops = &clk_rcg2_ops, |
| 1353 | VDD_CX_FMAX_MAP3( |
| 1354 | MIN, 19200000, |
| 1355 | LOWER, 40000000, |
| 1356 | LOW, 60000000), |
| 1357 | }, |
| 1358 | }; |
| 1359 | |
| 1360 | static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { |
| 1361 | .cmd_rcgr = 0xf05c, |
| 1362 | .mnd_width = 0, |
| 1363 | .hid_width = 5, |
| 1364 | .parent_map = gcc_parent_map_2, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 1365 | .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1366 | .clkr.hw.init = &(struct clk_init_data){ |
| 1367 | .name = "gcc_usb3_prim_phy_aux_clk_src", |
| 1368 | .parent_names = gcc_parent_names_2, |
| 1369 | .num_parents = 3, |
| 1370 | .flags = CLK_SET_RATE_PARENT, |
| 1371 | .ops = &clk_rcg2_ops, |
| 1372 | VDD_CX_FMAX_MAP1( |
| 1373 | MIN, 19200000), |
| 1374 | }, |
| 1375 | }; |
| 1376 | |
| 1377 | static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { |
| 1378 | .cmd_rcgr = 0x1005c, |
| 1379 | .mnd_width = 0, |
| 1380 | .hid_width = 5, |
| 1381 | .parent_map = gcc_parent_map_2, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 1382 | .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1383 | .enable_safe_config = true, |
| 1384 | .clkr.hw.init = &(struct clk_init_data){ |
| 1385 | .name = "gcc_usb3_sec_phy_aux_clk_src", |
| 1386 | .parent_names = gcc_parent_names_2, |
| 1387 | .num_parents = 3, |
| 1388 | .flags = CLK_SET_RATE_PARENT, |
| 1389 | .ops = &clk_rcg2_ops, |
| 1390 | VDD_CX_FMAX_MAP1( |
| 1391 | MIN, 19200000), |
| 1392 | }, |
| 1393 | }; |
| 1394 | |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 1395 | static struct clk_rcg2 gcc_vs_ctrl_clk_src = { |
| 1396 | .cmd_rcgr = 0x7a030, |
| 1397 | .mnd_width = 0, |
| 1398 | .hid_width = 5, |
| 1399 | .parent_map = gcc_parent_map_3, |
| 1400 | .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, |
| 1401 | .clkr.hw.init = &(struct clk_init_data){ |
| 1402 | .name = "gcc_vs_ctrl_clk_src", |
| 1403 | .parent_names = gcc_parent_names_3, |
| 1404 | .num_parents = 3, |
| 1405 | .flags = CLK_SET_RATE_PARENT, |
| 1406 | .ops = &clk_rcg2_ops, |
| 1407 | VDD_CX_FMAX_MAP1( |
| 1408 | MIN, 19200000), |
| 1409 | }, |
| 1410 | }; |
| 1411 | |
| 1412 | static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = { |
| 1413 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 1414 | F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), |
| 1415 | F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0), |
| 1416 | { } |
| 1417 | }; |
| 1418 | |
| 1419 | static struct clk_rcg2 gcc_vsensor_clk_src = { |
| 1420 | .cmd_rcgr = 0x7a018, |
| 1421 | .mnd_width = 0, |
| 1422 | .hid_width = 5, |
| 1423 | .parent_map = gcc_parent_map_9, |
| 1424 | .freq_tbl = ftbl_gcc_vsensor_clk_src, |
| 1425 | .clkr.hw.init = &(struct clk_init_data){ |
| 1426 | .name = "gcc_vsensor_clk_src", |
| 1427 | .parent_names = gcc_parent_names_9, |
| 1428 | .num_parents = 4, |
| 1429 | .flags = CLK_SET_RATE_PARENT, |
| 1430 | .ops = &clk_rcg2_ops, |
| 1431 | VDD_CX_FMAX_MAP3( |
| 1432 | MIN, 19200000, |
| 1433 | LOW, 300000000, |
| 1434 | LOW_L1, 600000000), |
| 1435 | }, |
| 1436 | }; |
| 1437 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1438 | static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { |
| 1439 | .halt_reg = 0x90014, |
| 1440 | .halt_check = BRANCH_HALT, |
| 1441 | .clkr = { |
| 1442 | .enable_reg = 0x90014, |
| 1443 | .enable_mask = BIT(0), |
| 1444 | .hw.init = &(struct clk_init_data){ |
| 1445 | .name = "gcc_aggre_noc_pcie_tbu_clk", |
| 1446 | .ops = &clk_branch2_ops, |
| 1447 | }, |
| 1448 | }, |
| 1449 | }; |
| 1450 | |
| 1451 | static struct clk_branch gcc_aggre_ufs_card_axi_clk = { |
| 1452 | .halt_reg = 0x82028, |
| 1453 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 1454 | .hwcg_reg = 0x82028, |
| 1455 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1456 | .clkr = { |
| 1457 | .enable_reg = 0x82028, |
| 1458 | .enable_mask = BIT(0), |
| 1459 | .hw.init = &(struct clk_init_data){ |
| 1460 | .name = "gcc_aggre_ufs_card_axi_clk", |
| 1461 | .parent_names = (const char *[]){ |
| 1462 | "gcc_ufs_card_axi_clk_src", |
| 1463 | }, |
| 1464 | .num_parents = 1, |
| 1465 | .flags = CLK_SET_RATE_PARENT, |
| 1466 | .ops = &clk_branch2_ops, |
| 1467 | }, |
| 1468 | }, |
| 1469 | }; |
| 1470 | |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 1471 | static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = { |
| 1472 | .halt_reg = 0x82028, |
| 1473 | .clkr = { |
| 1474 | .enable_reg = 0x82028, |
| 1475 | .enable_mask = BIT(1), |
| 1476 | .hw.init = &(struct clk_init_data){ |
| 1477 | .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk", |
| 1478 | .parent_names = (const char *[]){ |
| 1479 | "gcc_aggre_ufs_card_axi_clk", |
| 1480 | }, |
| 1481 | .num_parents = 1, |
| 1482 | .flags = CLK_SET_RATE_PARENT, |
| 1483 | .ops = &clk_branch2_hw_ctl_ops, |
| 1484 | }, |
| 1485 | }, |
| 1486 | }; |
| 1487 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1488 | static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { |
| 1489 | .halt_reg = 0x82024, |
| 1490 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 1491 | .hwcg_reg = 0x82024, |
| 1492 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1493 | .clkr = { |
| 1494 | .enable_reg = 0x82024, |
| 1495 | .enable_mask = BIT(0), |
| 1496 | .hw.init = &(struct clk_init_data){ |
| 1497 | .name = "gcc_aggre_ufs_phy_axi_clk", |
| 1498 | .parent_names = (const char *[]){ |
| 1499 | "gcc_ufs_phy_axi_clk_src", |
| 1500 | }, |
| 1501 | .num_parents = 1, |
| 1502 | .flags = CLK_SET_RATE_PARENT, |
| 1503 | .ops = &clk_branch2_ops, |
| 1504 | }, |
| 1505 | }, |
| 1506 | }; |
| 1507 | |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 1508 | static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { |
| 1509 | .halt_reg = 0x82024, |
| 1510 | .clkr = { |
| 1511 | .enable_reg = 0x82024, |
| 1512 | .enable_mask = BIT(1), |
| 1513 | .hw.init = &(struct clk_init_data){ |
| 1514 | .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", |
| 1515 | .parent_names = (const char *[]){ |
| 1516 | "gcc_aggre_ufs_phy_axi_clk", |
| 1517 | }, |
| 1518 | .num_parents = 1, |
| 1519 | .flags = CLK_SET_RATE_PARENT, |
| 1520 | .ops = &clk_branch2_hw_ctl_ops, |
| 1521 | }, |
| 1522 | }, |
| 1523 | }; |
| 1524 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1525 | static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { |
| 1526 | .halt_reg = 0x8201c, |
| 1527 | .halt_check = BRANCH_HALT, |
| 1528 | .clkr = { |
| 1529 | .enable_reg = 0x8201c, |
| 1530 | .enable_mask = BIT(0), |
| 1531 | .hw.init = &(struct clk_init_data){ |
| 1532 | .name = "gcc_aggre_usb3_prim_axi_clk", |
| 1533 | .parent_names = (const char *[]){ |
| 1534 | "gcc_usb30_prim_master_clk_src", |
| 1535 | }, |
| 1536 | .num_parents = 1, |
| 1537 | .flags = CLK_SET_RATE_PARENT, |
| 1538 | .ops = &clk_branch2_ops, |
| 1539 | }, |
| 1540 | }, |
| 1541 | }; |
| 1542 | |
| 1543 | static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { |
| 1544 | .halt_reg = 0x82020, |
| 1545 | .halt_check = BRANCH_HALT, |
| 1546 | .clkr = { |
| 1547 | .enable_reg = 0x82020, |
| 1548 | .enable_mask = BIT(0), |
| 1549 | .hw.init = &(struct clk_init_data){ |
| 1550 | .name = "gcc_aggre_usb3_sec_axi_clk", |
| 1551 | .parent_names = (const char *[]){ |
| 1552 | "gcc_usb30_sec_master_clk_src", |
| 1553 | }, |
| 1554 | .num_parents = 1, |
| 1555 | .flags = CLK_SET_RATE_PARENT, |
| 1556 | .ops = &clk_branch2_ops, |
| 1557 | }, |
| 1558 | }, |
| 1559 | }; |
| 1560 | |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 1561 | static struct clk_branch gcc_apc_vs_clk = { |
| 1562 | .halt_reg = 0x7a050, |
| 1563 | .halt_check = BRANCH_HALT, |
| 1564 | .clkr = { |
| 1565 | .enable_reg = 0x7a050, |
| 1566 | .enable_mask = BIT(0), |
| 1567 | .hw.init = &(struct clk_init_data){ |
| 1568 | .name = "gcc_apc_vs_clk", |
| 1569 | .parent_names = (const char *[]){ |
| 1570 | "gcc_vsensor_clk_src", |
| 1571 | }, |
| 1572 | .num_parents = 1, |
| 1573 | .flags = CLK_SET_RATE_PARENT, |
| 1574 | .ops = &clk_branch2_ops, |
| 1575 | }, |
| 1576 | }, |
| 1577 | }; |
| 1578 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1579 | static struct clk_branch gcc_boot_rom_ahb_clk = { |
| 1580 | .halt_reg = 0x38004, |
| 1581 | .halt_check = BRANCH_HALT_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 1582 | .hwcg_reg = 0x38004, |
| 1583 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1584 | .clkr = { |
| 1585 | .enable_reg = 0x52004, |
| 1586 | .enable_mask = BIT(10), |
| 1587 | .hw.init = &(struct clk_init_data){ |
| 1588 | .name = "gcc_boot_rom_ahb_clk", |
| 1589 | .ops = &clk_branch2_ops, |
| 1590 | }, |
| 1591 | }, |
| 1592 | }; |
| 1593 | |
| 1594 | static struct clk_branch gcc_camera_ahb_clk = { |
| 1595 | .halt_reg = 0xb008, |
| 1596 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 1597 | .hwcg_reg = 0xb008, |
| 1598 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1599 | .clkr = { |
| 1600 | .enable_reg = 0xb008, |
| 1601 | .enable_mask = BIT(0), |
| 1602 | .hw.init = &(struct clk_init_data){ |
| 1603 | .name = "gcc_camera_ahb_clk", |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 1604 | .flags = CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1605 | .ops = &clk_branch2_ops, |
| 1606 | }, |
| 1607 | }, |
| 1608 | }; |
| 1609 | |
| 1610 | static struct clk_branch gcc_camera_axi_clk = { |
| 1611 | .halt_reg = 0xb020, |
| 1612 | .halt_check = BRANCH_VOTED, |
| 1613 | .clkr = { |
| 1614 | .enable_reg = 0xb020, |
| 1615 | .enable_mask = BIT(0), |
| 1616 | .hw.init = &(struct clk_init_data){ |
| 1617 | .name = "gcc_camera_axi_clk", |
| 1618 | .ops = &clk_branch2_ops, |
| 1619 | }, |
| 1620 | }, |
| 1621 | }; |
| 1622 | |
| 1623 | static struct clk_branch gcc_camera_xo_clk = { |
| 1624 | .halt_reg = 0xb02c, |
| 1625 | .halt_check = BRANCH_HALT, |
| 1626 | .clkr = { |
| 1627 | .enable_reg = 0xb02c, |
| 1628 | .enable_mask = BIT(0), |
| 1629 | .hw.init = &(struct clk_init_data){ |
| 1630 | .name = "gcc_camera_xo_clk", |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 1631 | .flags = CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1632 | .ops = &clk_branch2_ops, |
| 1633 | }, |
| 1634 | }, |
| 1635 | }; |
| 1636 | |
| 1637 | static struct clk_branch gcc_ce1_ahb_clk = { |
| 1638 | .halt_reg = 0x4100c, |
| 1639 | .halt_check = BRANCH_HALT_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 1640 | .hwcg_reg = 0x4100c, |
| 1641 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1642 | .clkr = { |
| 1643 | .enable_reg = 0x52004, |
| 1644 | .enable_mask = BIT(3), |
| 1645 | .hw.init = &(struct clk_init_data){ |
| 1646 | .name = "gcc_ce1_ahb_clk", |
| 1647 | .ops = &clk_branch2_ops, |
| 1648 | }, |
| 1649 | }, |
| 1650 | }; |
| 1651 | |
| 1652 | static struct clk_branch gcc_ce1_axi_clk = { |
| 1653 | .halt_reg = 0x41008, |
| 1654 | .halt_check = BRANCH_HALT_VOTED, |
| 1655 | .clkr = { |
| 1656 | .enable_reg = 0x52004, |
| 1657 | .enable_mask = BIT(4), |
| 1658 | .hw.init = &(struct clk_init_data){ |
| 1659 | .name = "gcc_ce1_axi_clk", |
| 1660 | .ops = &clk_branch2_ops, |
| 1661 | }, |
| 1662 | }, |
| 1663 | }; |
| 1664 | |
| 1665 | static struct clk_branch gcc_ce1_clk = { |
| 1666 | .halt_reg = 0x41004, |
| 1667 | .halt_check = BRANCH_HALT_VOTED, |
| 1668 | .clkr = { |
| 1669 | .enable_reg = 0x52004, |
| 1670 | .enable_mask = BIT(5), |
| 1671 | .hw.init = &(struct clk_init_data){ |
| 1672 | .name = "gcc_ce1_clk", |
| 1673 | .ops = &clk_branch2_ops, |
| 1674 | }, |
| 1675 | }, |
| 1676 | }; |
| 1677 | |
| 1678 | static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { |
| 1679 | .halt_reg = 0x502c, |
| 1680 | .halt_check = BRANCH_HALT, |
| 1681 | .clkr = { |
| 1682 | .enable_reg = 0x502c, |
| 1683 | .enable_mask = BIT(0), |
| 1684 | .hw.init = &(struct clk_init_data){ |
| 1685 | .name = "gcc_cfg_noc_usb3_prim_axi_clk", |
| 1686 | .parent_names = (const char *[]){ |
| 1687 | "gcc_usb30_prim_master_clk_src", |
| 1688 | }, |
| 1689 | .num_parents = 1, |
| 1690 | .flags = CLK_SET_RATE_PARENT, |
| 1691 | .ops = &clk_branch2_ops, |
| 1692 | }, |
| 1693 | }, |
| 1694 | }; |
| 1695 | |
| 1696 | static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { |
| 1697 | .halt_reg = 0x5030, |
| 1698 | .halt_check = BRANCH_HALT, |
| 1699 | .clkr = { |
| 1700 | .enable_reg = 0x5030, |
| 1701 | .enable_mask = BIT(0), |
| 1702 | .hw.init = &(struct clk_init_data){ |
| 1703 | .name = "gcc_cfg_noc_usb3_sec_axi_clk", |
| 1704 | .parent_names = (const char *[]){ |
| 1705 | "gcc_usb30_sec_master_clk_src", |
| 1706 | }, |
| 1707 | .num_parents = 1, |
| 1708 | .flags = CLK_SET_RATE_PARENT, |
| 1709 | .ops = &clk_branch2_ops, |
| 1710 | }, |
| 1711 | }, |
| 1712 | }; |
| 1713 | |
| 1714 | static struct clk_branch gcc_cpuss_ahb_clk = { |
| 1715 | .halt_reg = 0x48000, |
| 1716 | .halt_check = BRANCH_HALT_VOTED, |
| 1717 | .clkr = { |
| 1718 | .enable_reg = 0x52004, |
| 1719 | .enable_mask = BIT(21), |
| 1720 | .hw.init = &(struct clk_init_data){ |
| 1721 | .name = "gcc_cpuss_ahb_clk", |
| 1722 | .parent_names = (const char *[]){ |
| 1723 | "gcc_cpuss_ahb_clk_src", |
| 1724 | }, |
| 1725 | .num_parents = 1, |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 1726 | .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1727 | .ops = &clk_branch2_ops, |
| 1728 | }, |
| 1729 | }, |
| 1730 | }; |
| 1731 | |
| 1732 | static struct clk_branch gcc_cpuss_dvm_bus_clk = { |
| 1733 | .halt_reg = 0x48190, |
| 1734 | .halt_check = BRANCH_HALT, |
| 1735 | .clkr = { |
| 1736 | .enable_reg = 0x48190, |
| 1737 | .enable_mask = BIT(0), |
| 1738 | .hw.init = &(struct clk_init_data){ |
| 1739 | .name = "gcc_cpuss_dvm_bus_clk", |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 1740 | .flags = CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1741 | .ops = &clk_branch2_ops, |
| 1742 | }, |
| 1743 | }, |
| 1744 | }; |
| 1745 | |
| 1746 | static struct clk_branch gcc_cpuss_gnoc_clk = { |
| 1747 | .halt_reg = 0x48004, |
| 1748 | .halt_check = BRANCH_HALT_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 1749 | .hwcg_reg = 0x48004, |
| 1750 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1751 | .clkr = { |
| 1752 | .enable_reg = 0x52004, |
| 1753 | .enable_mask = BIT(22), |
| 1754 | .hw.init = &(struct clk_init_data){ |
| 1755 | .name = "gcc_cpuss_gnoc_clk", |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 1756 | .flags = CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1757 | .ops = &clk_branch2_ops, |
| 1758 | }, |
| 1759 | }, |
| 1760 | }; |
| 1761 | |
| 1762 | static struct clk_branch gcc_cpuss_rbcpr_clk = { |
| 1763 | .halt_reg = 0x48008, |
| 1764 | .halt_check = BRANCH_HALT, |
| 1765 | .clkr = { |
| 1766 | .enable_reg = 0x48008, |
| 1767 | .enable_mask = BIT(0), |
| 1768 | .hw.init = &(struct clk_init_data){ |
| 1769 | .name = "gcc_cpuss_rbcpr_clk", |
| 1770 | .parent_names = (const char *[]){ |
| 1771 | "gcc_cpuss_rbcpr_clk_src", |
| 1772 | }, |
| 1773 | .num_parents = 1, |
| 1774 | .flags = CLK_SET_RATE_PARENT, |
| 1775 | .ops = &clk_branch2_ops, |
| 1776 | }, |
| 1777 | }, |
| 1778 | }; |
| 1779 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1780 | static struct clk_branch gcc_ddrss_gpu_axi_clk = { |
| 1781 | .halt_reg = 0x44038, |
Deepak Katragadda | d4ec4b7 | 2017-04-18 15:02:12 -0700 | [diff] [blame] | 1782 | .halt_check = BRANCH_VOTED, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1783 | .clkr = { |
| 1784 | .enable_reg = 0x44038, |
| 1785 | .enable_mask = BIT(0), |
| 1786 | .hw.init = &(struct clk_init_data){ |
| 1787 | .name = "gcc_ddrss_gpu_axi_clk", |
| 1788 | .ops = &clk_branch2_ops, |
| 1789 | }, |
| 1790 | }, |
| 1791 | }; |
| 1792 | |
| 1793 | static struct clk_branch gcc_disp_ahb_clk = { |
| 1794 | .halt_reg = 0xb00c, |
| 1795 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 1796 | .hwcg_reg = 0xb00c, |
| 1797 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1798 | .clkr = { |
| 1799 | .enable_reg = 0xb00c, |
| 1800 | .enable_mask = BIT(0), |
| 1801 | .hw.init = &(struct clk_init_data){ |
| 1802 | .name = "gcc_disp_ahb_clk", |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 1803 | .flags = CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1804 | .ops = &clk_branch2_ops, |
| 1805 | }, |
| 1806 | }, |
| 1807 | }; |
| 1808 | |
| 1809 | static struct clk_branch gcc_disp_axi_clk = { |
| 1810 | .halt_reg = 0xb024, |
| 1811 | .halt_check = BRANCH_VOTED, |
| 1812 | .clkr = { |
| 1813 | .enable_reg = 0xb024, |
| 1814 | .enable_mask = BIT(0), |
| 1815 | .hw.init = &(struct clk_init_data){ |
| 1816 | .name = "gcc_disp_axi_clk", |
| 1817 | .ops = &clk_branch2_ops, |
| 1818 | }, |
| 1819 | }, |
| 1820 | }; |
| 1821 | |
| 1822 | static struct clk_gate2 gcc_disp_gpll0_clk_src = { |
| 1823 | .udelay = 500, |
| 1824 | .clkr = { |
| 1825 | .enable_reg = 0x52004, |
| 1826 | .enable_mask = BIT(18), |
| 1827 | .hw.init = &(struct clk_init_data){ |
| 1828 | .name = "gcc_disp_gpll0_clk_src", |
| 1829 | .parent_names = (const char *[]){ |
| 1830 | "gpll0", |
| 1831 | }, |
| 1832 | .num_parents = 1, |
| 1833 | .flags = CLK_SET_RATE_PARENT, |
| 1834 | .ops = &clk_gate2_ops, |
| 1835 | }, |
| 1836 | }, |
| 1837 | }; |
| 1838 | |
| 1839 | static struct clk_gate2 gcc_disp_gpll0_div_clk_src = { |
| 1840 | .udelay = 500, |
| 1841 | .clkr = { |
| 1842 | .enable_reg = 0x52004, |
| 1843 | .enable_mask = BIT(19), |
| 1844 | .hw.init = &(struct clk_init_data){ |
| 1845 | .name = "gcc_disp_gpll0_div_clk_src", |
| 1846 | .parent_names = (const char *[]){ |
| 1847 | "gpll0_out_even", |
| 1848 | }, |
| 1849 | .num_parents = 1, |
| 1850 | .flags = CLK_SET_RATE_PARENT, |
| 1851 | .ops = &clk_gate2_ops, |
| 1852 | }, |
| 1853 | }, |
| 1854 | }; |
| 1855 | |
| 1856 | static struct clk_branch gcc_disp_xo_clk = { |
| 1857 | .halt_reg = 0xb030, |
| 1858 | .halt_check = BRANCH_HALT, |
| 1859 | .clkr = { |
| 1860 | .enable_reg = 0xb030, |
| 1861 | .enable_mask = BIT(0), |
| 1862 | .hw.init = &(struct clk_init_data){ |
| 1863 | .name = "gcc_disp_xo_clk", |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 1864 | .flags = CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1865 | .ops = &clk_branch2_ops, |
| 1866 | }, |
| 1867 | }, |
| 1868 | }; |
| 1869 | |
| 1870 | static struct clk_branch gcc_gp1_clk = { |
| 1871 | .halt_reg = 0x64000, |
| 1872 | .halt_check = BRANCH_HALT, |
| 1873 | .clkr = { |
| 1874 | .enable_reg = 0x64000, |
| 1875 | .enable_mask = BIT(0), |
| 1876 | .hw.init = &(struct clk_init_data){ |
| 1877 | .name = "gcc_gp1_clk", |
| 1878 | .parent_names = (const char *[]){ |
| 1879 | "gcc_gp1_clk_src", |
| 1880 | }, |
| 1881 | .num_parents = 1, |
| 1882 | .flags = CLK_SET_RATE_PARENT, |
| 1883 | .ops = &clk_branch2_ops, |
| 1884 | }, |
| 1885 | }, |
| 1886 | }; |
| 1887 | |
| 1888 | static struct clk_branch gcc_gp2_clk = { |
| 1889 | .halt_reg = 0x65000, |
| 1890 | .halt_check = BRANCH_HALT, |
| 1891 | .clkr = { |
| 1892 | .enable_reg = 0x65000, |
| 1893 | .enable_mask = BIT(0), |
| 1894 | .hw.init = &(struct clk_init_data){ |
| 1895 | .name = "gcc_gp2_clk", |
| 1896 | .parent_names = (const char *[]){ |
| 1897 | "gcc_gp2_clk_src", |
| 1898 | }, |
| 1899 | .num_parents = 1, |
| 1900 | .flags = CLK_SET_RATE_PARENT, |
| 1901 | .ops = &clk_branch2_ops, |
| 1902 | }, |
| 1903 | }, |
| 1904 | }; |
| 1905 | |
| 1906 | static struct clk_branch gcc_gp3_clk = { |
| 1907 | .halt_reg = 0x66000, |
| 1908 | .halt_check = BRANCH_HALT, |
| 1909 | .clkr = { |
| 1910 | .enable_reg = 0x66000, |
| 1911 | .enable_mask = BIT(0), |
| 1912 | .hw.init = &(struct clk_init_data){ |
| 1913 | .name = "gcc_gp3_clk", |
| 1914 | .parent_names = (const char *[]){ |
| 1915 | "gcc_gp3_clk_src", |
| 1916 | }, |
| 1917 | .num_parents = 1, |
| 1918 | .flags = CLK_SET_RATE_PARENT, |
| 1919 | .ops = &clk_branch2_ops, |
| 1920 | }, |
| 1921 | }, |
| 1922 | }; |
| 1923 | |
| 1924 | static struct clk_branch gcc_gpu_cfg_ahb_clk = { |
| 1925 | .halt_reg = 0x71004, |
| 1926 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 1927 | .hwcg_reg = 0x71004, |
| 1928 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1929 | .clkr = { |
| 1930 | .enable_reg = 0x71004, |
| 1931 | .enable_mask = BIT(0), |
| 1932 | .hw.init = &(struct clk_init_data){ |
| 1933 | .name = "gcc_gpu_cfg_ahb_clk", |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 1934 | .flags = CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1935 | .ops = &clk_branch2_ops, |
| 1936 | }, |
| 1937 | }, |
| 1938 | }; |
| 1939 | |
| 1940 | static struct clk_gate2 gcc_gpu_gpll0_clk_src = { |
| 1941 | .udelay = 500, |
| 1942 | .clkr = { |
| 1943 | .enable_reg = 0x52004, |
| 1944 | .enable_mask = BIT(15), |
| 1945 | .hw.init = &(struct clk_init_data){ |
| 1946 | .name = "gcc_gpu_gpll0_clk_src", |
| 1947 | .parent_names = (const char *[]){ |
| 1948 | "gpll0", |
| 1949 | }, |
| 1950 | .num_parents = 1, |
| 1951 | .flags = CLK_SET_RATE_PARENT, |
| 1952 | .ops = &clk_gate2_ops, |
| 1953 | }, |
| 1954 | }, |
| 1955 | }; |
| 1956 | |
| 1957 | static struct clk_gate2 gcc_gpu_gpll0_div_clk_src = { |
| 1958 | .udelay = 500, |
| 1959 | .clkr = { |
| 1960 | .enable_reg = 0x52004, |
| 1961 | .enable_mask = BIT(16), |
| 1962 | .hw.init = &(struct clk_init_data){ |
| 1963 | .name = "gcc_gpu_gpll0_div_clk_src", |
| 1964 | .parent_names = (const char *[]){ |
| 1965 | "gpll0_out_even", |
| 1966 | }, |
| 1967 | .num_parents = 1, |
| 1968 | .flags = CLK_SET_RATE_PARENT, |
| 1969 | .ops = &clk_gate2_ops, |
| 1970 | }, |
| 1971 | }, |
| 1972 | }; |
| 1973 | |
Deepak Katragadda | 69ba1ca | 2017-05-12 13:37:52 -0700 | [diff] [blame] | 1974 | static struct clk_branch gcc_gpu_iref_clk = { |
| 1975 | .halt_reg = 0x8c010, |
| 1976 | .halt_check = BRANCH_HALT, |
| 1977 | .clkr = { |
| 1978 | .enable_reg = 0x8c010, |
| 1979 | .enable_mask = BIT(0), |
| 1980 | .hw.init = &(struct clk_init_data){ |
| 1981 | .name = "gcc_gpu_iref_clk", |
| 1982 | .ops = &clk_branch2_ops, |
| 1983 | }, |
| 1984 | }, |
| 1985 | }; |
| 1986 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1987 | static struct clk_branch gcc_gpu_memnoc_gfx_clk = { |
| 1988 | .halt_reg = 0x7100c, |
Deepak Katragadda | d4ec4b7 | 2017-04-18 15:02:12 -0700 | [diff] [blame] | 1989 | .halt_check = BRANCH_VOTED, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1990 | .clkr = { |
| 1991 | .enable_reg = 0x7100c, |
| 1992 | .enable_mask = BIT(0), |
| 1993 | .hw.init = &(struct clk_init_data){ |
| 1994 | .name = "gcc_gpu_memnoc_gfx_clk", |
| 1995 | .ops = &clk_branch2_ops, |
| 1996 | }, |
| 1997 | }, |
| 1998 | }; |
| 1999 | |
| 2000 | static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { |
| 2001 | .halt_reg = 0x71018, |
| 2002 | .halt_check = BRANCH_HALT, |
| 2003 | .clkr = { |
| 2004 | .enable_reg = 0x71018, |
| 2005 | .enable_mask = BIT(0), |
| 2006 | .hw.init = &(struct clk_init_data){ |
| 2007 | .name = "gcc_gpu_snoc_dvm_gfx_clk", |
| 2008 | .ops = &clk_branch2_ops, |
| 2009 | }, |
| 2010 | }, |
| 2011 | }; |
| 2012 | |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 2013 | static struct clk_branch gcc_gpu_vs_clk = { |
| 2014 | .halt_reg = 0x7a04c, |
| 2015 | .halt_check = BRANCH_HALT, |
| 2016 | .clkr = { |
| 2017 | .enable_reg = 0x7a04c, |
| 2018 | .enable_mask = BIT(0), |
| 2019 | .hw.init = &(struct clk_init_data){ |
| 2020 | .name = "gcc_gpu_vs_clk", |
| 2021 | .parent_names = (const char *[]){ |
| 2022 | "gcc_vsensor_clk_src", |
| 2023 | }, |
| 2024 | .num_parents = 1, |
| 2025 | .flags = CLK_SET_RATE_PARENT, |
| 2026 | .ops = &clk_branch2_ops, |
| 2027 | }, |
| 2028 | }, |
| 2029 | }; |
| 2030 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2031 | static struct clk_branch gcc_mss_axis2_clk = { |
| 2032 | .halt_reg = 0x8a008, |
| 2033 | .halt_check = BRANCH_HALT, |
| 2034 | .clkr = { |
| 2035 | .enable_reg = 0x8a008, |
| 2036 | .enable_mask = BIT(0), |
| 2037 | .hw.init = &(struct clk_init_data){ |
| 2038 | .name = "gcc_mss_axis2_clk", |
| 2039 | .ops = &clk_branch2_ops, |
| 2040 | }, |
| 2041 | }, |
| 2042 | }; |
| 2043 | |
| 2044 | static struct clk_branch gcc_mss_cfg_ahb_clk = { |
| 2045 | .halt_reg = 0x8a000, |
| 2046 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2047 | .hwcg_reg = 0x8a000, |
| 2048 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2049 | .clkr = { |
| 2050 | .enable_reg = 0x8a000, |
| 2051 | .enable_mask = BIT(0), |
| 2052 | .hw.init = &(struct clk_init_data){ |
| 2053 | .name = "gcc_mss_cfg_ahb_clk", |
| 2054 | .ops = &clk_branch2_ops, |
| 2055 | }, |
| 2056 | }, |
| 2057 | }; |
| 2058 | |
| 2059 | static struct clk_gate2 gcc_mss_gpll0_div_clk_src = { |
| 2060 | .udelay = 500, |
| 2061 | .clkr = { |
| 2062 | .enable_reg = 0x52004, |
| 2063 | .enable_mask = BIT(17), |
| 2064 | .hw.init = &(struct clk_init_data){ |
| 2065 | .name = "gcc_mss_gpll0_div_clk_src", |
| 2066 | .ops = &clk_gate2_ops, |
| 2067 | }, |
| 2068 | }, |
| 2069 | }; |
| 2070 | |
| 2071 | static struct clk_branch gcc_mss_mfab_axis_clk = { |
| 2072 | .halt_reg = 0x8a004, |
| 2073 | .halt_check = BRANCH_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2074 | .hwcg_reg = 0x8a004, |
| 2075 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2076 | .clkr = { |
| 2077 | .enable_reg = 0x8a004, |
| 2078 | .enable_mask = BIT(0), |
| 2079 | .hw.init = &(struct clk_init_data){ |
| 2080 | .name = "gcc_mss_mfab_axis_clk", |
| 2081 | .ops = &clk_branch2_ops, |
| 2082 | }, |
| 2083 | }, |
| 2084 | }; |
| 2085 | |
| 2086 | static struct clk_branch gcc_mss_q6_memnoc_axi_clk = { |
| 2087 | .halt_reg = 0x8a154, |
| 2088 | .halt_check = BRANCH_VOTED, |
| 2089 | .clkr = { |
| 2090 | .enable_reg = 0x8a154, |
| 2091 | .enable_mask = BIT(0), |
| 2092 | .hw.init = &(struct clk_init_data){ |
| 2093 | .name = "gcc_mss_q6_memnoc_axi_clk", |
| 2094 | .ops = &clk_branch2_ops, |
| 2095 | }, |
| 2096 | }, |
| 2097 | }; |
| 2098 | |
| 2099 | static struct clk_branch gcc_mss_snoc_axi_clk = { |
| 2100 | .halt_reg = 0x8a150, |
| 2101 | .halt_check = BRANCH_HALT, |
| 2102 | .clkr = { |
| 2103 | .enable_reg = 0x8a150, |
| 2104 | .enable_mask = BIT(0), |
| 2105 | .hw.init = &(struct clk_init_data){ |
| 2106 | .name = "gcc_mss_snoc_axi_clk", |
| 2107 | .ops = &clk_branch2_ops, |
| 2108 | }, |
| 2109 | }, |
| 2110 | }; |
| 2111 | |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 2112 | static struct clk_branch gcc_mss_vs_clk = { |
| 2113 | .halt_reg = 0x7a048, |
| 2114 | .halt_check = BRANCH_HALT, |
| 2115 | .clkr = { |
| 2116 | .enable_reg = 0x7a048, |
| 2117 | .enable_mask = BIT(0), |
| 2118 | .hw.init = &(struct clk_init_data){ |
| 2119 | .name = "gcc_mss_vs_clk", |
| 2120 | .parent_names = (const char *[]){ |
| 2121 | "gcc_vsensor_clk_src", |
| 2122 | }, |
| 2123 | .num_parents = 1, |
| 2124 | .flags = CLK_SET_RATE_PARENT, |
| 2125 | .ops = &clk_branch2_ops, |
| 2126 | }, |
| 2127 | }, |
| 2128 | }; |
| 2129 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2130 | static struct clk_branch gcc_pcie_0_aux_clk = { |
| 2131 | .halt_reg = 0x6b01c, |
| 2132 | .halt_check = BRANCH_HALT_VOTED, |
| 2133 | .clkr = { |
| 2134 | .enable_reg = 0x5200c, |
| 2135 | .enable_mask = BIT(3), |
| 2136 | .hw.init = &(struct clk_init_data){ |
| 2137 | .name = "gcc_pcie_0_aux_clk", |
| 2138 | .parent_names = (const char *[]){ |
| 2139 | "gcc_pcie_0_aux_clk_src", |
| 2140 | }, |
| 2141 | .num_parents = 1, |
| 2142 | .flags = CLK_SET_RATE_PARENT, |
| 2143 | .ops = &clk_branch2_ops, |
| 2144 | }, |
| 2145 | }, |
| 2146 | }; |
| 2147 | |
| 2148 | static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { |
| 2149 | .halt_reg = 0x6b018, |
| 2150 | .halt_check = BRANCH_HALT_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2151 | .hwcg_reg = 0x6b018, |
| 2152 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2153 | .clkr = { |
| 2154 | .enable_reg = 0x5200c, |
| 2155 | .enable_mask = BIT(2), |
| 2156 | .hw.init = &(struct clk_init_data){ |
| 2157 | .name = "gcc_pcie_0_cfg_ahb_clk", |
| 2158 | .ops = &clk_branch2_ops, |
| 2159 | }, |
| 2160 | }, |
| 2161 | }; |
| 2162 | |
| 2163 | static struct clk_branch gcc_pcie_0_clkref_clk = { |
| 2164 | .halt_reg = 0x8c00c, |
| 2165 | .halt_check = BRANCH_HALT, |
| 2166 | .clkr = { |
| 2167 | .enable_reg = 0x8c00c, |
| 2168 | .enable_mask = BIT(0), |
| 2169 | .hw.init = &(struct clk_init_data){ |
| 2170 | .name = "gcc_pcie_0_clkref_clk", |
| 2171 | .ops = &clk_branch2_ops, |
| 2172 | }, |
| 2173 | }, |
| 2174 | }; |
| 2175 | |
| 2176 | static struct clk_branch gcc_pcie_0_mstr_axi_clk = { |
| 2177 | .halt_reg = 0x6b014, |
| 2178 | .halt_check = BRANCH_HALT_VOTED, |
| 2179 | .clkr = { |
| 2180 | .enable_reg = 0x5200c, |
| 2181 | .enable_mask = BIT(1), |
| 2182 | .hw.init = &(struct clk_init_data){ |
| 2183 | .name = "gcc_pcie_0_mstr_axi_clk", |
| 2184 | .ops = &clk_branch2_ops, |
| 2185 | }, |
| 2186 | }, |
| 2187 | }; |
| 2188 | |
Deepak Katragadda | 4f92344 | 2017-05-03 11:35:43 -0700 | [diff] [blame] | 2189 | static struct clk_branch gcc_pcie_0_pipe_clk = { |
| 2190 | .halt_reg = 0x6b020, |
| 2191 | .halt_check = BRANCH_VOTED, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2192 | .clkr = { |
| 2193 | .enable_reg = 0x5200c, |
| 2194 | .enable_mask = BIT(4), |
| 2195 | .hw.init = &(struct clk_init_data){ |
| 2196 | .name = "gcc_pcie_0_pipe_clk", |
Deepak Katragadda | 4f92344 | 2017-05-03 11:35:43 -0700 | [diff] [blame] | 2197 | .ops = &clk_branch2_ops, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2198 | }, |
| 2199 | }, |
| 2200 | }; |
| 2201 | |
| 2202 | static struct clk_branch gcc_pcie_0_slv_axi_clk = { |
| 2203 | .halt_reg = 0x6b010, |
| 2204 | .halt_check = BRANCH_HALT_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2205 | .hwcg_reg = 0x6b010, |
| 2206 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2207 | .clkr = { |
| 2208 | .enable_reg = 0x5200c, |
| 2209 | .enable_mask = BIT(0), |
| 2210 | .hw.init = &(struct clk_init_data){ |
| 2211 | .name = "gcc_pcie_0_slv_axi_clk", |
| 2212 | .ops = &clk_branch2_ops, |
| 2213 | }, |
| 2214 | }, |
| 2215 | }; |
| 2216 | |
| 2217 | static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { |
| 2218 | .halt_reg = 0x6b00c, |
| 2219 | .halt_check = BRANCH_HALT_VOTED, |
| 2220 | .clkr = { |
| 2221 | .enable_reg = 0x5200c, |
| 2222 | .enable_mask = BIT(5), |
| 2223 | .hw.init = &(struct clk_init_data){ |
| 2224 | .name = "gcc_pcie_0_slv_q2a_axi_clk", |
| 2225 | .ops = &clk_branch2_ops, |
| 2226 | }, |
| 2227 | }, |
| 2228 | }; |
| 2229 | |
| 2230 | static struct clk_branch gcc_pcie_1_aux_clk = { |
| 2231 | .halt_reg = 0x8d01c, |
| 2232 | .halt_check = BRANCH_HALT_VOTED, |
| 2233 | .clkr = { |
| 2234 | .enable_reg = 0x52004, |
| 2235 | .enable_mask = BIT(29), |
| 2236 | .hw.init = &(struct clk_init_data){ |
| 2237 | .name = "gcc_pcie_1_aux_clk", |
| 2238 | .parent_names = (const char *[]){ |
| 2239 | "gcc_pcie_1_aux_clk_src", |
| 2240 | }, |
| 2241 | .num_parents = 1, |
| 2242 | .flags = CLK_SET_RATE_PARENT, |
| 2243 | .ops = &clk_branch2_ops, |
| 2244 | }, |
| 2245 | }, |
| 2246 | }; |
| 2247 | |
| 2248 | static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { |
| 2249 | .halt_reg = 0x8d018, |
| 2250 | .halt_check = BRANCH_HALT_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2251 | .hwcg_reg = 0x8d018, |
| 2252 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2253 | .clkr = { |
| 2254 | .enable_reg = 0x52004, |
| 2255 | .enable_mask = BIT(28), |
| 2256 | .hw.init = &(struct clk_init_data){ |
| 2257 | .name = "gcc_pcie_1_cfg_ahb_clk", |
| 2258 | .ops = &clk_branch2_ops, |
| 2259 | }, |
| 2260 | }, |
| 2261 | }; |
| 2262 | |
| 2263 | static struct clk_branch gcc_pcie_1_clkref_clk = { |
| 2264 | .halt_reg = 0x8c02c, |
| 2265 | .halt_check = BRANCH_HALT, |
| 2266 | .clkr = { |
| 2267 | .enable_reg = 0x8c02c, |
| 2268 | .enable_mask = BIT(0), |
| 2269 | .hw.init = &(struct clk_init_data){ |
| 2270 | .name = "gcc_pcie_1_clkref_clk", |
| 2271 | .ops = &clk_branch2_ops, |
| 2272 | }, |
| 2273 | }, |
| 2274 | }; |
| 2275 | |
| 2276 | static struct clk_branch gcc_pcie_1_mstr_axi_clk = { |
| 2277 | .halt_reg = 0x8d014, |
| 2278 | .halt_check = BRANCH_HALT_VOTED, |
| 2279 | .clkr = { |
| 2280 | .enable_reg = 0x52004, |
| 2281 | .enable_mask = BIT(27), |
| 2282 | .hw.init = &(struct clk_init_data){ |
| 2283 | .name = "gcc_pcie_1_mstr_axi_clk", |
| 2284 | .ops = &clk_branch2_ops, |
| 2285 | }, |
| 2286 | }, |
| 2287 | }; |
| 2288 | |
Deepak Katragadda | 4f92344 | 2017-05-03 11:35:43 -0700 | [diff] [blame] | 2289 | static struct clk_branch gcc_pcie_1_pipe_clk = { |
| 2290 | .halt_reg = 0x8d020, |
| 2291 | .halt_check = BRANCH_VOTED, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2292 | .clkr = { |
| 2293 | .enable_reg = 0x52004, |
| 2294 | .enable_mask = BIT(30), |
| 2295 | .hw.init = &(struct clk_init_data){ |
| 2296 | .name = "gcc_pcie_1_pipe_clk", |
Deepak Katragadda | 4f92344 | 2017-05-03 11:35:43 -0700 | [diff] [blame] | 2297 | .ops = &clk_branch2_ops, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2298 | }, |
| 2299 | }, |
| 2300 | }; |
| 2301 | |
| 2302 | static struct clk_branch gcc_pcie_1_slv_axi_clk = { |
| 2303 | .halt_reg = 0x8d010, |
| 2304 | .halt_check = BRANCH_HALT_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2305 | .hwcg_reg = 0x8d010, |
| 2306 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2307 | .clkr = { |
| 2308 | .enable_reg = 0x52004, |
| 2309 | .enable_mask = BIT(26), |
| 2310 | .hw.init = &(struct clk_init_data){ |
| 2311 | .name = "gcc_pcie_1_slv_axi_clk", |
| 2312 | .ops = &clk_branch2_ops, |
| 2313 | }, |
| 2314 | }, |
| 2315 | }; |
| 2316 | |
| 2317 | static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { |
| 2318 | .halt_reg = 0x8d00c, |
| 2319 | .halt_check = BRANCH_HALT_VOTED, |
| 2320 | .clkr = { |
| 2321 | .enable_reg = 0x52004, |
| 2322 | .enable_mask = BIT(25), |
| 2323 | .hw.init = &(struct clk_init_data){ |
| 2324 | .name = "gcc_pcie_1_slv_q2a_axi_clk", |
| 2325 | .ops = &clk_branch2_ops, |
| 2326 | }, |
| 2327 | }, |
| 2328 | }; |
| 2329 | |
| 2330 | static struct clk_branch gcc_pcie_phy_aux_clk = { |
| 2331 | .halt_reg = 0x6f004, |
| 2332 | .halt_check = BRANCH_HALT, |
| 2333 | .clkr = { |
| 2334 | .enable_reg = 0x6f004, |
| 2335 | .enable_mask = BIT(0), |
| 2336 | .hw.init = &(struct clk_init_data){ |
| 2337 | .name = "gcc_pcie_phy_aux_clk", |
| 2338 | .parent_names = (const char *[]){ |
| 2339 | "gcc_pcie_0_aux_clk_src", |
| 2340 | }, |
| 2341 | .num_parents = 1, |
| 2342 | .flags = CLK_SET_RATE_PARENT, |
| 2343 | .ops = &clk_branch2_ops, |
| 2344 | }, |
| 2345 | }, |
| 2346 | }; |
| 2347 | |
| 2348 | static struct clk_branch gcc_pcie_phy_refgen_clk = { |
| 2349 | .halt_reg = 0x6f02c, |
| 2350 | .halt_check = BRANCH_HALT, |
| 2351 | .clkr = { |
| 2352 | .enable_reg = 0x6f02c, |
| 2353 | .enable_mask = BIT(0), |
| 2354 | .hw.init = &(struct clk_init_data){ |
| 2355 | .name = "gcc_pcie_phy_refgen_clk", |
| 2356 | .parent_names = (const char *[]){ |
| 2357 | "gcc_pcie_phy_refgen_clk_src", |
| 2358 | }, |
| 2359 | .num_parents = 1, |
| 2360 | .flags = CLK_SET_RATE_PARENT, |
| 2361 | .ops = &clk_branch2_ops, |
| 2362 | }, |
| 2363 | }, |
| 2364 | }; |
| 2365 | |
| 2366 | static struct clk_branch gcc_pdm2_clk = { |
| 2367 | .halt_reg = 0x3300c, |
| 2368 | .halt_check = BRANCH_HALT, |
| 2369 | .clkr = { |
| 2370 | .enable_reg = 0x3300c, |
| 2371 | .enable_mask = BIT(0), |
| 2372 | .hw.init = &(struct clk_init_data){ |
| 2373 | .name = "gcc_pdm2_clk", |
| 2374 | .parent_names = (const char *[]){ |
| 2375 | "gcc_pdm2_clk_src", |
| 2376 | }, |
| 2377 | .num_parents = 1, |
| 2378 | .flags = CLK_SET_RATE_PARENT, |
| 2379 | .ops = &clk_branch2_ops, |
| 2380 | }, |
| 2381 | }, |
| 2382 | }; |
| 2383 | |
| 2384 | static struct clk_branch gcc_pdm_ahb_clk = { |
| 2385 | .halt_reg = 0x33004, |
| 2386 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2387 | .hwcg_reg = 0x33004, |
| 2388 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2389 | .clkr = { |
| 2390 | .enable_reg = 0x33004, |
| 2391 | .enable_mask = BIT(0), |
| 2392 | .hw.init = &(struct clk_init_data){ |
| 2393 | .name = "gcc_pdm_ahb_clk", |
| 2394 | .ops = &clk_branch2_ops, |
| 2395 | }, |
| 2396 | }, |
| 2397 | }; |
| 2398 | |
| 2399 | static struct clk_branch gcc_pdm_xo4_clk = { |
| 2400 | .halt_reg = 0x33008, |
| 2401 | .halt_check = BRANCH_HALT, |
| 2402 | .clkr = { |
| 2403 | .enable_reg = 0x33008, |
| 2404 | .enable_mask = BIT(0), |
| 2405 | .hw.init = &(struct clk_init_data){ |
| 2406 | .name = "gcc_pdm_xo4_clk", |
| 2407 | .ops = &clk_branch2_ops, |
| 2408 | }, |
| 2409 | }, |
| 2410 | }; |
| 2411 | |
| 2412 | static struct clk_branch gcc_prng_ahb_clk = { |
| 2413 | .halt_reg = 0x34004, |
| 2414 | .halt_check = BRANCH_HALT_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2415 | .hwcg_reg = 0x34004, |
| 2416 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2417 | .clkr = { |
| 2418 | .enable_reg = 0x52004, |
| 2419 | .enable_mask = BIT(13), |
| 2420 | .hw.init = &(struct clk_init_data){ |
| 2421 | .name = "gcc_prng_ahb_clk", |
| 2422 | .ops = &clk_branch2_ops, |
| 2423 | }, |
| 2424 | }, |
| 2425 | }; |
| 2426 | |
| 2427 | static struct clk_branch gcc_qmip_camera_ahb_clk = { |
| 2428 | .halt_reg = 0xb014, |
| 2429 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2430 | .hwcg_reg = 0xb014, |
| 2431 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2432 | .clkr = { |
| 2433 | .enable_reg = 0xb014, |
| 2434 | .enable_mask = BIT(0), |
| 2435 | .hw.init = &(struct clk_init_data){ |
| 2436 | .name = "gcc_qmip_camera_ahb_clk", |
| 2437 | .ops = &clk_branch2_ops, |
| 2438 | }, |
| 2439 | }, |
| 2440 | }; |
| 2441 | |
| 2442 | static struct clk_branch gcc_qmip_disp_ahb_clk = { |
| 2443 | .halt_reg = 0xb018, |
| 2444 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2445 | .hwcg_reg = 0xb018, |
| 2446 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2447 | .clkr = { |
| 2448 | .enable_reg = 0xb018, |
| 2449 | .enable_mask = BIT(0), |
| 2450 | .hw.init = &(struct clk_init_data){ |
| 2451 | .name = "gcc_qmip_disp_ahb_clk", |
| 2452 | .ops = &clk_branch2_ops, |
| 2453 | }, |
| 2454 | }, |
| 2455 | }; |
| 2456 | |
| 2457 | static struct clk_branch gcc_qmip_video_ahb_clk = { |
| 2458 | .halt_reg = 0xb010, |
| 2459 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2460 | .hwcg_reg = 0xb010, |
| 2461 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2462 | .clkr = { |
| 2463 | .enable_reg = 0xb010, |
| 2464 | .enable_mask = BIT(0), |
| 2465 | .hw.init = &(struct clk_init_data){ |
| 2466 | .name = "gcc_qmip_video_ahb_clk", |
| 2467 | .ops = &clk_branch2_ops, |
| 2468 | }, |
| 2469 | }, |
| 2470 | }; |
| 2471 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2472 | static struct clk_branch gcc_qupv3_wrap0_s0_clk = { |
| 2473 | .halt_reg = 0x17030, |
| 2474 | .halt_check = BRANCH_HALT_VOTED, |
| 2475 | .clkr = { |
| 2476 | .enable_reg = 0x5200c, |
| 2477 | .enable_mask = BIT(10), |
| 2478 | .hw.init = &(struct clk_init_data){ |
| 2479 | .name = "gcc_qupv3_wrap0_s0_clk", |
| 2480 | .parent_names = (const char *[]){ |
| 2481 | "gcc_qupv3_wrap0_s0_clk_src", |
| 2482 | }, |
| 2483 | .num_parents = 1, |
| 2484 | .flags = CLK_SET_RATE_PARENT, |
| 2485 | .ops = &clk_branch2_ops, |
| 2486 | }, |
| 2487 | }, |
| 2488 | }; |
| 2489 | |
| 2490 | static struct clk_branch gcc_qupv3_wrap0_s1_clk = { |
| 2491 | .halt_reg = 0x17160, |
| 2492 | .halt_check = BRANCH_HALT_VOTED, |
| 2493 | .clkr = { |
| 2494 | .enable_reg = 0x5200c, |
| 2495 | .enable_mask = BIT(11), |
| 2496 | .hw.init = &(struct clk_init_data){ |
| 2497 | .name = "gcc_qupv3_wrap0_s1_clk", |
| 2498 | .parent_names = (const char *[]){ |
| 2499 | "gcc_qupv3_wrap0_s1_clk_src", |
| 2500 | }, |
| 2501 | .num_parents = 1, |
| 2502 | .flags = CLK_SET_RATE_PARENT, |
| 2503 | .ops = &clk_branch2_ops, |
| 2504 | }, |
| 2505 | }, |
| 2506 | }; |
| 2507 | |
| 2508 | static struct clk_branch gcc_qupv3_wrap0_s2_clk = { |
| 2509 | .halt_reg = 0x17290, |
| 2510 | .halt_check = BRANCH_HALT_VOTED, |
| 2511 | .clkr = { |
| 2512 | .enable_reg = 0x5200c, |
| 2513 | .enable_mask = BIT(12), |
| 2514 | .hw.init = &(struct clk_init_data){ |
| 2515 | .name = "gcc_qupv3_wrap0_s2_clk", |
| 2516 | .parent_names = (const char *[]){ |
| 2517 | "gcc_qupv3_wrap0_s2_clk_src", |
| 2518 | }, |
| 2519 | .num_parents = 1, |
| 2520 | .flags = CLK_SET_RATE_PARENT, |
| 2521 | .ops = &clk_branch2_ops, |
| 2522 | }, |
| 2523 | }, |
| 2524 | }; |
| 2525 | |
| 2526 | static struct clk_branch gcc_qupv3_wrap0_s3_clk = { |
| 2527 | .halt_reg = 0x173c0, |
| 2528 | .halt_check = BRANCH_HALT_VOTED, |
| 2529 | .clkr = { |
| 2530 | .enable_reg = 0x5200c, |
| 2531 | .enable_mask = BIT(13), |
| 2532 | .hw.init = &(struct clk_init_data){ |
| 2533 | .name = "gcc_qupv3_wrap0_s3_clk", |
| 2534 | .parent_names = (const char *[]){ |
| 2535 | "gcc_qupv3_wrap0_s3_clk_src", |
| 2536 | }, |
| 2537 | .num_parents = 1, |
| 2538 | .flags = CLK_SET_RATE_PARENT, |
| 2539 | .ops = &clk_branch2_ops, |
| 2540 | }, |
| 2541 | }, |
| 2542 | }; |
| 2543 | |
| 2544 | static struct clk_branch gcc_qupv3_wrap0_s4_clk = { |
| 2545 | .halt_reg = 0x174f0, |
| 2546 | .halt_check = BRANCH_HALT_VOTED, |
| 2547 | .clkr = { |
| 2548 | .enable_reg = 0x5200c, |
| 2549 | .enable_mask = BIT(14), |
| 2550 | .hw.init = &(struct clk_init_data){ |
| 2551 | .name = "gcc_qupv3_wrap0_s4_clk", |
| 2552 | .parent_names = (const char *[]){ |
| 2553 | "gcc_qupv3_wrap0_s4_clk_src", |
| 2554 | }, |
| 2555 | .num_parents = 1, |
| 2556 | .flags = CLK_SET_RATE_PARENT, |
| 2557 | .ops = &clk_branch2_ops, |
| 2558 | }, |
| 2559 | }, |
| 2560 | }; |
| 2561 | |
| 2562 | static struct clk_branch gcc_qupv3_wrap0_s5_clk = { |
| 2563 | .halt_reg = 0x17620, |
| 2564 | .halt_check = BRANCH_HALT_VOTED, |
| 2565 | .clkr = { |
| 2566 | .enable_reg = 0x5200c, |
| 2567 | .enable_mask = BIT(15), |
| 2568 | .hw.init = &(struct clk_init_data){ |
| 2569 | .name = "gcc_qupv3_wrap0_s5_clk", |
| 2570 | .parent_names = (const char *[]){ |
| 2571 | "gcc_qupv3_wrap0_s5_clk_src", |
| 2572 | }, |
| 2573 | .num_parents = 1, |
| 2574 | .flags = CLK_SET_RATE_PARENT, |
| 2575 | .ops = &clk_branch2_ops, |
| 2576 | }, |
| 2577 | }, |
| 2578 | }; |
| 2579 | |
| 2580 | static struct clk_branch gcc_qupv3_wrap0_s6_clk = { |
| 2581 | .halt_reg = 0x17750, |
| 2582 | .halt_check = BRANCH_HALT_VOTED, |
| 2583 | .clkr = { |
| 2584 | .enable_reg = 0x5200c, |
| 2585 | .enable_mask = BIT(16), |
| 2586 | .hw.init = &(struct clk_init_data){ |
| 2587 | .name = "gcc_qupv3_wrap0_s6_clk", |
| 2588 | .parent_names = (const char *[]){ |
| 2589 | "gcc_qupv3_wrap0_s6_clk_src", |
| 2590 | }, |
| 2591 | .num_parents = 1, |
| 2592 | .flags = CLK_SET_RATE_PARENT, |
| 2593 | .ops = &clk_branch2_ops, |
| 2594 | }, |
| 2595 | }, |
| 2596 | }; |
| 2597 | |
| 2598 | static struct clk_branch gcc_qupv3_wrap0_s7_clk = { |
| 2599 | .halt_reg = 0x17880, |
| 2600 | .halt_check = BRANCH_HALT_VOTED, |
| 2601 | .clkr = { |
| 2602 | .enable_reg = 0x5200c, |
| 2603 | .enable_mask = BIT(17), |
| 2604 | .hw.init = &(struct clk_init_data){ |
| 2605 | .name = "gcc_qupv3_wrap0_s7_clk", |
| 2606 | .parent_names = (const char *[]){ |
| 2607 | "gcc_qupv3_wrap0_s7_clk_src", |
| 2608 | }, |
| 2609 | .num_parents = 1, |
| 2610 | .flags = CLK_SET_RATE_PARENT, |
| 2611 | .ops = &clk_branch2_ops, |
| 2612 | }, |
| 2613 | }, |
| 2614 | }; |
| 2615 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2616 | static struct clk_branch gcc_qupv3_wrap1_s0_clk = { |
| 2617 | .halt_reg = 0x18014, |
| 2618 | .halt_check = BRANCH_HALT_VOTED, |
| 2619 | .clkr = { |
| 2620 | .enable_reg = 0x5200c, |
| 2621 | .enable_mask = BIT(22), |
| 2622 | .hw.init = &(struct clk_init_data){ |
| 2623 | .name = "gcc_qupv3_wrap1_s0_clk", |
| 2624 | .parent_names = (const char *[]){ |
| 2625 | "gcc_qupv3_wrap1_s0_clk_src", |
| 2626 | }, |
| 2627 | .num_parents = 1, |
| 2628 | .flags = CLK_SET_RATE_PARENT, |
| 2629 | .ops = &clk_branch2_ops, |
| 2630 | }, |
| 2631 | }, |
| 2632 | }; |
| 2633 | |
| 2634 | static struct clk_branch gcc_qupv3_wrap1_s1_clk = { |
| 2635 | .halt_reg = 0x18144, |
| 2636 | .halt_check = BRANCH_HALT_VOTED, |
| 2637 | .clkr = { |
| 2638 | .enable_reg = 0x5200c, |
| 2639 | .enable_mask = BIT(23), |
| 2640 | .hw.init = &(struct clk_init_data){ |
| 2641 | .name = "gcc_qupv3_wrap1_s1_clk", |
| 2642 | .parent_names = (const char *[]){ |
| 2643 | "gcc_qupv3_wrap1_s1_clk_src", |
| 2644 | }, |
| 2645 | .num_parents = 1, |
| 2646 | .flags = CLK_SET_RATE_PARENT, |
| 2647 | .ops = &clk_branch2_ops, |
| 2648 | }, |
| 2649 | }, |
| 2650 | }; |
| 2651 | |
| 2652 | static struct clk_branch gcc_qupv3_wrap1_s2_clk = { |
| 2653 | .halt_reg = 0x18274, |
| 2654 | .halt_check = BRANCH_HALT_VOTED, |
| 2655 | .clkr = { |
| 2656 | .enable_reg = 0x5200c, |
| 2657 | .enable_mask = BIT(24), |
| 2658 | .hw.init = &(struct clk_init_data){ |
| 2659 | .name = "gcc_qupv3_wrap1_s2_clk", |
| 2660 | .parent_names = (const char *[]){ |
| 2661 | "gcc_qupv3_wrap1_s2_clk_src", |
| 2662 | }, |
| 2663 | .num_parents = 1, |
| 2664 | .flags = CLK_SET_RATE_PARENT, |
| 2665 | .ops = &clk_branch2_ops, |
| 2666 | }, |
| 2667 | }, |
| 2668 | }; |
| 2669 | |
| 2670 | static struct clk_branch gcc_qupv3_wrap1_s3_clk = { |
| 2671 | .halt_reg = 0x183a4, |
| 2672 | .halt_check = BRANCH_HALT_VOTED, |
| 2673 | .clkr = { |
| 2674 | .enable_reg = 0x5200c, |
| 2675 | .enable_mask = BIT(25), |
| 2676 | .hw.init = &(struct clk_init_data){ |
| 2677 | .name = "gcc_qupv3_wrap1_s3_clk", |
| 2678 | .parent_names = (const char *[]){ |
| 2679 | "gcc_qupv3_wrap1_s3_clk_src", |
| 2680 | }, |
| 2681 | .num_parents = 1, |
| 2682 | .flags = CLK_SET_RATE_PARENT, |
| 2683 | .ops = &clk_branch2_ops, |
| 2684 | }, |
| 2685 | }, |
| 2686 | }; |
| 2687 | |
| 2688 | static struct clk_branch gcc_qupv3_wrap1_s4_clk = { |
| 2689 | .halt_reg = 0x184d4, |
| 2690 | .halt_check = BRANCH_HALT_VOTED, |
| 2691 | .clkr = { |
| 2692 | .enable_reg = 0x5200c, |
| 2693 | .enable_mask = BIT(26), |
| 2694 | .hw.init = &(struct clk_init_data){ |
| 2695 | .name = "gcc_qupv3_wrap1_s4_clk", |
| 2696 | .parent_names = (const char *[]){ |
| 2697 | "gcc_qupv3_wrap1_s4_clk_src", |
| 2698 | }, |
| 2699 | .num_parents = 1, |
| 2700 | .flags = CLK_SET_RATE_PARENT, |
| 2701 | .ops = &clk_branch2_ops, |
| 2702 | }, |
| 2703 | }, |
| 2704 | }; |
| 2705 | |
| 2706 | static struct clk_branch gcc_qupv3_wrap1_s5_clk = { |
| 2707 | .halt_reg = 0x18604, |
| 2708 | .halt_check = BRANCH_HALT_VOTED, |
| 2709 | .clkr = { |
| 2710 | .enable_reg = 0x5200c, |
| 2711 | .enable_mask = BIT(27), |
| 2712 | .hw.init = &(struct clk_init_data){ |
| 2713 | .name = "gcc_qupv3_wrap1_s5_clk", |
| 2714 | .parent_names = (const char *[]){ |
| 2715 | "gcc_qupv3_wrap1_s5_clk_src", |
| 2716 | }, |
| 2717 | .num_parents = 1, |
| 2718 | .flags = CLK_SET_RATE_PARENT, |
| 2719 | .ops = &clk_branch2_ops, |
| 2720 | }, |
| 2721 | }, |
| 2722 | }; |
| 2723 | |
| 2724 | static struct clk_branch gcc_qupv3_wrap1_s6_clk = { |
| 2725 | .halt_reg = 0x18734, |
| 2726 | .halt_check = BRANCH_HALT_VOTED, |
| 2727 | .clkr = { |
| 2728 | .enable_reg = 0x5200c, |
| 2729 | .enable_mask = BIT(28), |
| 2730 | .hw.init = &(struct clk_init_data){ |
| 2731 | .name = "gcc_qupv3_wrap1_s6_clk", |
| 2732 | .parent_names = (const char *[]){ |
| 2733 | "gcc_qupv3_wrap1_s6_clk_src", |
| 2734 | }, |
| 2735 | .num_parents = 1, |
| 2736 | .flags = CLK_SET_RATE_PARENT, |
| 2737 | .ops = &clk_branch2_ops, |
| 2738 | }, |
| 2739 | }, |
| 2740 | }; |
| 2741 | |
| 2742 | static struct clk_branch gcc_qupv3_wrap1_s7_clk = { |
| 2743 | .halt_reg = 0x18864, |
| 2744 | .halt_check = BRANCH_HALT_VOTED, |
| 2745 | .clkr = { |
| 2746 | .enable_reg = 0x5200c, |
| 2747 | .enable_mask = BIT(29), |
| 2748 | .hw.init = &(struct clk_init_data){ |
| 2749 | .name = "gcc_qupv3_wrap1_s7_clk", |
| 2750 | .parent_names = (const char *[]){ |
| 2751 | "gcc_qupv3_wrap1_s7_clk_src", |
| 2752 | }, |
| 2753 | .num_parents = 1, |
| 2754 | .flags = CLK_SET_RATE_PARENT, |
| 2755 | .ops = &clk_branch2_ops, |
| 2756 | }, |
| 2757 | }, |
| 2758 | }; |
| 2759 | |
| 2760 | static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { |
| 2761 | .halt_reg = 0x17004, |
| 2762 | .halt_check = BRANCH_HALT_VOTED, |
| 2763 | .clkr = { |
| 2764 | .enable_reg = 0x5200c, |
| 2765 | .enable_mask = BIT(6), |
| 2766 | .hw.init = &(struct clk_init_data){ |
| 2767 | .name = "gcc_qupv3_wrap_0_m_ahb_clk", |
| 2768 | .ops = &clk_branch2_ops, |
| 2769 | }, |
| 2770 | }, |
| 2771 | }; |
| 2772 | |
| 2773 | static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { |
| 2774 | .halt_reg = 0x17008, |
| 2775 | .halt_check = BRANCH_HALT_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2776 | .hwcg_reg = 0x17008, |
| 2777 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2778 | .clkr = { |
| 2779 | .enable_reg = 0x5200c, |
| 2780 | .enable_mask = BIT(7), |
| 2781 | .hw.init = &(struct clk_init_data){ |
| 2782 | .name = "gcc_qupv3_wrap_0_s_ahb_clk", |
| 2783 | .ops = &clk_branch2_ops, |
| 2784 | }, |
| 2785 | }, |
| 2786 | }; |
| 2787 | |
| 2788 | static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { |
| 2789 | .halt_reg = 0x1800c, |
| 2790 | .halt_check = BRANCH_HALT_VOTED, |
| 2791 | .clkr = { |
| 2792 | .enable_reg = 0x5200c, |
| 2793 | .enable_mask = BIT(20), |
| 2794 | .hw.init = &(struct clk_init_data){ |
| 2795 | .name = "gcc_qupv3_wrap_1_m_ahb_clk", |
| 2796 | .ops = &clk_branch2_ops, |
| 2797 | }, |
| 2798 | }, |
| 2799 | }; |
| 2800 | |
| 2801 | static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { |
| 2802 | .halt_reg = 0x18010, |
| 2803 | .halt_check = BRANCH_HALT_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2804 | .hwcg_reg = 0x18010, |
| 2805 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2806 | .clkr = { |
| 2807 | .enable_reg = 0x5200c, |
| 2808 | .enable_mask = BIT(21), |
| 2809 | .hw.init = &(struct clk_init_data){ |
| 2810 | .name = "gcc_qupv3_wrap_1_s_ahb_clk", |
| 2811 | .ops = &clk_branch2_ops, |
| 2812 | }, |
| 2813 | }, |
| 2814 | }; |
| 2815 | |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 2816 | static struct clk_branch gcc_sdcc1_ice_core_clk = { |
| 2817 | .halt_reg = 0x2600c, |
| 2818 | .halt_check = BRANCH_HALT, |
| 2819 | .clkr = { |
| 2820 | .enable_reg = 0x2600c, |
| 2821 | .enable_mask = BIT(0), |
| 2822 | .hw.init = &(struct clk_init_data){ |
| 2823 | .name = "gcc_sdcc1_ice_core_clk", |
| 2824 | .parent_names = (const char *[]){ |
| 2825 | "gcc_sdcc1_ice_core_clk_src", |
| 2826 | }, |
| 2827 | .num_parents = 1, |
| 2828 | .flags = CLK_SET_RATE_PARENT, |
| 2829 | .ops = &clk_branch2_ops, |
| 2830 | }, |
| 2831 | }, |
| 2832 | }; |
| 2833 | |
| 2834 | static struct clk_branch gcc_sdcc1_ahb_clk = { |
| 2835 | .halt_reg = 0x26008, |
| 2836 | .halt_check = BRANCH_HALT, |
| 2837 | .clkr = { |
| 2838 | .enable_reg = 0x26008, |
| 2839 | .enable_mask = BIT(0), |
| 2840 | .hw.init = &(struct clk_init_data){ |
| 2841 | .name = "gcc_sdcc1_ahb_clk", |
| 2842 | .ops = &clk_branch2_ops, |
| 2843 | }, |
| 2844 | }, |
| 2845 | }; |
| 2846 | |
| 2847 | static struct clk_branch gcc_sdcc1_apps_clk = { |
| 2848 | .halt_reg = 0x26004, |
| 2849 | .halt_check = BRANCH_HALT, |
| 2850 | .clkr = { |
| 2851 | .enable_reg = 0x26004, |
| 2852 | .enable_mask = BIT(0), |
| 2853 | .hw.init = &(struct clk_init_data){ |
| 2854 | .name = "gcc_sdcc1_apps_clk", |
| 2855 | .parent_names = (const char *[]){ |
| 2856 | "gcc_sdcc1_apps_clk_src", |
| 2857 | }, |
| 2858 | .num_parents = 1, |
| 2859 | .flags = CLK_SET_RATE_PARENT, |
| 2860 | .ops = &clk_branch2_ops, |
| 2861 | }, |
| 2862 | }, |
| 2863 | }; |
| 2864 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2865 | static struct clk_branch gcc_sdcc2_ahb_clk = { |
| 2866 | .halt_reg = 0x14008, |
| 2867 | .halt_check = BRANCH_HALT, |
| 2868 | .clkr = { |
| 2869 | .enable_reg = 0x14008, |
| 2870 | .enable_mask = BIT(0), |
| 2871 | .hw.init = &(struct clk_init_data){ |
| 2872 | .name = "gcc_sdcc2_ahb_clk", |
| 2873 | .ops = &clk_branch2_ops, |
| 2874 | }, |
| 2875 | }, |
| 2876 | }; |
| 2877 | |
| 2878 | static struct clk_branch gcc_sdcc2_apps_clk = { |
| 2879 | .halt_reg = 0x14004, |
| 2880 | .halt_check = BRANCH_HALT, |
| 2881 | .clkr = { |
| 2882 | .enable_reg = 0x14004, |
| 2883 | .enable_mask = BIT(0), |
| 2884 | .hw.init = &(struct clk_init_data){ |
| 2885 | .name = "gcc_sdcc2_apps_clk", |
| 2886 | .parent_names = (const char *[]){ |
| 2887 | "gcc_sdcc2_apps_clk_src", |
| 2888 | }, |
| 2889 | .num_parents = 1, |
| 2890 | .flags = CLK_SET_RATE_PARENT, |
| 2891 | .ops = &clk_branch2_ops, |
| 2892 | }, |
| 2893 | }, |
| 2894 | }; |
| 2895 | |
| 2896 | static struct clk_branch gcc_sdcc4_ahb_clk = { |
| 2897 | .halt_reg = 0x16008, |
| 2898 | .halt_check = BRANCH_HALT, |
| 2899 | .clkr = { |
| 2900 | .enable_reg = 0x16008, |
| 2901 | .enable_mask = BIT(0), |
| 2902 | .hw.init = &(struct clk_init_data){ |
| 2903 | .name = "gcc_sdcc4_ahb_clk", |
| 2904 | .ops = &clk_branch2_ops, |
| 2905 | }, |
| 2906 | }, |
| 2907 | }; |
| 2908 | |
| 2909 | static struct clk_branch gcc_sdcc4_apps_clk = { |
| 2910 | .halt_reg = 0x16004, |
| 2911 | .halt_check = BRANCH_HALT, |
| 2912 | .clkr = { |
| 2913 | .enable_reg = 0x16004, |
| 2914 | .enable_mask = BIT(0), |
| 2915 | .hw.init = &(struct clk_init_data){ |
| 2916 | .name = "gcc_sdcc4_apps_clk", |
| 2917 | .parent_names = (const char *[]){ |
| 2918 | "gcc_sdcc4_apps_clk_src", |
| 2919 | }, |
| 2920 | .num_parents = 1, |
| 2921 | .flags = CLK_SET_RATE_PARENT, |
| 2922 | .ops = &clk_branch2_ops, |
| 2923 | }, |
| 2924 | }, |
| 2925 | }; |
| 2926 | |
| 2927 | static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { |
| 2928 | .halt_reg = 0x414c, |
| 2929 | .halt_check = BRANCH_HALT_VOTED, |
| 2930 | .clkr = { |
| 2931 | .enable_reg = 0x52004, |
| 2932 | .enable_mask = BIT(0), |
| 2933 | .hw.init = &(struct clk_init_data){ |
| 2934 | .name = "gcc_sys_noc_cpuss_ahb_clk", |
| 2935 | .parent_names = (const char *[]){ |
| 2936 | "gcc_cpuss_ahb_clk_src", |
| 2937 | }, |
| 2938 | .num_parents = 1, |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 2939 | .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2940 | .ops = &clk_branch2_ops, |
| 2941 | }, |
| 2942 | }, |
| 2943 | }; |
| 2944 | |
| 2945 | static struct clk_branch gcc_tsif_ahb_clk = { |
| 2946 | .halt_reg = 0x36004, |
| 2947 | .halt_check = BRANCH_HALT, |
| 2948 | .clkr = { |
| 2949 | .enable_reg = 0x36004, |
| 2950 | .enable_mask = BIT(0), |
| 2951 | .hw.init = &(struct clk_init_data){ |
| 2952 | .name = "gcc_tsif_ahb_clk", |
| 2953 | .ops = &clk_branch2_ops, |
| 2954 | }, |
| 2955 | }, |
| 2956 | }; |
| 2957 | |
| 2958 | static struct clk_branch gcc_tsif_inactivity_timers_clk = { |
| 2959 | .halt_reg = 0x3600c, |
| 2960 | .halt_check = BRANCH_HALT, |
| 2961 | .clkr = { |
| 2962 | .enable_reg = 0x3600c, |
| 2963 | .enable_mask = BIT(0), |
| 2964 | .hw.init = &(struct clk_init_data){ |
| 2965 | .name = "gcc_tsif_inactivity_timers_clk", |
| 2966 | .ops = &clk_branch2_ops, |
| 2967 | }, |
| 2968 | }, |
| 2969 | }; |
| 2970 | |
| 2971 | static struct clk_branch gcc_tsif_ref_clk = { |
| 2972 | .halt_reg = 0x36008, |
| 2973 | .halt_check = BRANCH_HALT, |
| 2974 | .clkr = { |
| 2975 | .enable_reg = 0x36008, |
| 2976 | .enable_mask = BIT(0), |
| 2977 | .hw.init = &(struct clk_init_data){ |
| 2978 | .name = "gcc_tsif_ref_clk", |
| 2979 | .parent_names = (const char *[]){ |
| 2980 | "gcc_tsif_ref_clk_src", |
| 2981 | }, |
| 2982 | .num_parents = 1, |
| 2983 | .flags = CLK_SET_RATE_PARENT, |
| 2984 | .ops = &clk_branch2_ops, |
| 2985 | }, |
| 2986 | }, |
| 2987 | }; |
| 2988 | |
| 2989 | static struct clk_branch gcc_ufs_card_ahb_clk = { |
| 2990 | .halt_reg = 0x75010, |
| 2991 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2992 | .hwcg_reg = 0x75010, |
| 2993 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2994 | .clkr = { |
| 2995 | .enable_reg = 0x75010, |
| 2996 | .enable_mask = BIT(0), |
| 2997 | .hw.init = &(struct clk_init_data){ |
| 2998 | .name = "gcc_ufs_card_ahb_clk", |
| 2999 | .ops = &clk_branch2_ops, |
| 3000 | }, |
| 3001 | }, |
| 3002 | }; |
| 3003 | |
| 3004 | static struct clk_branch gcc_ufs_card_axi_clk = { |
| 3005 | .halt_reg = 0x7500c, |
| 3006 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3007 | .hwcg_reg = 0x7500c, |
| 3008 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3009 | .clkr = { |
| 3010 | .enable_reg = 0x7500c, |
| 3011 | .enable_mask = BIT(0), |
| 3012 | .hw.init = &(struct clk_init_data){ |
| 3013 | .name = "gcc_ufs_card_axi_clk", |
| 3014 | .parent_names = (const char *[]){ |
| 3015 | "gcc_ufs_card_axi_clk_src", |
| 3016 | }, |
| 3017 | .num_parents = 1, |
| 3018 | .flags = CLK_SET_RATE_PARENT, |
| 3019 | .ops = &clk_branch2_ops, |
| 3020 | }, |
| 3021 | }, |
| 3022 | }; |
| 3023 | |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3024 | static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = { |
| 3025 | .halt_reg = 0x7500c, |
| 3026 | .clkr = { |
| 3027 | .enable_reg = 0x7500c, |
| 3028 | .enable_mask = BIT(1), |
| 3029 | .hw.init = &(struct clk_init_data){ |
| 3030 | .name = "gcc_ufs_card_axi_hw_ctl_clk", |
| 3031 | .parent_names = (const char *[]){ |
| 3032 | "gcc_ufs_card_axi_clk", |
| 3033 | }, |
| 3034 | .num_parents = 1, |
| 3035 | .flags = CLK_SET_RATE_PARENT, |
| 3036 | .ops = &clk_branch2_hw_ctl_ops, |
| 3037 | }, |
| 3038 | }, |
| 3039 | }; |
| 3040 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3041 | static struct clk_branch gcc_ufs_card_clkref_clk = { |
| 3042 | .halt_reg = 0x8c004, |
| 3043 | .halt_check = BRANCH_HALT, |
| 3044 | .clkr = { |
| 3045 | .enable_reg = 0x8c004, |
| 3046 | .enable_mask = BIT(0), |
| 3047 | .hw.init = &(struct clk_init_data){ |
| 3048 | .name = "gcc_ufs_card_clkref_clk", |
| 3049 | .ops = &clk_branch2_ops, |
| 3050 | }, |
| 3051 | }, |
| 3052 | }; |
| 3053 | |
| 3054 | static struct clk_branch gcc_ufs_card_ice_core_clk = { |
| 3055 | .halt_reg = 0x75058, |
| 3056 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3057 | .hwcg_reg = 0x75058, |
| 3058 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3059 | .clkr = { |
| 3060 | .enable_reg = 0x75058, |
| 3061 | .enable_mask = BIT(0), |
| 3062 | .hw.init = &(struct clk_init_data){ |
| 3063 | .name = "gcc_ufs_card_ice_core_clk", |
| 3064 | .parent_names = (const char *[]){ |
| 3065 | "gcc_ufs_card_ice_core_clk_src", |
| 3066 | }, |
| 3067 | .num_parents = 1, |
| 3068 | .flags = CLK_SET_RATE_PARENT, |
| 3069 | .ops = &clk_branch2_ops, |
| 3070 | }, |
| 3071 | }, |
| 3072 | }; |
| 3073 | |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3074 | static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = { |
| 3075 | .halt_reg = 0x75058, |
| 3076 | .clkr = { |
| 3077 | .enable_reg = 0x75058, |
| 3078 | .enable_mask = BIT(1), |
| 3079 | .hw.init = &(struct clk_init_data){ |
| 3080 | .name = "gcc_ufs_card_ice_core_hw_ctl_clk", |
| 3081 | .parent_names = (const char *[]){ |
| 3082 | "gcc_ufs_card_ice_core_clk", |
| 3083 | }, |
| 3084 | .num_parents = 1, |
| 3085 | .flags = CLK_SET_RATE_PARENT, |
| 3086 | .ops = &clk_branch2_hw_ctl_ops, |
| 3087 | }, |
| 3088 | }, |
| 3089 | }; |
| 3090 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3091 | static struct clk_branch gcc_ufs_card_phy_aux_clk = { |
| 3092 | .halt_reg = 0x7508c, |
| 3093 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3094 | .hwcg_reg = 0x7508c, |
| 3095 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3096 | .clkr = { |
| 3097 | .enable_reg = 0x7508c, |
| 3098 | .enable_mask = BIT(0), |
| 3099 | .hw.init = &(struct clk_init_data){ |
| 3100 | .name = "gcc_ufs_card_phy_aux_clk", |
| 3101 | .parent_names = (const char *[]){ |
| 3102 | "gcc_ufs_card_phy_aux_clk_src", |
| 3103 | }, |
| 3104 | .num_parents = 1, |
| 3105 | .flags = CLK_SET_RATE_PARENT, |
| 3106 | .ops = &clk_branch2_ops, |
| 3107 | }, |
| 3108 | }, |
| 3109 | }; |
| 3110 | |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3111 | static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = { |
| 3112 | .halt_reg = 0x7508c, |
| 3113 | .clkr = { |
| 3114 | .enable_reg = 0x7508c, |
| 3115 | .enable_mask = BIT(1), |
| 3116 | .hw.init = &(struct clk_init_data){ |
| 3117 | .name = "gcc_ufs_card_phy_aux_hw_ctl_clk", |
| 3118 | .parent_names = (const char *[]){ |
| 3119 | "gcc_ufs_card_phy_aux_clk", |
| 3120 | }, |
| 3121 | .num_parents = 1, |
| 3122 | .flags = CLK_SET_RATE_PARENT, |
| 3123 | .ops = &clk_branch2_hw_ctl_ops, |
| 3124 | }, |
| 3125 | }, |
| 3126 | }; |
| 3127 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3128 | static struct clk_gate2 gcc_ufs_card_rx_symbol_0_clk = { |
| 3129 | .udelay = 500, |
| 3130 | .clkr = { |
| 3131 | .enable_reg = 0x75018, |
| 3132 | .enable_mask = BIT(0), |
| 3133 | .hw.init = &(struct clk_init_data){ |
| 3134 | .name = "gcc_ufs_card_rx_symbol_0_clk", |
| 3135 | .ops = &clk_gate2_ops, |
| 3136 | }, |
| 3137 | }, |
| 3138 | }; |
| 3139 | |
| 3140 | static struct clk_gate2 gcc_ufs_card_rx_symbol_1_clk = { |
| 3141 | .udelay = 500, |
| 3142 | .clkr = { |
| 3143 | .enable_reg = 0x750a8, |
| 3144 | .enable_mask = BIT(0), |
| 3145 | .hw.init = &(struct clk_init_data){ |
| 3146 | .name = "gcc_ufs_card_rx_symbol_1_clk", |
| 3147 | .ops = &clk_gate2_ops, |
| 3148 | }, |
| 3149 | }, |
| 3150 | }; |
| 3151 | |
| 3152 | static struct clk_gate2 gcc_ufs_card_tx_symbol_0_clk = { |
| 3153 | .udelay = 500, |
| 3154 | .clkr = { |
| 3155 | .enable_reg = 0x75014, |
| 3156 | .enable_mask = BIT(0), |
| 3157 | .hw.init = &(struct clk_init_data){ |
| 3158 | .name = "gcc_ufs_card_tx_symbol_0_clk", |
| 3159 | .ops = &clk_gate2_ops, |
| 3160 | }, |
| 3161 | }, |
| 3162 | }; |
| 3163 | |
| 3164 | static struct clk_branch gcc_ufs_card_unipro_core_clk = { |
| 3165 | .halt_reg = 0x75054, |
| 3166 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3167 | .hwcg_reg = 0x75054, |
| 3168 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3169 | .clkr = { |
| 3170 | .enable_reg = 0x75054, |
| 3171 | .enable_mask = BIT(0), |
| 3172 | .hw.init = &(struct clk_init_data){ |
| 3173 | .name = "gcc_ufs_card_unipro_core_clk", |
| 3174 | .parent_names = (const char *[]){ |
| 3175 | "gcc_ufs_card_unipro_core_clk_src", |
| 3176 | }, |
| 3177 | .num_parents = 1, |
| 3178 | .flags = CLK_SET_RATE_PARENT, |
| 3179 | .ops = &clk_branch2_ops, |
| 3180 | }, |
| 3181 | }, |
| 3182 | }; |
| 3183 | |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3184 | static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = { |
| 3185 | .halt_reg = 0x75054, |
| 3186 | .clkr = { |
| 3187 | .enable_reg = 0x75054, |
| 3188 | .enable_mask = BIT(1), |
| 3189 | .hw.init = &(struct clk_init_data){ |
| 3190 | .name = "gcc_ufs_card_unipro_core_hw_ctl_clk", |
| 3191 | .parent_names = (const char *[]){ |
| 3192 | "gcc_ufs_card_unipro_core_clk", |
| 3193 | }, |
| 3194 | .num_parents = 1, |
| 3195 | .flags = CLK_SET_RATE_PARENT, |
| 3196 | .ops = &clk_branch2_hw_ctl_ops, |
| 3197 | }, |
| 3198 | }, |
| 3199 | }; |
| 3200 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3201 | static struct clk_branch gcc_ufs_mem_clkref_clk = { |
| 3202 | .halt_reg = 0x8c000, |
| 3203 | .halt_check = BRANCH_HALT, |
| 3204 | .clkr = { |
| 3205 | .enable_reg = 0x8c000, |
| 3206 | .enable_mask = BIT(0), |
| 3207 | .hw.init = &(struct clk_init_data){ |
| 3208 | .name = "gcc_ufs_mem_clkref_clk", |
| 3209 | .ops = &clk_branch2_ops, |
| 3210 | }, |
| 3211 | }, |
| 3212 | }; |
| 3213 | |
| 3214 | static struct clk_branch gcc_ufs_phy_ahb_clk = { |
| 3215 | .halt_reg = 0x77010, |
| 3216 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3217 | .hwcg_reg = 0x77010, |
| 3218 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3219 | .clkr = { |
| 3220 | .enable_reg = 0x77010, |
| 3221 | .enable_mask = BIT(0), |
| 3222 | .hw.init = &(struct clk_init_data){ |
| 3223 | .name = "gcc_ufs_phy_ahb_clk", |
| 3224 | .ops = &clk_branch2_ops, |
| 3225 | }, |
| 3226 | }, |
| 3227 | }; |
| 3228 | |
| 3229 | static struct clk_branch gcc_ufs_phy_axi_clk = { |
| 3230 | .halt_reg = 0x7700c, |
| 3231 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3232 | .hwcg_reg = 0x7700c, |
| 3233 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3234 | .clkr = { |
| 3235 | .enable_reg = 0x7700c, |
| 3236 | .enable_mask = BIT(0), |
| 3237 | .hw.init = &(struct clk_init_data){ |
| 3238 | .name = "gcc_ufs_phy_axi_clk", |
| 3239 | .parent_names = (const char *[]){ |
| 3240 | "gcc_ufs_phy_axi_clk_src", |
| 3241 | }, |
| 3242 | .num_parents = 1, |
| 3243 | .flags = CLK_SET_RATE_PARENT, |
| 3244 | .ops = &clk_branch2_ops, |
| 3245 | }, |
| 3246 | }, |
| 3247 | }; |
| 3248 | |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3249 | static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { |
| 3250 | .halt_reg = 0x7700c, |
| 3251 | .clkr = { |
| 3252 | .enable_reg = 0x7700c, |
| 3253 | .enable_mask = BIT(1), |
| 3254 | .hw.init = &(struct clk_init_data){ |
| 3255 | .name = "gcc_ufs_phy_axi_hw_ctl_clk", |
| 3256 | .parent_names = (const char *[]){ |
| 3257 | "gcc_ufs_phy_axi_clk", |
| 3258 | }, |
| 3259 | .num_parents = 1, |
| 3260 | .flags = CLK_SET_RATE_PARENT, |
| 3261 | .ops = &clk_branch2_hw_ctl_ops, |
| 3262 | }, |
| 3263 | }, |
| 3264 | }; |
| 3265 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3266 | static struct clk_branch gcc_ufs_phy_ice_core_clk = { |
| 3267 | .halt_reg = 0x77058, |
| 3268 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3269 | .hwcg_reg = 0x77058, |
| 3270 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3271 | .clkr = { |
| 3272 | .enable_reg = 0x77058, |
| 3273 | .enable_mask = BIT(0), |
| 3274 | .hw.init = &(struct clk_init_data){ |
| 3275 | .name = "gcc_ufs_phy_ice_core_clk", |
| 3276 | .parent_names = (const char *[]){ |
| 3277 | "gcc_ufs_phy_ice_core_clk_src", |
| 3278 | }, |
| 3279 | .num_parents = 1, |
| 3280 | .flags = CLK_SET_RATE_PARENT, |
| 3281 | .ops = &clk_branch2_ops, |
| 3282 | }, |
| 3283 | }, |
| 3284 | }; |
| 3285 | |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3286 | static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { |
| 3287 | .halt_reg = 0x77058, |
| 3288 | .clkr = { |
| 3289 | .enable_reg = 0x77058, |
| 3290 | .enable_mask = BIT(1), |
| 3291 | .hw.init = &(struct clk_init_data){ |
| 3292 | .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", |
| 3293 | .parent_names = (const char *[]){ |
| 3294 | "gcc_ufs_phy_ice_core_clk", |
| 3295 | }, |
| 3296 | .num_parents = 1, |
| 3297 | .flags = CLK_SET_RATE_PARENT, |
| 3298 | .ops = &clk_branch2_hw_ctl_ops, |
| 3299 | }, |
| 3300 | }, |
| 3301 | }; |
| 3302 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3303 | static struct clk_branch gcc_ufs_phy_phy_aux_clk = { |
| 3304 | .halt_reg = 0x7708c, |
| 3305 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3306 | .hwcg_reg = 0x7708c, |
| 3307 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3308 | .clkr = { |
| 3309 | .enable_reg = 0x7708c, |
| 3310 | .enable_mask = BIT(0), |
| 3311 | .hw.init = &(struct clk_init_data){ |
| 3312 | .name = "gcc_ufs_phy_phy_aux_clk", |
| 3313 | .parent_names = (const char *[]){ |
| 3314 | "gcc_ufs_phy_phy_aux_clk_src", |
| 3315 | }, |
| 3316 | .num_parents = 1, |
| 3317 | .flags = CLK_SET_RATE_PARENT, |
| 3318 | .ops = &clk_branch2_ops, |
| 3319 | }, |
| 3320 | }, |
| 3321 | }; |
| 3322 | |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3323 | static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { |
| 3324 | .halt_reg = 0x7708c, |
| 3325 | .clkr = { |
| 3326 | .enable_reg = 0x7708c, |
| 3327 | .enable_mask = BIT(1), |
| 3328 | .hw.init = &(struct clk_init_data){ |
| 3329 | .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", |
| 3330 | .parent_names = (const char *[]){ |
| 3331 | "gcc_ufs_phy_phy_aux_clk", |
| 3332 | }, |
| 3333 | .num_parents = 1, |
| 3334 | .flags = CLK_SET_RATE_PARENT, |
| 3335 | .ops = &clk_branch2_hw_ctl_ops, |
| 3336 | }, |
| 3337 | }, |
| 3338 | }; |
| 3339 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3340 | static struct clk_gate2 gcc_ufs_phy_rx_symbol_0_clk = { |
| 3341 | .udelay = 500, |
| 3342 | .clkr = { |
| 3343 | .enable_reg = 0x77018, |
| 3344 | .enable_mask = BIT(0), |
| 3345 | .hw.init = &(struct clk_init_data){ |
| 3346 | .name = "gcc_ufs_phy_rx_symbol_0_clk", |
| 3347 | .ops = &clk_gate2_ops, |
| 3348 | }, |
| 3349 | }, |
| 3350 | }; |
| 3351 | |
| 3352 | static struct clk_gate2 gcc_ufs_phy_rx_symbol_1_clk = { |
| 3353 | .udelay = 500, |
| 3354 | .clkr = { |
| 3355 | .enable_reg = 0x770a8, |
| 3356 | .enable_mask = BIT(0), |
| 3357 | .hw.init = &(struct clk_init_data){ |
| 3358 | .name = "gcc_ufs_phy_rx_symbol_1_clk", |
| 3359 | .ops = &clk_gate2_ops, |
| 3360 | }, |
| 3361 | }, |
| 3362 | }; |
| 3363 | |
| 3364 | static struct clk_gate2 gcc_ufs_phy_tx_symbol_0_clk = { |
| 3365 | .udelay = 500, |
| 3366 | .clkr = { |
| 3367 | .enable_reg = 0x77014, |
| 3368 | .enable_mask = BIT(0), |
| 3369 | .hw.init = &(struct clk_init_data){ |
| 3370 | .name = "gcc_ufs_phy_tx_symbol_0_clk", |
| 3371 | .ops = &clk_gate2_ops, |
| 3372 | }, |
| 3373 | }, |
| 3374 | }; |
| 3375 | |
| 3376 | static struct clk_branch gcc_ufs_phy_unipro_core_clk = { |
| 3377 | .halt_reg = 0x77054, |
| 3378 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3379 | .hwcg_reg = 0x77054, |
| 3380 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3381 | .clkr = { |
| 3382 | .enable_reg = 0x77054, |
| 3383 | .enable_mask = BIT(0), |
| 3384 | .hw.init = &(struct clk_init_data){ |
| 3385 | .name = "gcc_ufs_phy_unipro_core_clk", |
| 3386 | .parent_names = (const char *[]){ |
| 3387 | "gcc_ufs_phy_unipro_core_clk_src", |
| 3388 | }, |
| 3389 | .num_parents = 1, |
| 3390 | .flags = CLK_SET_RATE_PARENT, |
| 3391 | .ops = &clk_branch2_ops, |
| 3392 | }, |
| 3393 | }, |
| 3394 | }; |
| 3395 | |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3396 | static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { |
| 3397 | .halt_reg = 0x77054, |
| 3398 | .clkr = { |
| 3399 | .enable_reg = 0x77054, |
| 3400 | .enable_mask = BIT(1), |
| 3401 | .hw.init = &(struct clk_init_data){ |
| 3402 | .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", |
| 3403 | .parent_names = (const char *[]){ |
| 3404 | "gcc_ufs_phy_unipro_core_clk", |
| 3405 | }, |
| 3406 | .num_parents = 1, |
| 3407 | .flags = CLK_SET_RATE_PARENT, |
| 3408 | .ops = &clk_branch2_hw_ctl_ops, |
| 3409 | }, |
| 3410 | }, |
| 3411 | }; |
| 3412 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3413 | static struct clk_branch gcc_usb30_prim_master_clk = { |
| 3414 | .halt_reg = 0xf00c, |
| 3415 | .halt_check = BRANCH_HALT, |
| 3416 | .clkr = { |
| 3417 | .enable_reg = 0xf00c, |
| 3418 | .enable_mask = BIT(0), |
| 3419 | .hw.init = &(struct clk_init_data){ |
| 3420 | .name = "gcc_usb30_prim_master_clk", |
| 3421 | .parent_names = (const char *[]){ |
| 3422 | "gcc_usb30_prim_master_clk_src", |
| 3423 | }, |
| 3424 | .num_parents = 1, |
| 3425 | .flags = CLK_SET_RATE_PARENT, |
| 3426 | .ops = &clk_branch2_ops, |
| 3427 | }, |
| 3428 | }, |
| 3429 | }; |
| 3430 | |
| 3431 | static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { |
| 3432 | .halt_reg = 0xf014, |
| 3433 | .halt_check = BRANCH_HALT, |
| 3434 | .clkr = { |
| 3435 | .enable_reg = 0xf014, |
| 3436 | .enable_mask = BIT(0), |
| 3437 | .hw.init = &(struct clk_init_data){ |
| 3438 | .name = "gcc_usb30_prim_mock_utmi_clk", |
| 3439 | .parent_names = (const char *[]){ |
| 3440 | "gcc_usb30_prim_mock_utmi_clk_src", |
| 3441 | }, |
| 3442 | .num_parents = 1, |
| 3443 | .flags = CLK_SET_RATE_PARENT, |
| 3444 | .ops = &clk_branch2_ops, |
| 3445 | }, |
| 3446 | }, |
| 3447 | }; |
| 3448 | |
| 3449 | static struct clk_branch gcc_usb30_prim_sleep_clk = { |
| 3450 | .halt_reg = 0xf010, |
| 3451 | .halt_check = BRANCH_HALT, |
| 3452 | .clkr = { |
| 3453 | .enable_reg = 0xf010, |
| 3454 | .enable_mask = BIT(0), |
| 3455 | .hw.init = &(struct clk_init_data){ |
| 3456 | .name = "gcc_usb30_prim_sleep_clk", |
| 3457 | .ops = &clk_branch2_ops, |
| 3458 | }, |
| 3459 | }, |
| 3460 | }; |
| 3461 | |
| 3462 | static struct clk_branch gcc_usb30_sec_master_clk = { |
| 3463 | .halt_reg = 0x1000c, |
| 3464 | .halt_check = BRANCH_HALT, |
| 3465 | .clkr = { |
| 3466 | .enable_reg = 0x1000c, |
| 3467 | .enable_mask = BIT(0), |
| 3468 | .hw.init = &(struct clk_init_data){ |
| 3469 | .name = "gcc_usb30_sec_master_clk", |
| 3470 | .parent_names = (const char *[]){ |
| 3471 | "gcc_usb30_sec_master_clk_src", |
| 3472 | }, |
| 3473 | .num_parents = 1, |
| 3474 | .flags = CLK_SET_RATE_PARENT, |
| 3475 | .ops = &clk_branch2_ops, |
| 3476 | }, |
| 3477 | }, |
| 3478 | }; |
| 3479 | |
| 3480 | static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { |
| 3481 | .halt_reg = 0x10014, |
| 3482 | .halt_check = BRANCH_HALT, |
| 3483 | .clkr = { |
| 3484 | .enable_reg = 0x10014, |
| 3485 | .enable_mask = BIT(0), |
| 3486 | .hw.init = &(struct clk_init_data){ |
| 3487 | .name = "gcc_usb30_sec_mock_utmi_clk", |
| 3488 | .parent_names = (const char *[]){ |
| 3489 | "gcc_usb30_sec_mock_utmi_clk_src", |
| 3490 | }, |
| 3491 | .num_parents = 1, |
| 3492 | .flags = CLK_SET_RATE_PARENT, |
| 3493 | .ops = &clk_branch2_ops, |
| 3494 | }, |
| 3495 | }, |
| 3496 | }; |
| 3497 | |
| 3498 | static struct clk_branch gcc_usb30_sec_sleep_clk = { |
| 3499 | .halt_reg = 0x10010, |
| 3500 | .halt_check = BRANCH_HALT, |
| 3501 | .clkr = { |
| 3502 | .enable_reg = 0x10010, |
| 3503 | .enable_mask = BIT(0), |
| 3504 | .hw.init = &(struct clk_init_data){ |
| 3505 | .name = "gcc_usb30_sec_sleep_clk", |
| 3506 | .ops = &clk_branch2_ops, |
| 3507 | }, |
| 3508 | }, |
| 3509 | }; |
| 3510 | |
| 3511 | static struct clk_branch gcc_usb3_prim_clkref_clk = { |
| 3512 | .halt_reg = 0x8c008, |
| 3513 | .halt_check = BRANCH_HALT, |
| 3514 | .clkr = { |
| 3515 | .enable_reg = 0x8c008, |
| 3516 | .enable_mask = BIT(0), |
| 3517 | .hw.init = &(struct clk_init_data){ |
| 3518 | .name = "gcc_usb3_prim_clkref_clk", |
| 3519 | .ops = &clk_branch2_ops, |
| 3520 | }, |
| 3521 | }, |
| 3522 | }; |
| 3523 | |
| 3524 | static struct clk_branch gcc_usb3_prim_phy_aux_clk = { |
| 3525 | .halt_reg = 0xf04c, |
| 3526 | .halt_check = BRANCH_HALT, |
| 3527 | .clkr = { |
| 3528 | .enable_reg = 0xf04c, |
| 3529 | .enable_mask = BIT(0), |
| 3530 | .hw.init = &(struct clk_init_data){ |
| 3531 | .name = "gcc_usb3_prim_phy_aux_clk", |
| 3532 | .parent_names = (const char *[]){ |
| 3533 | "gcc_usb3_prim_phy_aux_clk_src", |
| 3534 | }, |
| 3535 | .num_parents = 1, |
| 3536 | .flags = CLK_SET_RATE_PARENT, |
| 3537 | .ops = &clk_branch2_ops, |
| 3538 | }, |
| 3539 | }, |
| 3540 | }; |
| 3541 | |
| 3542 | static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { |
| 3543 | .halt_reg = 0xf050, |
| 3544 | .halt_check = BRANCH_HALT, |
| 3545 | .clkr = { |
| 3546 | .enable_reg = 0xf050, |
| 3547 | .enable_mask = BIT(0), |
| 3548 | .hw.init = &(struct clk_init_data){ |
| 3549 | .name = "gcc_usb3_prim_phy_com_aux_clk", |
| 3550 | .parent_names = (const char *[]){ |
| 3551 | "gcc_usb3_prim_phy_aux_clk_src", |
| 3552 | }, |
| 3553 | .num_parents = 1, |
| 3554 | .flags = CLK_SET_RATE_PARENT, |
| 3555 | .ops = &clk_branch2_ops, |
| 3556 | }, |
| 3557 | }, |
| 3558 | }; |
| 3559 | |
| 3560 | static struct clk_gate2 gcc_usb3_prim_phy_pipe_clk = { |
| 3561 | .udelay = 500, |
| 3562 | .clkr = { |
| 3563 | .enable_reg = 0xf054, |
| 3564 | .enable_mask = BIT(0), |
| 3565 | .hw.init = &(struct clk_init_data){ |
| 3566 | .name = "gcc_usb3_prim_phy_pipe_clk", |
| 3567 | .ops = &clk_gate2_ops, |
| 3568 | }, |
| 3569 | }, |
| 3570 | }; |
| 3571 | |
| 3572 | static struct clk_branch gcc_usb3_sec_clkref_clk = { |
| 3573 | .halt_reg = 0x8c028, |
| 3574 | .halt_check = BRANCH_HALT, |
| 3575 | .clkr = { |
| 3576 | .enable_reg = 0x8c028, |
| 3577 | .enable_mask = BIT(0), |
| 3578 | .hw.init = &(struct clk_init_data){ |
| 3579 | .name = "gcc_usb3_sec_clkref_clk", |
| 3580 | .ops = &clk_branch2_ops, |
| 3581 | }, |
| 3582 | }, |
| 3583 | }; |
| 3584 | |
| 3585 | static struct clk_branch gcc_usb3_sec_phy_aux_clk = { |
| 3586 | .halt_reg = 0x1004c, |
| 3587 | .halt_check = BRANCH_HALT, |
| 3588 | .clkr = { |
| 3589 | .enable_reg = 0x1004c, |
| 3590 | .enable_mask = BIT(0), |
| 3591 | .hw.init = &(struct clk_init_data){ |
| 3592 | .name = "gcc_usb3_sec_phy_aux_clk", |
| 3593 | .parent_names = (const char *[]){ |
| 3594 | "gcc_usb3_sec_phy_aux_clk_src", |
| 3595 | }, |
| 3596 | .num_parents = 1, |
| 3597 | .flags = CLK_SET_RATE_PARENT, |
| 3598 | .ops = &clk_branch2_ops, |
| 3599 | }, |
| 3600 | }, |
| 3601 | }; |
| 3602 | |
| 3603 | static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { |
| 3604 | .halt_reg = 0x10050, |
| 3605 | .halt_check = BRANCH_HALT, |
| 3606 | .clkr = { |
| 3607 | .enable_reg = 0x10050, |
| 3608 | .enable_mask = BIT(0), |
| 3609 | .hw.init = &(struct clk_init_data){ |
| 3610 | .name = "gcc_usb3_sec_phy_com_aux_clk", |
| 3611 | .parent_names = (const char *[]){ |
| 3612 | "gcc_usb3_sec_phy_aux_clk_src", |
| 3613 | }, |
| 3614 | .num_parents = 1, |
| 3615 | .flags = CLK_SET_RATE_PARENT, |
| 3616 | .ops = &clk_branch2_ops, |
| 3617 | }, |
| 3618 | }, |
| 3619 | }; |
| 3620 | |
| 3621 | static struct clk_gate2 gcc_usb3_sec_phy_pipe_clk = { |
| 3622 | .udelay = 500, |
| 3623 | .clkr = { |
| 3624 | .enable_reg = 0x10054, |
| 3625 | .enable_mask = BIT(0), |
| 3626 | .hw.init = &(struct clk_init_data){ |
| 3627 | .name = "gcc_usb3_sec_phy_pipe_clk", |
| 3628 | .ops = &clk_gate2_ops, |
| 3629 | }, |
| 3630 | }, |
| 3631 | }; |
| 3632 | |
| 3633 | static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { |
| 3634 | .halt_reg = 0x6a004, |
| 3635 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3636 | .hwcg_reg = 0x6a004, |
| 3637 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3638 | .clkr = { |
| 3639 | .enable_reg = 0x6a004, |
| 3640 | .enable_mask = BIT(0), |
| 3641 | .hw.init = &(struct clk_init_data){ |
| 3642 | .name = "gcc_usb_phy_cfg_ahb2phy_clk", |
| 3643 | .ops = &clk_branch2_ops, |
| 3644 | }, |
| 3645 | }, |
| 3646 | }; |
| 3647 | |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 3648 | static struct clk_branch gcc_vdda_vs_clk = { |
| 3649 | .halt_reg = 0x7a00c, |
| 3650 | .halt_check = BRANCH_HALT, |
| 3651 | .clkr = { |
| 3652 | .enable_reg = 0x7a00c, |
| 3653 | .enable_mask = BIT(0), |
| 3654 | .hw.init = &(struct clk_init_data){ |
| 3655 | .name = "gcc_vdda_vs_clk", |
| 3656 | .parent_names = (const char *[]){ |
| 3657 | "gcc_vsensor_clk_src", |
| 3658 | }, |
| 3659 | .num_parents = 1, |
| 3660 | .flags = CLK_SET_RATE_PARENT, |
| 3661 | .ops = &clk_branch2_ops, |
| 3662 | }, |
| 3663 | }, |
| 3664 | }; |
| 3665 | |
| 3666 | static struct clk_branch gcc_vddcx_vs_clk = { |
| 3667 | .halt_reg = 0x7a004, |
| 3668 | .halt_check = BRANCH_HALT, |
| 3669 | .clkr = { |
| 3670 | .enable_reg = 0x7a004, |
| 3671 | .enable_mask = BIT(0), |
| 3672 | .hw.init = &(struct clk_init_data){ |
| 3673 | .name = "gcc_vddcx_vs_clk", |
| 3674 | .parent_names = (const char *[]){ |
| 3675 | "gcc_vsensor_clk_src", |
| 3676 | }, |
| 3677 | .num_parents = 1, |
| 3678 | .flags = CLK_SET_RATE_PARENT, |
| 3679 | .ops = &clk_branch2_ops, |
| 3680 | }, |
| 3681 | }, |
| 3682 | }; |
| 3683 | |
| 3684 | static struct clk_branch gcc_vddmx_vs_clk = { |
| 3685 | .halt_reg = 0x7a008, |
| 3686 | .halt_check = BRANCH_HALT, |
| 3687 | .clkr = { |
| 3688 | .enable_reg = 0x7a008, |
| 3689 | .enable_mask = BIT(0), |
| 3690 | .hw.init = &(struct clk_init_data){ |
| 3691 | .name = "gcc_vddmx_vs_clk", |
| 3692 | .parent_names = (const char *[]){ |
| 3693 | "gcc_vsensor_clk_src", |
| 3694 | }, |
| 3695 | .num_parents = 1, |
| 3696 | .flags = CLK_SET_RATE_PARENT, |
| 3697 | .ops = &clk_branch2_ops, |
| 3698 | }, |
| 3699 | }, |
| 3700 | }; |
| 3701 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3702 | static struct clk_branch gcc_video_ahb_clk = { |
| 3703 | .halt_reg = 0xb004, |
| 3704 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3705 | .hwcg_reg = 0xb004, |
| 3706 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3707 | .clkr = { |
| 3708 | .enable_reg = 0xb004, |
| 3709 | .enable_mask = BIT(0), |
| 3710 | .hw.init = &(struct clk_init_data){ |
| 3711 | .name = "gcc_video_ahb_clk", |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 3712 | .flags = CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3713 | .ops = &clk_branch2_ops, |
| 3714 | }, |
| 3715 | }, |
| 3716 | }; |
| 3717 | |
| 3718 | static struct clk_branch gcc_video_axi_clk = { |
| 3719 | .halt_reg = 0xb01c, |
| 3720 | .halt_check = BRANCH_VOTED, |
| 3721 | .clkr = { |
| 3722 | .enable_reg = 0xb01c, |
| 3723 | .enable_mask = BIT(0), |
| 3724 | .hw.init = &(struct clk_init_data){ |
| 3725 | .name = "gcc_video_axi_clk", |
| 3726 | .ops = &clk_branch2_ops, |
| 3727 | }, |
| 3728 | }, |
| 3729 | }; |
| 3730 | |
| 3731 | static struct clk_branch gcc_video_xo_clk = { |
| 3732 | .halt_reg = 0xb028, |
| 3733 | .halt_check = BRANCH_HALT, |
| 3734 | .clkr = { |
| 3735 | .enable_reg = 0xb028, |
| 3736 | .enable_mask = BIT(0), |
| 3737 | .hw.init = &(struct clk_init_data){ |
| 3738 | .name = "gcc_video_xo_clk", |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 3739 | .flags = CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3740 | .ops = &clk_branch2_ops, |
| 3741 | }, |
| 3742 | }, |
| 3743 | }; |
| 3744 | |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 3745 | static struct clk_branch gcc_vs_ctrl_ahb_clk = { |
| 3746 | .halt_reg = 0x7a014, |
| 3747 | .halt_check = BRANCH_HALT, |
| 3748 | .hwcg_reg = 0x7a014, |
| 3749 | .hwcg_bit = 1, |
| 3750 | .clkr = { |
| 3751 | .enable_reg = 0x7a014, |
| 3752 | .enable_mask = BIT(0), |
| 3753 | .hw.init = &(struct clk_init_data){ |
| 3754 | .name = "gcc_vs_ctrl_ahb_clk", |
| 3755 | .ops = &clk_branch2_ops, |
| 3756 | }, |
| 3757 | }, |
| 3758 | }; |
| 3759 | |
| 3760 | static struct clk_branch gcc_vs_ctrl_clk = { |
| 3761 | .halt_reg = 0x7a010, |
| 3762 | .halt_check = BRANCH_HALT, |
| 3763 | .clkr = { |
| 3764 | .enable_reg = 0x7a010, |
| 3765 | .enable_mask = BIT(0), |
| 3766 | .hw.init = &(struct clk_init_data){ |
| 3767 | .name = "gcc_vs_ctrl_clk", |
| 3768 | .parent_names = (const char *[]){ |
| 3769 | "gcc_vs_ctrl_clk_src", |
| 3770 | }, |
| 3771 | .num_parents = 1, |
| 3772 | .flags = CLK_SET_RATE_PARENT, |
| 3773 | .ops = &clk_branch2_ops, |
| 3774 | }, |
| 3775 | }, |
| 3776 | }; |
| 3777 | |
Deepak Katragadda | d075ba3 | 2017-04-06 13:45:47 -0700 | [diff] [blame] | 3778 | struct clk_hw *gcc_sdm845_hws[] = { |
| 3779 | [MEASURE_ONLY_SNOC_CLK] = &measure_only_snoc_clk.hw, |
| 3780 | [MEASURE_ONLY_CNOC_CLK] = &measure_only_cnoc_clk.hw, |
| 3781 | [MEASURE_ONLY_BIMC_CLK] = &measure_only_bimc_clk.hw, |
| 3782 | [MEASURE_ONLY_IPA_2X_CLK] = &measure_only_ipa_2x_clk.hw, |
| 3783 | }; |
| 3784 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 3785 | static struct clk_regmap *gcc_sdm845_clocks[] = { |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3786 | [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, |
| 3787 | [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3788 | [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = |
| 3789 | &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3790 | [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3791 | [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = |
| 3792 | &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3793 | [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, |
| 3794 | [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 3795 | [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3796 | [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, |
| 3797 | [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, |
| 3798 | [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr, |
| 3799 | [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, |
| 3800 | [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, |
| 3801 | [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, |
| 3802 | [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, |
| 3803 | [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, |
| 3804 | [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, |
| 3805 | [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, |
| 3806 | [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, |
| 3807 | [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr, |
| 3808 | [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, |
| 3809 | [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, |
| 3810 | [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3811 | [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, |
| 3812 | [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, |
| 3813 | [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr, |
| 3814 | [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, |
| 3815 | [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, |
| 3816 | [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, |
| 3817 | [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, |
| 3818 | [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, |
| 3819 | [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, |
| 3820 | [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, |
| 3821 | [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, |
| 3822 | [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, |
| 3823 | [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, |
| 3824 | [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, |
| 3825 | [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, |
Deepak Katragadda | 69ba1ca | 2017-05-12 13:37:52 -0700 | [diff] [blame] | 3826 | [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3827 | [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, |
| 3828 | [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 3829 | [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3830 | [GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr, |
| 3831 | [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, |
| 3832 | [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr, |
| 3833 | [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr, |
| 3834 | [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr, |
| 3835 | [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 3836 | [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3837 | [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, |
| 3838 | [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, |
| 3839 | [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, |
| 3840 | [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr, |
| 3841 | [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, |
| 3842 | [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, |
| 3843 | [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, |
| 3844 | [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, |
| 3845 | [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, |
| 3846 | [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, |
| 3847 | [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, |
| 3848 | [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr, |
| 3849 | [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, |
| 3850 | [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, |
| 3851 | [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, |
| 3852 | [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, |
| 3853 | [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, |
| 3854 | [GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr, |
| 3855 | [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, |
| 3856 | [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, |
| 3857 | [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, |
| 3858 | [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, |
| 3859 | [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, |
| 3860 | [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, |
| 3861 | [GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr, |
| 3862 | [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, |
| 3863 | [GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3864 | [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, |
| 3865 | [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, |
| 3866 | [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, |
| 3867 | [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, |
| 3868 | [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, |
| 3869 | [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, |
| 3870 | [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, |
| 3871 | [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, |
| 3872 | [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, |
| 3873 | [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, |
| 3874 | [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, |
| 3875 | [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, |
| 3876 | [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, |
| 3877 | [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, |
| 3878 | [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, |
| 3879 | [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3880 | [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, |
| 3881 | [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, |
| 3882 | [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, |
| 3883 | [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, |
| 3884 | [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, |
| 3885 | [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, |
| 3886 | [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, |
| 3887 | [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, |
| 3888 | [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, |
| 3889 | [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, |
| 3890 | [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, |
| 3891 | [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, |
| 3892 | [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, |
| 3893 | [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, |
| 3894 | [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, |
| 3895 | [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, |
| 3896 | [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, |
| 3897 | [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, |
| 3898 | [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, |
| 3899 | [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3900 | [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, |
| 3901 | [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, |
| 3902 | [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, |
| 3903 | [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, |
| 3904 | [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, |
| 3905 | [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, |
| 3906 | [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, |
| 3907 | [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, |
| 3908 | [GCC_TSIF_INACTIVITY_TIMERS_CLK] = |
| 3909 | &gcc_tsif_inactivity_timers_clk.clkr, |
| 3910 | [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, |
| 3911 | [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr, |
| 3912 | [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, |
| 3913 | [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3914 | [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3915 | [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, |
| 3916 | [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr, |
| 3917 | [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3918 | [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = |
| 3919 | &gcc_ufs_card_ice_core_hw_ctl_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3920 | [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, |
| 3921 | [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3922 | [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = |
| 3923 | &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3924 | [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, |
| 3925 | [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, |
| 3926 | [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, |
| 3927 | [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, |
| 3928 | [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3929 | [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = |
| 3930 | &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3931 | [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = |
| 3932 | &gcc_ufs_card_unipro_core_clk_src.clkr, |
| 3933 | [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, |
| 3934 | [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, |
| 3935 | [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3936 | [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3937 | [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, |
| 3938 | [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3939 | [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = |
| 3940 | &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3941 | [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, |
| 3942 | [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3943 | [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3944 | [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, |
| 3945 | [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, |
| 3946 | [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, |
| 3947 | [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, |
| 3948 | [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3949 | [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = |
| 3950 | &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3951 | [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = |
| 3952 | &gcc_ufs_phy_unipro_core_clk_src.clkr, |
| 3953 | [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, |
| 3954 | [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, |
| 3955 | [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, |
| 3956 | [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = |
| 3957 | &gcc_usb30_prim_mock_utmi_clk_src.clkr, |
| 3958 | [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, |
| 3959 | [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, |
| 3960 | [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, |
| 3961 | [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, |
| 3962 | [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = |
| 3963 | &gcc_usb30_sec_mock_utmi_clk_src.clkr, |
| 3964 | [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, |
| 3965 | [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, |
| 3966 | [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, |
| 3967 | [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, |
| 3968 | [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, |
| 3969 | [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, |
| 3970 | [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr, |
| 3971 | [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, |
| 3972 | [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, |
| 3973 | [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, |
| 3974 | [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, |
| 3975 | [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 3976 | [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr, |
| 3977 | [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr, |
| 3978 | [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3979 | [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, |
| 3980 | [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr, |
| 3981 | [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 3982 | [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr, |
| 3983 | [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr, |
| 3984 | [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr, |
| 3985 | [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3986 | [GPLL0] = &gpll0.clkr, |
| 3987 | [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, |
Deepak Katragadda | f56802e | 2017-07-14 13:39:03 -0700 | [diff] [blame] | 3988 | [GPLL4] = &gpll4.clkr, |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 3989 | [GCC_SDCC1_AHB_CLK] = NULL, |
| 3990 | [GCC_SDCC1_APPS_CLK] = NULL, |
| 3991 | [GCC_SDCC1_ICE_CORE_CLK] = NULL, |
| 3992 | [GCC_SDCC1_APPS_CLK_SRC] = NULL, |
| 3993 | [GCC_SDCC1_ICE_CORE_CLK_SRC] = NULL, |
| 3994 | [GPLL6] = NULL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3995 | }; |
| 3996 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 3997 | static const struct qcom_reset_map gcc_sdm845_resets[] = { |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3998 | [GCC_MMSS_BCR] = { 0xb000 }, |
| 3999 | [GCC_PCIE_0_BCR] = { 0x6b000 }, |
| 4000 | [GCC_PCIE_1_BCR] = { 0x8d000 }, |
| 4001 | [GCC_PCIE_PHY_BCR] = { 0x6f000 }, |
| 4002 | [GCC_PDM_BCR] = { 0x33000 }, |
| 4003 | [GCC_PRNG_BCR] = { 0x34000 }, |
| 4004 | [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, |
| 4005 | [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, |
Deepak Katragadda | 15e9aca | 2017-03-14 14:10:59 -0700 | [diff] [blame] | 4006 | [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, |
| 4007 | [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4008 | [GCC_SDCC2_BCR] = { 0x14000 }, |
| 4009 | [GCC_SDCC4_BCR] = { 0x16000 }, |
| 4010 | [GCC_TSIF_BCR] = { 0x36000 }, |
| 4011 | [GCC_UFS_CARD_BCR] = { 0x75000 }, |
| 4012 | [GCC_UFS_PHY_BCR] = { 0x77000 }, |
| 4013 | [GCC_USB30_PRIM_BCR] = { 0xf000 }, |
| 4014 | [GCC_USB30_SEC_BCR] = { 0x10000 }, |
Deepak Katragadda | 15e9aca | 2017-03-14 14:10:59 -0700 | [diff] [blame] | 4015 | [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, |
| 4016 | [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, |
| 4017 | [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, |
| 4018 | [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, |
| 4019 | [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, |
| 4020 | [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4021 | [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, |
Deepak Katragadda | 1a64727 | 2017-04-21 14:16:44 -0700 | [diff] [blame] | 4022 | [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, |
| 4023 | [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 4024 | [GCC_SDCC1_BCR] = { 0x26000 }, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4025 | }; |
| 4026 | |
Taniya Das | 5bac2ec | 2017-04-13 15:22:34 +0530 | [diff] [blame] | 4027 | /* List of RCG clocks and corresponding flags requested for DFS Mode */ |
| 4028 | static struct clk_dfs gcc_dfs_clocks[] = { |
| 4029 | { &gcc_qupv3_wrap0_s0_clk_src, DFS_ENABLE_RCG }, |
| 4030 | { &gcc_qupv3_wrap0_s1_clk_src, DFS_ENABLE_RCG }, |
| 4031 | { &gcc_qupv3_wrap0_s2_clk_src, DFS_ENABLE_RCG }, |
| 4032 | { &gcc_qupv3_wrap0_s3_clk_src, DFS_ENABLE_RCG }, |
| 4033 | { &gcc_qupv3_wrap0_s4_clk_src, DFS_ENABLE_RCG }, |
| 4034 | { &gcc_qupv3_wrap0_s5_clk_src, DFS_ENABLE_RCG }, |
| 4035 | { &gcc_qupv3_wrap0_s6_clk_src, DFS_ENABLE_RCG }, |
| 4036 | { &gcc_qupv3_wrap0_s7_clk_src, DFS_ENABLE_RCG }, |
| 4037 | { &gcc_qupv3_wrap1_s0_clk_src, DFS_ENABLE_RCG }, |
| 4038 | { &gcc_qupv3_wrap1_s1_clk_src, DFS_ENABLE_RCG }, |
| 4039 | { &gcc_qupv3_wrap1_s2_clk_src, DFS_ENABLE_RCG }, |
| 4040 | { &gcc_qupv3_wrap1_s3_clk_src, DFS_ENABLE_RCG }, |
| 4041 | { &gcc_qupv3_wrap1_s4_clk_src, DFS_ENABLE_RCG }, |
| 4042 | { &gcc_qupv3_wrap1_s5_clk_src, DFS_ENABLE_RCG }, |
| 4043 | { &gcc_qupv3_wrap1_s6_clk_src, DFS_ENABLE_RCG }, |
| 4044 | { &gcc_qupv3_wrap1_s7_clk_src, DFS_ENABLE_RCG }, |
| 4045 | }; |
| 4046 | |
| 4047 | static const struct qcom_cc_dfs_desc gcc_sdm845_dfs_desc = { |
| 4048 | .clks = gcc_dfs_clocks, |
| 4049 | .num_clks = ARRAY_SIZE(gcc_dfs_clocks), |
| 4050 | }; |
| 4051 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4052 | static const struct regmap_config gcc_sdm845_regmap_config = { |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4053 | .reg_bits = 32, |
| 4054 | .reg_stride = 4, |
| 4055 | .val_bits = 32, |
| 4056 | .max_register = 0x182090, |
| 4057 | .fast_io = true, |
| 4058 | }; |
| 4059 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4060 | static const struct qcom_cc_desc gcc_sdm845_desc = { |
| 4061 | .config = &gcc_sdm845_regmap_config, |
| 4062 | .clks = gcc_sdm845_clocks, |
| 4063 | .num_clks = ARRAY_SIZE(gcc_sdm845_clocks), |
| 4064 | .resets = gcc_sdm845_resets, |
| 4065 | .num_resets = ARRAY_SIZE(gcc_sdm845_resets), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4066 | }; |
| 4067 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4068 | static const struct of_device_id gcc_sdm845_match_table[] = { |
| 4069 | { .compatible = "qcom,gcc-sdm845" }, |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 4070 | { .compatible = "qcom,gcc-sdm845-v2" }, |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 4071 | { .compatible = "qcom,gcc-sdm670" }, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4072 | { } |
| 4073 | }; |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4074 | MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table); |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4075 | |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 4076 | static void gcc_sdm845_fixup_sdm845v2(void) |
| 4077 | { |
| 4078 | gcc_qupv3_wrap0_s0_clk_src.freq_tbl = |
| 4079 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4080 | gcc_qupv3_wrap0_s0_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4081 | 50000000; |
| 4082 | gcc_qupv3_wrap0_s0_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4083 | 128000000; |
| 4084 | gcc_qupv3_wrap0_s1_clk_src.freq_tbl = |
| 4085 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4086 | gcc_qupv3_wrap0_s1_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4087 | 50000000; |
| 4088 | gcc_qupv3_wrap0_s1_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4089 | 128000000; |
| 4090 | gcc_qupv3_wrap0_s2_clk_src.freq_tbl = |
| 4091 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4092 | gcc_qupv3_wrap0_s2_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4093 | 50000000; |
| 4094 | gcc_qupv3_wrap0_s2_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4095 | 128000000; |
| 4096 | gcc_qupv3_wrap0_s3_clk_src.freq_tbl = |
| 4097 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4098 | gcc_qupv3_wrap0_s3_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4099 | 50000000; |
| 4100 | gcc_qupv3_wrap0_s3_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4101 | 128000000; |
| 4102 | gcc_qupv3_wrap0_s4_clk_src.freq_tbl = |
| 4103 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4104 | gcc_qupv3_wrap0_s4_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4105 | 50000000; |
| 4106 | gcc_qupv3_wrap0_s4_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4107 | 128000000; |
| 4108 | gcc_qupv3_wrap0_s5_clk_src.freq_tbl = |
| 4109 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4110 | gcc_qupv3_wrap0_s5_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4111 | 50000000; |
| 4112 | gcc_qupv3_wrap0_s5_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4113 | 128000000; |
| 4114 | gcc_qupv3_wrap0_s6_clk_src.freq_tbl = |
| 4115 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4116 | gcc_qupv3_wrap0_s6_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4117 | 50000000; |
| 4118 | gcc_qupv3_wrap0_s6_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4119 | 128000000; |
| 4120 | gcc_qupv3_wrap0_s7_clk_src.freq_tbl = |
| 4121 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4122 | gcc_qupv3_wrap0_s7_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4123 | 50000000; |
| 4124 | gcc_qupv3_wrap0_s7_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4125 | 128000000; |
| 4126 | gcc_qupv3_wrap1_s0_clk_src.freq_tbl = |
| 4127 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4128 | gcc_qupv3_wrap1_s0_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4129 | 50000000; |
| 4130 | gcc_qupv3_wrap1_s0_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4131 | 128000000; |
| 4132 | gcc_qupv3_wrap1_s1_clk_src.freq_tbl = |
| 4133 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4134 | gcc_qupv3_wrap1_s1_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4135 | 50000000; |
| 4136 | gcc_qupv3_wrap1_s1_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4137 | 128000000; |
| 4138 | gcc_qupv3_wrap1_s2_clk_src.freq_tbl = |
| 4139 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4140 | gcc_qupv3_wrap1_s2_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4141 | 50000000; |
| 4142 | gcc_qupv3_wrap1_s2_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4143 | 128000000; |
| 4144 | gcc_qupv3_wrap1_s3_clk_src.freq_tbl = |
| 4145 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4146 | gcc_qupv3_wrap1_s3_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4147 | 50000000; |
| 4148 | gcc_qupv3_wrap1_s3_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4149 | 128000000; |
| 4150 | gcc_qupv3_wrap1_s4_clk_src.freq_tbl = |
| 4151 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4152 | gcc_qupv3_wrap1_s4_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4153 | 50000000; |
| 4154 | gcc_qupv3_wrap1_s4_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4155 | 128000000; |
| 4156 | gcc_qupv3_wrap1_s5_clk_src.freq_tbl = |
| 4157 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4158 | gcc_qupv3_wrap1_s5_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4159 | 50000000; |
| 4160 | gcc_qupv3_wrap1_s5_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4161 | 128000000; |
| 4162 | gcc_qupv3_wrap1_s6_clk_src.freq_tbl = |
| 4163 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4164 | gcc_qupv3_wrap1_s6_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4165 | 50000000; |
| 4166 | gcc_qupv3_wrap1_s6_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4167 | 128000000; |
| 4168 | gcc_qupv3_wrap1_s7_clk_src.freq_tbl = |
| 4169 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4170 | gcc_qupv3_wrap1_s7_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4171 | 50000000; |
| 4172 | gcc_qupv3_wrap1_s7_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4173 | 128000000; |
| 4174 | gcc_ufs_card_axi_clk_src.freq_tbl = |
| 4175 | ftbl_gcc_ufs_card_axi_clk_src_sdm845_v2; |
| 4176 | gcc_ufs_card_axi_clk_src.clkr.hw.init->rate_max[VDD_CX_HIGH] = |
| 4177 | 240000000; |
| 4178 | gcc_ufs_phy_axi_clk_src.freq_tbl = |
| 4179 | ftbl_gcc_ufs_card_axi_clk_src_sdm845_v2; |
Deepak Katragadda | 6655540 | 2017-09-27 16:13:22 -0700 | [diff] [blame] | 4180 | gcc_vsensor_clk_src.clkr.hw.init->rate_max[VDD_CX_LOW] = 600000000; |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 4181 | } |
| 4182 | |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 4183 | static void gcc_sdm845_fixup_sdm670(void) |
| 4184 | { |
| 4185 | gcc_sdm845_fixup_sdm845v2(); |
| 4186 | |
| 4187 | gcc_sdm845_clocks[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr; |
| 4188 | gcc_sdm845_clocks[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr; |
| 4189 | gcc_sdm845_clocks[GCC_SDCC1_ICE_CORE_CLK] = |
| 4190 | &gcc_sdcc1_ice_core_clk.clkr; |
| 4191 | gcc_sdm845_clocks[GCC_SDCC1_APPS_CLK_SRC] = |
| 4192 | &gcc_sdcc1_apps_clk_src.clkr; |
| 4193 | gcc_sdm845_clocks[GCC_SDCC1_ICE_CORE_CLK_SRC] = |
| 4194 | &gcc_sdcc1_ice_core_clk_src.clkr; |
| 4195 | gcc_sdm845_clocks[GPLL6] = &gpll6.clkr; |
| 4196 | gcc_sdm845_clocks[GCC_AGGRE_UFS_CARD_AXI_CLK] = NULL; |
| 4197 | gcc_sdm845_clocks[GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = NULL; |
| 4198 | gcc_sdm845_clocks[GCC_AGGRE_USB3_SEC_AXI_CLK] = NULL; |
| 4199 | gcc_sdm845_clocks[GCC_AGGRE_NOC_PCIE_TBU_CLK] = NULL; |
| 4200 | gcc_sdm845_clocks[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = NULL; |
| 4201 | gcc_sdm845_clocks[GCC_PCIE_0_AUX_CLK] = NULL; |
| 4202 | gcc_sdm845_clocks[GCC_PCIE_0_AUX_CLK_SRC] = NULL; |
| 4203 | gcc_sdm845_clocks[GCC_PCIE_0_CFG_AHB_CLK] = NULL; |
| 4204 | gcc_sdm845_clocks[GCC_PCIE_0_CLKREF_CLK] = NULL; |
| 4205 | gcc_sdm845_clocks[GCC_PCIE_0_MSTR_AXI_CLK] = NULL; |
| 4206 | gcc_sdm845_clocks[GCC_PCIE_0_PIPE_CLK] = NULL; |
| 4207 | gcc_sdm845_clocks[GCC_PCIE_0_SLV_AXI_CLK] = NULL; |
| 4208 | gcc_sdm845_clocks[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = NULL; |
| 4209 | gcc_sdm845_clocks[GCC_PCIE_1_AUX_CLK] = NULL; |
| 4210 | gcc_sdm845_clocks[GCC_PCIE_1_AUX_CLK_SRC] = NULL; |
| 4211 | gcc_sdm845_clocks[GCC_PCIE_1_CFG_AHB_CLK] = NULL; |
| 4212 | gcc_sdm845_clocks[GCC_PCIE_1_CLKREF_CLK] = NULL; |
| 4213 | gcc_sdm845_clocks[GCC_PCIE_1_MSTR_AXI_CLK] = NULL; |
| 4214 | gcc_sdm845_clocks[GCC_PCIE_1_PIPE_CLK] = NULL; |
| 4215 | gcc_sdm845_clocks[GCC_PCIE_1_SLV_AXI_CLK] = NULL; |
| 4216 | gcc_sdm845_clocks[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = NULL; |
| 4217 | gcc_sdm845_clocks[GCC_PCIE_PHY_AUX_CLK] = NULL; |
| 4218 | gcc_sdm845_clocks[GCC_PCIE_PHY_REFGEN_CLK] = NULL; |
| 4219 | gcc_sdm845_clocks[GCC_PCIE_PHY_REFGEN_CLK_SRC] = NULL; |
| 4220 | gcc_sdm845_clocks[GCC_UFS_CARD_AHB_CLK] = NULL; |
| 4221 | gcc_sdm845_clocks[GCC_UFS_CARD_AXI_CLK] = NULL; |
| 4222 | gcc_sdm845_clocks[GCC_UFS_CARD_AXI_HW_CTL_CLK] = NULL; |
| 4223 | gcc_sdm845_clocks[GCC_UFS_CARD_AXI_CLK_SRC] = NULL; |
| 4224 | gcc_sdm845_clocks[GCC_UFS_CARD_CLKREF_CLK] = NULL; |
| 4225 | gcc_sdm845_clocks[GCC_UFS_CARD_ICE_CORE_CLK] = NULL; |
| 4226 | gcc_sdm845_clocks[GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = NULL; |
| 4227 | gcc_sdm845_clocks[GCC_UFS_CARD_ICE_CORE_CLK_SRC] = NULL; |
| 4228 | gcc_sdm845_clocks[GCC_UFS_CARD_PHY_AUX_CLK] = NULL; |
| 4229 | gcc_sdm845_clocks[GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = NULL; |
| 4230 | gcc_sdm845_clocks[GCC_UFS_CARD_PHY_AUX_CLK_SRC] = NULL; |
| 4231 | gcc_sdm845_clocks[GCC_UFS_CARD_RX_SYMBOL_0_CLK] = NULL; |
| 4232 | gcc_sdm845_clocks[GCC_UFS_CARD_RX_SYMBOL_1_CLK] = NULL; |
| 4233 | gcc_sdm845_clocks[GCC_UFS_CARD_TX_SYMBOL_0_CLK] = NULL; |
| 4234 | gcc_sdm845_clocks[GCC_UFS_CARD_UNIPRO_CORE_CLK] = NULL; |
| 4235 | gcc_sdm845_clocks[GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = NULL; |
| 4236 | gcc_sdm845_clocks[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = NULL; |
| 4237 | gcc_sdm845_clocks[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = NULL; |
| 4238 | gcc_sdm845_clocks[GCC_USB30_SEC_MASTER_CLK] = NULL; |
| 4239 | gcc_sdm845_clocks[GCC_USB30_SEC_MASTER_CLK_SRC] = NULL; |
| 4240 | gcc_sdm845_clocks[GCC_USB30_SEC_MOCK_UTMI_CLK] = NULL; |
| 4241 | gcc_sdm845_clocks[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = NULL; |
| 4242 | gcc_sdm845_clocks[GCC_USB30_SEC_SLEEP_CLK] = NULL; |
| 4243 | gcc_sdm845_clocks[GCC_USB3_SEC_CLKREF_CLK] = NULL; |
| 4244 | gcc_sdm845_clocks[GCC_USB3_SEC_PHY_AUX_CLK] = NULL; |
| 4245 | gcc_sdm845_clocks[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = NULL; |
| 4246 | gcc_sdm845_clocks[GCC_USB3_SEC_PHY_COM_AUX_CLK] = NULL; |
| 4247 | gcc_sdm845_clocks[GCC_USB3_SEC_PHY_PIPE_CLK] = NULL; |
| 4248 | |
| 4249 | gcc_cpuss_rbcpr_clk_src.freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src_sdm670; |
| 4250 | gcc_cpuss_rbcpr_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
Deepak Katragadda | 6655540 | 2017-09-27 16:13:22 -0700 | [diff] [blame] | 4251 | 50000000; |
| 4252 | gcc_sdcc2_apps_clk_src.clkr.hw.init->rate_max[VDD_CX_LOWER] = 50000000; |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 4253 | gcc_sdcc2_apps_clk_src.clkr.hw.init->rate_max[VDD_CX_LOW_L1] = |
Deepak Katragadda | 6655540 | 2017-09-27 16:13:22 -0700 | [diff] [blame] | 4254 | 100000000; |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 4255 | gcc_sdcc2_apps_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
Deepak Katragadda | 6655540 | 2017-09-27 16:13:22 -0700 | [diff] [blame] | 4256 | 201500000; |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 4257 | gcc_sdcc4_apps_clk_src.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src_sdm670; |
Deepak Katragadda | 6655540 | 2017-09-27 16:13:22 -0700 | [diff] [blame] | 4258 | gcc_sdcc4_apps_clk_src.clkr.hw.init->rate_max[VDD_CX_LOWER] = 33333333; |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 4259 | } |
| 4260 | |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 4261 | static int gcc_sdm845_fixup(struct platform_device *pdev) |
| 4262 | { |
| 4263 | const char *compat = NULL; |
| 4264 | int compatlen = 0; |
| 4265 | |
| 4266 | compat = of_get_property(pdev->dev.of_node, "compatible", &compatlen); |
| 4267 | if (!compat || (compatlen <= 0)) |
| 4268 | return -EINVAL; |
| 4269 | |
| 4270 | if (!strcmp(compat, "qcom,gcc-sdm845-v2")) |
| 4271 | gcc_sdm845_fixup_sdm845v2(); |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 4272 | else if (!strcmp(compat, "qcom,gcc-sdm670")) |
| 4273 | gcc_sdm845_fixup_sdm670(); |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 4274 | |
| 4275 | return 0; |
| 4276 | } |
| 4277 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4278 | static int gcc_sdm845_probe(struct platform_device *pdev) |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4279 | { |
Deepak Katragadda | d075ba3 | 2017-04-06 13:45:47 -0700 | [diff] [blame] | 4280 | struct clk *clk; |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4281 | struct regmap *regmap; |
Deepak Katragadda | d075ba3 | 2017-04-06 13:45:47 -0700 | [diff] [blame] | 4282 | int i, ret = 0; |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4283 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4284 | regmap = qcom_cc_map(pdev, &gcc_sdm845_desc); |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4285 | if (IS_ERR(regmap)) |
| 4286 | return PTR_ERR(regmap); |
| 4287 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4288 | vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx"); |
| 4289 | if (IS_ERR(vdd_cx.regulator[0])) { |
| 4290 | if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER)) |
| 4291 | dev_err(&pdev->dev, |
| 4292 | "Unable to get vdd_cx regulator\n"); |
| 4293 | return PTR_ERR(vdd_cx.regulator[0]); |
| 4294 | } |
| 4295 | |
| 4296 | vdd_cx_ao.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx_ao"); |
| 4297 | if (IS_ERR(vdd_cx_ao.regulator[0])) { |
| 4298 | if (!(PTR_ERR(vdd_cx_ao.regulator[0]) == -EPROBE_DEFER)) |
| 4299 | dev_err(&pdev->dev, |
| 4300 | "Unable to get vdd_cx_ao regulator\n"); |
| 4301 | return PTR_ERR(vdd_cx_ao.regulator[0]); |
| 4302 | } |
| 4303 | |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 4304 | ret = gcc_sdm845_fixup(pdev); |
| 4305 | if (ret) |
| 4306 | return ret; |
| 4307 | |
Deepak Katragadda | d075ba3 | 2017-04-06 13:45:47 -0700 | [diff] [blame] | 4308 | /* Register the dummy measurement clocks */ |
| 4309 | for (i = 0; i < ARRAY_SIZE(gcc_sdm845_hws); i++) { |
| 4310 | clk = devm_clk_register(&pdev->dev, gcc_sdm845_hws[i]); |
| 4311 | if (IS_ERR(clk)) |
| 4312 | return PTR_ERR(clk); |
| 4313 | } |
| 4314 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4315 | ret = qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap); |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4316 | if (ret) { |
| 4317 | dev_err(&pdev->dev, "Failed to register GCC clocks\n"); |
| 4318 | return ret; |
| 4319 | } |
| 4320 | |
| 4321 | /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */ |
| 4322 | regmap_update_bits(regmap, GCC_MMSS_MISC, 0x3, 0x3); |
| 4323 | regmap_update_bits(regmap, GCC_GPU_MISC, 0x3, 0x3); |
| 4324 | |
Deepak Katragadda | 5783d77 | 2017-08-04 13:33:36 -0700 | [diff] [blame] | 4325 | /* Keep this clock on all the time on SDM845 v1 */ |
| 4326 | if (of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-sdm845")) |
| 4327 | clk_prepare_enable(gcc_aggre_noc_pcie_tbu_clk.clkr.hw.clk); |
| 4328 | |
Taniya Das | 5bac2ec | 2017-04-13 15:22:34 +0530 | [diff] [blame] | 4329 | /* DFS clock registration */ |
| 4330 | ret = qcom_cc_register_rcg_dfs(pdev, &gcc_sdm845_dfs_desc); |
| 4331 | if (ret) |
| 4332 | dev_err(&pdev->dev, "Failed to register with DFS!\n"); |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4333 | |
| 4334 | dev_info(&pdev->dev, "Registered GCC clocks\n"); |
| 4335 | return ret; |
| 4336 | } |
| 4337 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4338 | static struct platform_driver gcc_sdm845_driver = { |
| 4339 | .probe = gcc_sdm845_probe, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4340 | .driver = { |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4341 | .name = "gcc-sdm845", |
| 4342 | .of_match_table = gcc_sdm845_match_table, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4343 | }, |
| 4344 | }; |
| 4345 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4346 | static int __init gcc_sdm845_init(void) |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4347 | { |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4348 | return platform_driver_register(&gcc_sdm845_driver); |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4349 | } |
Deepak Katragadda | ef44e10 | 2017-06-21 10:30:46 -0700 | [diff] [blame] | 4350 | subsys_initcall(gcc_sdm845_init); |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4351 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4352 | static void __exit gcc_sdm845_exit(void) |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4353 | { |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4354 | platform_driver_unregister(&gcc_sdm845_driver); |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4355 | } |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4356 | module_exit(gcc_sdm845_exit); |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4357 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4358 | MODULE_DESCRIPTION("QTI GCC SDM845 Driver"); |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4359 | MODULE_LICENSE("GPL v2"); |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4360 | MODULE_ALIAS("platform:gcc-sdm845"); |