Greg Ungerer | 2fba4f0 | 2009-04-27 15:38:03 +1000 | [diff] [blame] | 1 | /* |
Philippe De Muyter | 03cbc385 | 2010-08-19 19:04:58 +0200 | [diff] [blame] | 2 | * intc-2.c |
| 3 | * |
Philippe De Muyter | 8851338 | 2010-09-01 15:23:28 +0200 | [diff] [blame] | 4 | * General interrupt controller code for the many ColdFire cores that use |
| 5 | * interrupt controllers with 63 interrupt sources, organized as 56 fully- |
| 6 | * programmable + 7 fixed-level interrupt sources. This includes the 523x |
| 7 | * family, the 5270, 5271, 5274, 5275, and the 528x family which have two such |
| 8 | * controllers, and the 547x and 548x families which have only one of them. |
Greg Ungerer | 2fba4f0 | 2009-04-27 15:38:03 +1000 | [diff] [blame] | 9 | * |
| 10 | * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com> |
| 11 | * |
| 12 | * This file is subject to the terms and conditions of the GNU General Public |
| 13 | * License. See the file COPYING in the main directory of this archive |
| 14 | * for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/types.h> |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/irq.h> |
| 22 | #include <linux/io.h> |
| 23 | #include <asm/coldfire.h> |
| 24 | #include <asm/mcfsim.h> |
| 25 | #include <asm/traps.h> |
| 26 | |
| 27 | /* |
Philippe De Muyter | 8851338 | 2010-09-01 15:23:28 +0200 | [diff] [blame] | 28 | * Bit definitions for the ICR family of registers. |
Greg Ungerer | 2fba4f0 | 2009-04-27 15:38:03 +1000 | [diff] [blame] | 29 | */ |
Philippe De Muyter | 8851338 | 2010-09-01 15:23:28 +0200 | [diff] [blame] | 30 | #define MCFSIM_ICR_LEVEL(l) ((l)<<3) /* Level l intr */ |
| 31 | #define MCFSIM_ICR_PRI(p) (p) /* Priority p intr */ |
| 32 | |
| 33 | /* |
| 34 | * Each vector needs a unique priority and level associated with it. |
| 35 | * We don't really care so much what they are, we don't rely on the |
| 36 | * traditional priority interrupt scheme of the m68k/ColdFire. |
| 37 | */ |
| 38 | static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6); |
| 39 | |
| 40 | #ifdef MCFICM_INTC1 |
| 41 | #define NR_VECS 128 |
| 42 | #else |
| 43 | #define NR_VECS 64 |
| 44 | #endif |
Greg Ungerer | 2fba4f0 | 2009-04-27 15:38:03 +1000 | [diff] [blame] | 45 | |
Thomas Gleixner | 0bc0f3a | 2011-02-06 23:39:14 +0000 | [diff] [blame] | 46 | static void intc_irq_mask(struct irq_data *d) |
Greg Ungerer | 2fba4f0 | 2009-04-27 15:38:03 +1000 | [diff] [blame] | 47 | { |
Greg Ungerer | 49bc6de | 2011-03-07 17:21:43 +1000 | [diff] [blame^] | 48 | unsigned int irq = d->irq - MCFINT_VECBASE; |
| 49 | unsigned long imraddr; |
| 50 | u32 val, imrbit; |
Thomas Gleixner | 0bc0f3a | 2011-02-06 23:39:14 +0000 | [diff] [blame] | 51 | |
Philippe De Muyter | 8851338 | 2010-09-01 15:23:28 +0200 | [diff] [blame] | 52 | #ifdef MCFICM_INTC1 |
Greg Ungerer | 49bc6de | 2011-03-07 17:21:43 +1000 | [diff] [blame^] | 53 | imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; |
Philippe De Muyter | 8851338 | 2010-09-01 15:23:28 +0200 | [diff] [blame] | 54 | #else |
Greg Ungerer | 49bc6de | 2011-03-07 17:21:43 +1000 | [diff] [blame^] | 55 | imraddr = MCFICM_INTC0; |
Philippe De Muyter | 8851338 | 2010-09-01 15:23:28 +0200 | [diff] [blame] | 56 | #endif |
Greg Ungerer | 49bc6de | 2011-03-07 17:21:43 +1000 | [diff] [blame^] | 57 | imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL; |
| 58 | imrbit = 0x1 << (irq & 0x1f); |
Greg Ungerer | 2fba4f0 | 2009-04-27 15:38:03 +1000 | [diff] [blame] | 59 | |
Greg Ungerer | 49bc6de | 2011-03-07 17:21:43 +1000 | [diff] [blame^] | 60 | val = __raw_readl(imraddr); |
| 61 | __raw_writel(val | imrbit, imraddr); |
Greg Ungerer | 2fba4f0 | 2009-04-27 15:38:03 +1000 | [diff] [blame] | 62 | } |
| 63 | |
Thomas Gleixner | 0bc0f3a | 2011-02-06 23:39:14 +0000 | [diff] [blame] | 64 | static void intc_irq_unmask(struct irq_data *d) |
Greg Ungerer | 2fba4f0 | 2009-04-27 15:38:03 +1000 | [diff] [blame] | 65 | { |
Greg Ungerer | 49bc6de | 2011-03-07 17:21:43 +1000 | [diff] [blame^] | 66 | unsigned int irq = d->irq - MCFINT_VECBASE; |
| 67 | unsigned long intaddr, imraddr, icraddr; |
| 68 | u32 val, imrbit; |
Thomas Gleixner | 0bc0f3a | 2011-02-06 23:39:14 +0000 | [diff] [blame] | 69 | |
Philippe De Muyter | 8851338 | 2010-09-01 15:23:28 +0200 | [diff] [blame] | 70 | #ifdef MCFICM_INTC1 |
Greg Ungerer | 49bc6de | 2011-03-07 17:21:43 +1000 | [diff] [blame^] | 71 | intaddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; |
Philippe De Muyter | 8851338 | 2010-09-01 15:23:28 +0200 | [diff] [blame] | 72 | #else |
Greg Ungerer | 49bc6de | 2011-03-07 17:21:43 +1000 | [diff] [blame^] | 73 | intaddr = MCFICM_INTC0; |
Philippe De Muyter | 8851338 | 2010-09-01 15:23:28 +0200 | [diff] [blame] | 74 | #endif |
Greg Ungerer | 49bc6de | 2011-03-07 17:21:43 +1000 | [diff] [blame^] | 75 | imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL); |
| 76 | icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f); |
| 77 | imrbit = 0x1 << (irq & 0x1f); |
Greg Ungerer | 2fba4f0 | 2009-04-27 15:38:03 +1000 | [diff] [blame] | 78 | |
Greg Ungerer | 49bc6de | 2011-03-07 17:21:43 +1000 | [diff] [blame^] | 79 | /* Don't set the "maskall" bit! */ |
| 80 | if ((irq & 0x20) == 0) |
| 81 | imrbit |= 0x1; |
Greg Ungerer | 2fba4f0 | 2009-04-27 15:38:03 +1000 | [diff] [blame] | 82 | |
Greg Ungerer | 49bc6de | 2011-03-07 17:21:43 +1000 | [diff] [blame^] | 83 | if (__raw_readb(icraddr) == 0) |
| 84 | __raw_writeb(intc_intpri--, icraddr); |
Greg Ungerer | 2fba4f0 | 2009-04-27 15:38:03 +1000 | [diff] [blame] | 85 | |
Greg Ungerer | 49bc6de | 2011-03-07 17:21:43 +1000 | [diff] [blame^] | 86 | val = __raw_readl(imraddr); |
| 87 | __raw_writel(val & ~imrbit, imraddr); |
Greg Ungerer | 2fba4f0 | 2009-04-27 15:38:03 +1000 | [diff] [blame] | 88 | } |
| 89 | |
Thomas Gleixner | 0bc0f3a | 2011-02-06 23:39:14 +0000 | [diff] [blame] | 90 | static int intc_irq_set_type(struct irq_data *d, unsigned int type) |
Greg Ungerer | 04570b4 | 2010-09-09 17:12:53 +1000 | [diff] [blame] | 91 | { |
| 92 | return 0; |
| 93 | } |
| 94 | |
Greg Ungerer | 2fba4f0 | 2009-04-27 15:38:03 +1000 | [diff] [blame] | 95 | static struct irq_chip intc_irq_chip = { |
| 96 | .name = "CF-INTC", |
Thomas Gleixner | 0bc0f3a | 2011-02-06 23:39:14 +0000 | [diff] [blame] | 97 | .irq_mask = intc_irq_mask, |
| 98 | .irq_unmask = intc_irq_unmask, |
| 99 | .irq_set_type = intc_irq_set_type, |
Greg Ungerer | 2fba4f0 | 2009-04-27 15:38:03 +1000 | [diff] [blame] | 100 | }; |
| 101 | |
| 102 | void __init init_IRQ(void) |
| 103 | { |
| 104 | int irq; |
| 105 | |
| 106 | init_vectors(); |
| 107 | |
| 108 | /* Mask all interrupt sources */ |
Greg Ungerer | 254eef7 | 2011-03-05 22:17:17 +1000 | [diff] [blame] | 109 | __raw_writel(0x1, MCFICM_INTC0 + MCFINTC_IMRL); |
Philippe De Muyter | 8851338 | 2010-09-01 15:23:28 +0200 | [diff] [blame] | 110 | #ifdef MCFICM_INTC1 |
Greg Ungerer | 254eef7 | 2011-03-05 22:17:17 +1000 | [diff] [blame] | 111 | __raw_writel(0x1, MCFICM_INTC1 + MCFINTC_IMRL); |
Philippe De Muyter | 8851338 | 2010-09-01 15:23:28 +0200 | [diff] [blame] | 112 | #endif |
Greg Ungerer | 2fba4f0 | 2009-04-27 15:38:03 +1000 | [diff] [blame] | 113 | |
Greg Ungerer | 49bc6de | 2011-03-07 17:21:43 +1000 | [diff] [blame^] | 114 | for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) { |
Greg Ungerer | 04570b4 | 2010-09-09 17:12:53 +1000 | [diff] [blame] | 115 | set_irq_chip(irq, &intc_irq_chip); |
| 116 | set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); |
| 117 | set_irq_handler(irq, handle_level_irq); |
Greg Ungerer | 2fba4f0 | 2009-04-27 15:38:03 +1000 | [diff] [blame] | 118 | } |
| 119 | } |
| 120 | |