blob: 80b777e4247b168644ca75691de11ea9d17e6edb [file] [log] [blame]
Sergei Shtylyov60e7a822007-05-05 22:03:49 +02001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 * Due to massive hardware bugs, UltraDMA is only supported
4 * on the 646U2 and not on the 646U.
5 *
6 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
8 *
9 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
Sergei Shtylyovf92d50e62007-03-03 17:48:53 +010010 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 */
12
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#include <linux/module.h>
14#include <linux/types.h>
15#include <linux/pci.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070016#include <linux/ide.h>
17#include <linux/init.h>
18
19#include <asm/io.h>
20
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +020021#define DRV_NAME "cmd64x"
22
Linus Torvalds1da177e2005-04-16 15:20:36 -070023#define CMD_DEBUG 0
24
25#if CMD_DEBUG
26#define cmdprintk(x...) printk(x)
27#else
28#define cmdprintk(x...)
29#endif
30
31/*
32 * CMD64x specific registers definition.
33 */
34#define CFR 0x50
Sergei Shtylyove51e2522007-05-05 22:03:49 +020035#define CFR_INTR_CH0 0x04
Linus Torvalds1da177e2005-04-16 15:20:36 -070036
37#define CMDTIM 0x52
38#define ARTTIM0 0x53
39#define DRWTIM0 0x54
40#define ARTTIM1 0x55
41#define DRWTIM1 0x56
42#define ARTTIM23 0x57
43#define ARTTIM23_DIS_RA2 0x04
44#define ARTTIM23_DIS_RA3 0x08
45#define ARTTIM23_INTR_CH1 0x10
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#define DRWTIM2 0x58
47#define BRST 0x59
48#define DRWTIM3 0x5b
49
50#define BMIDECR0 0x70
51#define MRDMODE 0x71
52#define MRDMODE_INTR_CH0 0x04
53#define MRDMODE_INTR_CH1 0x08
Linus Torvalds1da177e2005-04-16 15:20:36 -070054#define UDIDETCR0 0x73
55#define DTPR0 0x74
56#define BMIDECR1 0x78
57#define BMIDECSR 0x79
Linus Torvalds1da177e2005-04-16 15:20:36 -070058#define UDIDETCR1 0x7B
59#define DTPR1 0x7C
60
Sergei Shtylyove277a1a2007-03-17 21:57:24 +010061static u8 quantize_timing(int timing, int quant)
62{
63 return (timing + quant - 1) / quant;
64}
65
Linus Torvalds1da177e2005-04-16 15:20:36 -070066/*
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020067 * This routine calculates active/recovery counts and then writes them into
68 * the chipset registers.
Linus Torvalds1da177e2005-04-16 15:20:36 -070069 */
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020070static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
Linus Torvalds1da177e2005-04-16 15:20:36 -070071{
Bartlomiej Zolnierkiewiczebae41a2008-04-27 15:38:29 +020072 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
Bartlomiej Zolnierkiewicz30e5ee42008-07-15 21:21:46 +020073 int clock_time = 1000 / (ide_pci_clk ? ide_pci_clk : 33);
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020074 u8 cycle_count, active_count, recovery_count, drwtim;
75 static const u8 recovery_values[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -070076 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020077 static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
Linus Torvalds1da177e2005-04-16 15:20:36 -070078
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020079 cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
80 cycle_time, active_time);
81
82 cycle_count = quantize_timing( cycle_time, clock_time);
83 active_count = quantize_timing(active_time, clock_time);
84 recovery_count = cycle_count - active_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -070085
86 /*
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020087 * In case we've got too long recovery phase, try to lengthen
88 * the active phase
Linus Torvalds1da177e2005-04-16 15:20:36 -070089 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070090 if (recovery_count > 16) {
91 active_count += recovery_count - 16;
92 recovery_count = 16;
93 }
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020094 if (active_count > 16) /* shouldn't actually happen... */
95 active_count = 16;
Linus Torvalds1da177e2005-04-16 15:20:36 -070096
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020097 cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
98 cycle_count, active_count, recovery_count);
Linus Torvalds1da177e2005-04-16 15:20:36 -070099
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200100 /*
101 * Convert values to internal chipset representation
102 */
103 recovery_count = recovery_values[recovery_count];
104 active_count &= 0x0f;
105
106 /* Program the active/recovery counts into the DRWTIM register */
107 drwtim = (active_count << 4) | recovery_count;
108 (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
109 cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
110}
111
112/*
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200113 * This routine writes into the chipset registers
114 * PIO setup/active/recovery timings.
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200115 */
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200116static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200117{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100118 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100119 struct pci_dev *dev = to_pci_dev(hwif->dev);
Bartlomiej Zolnierkiewicz86a0e122008-07-16 20:33:38 +0200120 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200121 unsigned int cycle_time;
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200122 u8 setup_count, arttim = 0;
123
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200124 static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
125 static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200126
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200127 cycle_time = ide_pio_cycle_time(drive, pio);
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200128
Bartlomiej Zolnierkiewicz86a0e122008-07-16 20:33:38 +0200129 program_cycle_times(drive, cycle_time, t->active);
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200130
Bartlomiej Zolnierkiewicz86a0e122008-07-16 20:33:38 +0200131 setup_count = quantize_timing(t->setup,
Bartlomiej Zolnierkiewicz30e5ee42008-07-15 21:21:46 +0200132 1000 / (ide_pci_clk ? ide_pci_clk : 33));
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200133
134 /*
135 * The primary channel has individual address setup timing registers
136 * for each drive and the hardware selects the slowest timing itself.
137 * The secondary channel has one common register and we have to select
138 * the slowest address setup timing ourselves.
139 */
140 if (hwif->channel) {
Bartlomiej Zolnierkiewicz5d44a152009-01-06 17:20:55 +0100141 ide_drive_t *pair = ide_get_pair_dev(drive);
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200142
143 drive->drive_data = setup_count;
Bartlomiej Zolnierkiewicz5d44a152009-01-06 17:20:55 +0100144
145 if (pair)
146 setup_count = max_t(u8, setup_count, pair->drive_data);
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200147 }
148
149 if (setup_count > 5) /* shouldn't actually happen... */
150 setup_count = 5;
151 cmdprintk("Final address setup count: %d\n", setup_count);
152
153 /*
154 * Program the address setup clocks into the ARTTIM registers.
155 * Avoid clearing the secondary channel's interrupt bit.
156 */
157 (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
158 if (hwif->channel)
159 arttim &= ~ARTTIM23_INTR_CH1;
160 arttim &= ~0xc0;
161 arttim |= setup_values[setup_count];
162 (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
163 cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
Sergei Shtylyovf92d50e62007-03-03 17:48:53 +0100164}
165
166/*
167 * Attempts to set drive's PIO mode.
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200168 * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
Sergei Shtylyovf92d50e62007-03-03 17:48:53 +0100169 */
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200170
171static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio)
Sergei Shtylyovf92d50e62007-03-03 17:48:53 +0100172{
173 /*
174 * Filter out the prefetch control values
175 * to prevent PIO5 from being programmed
176 */
177 if (pio == 8 || pio == 9)
178 return;
179
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200180 cmd64x_tune_pio(drive, pio);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181}
182
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200183static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100185 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100186 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200187 u8 unit = drive->dn & 0x01;
188 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189
Sergei Shtylyovf92d50e62007-03-03 17:48:53 +0100190 if (speed >= XFER_SW_DMA_0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191 (void) pci_read_config_byte(dev, pciU, &regU);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192 regU &= ~(unit ? 0xCA : 0x35);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193 }
194
195 switch(speed) {
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200196 case XFER_UDMA_5:
197 regU |= unit ? 0x0A : 0x05;
198 break;
199 case XFER_UDMA_4:
200 regU |= unit ? 0x4A : 0x15;
201 break;
202 case XFER_UDMA_3:
203 regU |= unit ? 0x8A : 0x25;
204 break;
205 case XFER_UDMA_2:
206 regU |= unit ? 0x42 : 0x11;
207 break;
208 case XFER_UDMA_1:
209 regU |= unit ? 0x82 : 0x21;
210 break;
211 case XFER_UDMA_0:
212 regU |= unit ? 0xC2 : 0x31;
213 break;
214 case XFER_MW_DMA_2:
215 program_cycle_times(drive, 120, 70);
216 break;
217 case XFER_MW_DMA_1:
218 program_cycle_times(drive, 150, 80);
219 break;
220 case XFER_MW_DMA_0:
221 program_cycle_times(drive, 480, 215);
222 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700223 }
224
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200225 if (speed >= XFER_SW_DMA_0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226 (void) pci_write_config_byte(dev, pciU, regU);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227}
228
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200229static int cmd648_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100231 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100232 unsigned long base = hwif->dma_base - (hwif->channel * 8);
Bartlomiej Zolnierkiewicz653bcf52008-10-13 21:39:46 +0200233 int err = ide_dma_end(drive);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200234 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
235 MRDMODE_INTR_CH0;
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100236 u8 mrdmode = inb(base + 1);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200237
238 /* clear the interrupt bit */
Sergei Shtylyov61832892007-11-13 22:09:14 +0100239 outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100240 base + 1);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200241
242 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243}
244
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200245static int cmd64x_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100247 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100248 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200249 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
250 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
251 CFR_INTR_CH0;
252 u8 irq_stat = 0;
Bartlomiej Zolnierkiewicz653bcf52008-10-13 21:39:46 +0200253 int err = ide_dma_end(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200255 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
256 /* clear the interrupt bit */
257 (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
258
259 return err;
260}
261
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200262static int cmd648_dma_test_irq(ide_drive_t *drive)
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200263{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100264 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100265 unsigned long base = hwif->dma_base - (hwif->channel * 8);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200266 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
267 MRDMODE_INTR_CH0;
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200268 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100269 u8 mrdmode = inb(base + 1);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200270
271#ifdef DEBUG
272 printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n",
273 drive->name, dma_stat, mrdmode, irq_mask);
274#endif
275 if (!(mrdmode & irq_mask))
276 return 0;
277
278 /* return 1 if INTR asserted */
279 if (dma_stat & 4)
280 return 1;
281
282 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700283}
284
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200285static int cmd64x_dma_test_irq(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700286{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100287 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100288 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200289 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
290 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
291 CFR_INTR_CH0;
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200292 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200293 u8 irq_stat = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294
Sergei Shtylyove51e2522007-05-05 22:03:49 +0200295 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
296
Linus Torvalds1da177e2005-04-16 15:20:36 -0700297#ifdef DEBUG
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200298 printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n",
299 drive->name, dma_stat, irq_stat, irq_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700300#endif
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200301 if (!(irq_stat & irq_mask))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700302 return 0;
303
304 /* return 1 if INTR asserted */
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200305 if (dma_stat & 4)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700306 return 1;
307
308 return 0;
309}
310
311/*
312 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
313 * event order for DMA transfers.
314 */
315
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200316static int cmd646_1_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700317{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100318 ide_hwif_t *hwif = drive->hwif;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319 u8 dma_stat = 0, dma_cmd = 0;
320
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321 /* get DMA status */
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200322 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323 /* read DMA command state */
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200324 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325 /* stop DMA */
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200326 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700327 /* clear the INTR & ERROR bits */
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200328 outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329 /* verify good DMA status */
330 return (dma_stat & 7) != 4;
331}
332
Bartlomiej Zolnierkiewicz2ed0ef52009-03-24 23:22:53 +0100333static int init_chipset_cmd64x(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700335 u8 mrdmode = 0;
336
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337 /* Set a good latency timer and cache line size value. */
338 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
339 /* FIXME: pci_set_master() to ensure a good latency timer value */
340
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200341 /*
342 * Enable interrupts, select MEMORY READ LINE for reads.
343 *
344 * NOTE: although not mentioned in the PCI0646U specs,
345 * bits 0-1 are write only and won't be read back as
346 * set or not -- PCI0646U2 specs clarify this point.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700347 */
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200348 (void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
349 mrdmode &= ~0x30;
350 (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351
Linus Torvalds1da177e2005-04-16 15:20:36 -0700352 return 0;
353}
354
Bartlomiej Zolnierkiewiczf454cbe2008-08-05 18:17:04 +0200355static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100357 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200358 u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200360 switch (dev->device) {
361 case PCI_DEVICE_ID_CMD_648:
362 case PCI_DEVICE_ID_CMD_649:
363 pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
Bartlomiej Zolnierkiewicz49521f92007-07-09 23:17:58 +0200364 return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200365 default:
Bartlomiej Zolnierkiewicz49521f92007-07-09 23:17:58 +0200366 return ATA_CBL_PATA40;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700368}
369
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200370static const struct ide_port_ops cmd64x_port_ops = {
371 .set_pio_mode = cmd64x_set_pio_mode,
372 .set_dma_mode = cmd64x_set_dma_mode,
373 .cable_detect = cmd64x_cable_detect,
374};
375
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200376static const struct ide_dma_ops cmd64x_dma_ops = {
377 .dma_host_set = ide_dma_host_set,
378 .dma_setup = ide_dma_setup,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200379 .dma_start = ide_dma_start,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200380 .dma_end = cmd64x_dma_end,
381 .dma_test_irq = cmd64x_dma_test_irq,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200382 .dma_lost_irq = ide_dma_lost_irq,
Bartlomiej Zolnierkiewicz22117d62009-03-27 12:46:47 +0100383 .dma_timer_expiry = ide_dma_sff_timer_expiry,
Sergei Shtylyov592b5312009-01-06 17:21:02 +0100384 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200385};
386
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200387static const struct ide_dma_ops cmd646_rev1_dma_ops = {
388 .dma_host_set = ide_dma_host_set,
389 .dma_setup = ide_dma_setup,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200390 .dma_start = ide_dma_start,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200391 .dma_end = cmd646_1_dma_end,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200392 .dma_test_irq = ide_dma_test_irq,
393 .dma_lost_irq = ide_dma_lost_irq,
Bartlomiej Zolnierkiewicz22117d62009-03-27 12:46:47 +0100394 .dma_timer_expiry = ide_dma_sff_timer_expiry,
Sergei Shtylyov592b5312009-01-06 17:21:02 +0100395 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200396};
397
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200398static const struct ide_dma_ops cmd648_dma_ops = {
399 .dma_host_set = ide_dma_host_set,
400 .dma_setup = ide_dma_setup,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200401 .dma_start = ide_dma_start,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200402 .dma_end = cmd648_dma_end,
403 .dma_test_irq = cmd648_dma_test_irq,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200404 .dma_lost_irq = ide_dma_lost_irq,
Bartlomiej Zolnierkiewicz22117d62009-03-27 12:46:47 +0100405 .dma_timer_expiry = ide_dma_sff_timer_expiry,
Sergei Shtylyov592b5312009-01-06 17:21:02 +0100406 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200407};
408
Bartlomiej Zolnierkiewicz85620432007-10-20 00:32:34 +0200409static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200410 { /* 0: CMD643 */
411 .name = DRV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412 .init_chipset = init_chipset_cmd64x,
Sergei Shtylyov7accbff2007-05-05 22:03:49 +0200413 .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200414 .port_ops = &cmd64x_port_ops,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200415 .dma_ops = &cmd64x_dma_ops,
Bartlomiej Zolnierkiewicz8ac2b42a2008-02-01 23:09:30 +0100416 .host_flags = IDE_HFLAG_CLEAR_SIMPLEX |
Bartlomiej Zolnierkiewicz5e71d9c2008-04-26 17:36:35 +0200417 IDE_HFLAG_ABUSE_PREFETCH,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +0200418 .pio_mask = ATA_PIO5,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +0200419 .mwdma_mask = ATA_MWDMA2,
Bartlomiej Zolnierkiewicz18137202007-05-10 00:01:07 +0200420 .udma_mask = 0x00, /* no udma */
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200421 },
422 { /* 1: CMD646 */
423 .name = DRV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424 .init_chipset = init_chipset_cmd64x,
Sergei Shtylyov7accbff2007-05-05 22:03:49 +0200425 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200426 .port_ops = &cmd64x_port_ops,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200427 .dma_ops = &cmd648_dma_ops,
Bartlomiej Zolnierkiewicz6b5cde32008-12-29 20:27:32 +0100428 .host_flags = IDE_HFLAG_SERIALIZE |
429 IDE_HFLAG_ABUSE_PREFETCH,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +0200430 .pio_mask = ATA_PIO5,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +0200431 .mwdma_mask = ATA_MWDMA2,
432 .udma_mask = ATA_UDMA2,
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200433 },
434 { /* 2: CMD648 */
435 .name = DRV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436 .init_chipset = init_chipset_cmd64x,
Sergei Shtylyov7accbff2007-05-05 22:03:49 +0200437 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200438 .port_ops = &cmd64x_port_ops,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200439 .dma_ops = &cmd648_dma_ops,
Bartlomiej Zolnierkiewicz5e71d9c2008-04-26 17:36:35 +0200440 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +0200441 .pio_mask = ATA_PIO5,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +0200442 .mwdma_mask = ATA_MWDMA2,
443 .udma_mask = ATA_UDMA4,
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200444 },
445 { /* 3: CMD649 */
446 .name = DRV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447 .init_chipset = init_chipset_cmd64x,
Sergei Shtylyov7accbff2007-05-05 22:03:49 +0200448 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200449 .port_ops = &cmd64x_port_ops,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200450 .dma_ops = &cmd648_dma_ops,
Bartlomiej Zolnierkiewicz5e71d9c2008-04-26 17:36:35 +0200451 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +0200452 .pio_mask = ATA_PIO5,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +0200453 .mwdma_mask = ATA_MWDMA2,
454 .udma_mask = ATA_UDMA5,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455 }
456};
457
458static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
459{
Bartlomiej Zolnierkiewicz039788e2007-10-20 00:32:34 +0200460 struct ide_port_info d;
Bartlomiej Zolnierkiewiczbfd314a2007-10-19 00:30:09 +0200461 u8 idx = id->driver_data;
Sergei Shtylyov7accbff2007-05-05 22:03:49 +0200462
Bartlomiej Zolnierkiewiczbfd314a2007-10-19 00:30:09 +0200463 d = cmd64x_chipsets[idx];
464
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200465 if (idx == 1) {
466 /*
467 * UltraDMA only supported on PCI646U and PCI646U2, which
468 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
469 * Actually, although the CMD tech support people won't
470 * tell me the details, the 0x03 revision cannot support
471 * UDMA correctly without hardware modifications, and even
472 * then it only works with Quantum disks due to some
473 * hold time assumptions in the 646U part which are fixed
474 * in the 646U2.
475 *
476 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
477 */
478 if (dev->revision < 5) {
479 d.udma_mask = 0x00;
480 /*
481 * The original PCI0646 didn't have the primary
482 * channel enable bit, it appeared starting with
483 * PCI0646U (i.e. revision ID 3).
484 */
485 if (dev->revision < 3) {
486 d.enablebits[0].reg = 0;
487 if (dev->revision == 1)
488 d.dma_ops = &cmd646_rev1_dma_ops;
489 else
490 d.dma_ops = &cmd64x_dma_ops;
491 }
492 }
493 }
Bartlomiej Zolnierkiewiczbfd314a2007-10-19 00:30:09 +0200494
Bartlomiej Zolnierkiewicz6cdf6eb2008-07-24 22:53:14 +0200495 return ide_pci_init_one(dev, &d, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700496}
497
Bartlomiej Zolnierkiewicz9cbcc5e2007-10-16 22:29:56 +0200498static const struct pci_device_id cmd64x_pci_tbl[] = {
499 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
500 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
501 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
502 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503 { 0, },
504};
505MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
506
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +0200507static struct pci_driver cmd64x_pci_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508 .name = "CMD64x_IDE",
509 .id_table = cmd64x_pci_tbl,
510 .probe = cmd64x_init_one,
Bartlomiej Zolnierkiewicze2b15b42008-07-24 22:53:20 +0200511 .remove = ide_pci_remove,
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +0200512 .suspend = ide_pci_suspend,
513 .resume = ide_pci_resume,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700514};
515
Bartlomiej Zolnierkiewicz82ab1ee2007-01-27 13:46:56 +0100516static int __init cmd64x_ide_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700517{
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +0200518 return ide_pci_register_driver(&cmd64x_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519}
520
Bartlomiej Zolnierkiewicze2b15b42008-07-24 22:53:20 +0200521static void __exit cmd64x_ide_exit(void)
522{
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +0200523 pci_unregister_driver(&cmd64x_pci_driver);
Bartlomiej Zolnierkiewicze2b15b42008-07-24 22:53:20 +0200524}
525
Linus Torvalds1da177e2005-04-16 15:20:36 -0700526module_init(cmd64x_ide_init);
Bartlomiej Zolnierkiewicze2b15b42008-07-24 22:53:20 +0200527module_exit(cmd64x_ide_exit);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528
529MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
530MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
531MODULE_LICENSE("GPL");