blob: 75ba2311b54f3f37b62176a37e032c480be9f3f1 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Standard PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
Kristen Accardi8cf4c192005-08-16 15:16:10 -070026 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027 *
28 */
29
Linus Torvalds1da177e2005-04-16 15:20:36 -070030#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070033#include <linux/pci.h>
Andrew Mortond4d28dd2005-11-13 16:06:40 -080034#include <linux/interrupt.h>
35
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#include "shpchp.h"
37
Linus Torvalds1da177e2005-04-16 15:20:36 -070038/* Slot Available Register I field definition */
39#define SLOT_33MHZ 0x0000001f
40#define SLOT_66MHZ_PCIX 0x00001f00
41#define SLOT_100MHZ_PCIX 0x001f0000
42#define SLOT_133MHZ_PCIX 0x1f000000
43
44/* Slot Available Register II field definition */
45#define SLOT_66MHZ 0x0000001f
46#define SLOT_66MHZ_PCIX_266 0x00000f00
47#define SLOT_100MHZ_PCIX_266 0x0000f000
48#define SLOT_133MHZ_PCIX_266 0x000f0000
49#define SLOT_66MHZ_PCIX_533 0x00f00000
50#define SLOT_100MHZ_PCIX_533 0x0f000000
51#define SLOT_133MHZ_PCIX_533 0xf0000000
52
Linus Torvalds1da177e2005-04-16 15:20:36 -070053/* Slot Configuration */
54#define SLOT_NUM 0x0000001F
55#define FIRST_DEV_NUM 0x00001F00
56#define PSN 0x07FF0000
57#define UPDOWN 0x20000000
58#define MRLSENSOR 0x40000000
59#define ATTN_BUTTON 0x80000000
60
Kenji Kaneshige2b34da72006-05-02 11:09:42 +090061/*
Kenji Kaneshigec4cecc12006-05-12 11:10:56 +090062 * Interrupt Locator Register definitions
63 */
64#define CMD_INTR_PENDING (1 << 0)
65#define SLOT_INTR_PENDING(i) (1 << (i + 1))
66
67/*
Kenji Kaneshigee7138722006-05-02 11:12:37 +090068 * Controller SERR-INT Register
69 */
70#define GLOBAL_INTR_MASK (1 << 0)
71#define GLOBAL_SERR_MASK (1 << 1)
72#define COMMAND_INTR_MASK (1 << 2)
73#define ARBITER_SERR_MASK (1 << 3)
74#define COMMAND_DETECTED (1 << 16)
75#define ARBITER_DETECTED (1 << 17)
76#define SERR_INTR_RSVDZ_MASK 0xfffc0000
77
78/*
Kenji Kaneshige2b34da72006-05-02 11:09:42 +090079 * Logical Slot Register definitions
80 */
81#define SLOT_REG(i) (SLOT1 + (4 * i))
82
Kenji Kaneshige58587592006-05-02 11:10:37 +090083#define SLOT_STATE_SHIFT (0)
84#define SLOT_STATE_MASK (3 << 0)
85#define SLOT_STATE_PWRONLY (1)
86#define SLOT_STATE_ENABLED (2)
87#define SLOT_STATE_DISABLED (3)
88#define PWR_LED_STATE_SHIFT (2)
89#define PWR_LED_STATE_MASK (3 << 2)
90#define ATN_LED_STATE_SHIFT (4)
91#define ATN_LED_STATE_MASK (3 << 4)
92#define ATN_LED_STATE_ON (1)
93#define ATN_LED_STATE_BLINK (2)
94#define ATN_LED_STATE_OFF (3)
95#define POWER_FAULT (1 << 6)
96#define ATN_BUTTON (1 << 7)
97#define MRL_SENSOR (1 << 8)
98#define MHZ66_CAP (1 << 9)
99#define PRSNT_SHIFT (10)
100#define PRSNT_MASK (3 << 10)
101#define PCIX_CAP_SHIFT (12)
102#define PCIX_CAP_MASK_PI1 (3 << 12)
103#define PCIX_CAP_MASK_PI2 (7 << 12)
104#define PRSNT_CHANGE_DETECTED (1 << 16)
105#define ISO_PFAULT_DETECTED (1 << 17)
106#define BUTTON_PRESS_DETECTED (1 << 18)
107#define MRL_CHANGE_DETECTED (1 << 19)
108#define CON_PFAULT_DETECTED (1 << 20)
109#define PRSNT_CHANGE_INTR_MASK (1 << 24)
110#define ISO_PFAULT_INTR_MASK (1 << 25)
111#define BUTTON_PRESS_INTR_MASK (1 << 26)
112#define MRL_CHANGE_INTR_MASK (1 << 27)
113#define CON_PFAULT_INTR_MASK (1 << 28)
114#define MRL_CHANGE_SERR_MASK (1 << 29)
115#define CON_PFAULT_SERR_MASK (1 << 30)
Dan Carpenter3b8fdb72010-05-26 12:46:39 +0200116#define SLOT_REG_RSVDZ_MASK ((1 << 15) | (7 << 21))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117
Kenji Kaneshige40853992006-05-12 11:11:48 +0900118/*
119 * SHPC Command Code definitnions
120 *
121 * Slot Operation 00h - 3Fh
122 * Set Bus Segment Speed/Mode A 40h - 47h
123 * Power-Only All Slots 48h
124 * Enable All Slots 49h
125 * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh
126 * Reserved Command Codes 60h - BFh
127 * Vendor Specific Commands C0h - FFh
128 */
129#define SET_SLOT_PWR 0x01 /* Slot Operation */
130#define SET_SLOT_ENABLE 0x02
131#define SET_SLOT_DISABLE 0x03
132#define SET_PWR_ON 0x04
133#define SET_PWR_BLINK 0x08
134#define SET_PWR_OFF 0x0c
135#define SET_ATTN_ON 0x10
136#define SET_ATTN_BLINK 0x20
137#define SET_ATTN_OFF 0x30
138#define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139#define SETA_PCI_66MHZ 0x41
140#define SETA_PCIX_66MHZ 0x42
141#define SETA_PCIX_100MHZ 0x43
142#define SETA_PCIX_133MHZ 0x44
Kenji Kaneshige40853992006-05-12 11:11:48 +0900143#define SETA_RESERVED1 0x45
144#define SETA_RESERVED2 0x46
145#define SETA_RESERVED3 0x47
146#define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */
147#define SET_ENABLE_ALL 0x49 /* Enable All Slots */
148#define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149#define SETB_PCI_66MHZ 0x51
150#define SETB_PCIX_66MHZ_PM 0x52
151#define SETB_PCIX_100MHZ_PM 0x53
152#define SETB_PCIX_133MHZ_PM 0x54
153#define SETB_PCIX_66MHZ_EM 0x55
154#define SETB_PCIX_100MHZ_EM 0x56
155#define SETB_PCIX_133MHZ_EM 0x57
156#define SETB_PCIX_66MHZ_266 0x58
157#define SETB_PCIX_100MHZ_266 0x59
158#define SETB_PCIX_133MHZ_266 0x5a
159#define SETB_PCIX_66MHZ_533 0x5b
160#define SETB_PCIX_100MHZ_533 0x5c
161#define SETB_PCIX_133MHZ_533 0x5d
Kenji Kaneshige40853992006-05-12 11:11:48 +0900162#define SETB_RESERVED1 0x5e
163#define SETB_RESERVED2 0x5f
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164
Kenji Kaneshige40853992006-05-12 11:11:48 +0900165/*
166 * SHPC controller command error code
167 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168#define SWITCH_OPEN 0x1
169#define INVALID_CMD 0x2
170#define INVALID_SPEED_MODE 0x4
171
Kenji Kaneshige40853992006-05-12 11:11:48 +0900172/*
173 * For accessing SHPC Working Register Set via PCI Configuration Space
174 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175#define DWORD_SELECT 0x2
176#define DWORD_DATA 0x4
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177
178/* Field Offset in Logical Slot Register - byte boundary */
179#define SLOT_EVENT_LATCH 0x2
180#define SLOT_SERR_INT_MASK 0x3
181
David Howells7d12e782006-10-05 14:55:46 +0100182static irqreturn_t shpc_isr(int irq, void *dev_id);
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800183static void start_int_poll_timer(struct controller *ctrl, int sec);
Kenji Kaneshiged29aadd2006-01-26 09:59:24 +0900184static int hpc_check_cmd_status(struct controller *ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900186static inline u8 shpc_readb(struct controller *ctrl, int reg)
187{
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800188 return readb(ctrl->creg + reg);
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900189}
190
191static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val)
192{
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800193 writeb(val, ctrl->creg + reg);
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900194}
195
196static inline u16 shpc_readw(struct controller *ctrl, int reg)
197{
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800198 return readw(ctrl->creg + reg);
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900199}
200
201static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
202{
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800203 writew(val, ctrl->creg + reg);
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900204}
205
206static inline u32 shpc_readl(struct controller *ctrl, int reg)
207{
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800208 return readl(ctrl->creg + reg);
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900209}
210
211static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
212{
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800213 writel(val, ctrl->creg + reg);
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900214}
215
216static inline int shpc_indirect_read(struct controller *ctrl, int index,
217 u32 *value)
218{
219 int rc;
220 u32 cap_offset = ctrl->cap_offset;
221 struct pci_dev *pdev = ctrl->pci_dev;
222
223 rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
224 if (rc)
225 return rc;
226 return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
227}
228
Kenji Kaneshigef4263952006-05-12 11:13:02 +0900229/*
230 * This is the interrupt polling timeout function.
231 */
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800232static void int_poll_timeout(unsigned long data)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233{
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800234 struct controller *ctrl = (struct controller *)data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235
Kenji Kaneshigef4263952006-05-12 11:13:02 +0900236 /* Poll for interrupt events. regs == NULL => polling */
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800237 shpc_isr(0, ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800239 init_timer(&ctrl->poll_timer);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240 if (!shpchp_poll_time)
Kenji Kaneshigef4263952006-05-12 11:13:02 +0900241 shpchp_poll_time = 2; /* default polling interval is 2 sec */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800243 start_int_poll_timer(ctrl, shpchp_poll_time);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244}
245
Kenji Kaneshigef4263952006-05-12 11:13:02 +0900246/*
247 * This function starts the interrupt polling timer.
248 */
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800249static void start_int_poll_timer(struct controller *ctrl, int sec)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700250{
Kenji Kaneshigef4263952006-05-12 11:13:02 +0900251 /* Clamp to sane value */
252 if ((sec <= 0) || (sec > 60))
253 sec = 2;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800255 ctrl->poll_timer.function = &int_poll_timeout;
256 ctrl->poll_timer.data = (unsigned long)ctrl;
257 ctrl->poll_timer.expires = jiffies + sec * HZ;
258 add_timer(&ctrl->poll_timer);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259}
260
Kenji Kaneshiged1729cc2006-09-28 15:51:21 -0700261static inline int is_ctrl_busy(struct controller *ctrl)
262{
263 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS);
264 return cmd_status & 0x1;
265}
266
Kenji Kaneshigeb4a1eff2006-09-22 12:52:37 -0700267/*
268 * Returns 1 if SHPC finishes executing a command within 1 sec,
269 * otherwise returns 0.
270 */
271static inline int shpc_poll_ctrl_busy(struct controller *ctrl)
272{
273 int i;
Kenji Kaneshigeb4a1eff2006-09-22 12:52:37 -0700274
Kenji Kaneshiged1729cc2006-09-28 15:51:21 -0700275 if (!is_ctrl_busy(ctrl))
Kenji Kaneshigeb4a1eff2006-09-22 12:52:37 -0700276 return 1;
277
278 /* Check every 0.1 sec for a total of 1 sec */
279 for (i = 0; i < 10; i++) {
280 msleep(100);
Kenji Kaneshiged1729cc2006-09-28 15:51:21 -0700281 if (!is_ctrl_busy(ctrl))
Kenji Kaneshigeb4a1eff2006-09-22 12:52:37 -0700282 return 1;
283 }
284
285 return 0;
286}
287
Kenji Kaneshigebd62e272005-11-25 12:28:53 +0900288static inline int shpc_wait_cmd(struct controller *ctrl)
289{
290 int retval = 0;
Kenji Kaneshigeb4a1eff2006-09-22 12:52:37 -0700291 unsigned long timeout = msecs_to_jiffies(1000);
292 int rc;
293
294 if (shpchp_poll_mode)
295 rc = shpc_poll_ctrl_busy(ctrl);
296 else
297 rc = wait_event_interruptible_timeout(ctrl->queue,
Kenji Kaneshige6aa562c2006-09-28 15:51:36 -0700298 !is_ctrl_busy(ctrl), timeout);
Kenji Kaneshiged1729cc2006-09-28 15:51:21 -0700299 if (!rc && is_ctrl_busy(ctrl)) {
Kenji Kaneshigebd62e272005-11-25 12:28:53 +0900300 retval = -EIO;
Taku Izumif98ca312008-10-23 11:52:12 +0900301 ctrl_err(ctrl, "Command not completed in 1000 msec\n");
Kenji Kaneshigebd62e272005-11-25 12:28:53 +0900302 } else if (rc < 0) {
303 retval = -EINTR;
Taku Izumif98ca312008-10-23 11:52:12 +0900304 ctrl_info(ctrl, "Command was interrupted by a signal\n");
Kenji Kaneshigebd62e272005-11-25 12:28:53 +0900305 }
Kenji Kaneshigebd62e272005-11-25 12:28:53 +0900306
307 return retval;
308}
309
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
311{
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900312 struct controller *ctrl = slot->ctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700313 u16 cmd_status;
314 int retval = 0;
315 u16 temp_word;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700316
Kenji Kaneshiged29aadd2006-01-26 09:59:24 +0900317 mutex_lock(&slot->ctrl->cmd_lock);
318
Kenji Kaneshigeb4a1eff2006-09-22 12:52:37 -0700319 if (!shpc_poll_ctrl_busy(ctrl)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320 /* After 1 sec and and the controller is still busy */
Taku Izumibe7bce22008-10-23 11:54:39 +0900321 ctrl_err(ctrl, "Controller is still busy after 1 sec\n");
Kenji Kaneshiged29aadd2006-01-26 09:59:24 +0900322 retval = -EBUSY;
323 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700324 }
325
326 ++t_slot;
327 temp_word = (t_slot << 8) | (cmd & 0xFF);
Taku Izumif98ca312008-10-23 11:52:12 +0900328 ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd);
Kenji Kaneshige9f593e32007-01-09 13:03:10 -0800329
Linus Torvalds1da177e2005-04-16 15:20:36 -0700330 /* To make sure the Controller Busy bit is 0 before we send out the
Kenji Kaneshige9f593e32007-01-09 13:03:10 -0800331 * command.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332 */
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900333 shpc_writew(ctrl, CMD, temp_word);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334
Kenji Kaneshigebd62e272005-11-25 12:28:53 +0900335 /*
336 * Wait for command completion.
337 */
338 retval = shpc_wait_cmd(slot->ctrl);
Kenji Kaneshiged29aadd2006-01-26 09:59:24 +0900339 if (retval)
340 goto out;
341
342 cmd_status = hpc_check_cmd_status(slot->ctrl);
343 if (cmd_status) {
Taku Izumibe7bce22008-10-23 11:54:39 +0900344 ctrl_err(ctrl,
345 "Failed to issued command 0x%x (error code = %d)\n",
346 cmd, cmd_status);
Kenji Kaneshiged29aadd2006-01-26 09:59:24 +0900347 retval = -EIO;
348 }
349 out:
350 mutex_unlock(&slot->ctrl->cmd_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351 return retval;
352}
353
354static int hpc_check_cmd_status(struct controller *ctrl)
355{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356 int retval = 0;
Kenji Kaneshige1555b332007-01-09 13:03:01 -0800357 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
Kenji Kaneshige9f593e32007-01-09 13:03:10 -0800358
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359 switch (cmd_status >> 1) {
360 case 0:
361 retval = 0;
362 break;
363 case 1:
364 retval = SWITCH_OPEN;
Taku Izumibe7bce22008-10-23 11:54:39 +0900365 ctrl_err(ctrl, "Switch opened!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366 break;
367 case 2:
368 retval = INVALID_CMD;
Taku Izumibe7bce22008-10-23 11:54:39 +0900369 ctrl_err(ctrl, "Invalid HPC command!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370 break;
371 case 4:
372 retval = INVALID_SPEED_MODE;
Taku Izumibe7bce22008-10-23 11:54:39 +0900373 ctrl_err(ctrl, "Invalid bus speed/mode!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374 break;
375 default:
376 retval = cmd_status;
377 }
378
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379 return retval;
380}
381
382
383static int hpc_get_attention_status(struct slot *slot, u8 *status)
384{
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900385 struct controller *ctrl = slot->ctrl;
Kenji Kaneshige1555b332007-01-09 13:03:01 -0800386 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
387 u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388
Kenji Kaneshige58587592006-05-02 11:10:37 +0900389 switch (state) {
390 case ATN_LED_STATE_ON:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391 *status = 1; /* On */
392 break;
Kenji Kaneshige58587592006-05-02 11:10:37 +0900393 case ATN_LED_STATE_BLINK:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394 *status = 2; /* Blink */
395 break;
Kenji Kaneshige58587592006-05-02 11:10:37 +0900396 case ATN_LED_STATE_OFF:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700397 *status = 0; /* Off */
398 break;
399 default:
Kenji Kaneshige58587592006-05-02 11:10:37 +0900400 *status = 0xFF; /* Reserved */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700401 break;
402 }
403
Linus Torvalds1da177e2005-04-16 15:20:36 -0700404 return 0;
405}
406
407static int hpc_get_power_status(struct slot * slot, u8 *status)
408{
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900409 struct controller *ctrl = slot->ctrl;
Kenji Kaneshige1555b332007-01-09 13:03:01 -0800410 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
411 u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412
Kenji Kaneshige58587592006-05-02 11:10:37 +0900413 switch (state) {
414 case SLOT_STATE_PWRONLY:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700415 *status = 2; /* Powered only */
416 break;
Kenji Kaneshige58587592006-05-02 11:10:37 +0900417 case SLOT_STATE_ENABLED:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418 *status = 1; /* Enabled */
419 break;
Kenji Kaneshige58587592006-05-02 11:10:37 +0900420 case SLOT_STATE_DISABLED:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700421 *status = 0; /* Disabled */
422 break;
423 default:
Kenji Kaneshige58587592006-05-02 11:10:37 +0900424 *status = 0xFF; /* Reserved */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425 break;
426 }
427
Kenji Kaneshige58587592006-05-02 11:10:37 +0900428 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429}
430
431
432static int hpc_get_latch_status(struct slot *slot, u8 *status)
433{
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900434 struct controller *ctrl = slot->ctrl;
Kenji Kaneshige1555b332007-01-09 13:03:01 -0800435 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436
Kenji Kaneshige58587592006-05-02 11:10:37 +0900437 *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438
Linus Torvalds1da177e2005-04-16 15:20:36 -0700439 return 0;
440}
441
442static int hpc_get_adapter_status(struct slot *slot, u8 *status)
443{
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900444 struct controller *ctrl = slot->ctrl;
Kenji Kaneshige1555b332007-01-09 13:03:01 -0800445 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
446 u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447
Kenji Kaneshige58587592006-05-02 11:10:37 +0900448 *status = (state != 0x3) ? 1 : 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700449
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450 return 0;
451}
452
453static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
454{
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900455 struct controller *ctrl = slot->ctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900457 *prog_int = shpc_readb(ctrl, PROG_INTERFACE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700458
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459 return 0;
460}
461
462static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
463{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464 int retval = 0;
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900465 struct controller *ctrl = slot->ctrl;
Kenji Kaneshige2b34da72006-05-02 11:09:42 +0900466 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
Kenji Kaneshige58587592006-05-02 11:10:37 +0900467 u8 m66_cap = !!(slot_reg & MHZ66_CAP);
Kenji Kaneshige795eb5c2006-05-02 11:11:54 +0900468 u8 pi, pcix_cap;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700469
Kenji Kaneshige795eb5c2006-05-02 11:11:54 +0900470 if ((retval = hpc_get_prog_int(slot, &pi)))
471 return retval;
472
473 switch (pi) {
474 case 1:
475 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT;
476 break;
477 case 2:
478 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT;
479 break;
480 default:
481 return -ENODEV;
482 }
483
Taku Izumif98ca312008-10-23 11:52:12 +0900484 ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
485 __func__, slot_reg, pcix_cap, m66_cap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700486
Kenji Kaneshige0afabe92006-03-01 14:55:11 +0900487 switch (pcix_cap) {
488 case 0x0:
489 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
490 break;
491 case 0x1:
492 *value = PCI_SPEED_66MHz_PCIX;
493 break;
494 case 0x3:
495 *value = PCI_SPEED_133MHz_PCIX;
496 break;
497 case 0x4:
498 *value = PCI_SPEED_133MHz_PCIX_266;
499 break;
500 case 0x5:
501 *value = PCI_SPEED_133MHz_PCIX_533;
502 break;
503 case 0x2:
504 default:
505 *value = PCI_SPEED_UNKNOWN;
506 retval = -ENODEV;
507 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508 }
509
Taku Izumif98ca312008-10-23 11:52:12 +0900510 ctrl_dbg(ctrl, "Adapter speed = %d\n", *value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700511 return retval;
512}
513
514static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
515{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700516 int retval = 0;
Kenji Kaneshige1555b332007-01-09 13:03:01 -0800517 struct controller *ctrl = slot->ctrl;
518 u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
519 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700520
521 if (pi == 2) {
Kenji Kaneshige87d6c552005-11-24 11:35:05 +0900522 *mode = (sec_bus_status & 0x0100) >> 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700523 } else {
524 retval = -1;
525 }
526
Taku Izumif98ca312008-10-23 11:52:12 +0900527 ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528 return retval;
529}
530
531static int hpc_query_power_fault(struct slot * slot)
532{
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900533 struct controller *ctrl = slot->ctrl;
Kenji Kaneshige1555b332007-01-09 13:03:01 -0800534 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700535
Linus Torvalds1da177e2005-04-16 15:20:36 -0700536 /* Note: Logic 0 => fault */
Kenji Kaneshige58587592006-05-02 11:10:37 +0900537 return !(slot_reg & POWER_FAULT);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538}
539
540static int hpc_set_attention_status(struct slot *slot, u8 value)
541{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700542 u8 slot_cmd = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700543
544 switch (value) {
Kenji Kaneshige9f593e32007-01-09 13:03:10 -0800545 case 0 :
Kenji Kaneshige40853992006-05-12 11:11:48 +0900546 slot_cmd = SET_ATTN_OFF; /* OFF */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700547 break;
548 case 1:
Kenji Kaneshige40853992006-05-12 11:11:48 +0900549 slot_cmd = SET_ATTN_ON; /* ON */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700550 break;
551 case 2:
Kenji Kaneshige40853992006-05-12 11:11:48 +0900552 slot_cmd = SET_ATTN_BLINK; /* BLINK */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700553 break;
554 default:
555 return -1;
556 }
557
Kenji Kaneshiged4fbf602006-05-12 11:05:59 +0900558 return shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700559}
560
561
562static void hpc_set_green_led_on(struct slot *slot)
563{
Kenji Kaneshige40853992006-05-12 11:11:48 +0900564 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565}
566
567static void hpc_set_green_led_off(struct slot *slot)
568{
Kenji Kaneshige40853992006-05-12 11:11:48 +0900569 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700570}
571
572static void hpc_set_green_led_blink(struct slot *slot)
573{
Kenji Kaneshige40853992006-05-12 11:11:48 +0900574 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700575}
576
Linus Torvalds1da177e2005-04-16 15:20:36 -0700577static void hpc_release_ctlr(struct controller *ctrl)
578{
Kenji Kaneshigef7391f52006-02-21 15:45:45 -0800579 int i;
Kenji Kaneshiged49f2c42006-05-03 23:34:17 +0900580 u32 slot_reg, serr_int;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700581
Kenji Kaneshigef7391f52006-02-21 15:45:45 -0800582 /*
Kenji Kaneshige795eb5c2006-05-02 11:11:54 +0900583 * Mask event interrupts and SERRs of all slots
Kenji Kaneshigef7391f52006-02-21 15:45:45 -0800584 */
Kenji Kaneshige795eb5c2006-05-02 11:11:54 +0900585 for (i = 0; i < ctrl->num_slots; i++) {
586 slot_reg = shpc_readl(ctrl, SLOT_REG(i));
587 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
588 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
589 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
590 CON_PFAULT_SERR_MASK);
591 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
592 shpc_writel(ctrl, SLOT_REG(i), slot_reg);
593 }
Kenji Kaneshigef7391f52006-02-21 15:45:45 -0800594
595 cleanup_slots(ctrl);
596
Kenji Kaneshiged49f2c42006-05-03 23:34:17 +0900597 /*
Joe Perches36098012007-12-17 11:40:11 -0800598 * Mask SERR and System Interrupt generation
Kenji Kaneshiged49f2c42006-05-03 23:34:17 +0900599 */
600 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
601 serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
602 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
603 serr_int &= ~SERR_INTR_RSVDZ_MASK;
604 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
605
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800606 if (shpchp_poll_mode)
607 del_timer(&ctrl->poll_timer);
608 else {
609 free_irq(ctrl->pci_dev->irq, ctrl);
610 pci_disable_msi(ctrl->pci_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700611 }
Kenji Kaneshigef7391f52006-02-21 15:45:45 -0800612
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800613 iounmap(ctrl->creg);
614 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615}
616
617static int hpc_power_on_slot(struct slot * slot)
618{
Kenji Kaneshiged4fbf602006-05-12 11:05:59 +0900619 int retval;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620
Kenji Kaneshige40853992006-05-12 11:11:48 +0900621 retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);
Kenji Kaneshige1555b332007-01-09 13:03:01 -0800622 if (retval)
Taku Izumif98ca312008-10-23 11:52:12 +0900623 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700624
Kenji Kaneshige1555b332007-01-09 13:03:01 -0800625 return retval;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700626}
627
628static int hpc_slot_enable(struct slot * slot)
629{
Kenji Kaneshiged4fbf602006-05-12 11:05:59 +0900630 int retval;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700631
Kenji Kaneshige40853992006-05-12 11:11:48 +0900632 /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
633 retval = shpc_write_cmd(slot, slot->hp_slot,
634 SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);
Kenji Kaneshige1555b332007-01-09 13:03:01 -0800635 if (retval)
Taku Izumif98ca312008-10-23 11:52:12 +0900636 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700637
Kenji Kaneshige1555b332007-01-09 13:03:01 -0800638 return retval;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700639}
640
641static int hpc_slot_disable(struct slot * slot)
642{
Kenji Kaneshiged4fbf602006-05-12 11:05:59 +0900643 int retval;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700644
Kenji Kaneshige40853992006-05-12 11:11:48 +0900645 /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */
646 retval = shpc_write_cmd(slot, slot->hp_slot,
647 SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);
Kenji Kaneshige1555b332007-01-09 13:03:01 -0800648 if (retval)
Taku Izumif98ca312008-10-23 11:52:12 +0900649 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700650
Kenji Kaneshige1555b332007-01-09 13:03:01 -0800651 return retval;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700652}
653
Matthew Wilcox3749c512009-12-13 08:11:32 -0500654static int shpc_get_cur_bus_speed(struct controller *ctrl)
655{
656 int retval = 0;
657 struct pci_bus *bus = ctrl->pci_dev->subordinate;
658 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
659 u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
660 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
661 u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
662
663 if ((pi == 1) && (speed_mode > 4)) {
664 retval = -ENODEV;
665 goto out;
666 }
667
668 switch (speed_mode) {
669 case 0x0:
670 bus_speed = PCI_SPEED_33MHz;
671 break;
672 case 0x1:
673 bus_speed = PCI_SPEED_66MHz;
674 break;
675 case 0x2:
676 bus_speed = PCI_SPEED_66MHz_PCIX;
677 break;
678 case 0x3:
679 bus_speed = PCI_SPEED_100MHz_PCIX;
680 break;
681 case 0x4:
682 bus_speed = PCI_SPEED_133MHz_PCIX;
683 break;
684 case 0x5:
685 bus_speed = PCI_SPEED_66MHz_PCIX_ECC;
686 break;
687 case 0x6:
688 bus_speed = PCI_SPEED_100MHz_PCIX_ECC;
689 break;
690 case 0x7:
691 bus_speed = PCI_SPEED_133MHz_PCIX_ECC;
692 break;
693 case 0x8:
694 bus_speed = PCI_SPEED_66MHz_PCIX_266;
695 break;
696 case 0x9:
697 bus_speed = PCI_SPEED_100MHz_PCIX_266;
698 break;
699 case 0xa:
700 bus_speed = PCI_SPEED_133MHz_PCIX_266;
701 break;
702 case 0xb:
703 bus_speed = PCI_SPEED_66MHz_PCIX_533;
704 break;
705 case 0xc:
706 bus_speed = PCI_SPEED_100MHz_PCIX_533;
707 break;
708 case 0xd:
709 bus_speed = PCI_SPEED_133MHz_PCIX_533;
710 break;
711 default:
712 retval = -ENODEV;
713 break;
714 }
715
716 out:
717 bus->cur_bus_speed = bus_speed;
718 dbg("Current bus speed = %d\n", bus_speed);
719 return retval;
720}
721
722
Linus Torvalds1da177e2005-04-16 15:20:36 -0700723static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
724{
Kenji Kaneshige0afabe92006-03-01 14:55:11 +0900725 int retval;
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900726 struct controller *ctrl = slot->ctrl;
Kenji Kaneshige0afabe92006-03-01 14:55:11 +0900727 u8 pi, cmd;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700728
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900729 pi = shpc_readb(ctrl, PROG_INTERFACE);
Kenji Kaneshige0afabe92006-03-01 14:55:11 +0900730 if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
731 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700732
Kenji Kaneshige0afabe92006-03-01 14:55:11 +0900733 switch (value) {
734 case PCI_SPEED_33MHz:
735 cmd = SETA_PCI_33MHZ;
736 break;
737 case PCI_SPEED_66MHz:
738 cmd = SETA_PCI_66MHZ;
739 break;
740 case PCI_SPEED_66MHz_PCIX:
741 cmd = SETA_PCIX_66MHZ;
742 break;
743 case PCI_SPEED_100MHz_PCIX:
744 cmd = SETA_PCIX_100MHZ;
745 break;
746 case PCI_SPEED_133MHz_PCIX:
747 cmd = SETA_PCIX_133MHZ;
748 break;
749 case PCI_SPEED_66MHz_PCIX_ECC:
750 cmd = SETB_PCIX_66MHZ_EM;
751 break;
752 case PCI_SPEED_100MHz_PCIX_ECC:
753 cmd = SETB_PCIX_100MHZ_EM;
754 break;
755 case PCI_SPEED_133MHz_PCIX_ECC:
756 cmd = SETB_PCIX_133MHZ_EM;
757 break;
758 case PCI_SPEED_66MHz_PCIX_266:
759 cmd = SETB_PCIX_66MHZ_266;
760 break;
761 case PCI_SPEED_100MHz_PCIX_266:
762 cmd = SETB_PCIX_100MHZ_266;
763 break;
764 case PCI_SPEED_133MHz_PCIX_266:
765 cmd = SETB_PCIX_133MHZ_266;
766 break;
767 case PCI_SPEED_66MHz_PCIX_533:
768 cmd = SETB_PCIX_66MHZ_533;
769 break;
770 case PCI_SPEED_100MHz_PCIX_533:
771 cmd = SETB_PCIX_100MHZ_533;
772 break;
773 case PCI_SPEED_133MHz_PCIX_533:
774 cmd = SETB_PCIX_133MHZ_533;
775 break;
776 default:
777 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700778 }
Kenji Kaneshige0afabe92006-03-01 14:55:11 +0900779
780 retval = shpc_write_cmd(slot, 0, cmd);
781 if (retval)
Taku Izumif98ca312008-10-23 11:52:12 +0900782 ctrl_err(ctrl, "%s: Write command failed!\n", __func__);
Matthew Wilcox3749c512009-12-13 08:11:32 -0500783 else
784 shpc_get_cur_bus_speed(ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700785
Linus Torvalds1da177e2005-04-16 15:20:36 -0700786 return retval;
787}
788
David Howells7d12e782006-10-05 14:55:46 +0100789static irqreturn_t shpc_isr(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790{
Kenji Kaneshigec4cecc12006-05-12 11:10:56 +0900791 struct controller *ctrl = (struct controller *)dev_id;
Kenji Kaneshigec4cecc12006-05-12 11:10:56 +0900792 u32 serr_int, slot_reg, intr_loc, intr_loc2;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700793 int hp_slot;
794
Linus Torvalds1da177e2005-04-16 15:20:36 -0700795 /* Check to see if it was our interrupt */
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900796 intr_loc = shpc_readl(ctrl, INTR_LOC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700797 if (!intr_loc)
798 return IRQ_NONE;
Kenji Kaneshigec4cecc12006-05-12 11:10:56 +0900799
Taku Izumif98ca312008-10-23 11:52:12 +0900800 ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801
802 if(!shpchp_poll_mode) {
Kenji Kaneshigec4cecc12006-05-12 11:10:56 +0900803 /*
804 * Mask Global Interrupt Mask - see implementation
805 * note on p. 139 of SHPC spec rev 1.0
806 */
807 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
808 serr_int |= GLOBAL_INTR_MASK;
809 serr_int &= ~SERR_INTR_RSVDZ_MASK;
810 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700811
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900812 intr_loc2 = shpc_readl(ctrl, INTR_LOC);
Taku Izumif98ca312008-10-23 11:52:12 +0900813 ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814 }
815
Kenji Kaneshigec4cecc12006-05-12 11:10:56 +0900816 if (intr_loc & CMD_INTR_PENDING) {
Kenji Kaneshige9f593e32007-01-09 13:03:10 -0800817 /*
818 * Command Complete Interrupt Pending
Kenji Kaneshigef467f612005-11-24 11:39:29 +0900819 * RO only - clear by writing 1 to the Command Completion
Linus Torvalds1da177e2005-04-16 15:20:36 -0700820 * Detect bit in Controller SERR-INT register
821 */
Kenji Kaneshigec4cecc12006-05-12 11:10:56 +0900822 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
823 serr_int &= ~SERR_INTR_RSVDZ_MASK;
824 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
825
Linus Torvalds1da177e2005-04-16 15:20:36 -0700826 wake_up_interruptible(&ctrl->queue);
827 }
828
Kenji Kaneshigec4cecc12006-05-12 11:10:56 +0900829 if (!(intr_loc & ~CMD_INTR_PENDING))
Kenji Kaneshigee4e73042006-01-26 10:05:57 +0900830 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700831
Kenji Kaneshige9f593e32007-01-09 13:03:10 -0800832 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
Kenji Kaneshigec4cecc12006-05-12 11:10:56 +0900833 /* To find out which slot has interrupt pending */
834 if (!(intr_loc & SLOT_INTR_PENDING(hp_slot)))
835 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700836
Kenji Kaneshigec4cecc12006-05-12 11:10:56 +0900837 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
Taku Izumibe7bce22008-10-23 11:54:39 +0900838 ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n",
839 hp_slot, slot_reg);
Kenji Kaneshigec4cecc12006-05-12 11:10:56 +0900840
841 if (slot_reg & MRL_CHANGE_DETECTED)
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800842 shpchp_handle_switch_change(hp_slot, ctrl);
Kenji Kaneshigec4cecc12006-05-12 11:10:56 +0900843
844 if (slot_reg & BUTTON_PRESS_DETECTED)
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800845 shpchp_handle_attention_button(hp_slot, ctrl);
Kenji Kaneshigec4cecc12006-05-12 11:10:56 +0900846
847 if (slot_reg & PRSNT_CHANGE_DETECTED)
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800848 shpchp_handle_presence_change(hp_slot, ctrl);
Kenji Kaneshigec4cecc12006-05-12 11:10:56 +0900849
850 if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED))
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800851 shpchp_handle_power_fault(hp_slot, ctrl);
Kenji Kaneshigec4cecc12006-05-12 11:10:56 +0900852
853 /* Clear all slot events */
854 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
855 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700856 }
Kenji Kaneshigee4e73042006-01-26 10:05:57 +0900857 out:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700858 if (!shpchp_poll_mode) {
859 /* Unmask Global Interrupt Mask */
Kenji Kaneshigec4cecc12006-05-12 11:10:56 +0900860 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
861 serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK);
862 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700863 }
Kenji Kaneshige9f593e32007-01-09 13:03:10 -0800864
Linus Torvalds1da177e2005-04-16 15:20:36 -0700865 return IRQ_HANDLED;
866}
867
Matthew Wilcox3749c512009-12-13 08:11:32 -0500868static int shpc_get_max_bus_speed(struct controller *ctrl)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869{
Kenji Kaneshige0afabe92006-03-01 14:55:11 +0900870 int retval = 0;
Matthew Wilcox3749c512009-12-13 08:11:32 -0500871 struct pci_bus *bus = ctrl->pci_dev->subordinate;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700872 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900873 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
874 u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
875 u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876
Linus Torvalds1da177e2005-04-16 15:20:36 -0700877 if (pi == 2) {
Kenji Kaneshige6558b6a2005-11-24 13:44:01 +0900878 if (slot_avail2 & SLOT_133MHZ_PCIX_533)
Kenji Kaneshige0afabe92006-03-01 14:55:11 +0900879 bus_speed = PCI_SPEED_133MHz_PCIX_533;
Kenji Kaneshige6558b6a2005-11-24 13:44:01 +0900880 else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
Kenji Kaneshige0afabe92006-03-01 14:55:11 +0900881 bus_speed = PCI_SPEED_100MHz_PCIX_533;
Kenji Kaneshige6558b6a2005-11-24 13:44:01 +0900882 else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
Kenji Kaneshige0afabe92006-03-01 14:55:11 +0900883 bus_speed = PCI_SPEED_66MHz_PCIX_533;
Kenji Kaneshige6558b6a2005-11-24 13:44:01 +0900884 else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
Kenji Kaneshige0afabe92006-03-01 14:55:11 +0900885 bus_speed = PCI_SPEED_133MHz_PCIX_266;
Kenji Kaneshige6558b6a2005-11-24 13:44:01 +0900886 else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
Kenji Kaneshige0afabe92006-03-01 14:55:11 +0900887 bus_speed = PCI_SPEED_100MHz_PCIX_266;
Kenji Kaneshige6558b6a2005-11-24 13:44:01 +0900888 else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
Kenji Kaneshige0afabe92006-03-01 14:55:11 +0900889 bus_speed = PCI_SPEED_66MHz_PCIX_266;
890 }
891
892 if (bus_speed == PCI_SPEED_UNKNOWN) {
Kenji Kaneshige6558b6a2005-11-24 13:44:01 +0900893 if (slot_avail1 & SLOT_133MHZ_PCIX)
Kenji Kaneshige0afabe92006-03-01 14:55:11 +0900894 bus_speed = PCI_SPEED_133MHz_PCIX;
Kenji Kaneshige6558b6a2005-11-24 13:44:01 +0900895 else if (slot_avail1 & SLOT_100MHZ_PCIX)
Kenji Kaneshige0afabe92006-03-01 14:55:11 +0900896 bus_speed = PCI_SPEED_100MHz_PCIX;
Kenji Kaneshige6558b6a2005-11-24 13:44:01 +0900897 else if (slot_avail1 & SLOT_66MHZ_PCIX)
Kenji Kaneshige0afabe92006-03-01 14:55:11 +0900898 bus_speed = PCI_SPEED_66MHz_PCIX;
Kenji Kaneshige6558b6a2005-11-24 13:44:01 +0900899 else if (slot_avail2 & SLOT_66MHZ)
Kenji Kaneshige0afabe92006-03-01 14:55:11 +0900900 bus_speed = PCI_SPEED_66MHz;
Kenji Kaneshige6558b6a2005-11-24 13:44:01 +0900901 else if (slot_avail1 & SLOT_33MHZ)
Kenji Kaneshige0afabe92006-03-01 14:55:11 +0900902 bus_speed = PCI_SPEED_33MHz;
903 else
904 retval = -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700905 }
906
Matthew Wilcox3749c512009-12-13 08:11:32 -0500907 bus->max_bus_speed = bus_speed;
Taku Izumif98ca312008-10-23 11:52:12 +0900908 ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed);
Kenji Kaneshige1555b332007-01-09 13:03:01 -0800909
Linus Torvalds1da177e2005-04-16 15:20:36 -0700910 return retval;
911}
912
Linus Torvalds1da177e2005-04-16 15:20:36 -0700913static struct hpc_ops shpchp_hpc_ops = {
914 .power_on_slot = hpc_power_on_slot,
915 .slot_enable = hpc_slot_enable,
916 .slot_disable = hpc_slot_disable,
Kenji Kaneshige9f593e32007-01-09 13:03:10 -0800917 .set_bus_speed_mode = hpc_set_bus_speed_mode,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700918 .set_attention_status = hpc_set_attention_status,
919 .get_power_status = hpc_get_power_status,
920 .get_attention_status = hpc_get_attention_status,
921 .get_latch_status = hpc_get_latch_status,
922 .get_adapter_status = hpc_get_adapter_status,
923
Linus Torvalds1da177e2005-04-16 15:20:36 -0700924 .get_adapter_speed = hpc_get_adapter_speed,
925 .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap,
926 .get_prog_int = hpc_get_prog_int,
927
928 .query_power_fault = hpc_query_power_fault,
929 .green_led_on = hpc_set_green_led_on,
930 .green_led_off = hpc_set_green_led_off,
931 .green_led_blink = hpc_set_green_led_blink,
Kenji Kaneshige9f593e32007-01-09 13:03:10 -0800932
Linus Torvalds1da177e2005-04-16 15:20:36 -0700933 .release_ctlr = hpc_release_ctlr,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700934};
935
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800936int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700937{
Amol Lad662a98f2006-10-05 12:07:32 +0530938 int rc = -1, num_slots = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700939 u8 hp_slot;
Kenji Kaneshige04559862005-11-24 11:36:59 +0900940 u32 shpc_base_offset;
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900941 u32 tempdword, slot_reg, slot_config;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700942 u8 i;
943
Kenji Kaneshige04559862005-11-24 11:36:59 +0900944 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
Taku Izumibe7bce22008-10-23 11:54:39 +0900945 ctrl_dbg(ctrl, "Hotplug Controller:\n");
Kenji Kaneshige04559862005-11-24 11:36:59 +0900946
Bjorn Helgaas4cac2eb2011-08-23 10:16:43 -0600947 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
948 pdev->device == PCI_DEVICE_ID_AMD_GOLAM_7450) {
Kenji Kaneshige04559862005-11-24 11:36:59 +0900949 /* amd shpc driver doesn't use Base Offset; assume 0 */
950 ctrl->mmio_base = pci_resource_start(pdev, 0);
951 ctrl->mmio_size = pci_resource_len(pdev, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700952 } else {
Kenji Kaneshige04559862005-11-24 11:36:59 +0900953 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
954 if (!ctrl->cap_offset) {
Taku Izumibe7bce22008-10-23 11:54:39 +0900955 ctrl_err(ctrl, "Cannot find PCI capability\n");
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800956 goto abort;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700957 }
Taku Izumibe7bce22008-10-23 11:54:39 +0900958 ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset);
Kenji Kaneshige04559862005-11-24 11:36:59 +0900959
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900960 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700961 if (rc) {
Taku Izumibe7bce22008-10-23 11:54:39 +0900962 ctrl_err(ctrl, "Cannot read base_offset\n");
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800963 goto abort;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700964 }
965
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900966 rc = shpc_indirect_read(ctrl, 3, &tempdword);
Kenji Kaneshige04559862005-11-24 11:36:59 +0900967 if (rc) {
Taku Izumibe7bce22008-10-23 11:54:39 +0900968 ctrl_err(ctrl, "Cannot read slot config\n");
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800969 goto abort;
Kenji Kaneshige04559862005-11-24 11:36:59 +0900970 }
971 num_slots = tempdword & SLOT_NUM;
Taku Izumibe7bce22008-10-23 11:54:39 +0900972 ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots);
Kenji Kaneshige04559862005-11-24 11:36:59 +0900973
974 for (i = 0; i < 9 + num_slots; i++) {
Kenji Kaneshige75d97c52006-05-02 11:08:42 +0900975 rc = shpc_indirect_read(ctrl, i, &tempdword);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700976 if (rc) {
Taku Izumibe7bce22008-10-23 11:54:39 +0900977 ctrl_err(ctrl,
978 "Cannot read creg (index = %d)\n", i);
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800979 goto abort;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700980 }
Taku Izumibe7bce22008-10-23 11:54:39 +0900981 ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700982 }
Kenji Kaneshige04559862005-11-24 11:36:59 +0900983
984 ctrl->mmio_base =
985 pci_resource_start(pdev, 0) + shpc_base_offset;
986 ctrl->mmio_size = 0x24 + 0x4 * num_slots;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700987 }
988
Taku Izumif98ca312008-10-23 11:52:12 +0900989 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
990 pdev->vendor, pdev->device, pdev->subsystem_vendor,
991 pdev->subsystem_device);
Kenji Kaneshige9f593e32007-01-09 13:03:10 -0800992
Amol Lad662a98f2006-10-05 12:07:32 +0530993 rc = pci_enable_device(pdev);
994 if (rc) {
Taku Izumibe7bce22008-10-23 11:54:39 +0900995 ctrl_err(ctrl, "pci_enable_device failed\n");
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -0800996 goto abort;
Amol Lad662a98f2006-10-05 12:07:32 +0530997 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700998
Kenji Kaneshige04559862005-11-24 11:36:59 +0900999 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
Taku Izumibe7bce22008-10-23 11:54:39 +09001000 ctrl_err(ctrl, "Cannot reserve MMIO region\n");
Amol Lad662a98f2006-10-05 12:07:32 +05301001 rc = -1;
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -08001002 goto abort;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001003 }
1004
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -08001005 ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
1006 if (!ctrl->creg) {
Taku Izumibe7bce22008-10-23 11:54:39 +09001007 ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n",
1008 ctrl->mmio_size, ctrl->mmio_base);
Kenji Kaneshige04559862005-11-24 11:36:59 +09001009 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
Amol Lad662a98f2006-10-05 12:07:32 +05301010 rc = -1;
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -08001011 goto abort;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001012 }
Taku Izumibe7bce22008-10-23 11:54:39 +09001013 ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001014
Ingo Molnar6aa4cdd2006-01-13 16:02:15 +01001015 mutex_init(&ctrl->crit_sect);
Kenji Kaneshiged29aadd2006-01-26 09:59:24 +09001016 mutex_init(&ctrl->cmd_lock);
1017
Linus Torvalds1da177e2005-04-16 15:20:36 -07001018 /* Setup wait queue */
1019 init_waitqueue_head(&ctrl->queue);
1020
Kenji Kaneshige75d97c52006-05-02 11:08:42 +09001021 ctrl->hpc_ops = &shpchp_hpc_ops;
1022
Linus Torvalds1da177e2005-04-16 15:20:36 -07001023 /* Return PCI Controller Info */
Kenji Kaneshige75d97c52006-05-02 11:08:42 +09001024 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -08001025 ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
1026 ctrl->num_slots = slot_config & SLOT_NUM;
1027 ctrl->first_slot = (slot_config & PSN) >> 16;
1028 ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001029
1030 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
Kenji Kaneshige75d97c52006-05-02 11:08:42 +09001031 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
Taku Izumibe7bce22008-10-23 11:54:39 +09001032 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
Kenji Kaneshigee7138722006-05-02 11:12:37 +09001033 tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
1034 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
1035 tempdword &= ~SERR_INTR_RSVDZ_MASK;
Kenji Kaneshige75d97c52006-05-02 11:08:42 +09001036 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1037 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
Taku Izumibe7bce22008-10-23 11:54:39 +09001038 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001039
1040 /* Mask the MRL sensor SERR Mask of individual slot in
1041 * Slot SERR-INT Mask & clear all the existing event if any
1042 */
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -08001043 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
Kenji Kaneshige2b34da72006-05-02 11:09:42 +09001044 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
Taku Izumibe7bce22008-10-23 11:54:39 +09001045 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
1046 hp_slot, slot_reg);
Kenji Kaneshige795eb5c2006-05-02 11:11:54 +09001047 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1048 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1049 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
1050 CON_PFAULT_SERR_MASK);
1051 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
1052 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001053 }
Kenji Kaneshige9f593e32007-01-09 13:03:10 -08001054
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -08001055 if (shpchp_poll_mode) {
1056 /* Install interrupt polling timer. Start with 10 sec delay */
1057 init_timer(&ctrl->poll_timer);
1058 start_int_poll_timer(ctrl, 10);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001059 } else {
1060 /* Installs the interrupt handler */
1061 rc = pci_enable_msi(pdev);
1062 if (rc) {
Taku Izumif98ca312008-10-23 11:52:12 +09001063 ctrl_info(ctrl,
1064 "Can't get msi for the hotplug controller\n");
1065 ctrl_info(ctrl,
1066 "Use INTx for the hotplug controller\n");
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -08001067 }
Kenji Kaneshige9f593e32007-01-09 13:03:10 -08001068
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -08001069 rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,
1070 MY_NAME, (void *)ctrl);
Tejun Heoe24dcbe2010-10-18 08:33:02 +02001071 ctrl_dbg(ctrl, "request_irq %d (returns %d)\n",
1072 ctrl->pci_dev->irq, rc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001073 if (rc) {
Taku Izumif98ca312008-10-23 11:52:12 +09001074 ctrl_err(ctrl, "Can't get irq %d for the hotplug "
1075 "controller\n", ctrl->pci_dev->irq);
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -08001076 goto abort_iounmap;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001077 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001078 }
Taku Izumibe7bce22008-10-23 11:54:39 +09001079 ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001080
Matthew Wilcox3749c512009-12-13 08:11:32 -05001081 shpc_get_max_bus_speed(ctrl);
1082 shpc_get_cur_bus_speed(ctrl);
1083
Kenji Kaneshige795eb5c2006-05-02 11:11:54 +09001084 /*
1085 * Unmask all event interrupts of all slots
1086 */
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -08001087 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
Kenji Kaneshige2b34da72006-05-02 11:09:42 +09001088 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
Taku Izumibe7bce22008-10-23 11:54:39 +09001089 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
1090 hp_slot, slot_reg);
Kenji Kaneshige795eb5c2006-05-02 11:11:54 +09001091 slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1092 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1093 CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK);
1094 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001095 }
1096 if (!shpchp_poll_mode) {
1097 /* Unmask all general input interrupts and SERR */
Kenji Kaneshige75d97c52006-05-02 11:08:42 +09001098 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
Kenji Kaneshigee7138722006-05-02 11:12:37 +09001099 tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK |
1100 SERR_INTR_RSVDZ_MASK);
Kenji Kaneshige75d97c52006-05-02 11:08:42 +09001101 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1102 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
Taku Izumibe7bce22008-10-23 11:54:39 +09001103 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001104 }
1105
Linus Torvalds1da177e2005-04-16 15:20:36 -07001106 return 0;
1107
1108 /* We end up here for the many possible ways to fail this API. */
Kenji Kaneshige0abe68c2006-12-16 15:25:34 -08001109abort_iounmap:
1110 iounmap(ctrl->creg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001111abort:
Amol Lad662a98f2006-10-05 12:07:32 +05301112 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001113}